WO2016071813A2 - Architecture d'un oscillateur à commande numérique (dco) - Google Patents

Architecture d'un oscillateur à commande numérique (dco) Download PDF

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Publication number
WO2016071813A2
WO2016071813A2 PCT/IB2015/058390 IB2015058390W WO2016071813A2 WO 2016071813 A2 WO2016071813 A2 WO 2016071813A2 IB 2015058390 W IB2015058390 W IB 2015058390W WO 2016071813 A2 WO2016071813 A2 WO 2016071813A2
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Prior art keywords
delay
input
line
digitally controlled
output
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PCT/IB2015/058390
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English (en)
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WO2016071813A3 (fr
Inventor
Raffaele Giordano
Sandro CADEDDU
Alberto ALOISIO
Fabrizio AMELI
Valerio BOCCI
Vincenzo Izzo
Adriano LAI
Stefano MASTROIANNI
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Istituto Nazionale Di Fisica Nucleare
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels

Definitions

  • the present invention is related to a digitally controlled oscillator architecture, an electronic device incorporating this oscillator therein, namely a phase locked loop and others, a delay locked loop based on the same architecture and a method for the implementation thereof .
  • DCO digitally controlled oscillator
  • PLL phase locked loop
  • DLL delay locked loop
  • Phase locked loops are mainly used for frequency synthesis, phase de-skew and jitter filtering of clock signals and for clock recovery from serial streams. These components are used in a variety of different applications, including microprocessors and controllers, System-on-Chips (SoC) , radio transceivers, video screens (TVs, monitors), high-speed serial data transmissions, and high-speed optical communications.
  • SoC System-on-Chips
  • a PLL includes analog components, i.e. a voltage controlled oscillator (VCO) and loop filters, and it is usually implemented as a full custom block, i.e. a block whose layout is manually designed, in integrated circuits (ICs) .
  • VCO voltage controlled oscillator
  • ICs integrated circuits
  • the main component of an All-Digital PLL is a digitally controlled oscillator (DCO) , which replaces the VCO of a classic PLL.
  • DCO digitally controlled oscillator
  • DAC digital-to-analog converter
  • a class of DCOs with a lower frequency performance with respect to the aforementioned types consists of path- selection DCOs, which are based on a multiplexer and a multi-output delay line.
  • this kind of DCO is disclosed in Bocci, V. et al . , "Time-multiplexing of signal using highly integrated digital delay: an FPGA implementation" in Nuclear Science Symposium Conference Record, 2005 IEEE. IEEE, 2005. p. 398-402.
  • path selection DCOs the outputs of the line are connected to the inputs of the multiplexer, which therefore can select different propagation paths in such a way to vary the oscillation period.
  • path-selection DCOs are limited in resolution by the delay of the buffers of the line, their usage requires the adoption of other techniques based on analog effects for fine delay modulation, as disclosed in Jen-Shim Chiang, Kuang-Yuan Chen, "The design of an all- digital phase-locked loop with small DCO hardware and fast phase lock" IEEE Trans. Circuits Syst. II: Analog Digital Signal Process. 46 (7) (1999) 945 - 950; in Chia- Tsun Wu, Wang Wei, I-Chyn Wey, An-Yeu (Andy) Wu, "A Scalable DCO Design for Portable ADPLL Designs” in Proceedings of ISCAS, vol. 6, 2005, pp.
  • US 5,638,010 A discloses a DCO architecture requiring an external clock for its operation, i.e. another component to be customized and optimized.
  • US 6,366,150 Bl discloses another DCO architecture wherein a transistor chain is inserted.
  • US 8,519,801 B2 (Chen et al . ) discloses a digitally controlled oscillator with cross-coupled transistors and a capacitor array; and US 8,610,511 Bl (Elrabaa) discloses another DCO including varactors.
  • the technical problem underlying the present invention is to devise a digitally controlled oscillator (DCO architecture which can overcome the drawbacks mentioned with reference to the above prior art.
  • DCO digitally controlled oscillator
  • the main advantage achieved by the DCO architecture according to the present invention is being natively digital and therefore not dependent upon any particular technology process for the manufacture thereof.
  • the present invention embraces all the electronic device, e.g. a Phase Locked Loop (PLL) , a Time to Digital Converter (TDC) , a Local oscillator, a Direct Digital Synthesizer (DDS), a Delay Locked Loop (DLL) and others, using a claimed DCO or DCDL architecture.
  • PLL Phase Locked Loop
  • TDC Time to Digital Converter
  • DDS Direct Digital Synthesizer
  • DLL Delay Locked Loop
  • DCDL DCDL architecture
  • the above architecture can be described using a common hardware description language (HDL) and it can be implemented by means of APR tools. Therefore, the designer is allowed to easily integrate the DCO of the present invention in a pure digital design flow, i.e. to automatically generate DCOs with features which can be defined at a synthesis step.
  • HDL hardware description language
  • the present invention is also referred to a method for the automatic synthesis of a DCO architecture.
  • Figure 1 shows a simplified bock-diagram of a digitally controlled oscillator architecture according to a preferred embodiment of the present invention
  • Figure 2 shows a block diagram of a more specific embodiment of the architecture shown in Figure 1 ;
  • Figure 3 shows a block diagram of a specific embodiment of a DCDL architecture according to the present invention, implemented in a Xilinx Kintex 7 FPGA;
  • Figure 4 shows the diagram depicting the oscillation period of a DCO of the present invention, implemented in a Kintex-7 325T FPGA, versus an oscillator control code (7-bit) at a temperature of 33°C.
  • a DCO is shown, based on a digital delay line, i.e. a digitally controlled delay line (DCDL) .
  • the output of the DCDL might be logically inverted with respect to the input. If the output is not inverted, the inversion is performed by a feedback logic, and the inverted signal is then routed back at the input of the DCDL in order to realize an oscillation.
  • DCDL digitally controlled delay line
  • Each element has a first input (A) connected to the output of the previous element and a second input (B) driven by a high-fan out distribution network (HFN) .
  • HFN high-fan out distribution network
  • a high-fan out network is a network distributing a single input to multiple inputs, and having a uniform delay from its input to each output.
  • a control encoder (shown in Figure 1) appropriately sets the S input of each delay element in such a way that a number
  • N ctrl(n - 1 : 0) (1) of elements is crossed by the input signal before reaching the output. Assuming that the delay through each element is uniform and equal to t P d, then the delay from (in) to (out) is defined as:
  • the oscillation period is:
  • the first element of the delay line has the input A to a constant logical value and the encoder sets "S" inputs of the delay elements in order to propagate the constant value in all the elements prior to the injection element.
  • the encoder output is synchronized with the clock generated by the oscillator and it has a phase relationship with respect to it such to avoid the injection of glitches in the chain when changing the control code.
  • ⁇ a chain of delay elements having each at least three inputs, a first input driven by the output of the previous element and used for propagation in the line, a second input for the injection of a signal in the chain and a third input (or further inputs) for the selection of the behaviour of the delay element (injection or propagation);
  • HFNs comprising clock trees
  • dedicated tools are already integrated in modern CAD systems in order to realize these structures with minimum skew.
  • N is the number of delay elements selected in the delay chain
  • t P d C is the delay due to a single delay element
  • t pdn is the propagation delay between two subsequent delay elements.
  • the to term accounts for the propagation delay in the distribution paths of the feedback circuit and the skew among different paths causes an error for this term.
  • CAD tools such as clock tree synthesis (CTS) automatically minimize the skew among different paths in the distribution of a signal to different points of the circuit.
  • CTS clock tree synthesis
  • the error on the t P d C term is dominated by process parameters variations and mismatches due to the lithographic process. These errors are beyond the designer's control, but they can be minimized by means of a suitable placement procedure. In particular, minimizing the placement area of the delay cells also minimizes the probability of having significant mismatches among them.
  • the designer can easily control the error on term (t pc m) by means of CAD tools available in a standard digital design flow. That can be achieved by constraining the propagation delay between two subsequent chain elements N and N+l. Alternatively, a manual placement of the delay chain can be performed.
  • T k and T k ⁇ i be the oscillation periods corresponding to the control codes k and k + 1, let a and p be two positive integers such that p > a, and let d a , P (t) be a time- dependent bit sequence. So, if one adds the control code k to the modulating sequence d a , P (t) to alternately select the periods T k and T k+i , the average period of oscillation T can be c
  • a is the number of clock cycles with period Tk ⁇ i and p is the period of the modulating sequence, expressed in clock cycles.
  • the procedure does not require the designer to perform any manual optimization of the circuit layout.
  • the whole method can be automated, and performed, for example, by means of an appropriate script for the description of the oscillator and for the subsequent phases.
  • the very implementation phases 4, 5, 6, 7 and verification phases 8, 9 can be performed in an automatic way by means of standard software tools, typically available in modern CAD suites for digital circuit design.
  • This embodiment defines a digitally-controlled delay line (DCDL) based on a chain of two-input multiplexers, where each multiplexer (shortly referred as mux) has a first input connected to the output of the previous mux, and on a clock tree which distributes the input signal to the second input of each mux.
  • DCDL digitally-controlled delay line
  • said clock tree works as the above high fan- out network, providing that the delay from the input of the delay line ("in") to the input of each mux is constant (to) , so the variation of the line delay is only due to the number of muxes that the input signal has to cross before reaching the output ("out"), i.e. as in a standard digital synchronous circuit.
  • the multiplexers work as delay elements, each having at least three inputs.
  • the ctrl input is synchronized with the oscillator clock in order to avoid metastability problems in the encoder.
  • the delay chain drives the injected logical value to the output without inversion, therefore the inversion from "out” to "in” is performed by a dedicated inverter.
  • the interpolation between periods is not shown.
  • DCDL architecture A specific embodiment of a DCDL architecture is herein disclosed with reference to figure 3.
  • This architecture can be profitably implemented in Field Programmable Gate Arrays (FPGA) by means of arithmetic carry propagation primitives (CPP) and clock buffers, i.e. elements which can be found in most of the modern devices.
  • CPP arithmetic carry propagation primitives
  • clock buffers i.e. elements which can be found in most of the modern devices.
  • CPP Xilinx 7-Series FPGAs
  • FIG. 3 shows a block diagram of the DCDL implemented in a Xilinx Kintex-7 325T FPGA.
  • the DCDL includes 128 elements obtained by chaining 32 CARRY4s.
  • a thermometric control encoder is implemented in the FPGA fabric in order to drive CARRY4s selection inputs.
  • the HFN is realized by simply instantiating a clock buffer (BUFR) in order to access one of the clock trees of the device.
  • BUFR clock buffer
  • the implementation flow is performed by synthesizing the HDL description of the delay line, and then by laying it out by means of APR tools.
  • the timing constraints for input and output nets and the placement constraints are passed to the placer and router. However, it is important to notice that the constraints have the only function of keeping the CARRY4s primitives adjacent to each other, and no manual editing of the layout is needed.
  • the architecture is fully digital, all the timing properties of the delay line are testable with a post- layout simulation and by means of a static timing analysis.
  • the maximum length of the line i.e. the number of needed delay taps can be easily set by the designer by means of a dedicated parameter in the HDL description. This ensures different line lengths can be easily generated without any manual effort.
  • the average propagation delay trough the multiplexers (tpd) was measured to be lips, which provided a very fine-grained delay resolution.
  • the logic footprint of the described implementation is just 94 slices (0.2% of the available) .
  • the needed clock resources are not necessarily global (BUFGs); in fact, local clock primitives (such as BUFHs or BUFRs) work very well for this purpose.
  • a medium sized FPGA such as the Xilinx Kintex-7 325T, embeds more than two hundred regional clock buffers (40 BUFRs + 168 BUFHs) and 32 global clock buffers.
  • CARRY4 primitive is used because it is the fastest available in the considered FPGA.
  • CPPs are nowadays a standard component of most FPGA families.
  • Xilinx and Altera are among the main FPGA vendors, and the present concept has been tested on Xilinx Kintex-7 devices, but it can be implemented on most of the Xilinx families, including, among the others, Ultrascale, Virtex-7, Kintex-7, Artix-7, Virtex-6, Spartan-6, Virtex-5 and Spartan-3.
  • Most recent families, such as the Ultrascale offer CPPs embedding even more multiplexers (up to 8), making the design even more compact.
  • Altera devices offer equivalent arithmetic carry propagation logic which can be exploited for the purpose, the so-called "Carry Chain” primitive.
  • Other vendors also offer similar logic resources. It is interesting to note that, according to the needed delay resolution, a designer might use alternative slower primitives (even look up tables) to implement the delay elements.
  • a demonstrator of the present invention has been implemented by means of a Xilinx Kintex-7 325T field programmable gate array (FPGA) .
  • FPGA field programmable gate array
  • a digital application specific integrated circuit (ASIC) implemented in UMC 130nm CMOS technology has been produced and it realizes the architecture of the present invention.
  • Post-layout simulations are very encouraging and the results show that, under typical conditions, it is possible to achieve a frequency range from 25 to 1400 MHz, with an LSB average of about 150ps and a DNL within the range [-7% ; 5%] .
  • the present DCO has been described under the approximation that to and t Pd are uniform through all the delay elements.
  • the response curve of the oscillator, and then its differential non-linearity (DNL) and integral non-linearity (INL) depends on the uniformity of to and t P d .
  • the measurement of the response of the oscillator allows us to obtain an estimate of t 0 (j) for each j and therefore the oscillator is an instrument for the direct measurement of the skew of the HFN.
  • a DCO of the invention can measure the skew thereof. This tool could be used for the automatic characterization skew of a HFN in digital circuits.
  • the DCO can also be used for the verification of the expected performance between post-layout simulations and actual measurement results.
  • a method may be outlined consisting of the following steps :
  • the implementation of the present DCO is easily possible on a single chip also in a large number.
  • the possibility of having a large number of oscillators in a single chip allows to build devices for the generation of electronic noise (jamming) by adding on-air or on cable modulated or non modulated carriers.
  • systems such as Bluetooth ® and Wi-fi ® operate on a channel only when there is no signal, the presence of a carrier inhibit the transmission of the data.
  • the simultaneously blinding of different channels is possible using a number of oscillators equal to the number of available channels, each one tuned to a specific frequency.
  • deleting some channels can be done by on-site systems (weak because accessible from user) or off-site system (accessible only by the provider) on the branches of the signal distribution.
  • the channel to be deleted can be trapped by notch filters but this is not cheap and not very flexible. Thanks to the implementation of this DCO it is possible to use a simultaneous jamming of each individual carriers and operate the selection of each channel from a remote station.
  • delays in clock distribution paths may change during operation, mainly due to temperature and voltage variations. These variations are typically slow with respect to the clock period, so they span many clock cycles. Therefore, clock domains operating at the same average frequency happen to slowly vary their relative phase. In this case, the system is multi-synchronous and the data crossing between clock domains must be handled. Multi-synchronous logic can be found for instance in phase-adaptive RAM access circuits and in clock data recovery blocks of high-speed SERDESes.
  • a possible solution is the use of a conflict detector, which identifies whether the relative phase of the transmitter clock (TCLK) and receiver clock (RCLK) is within a forbidden interval ([0; t a +t b ] ) .
  • the values for t a and t b depend on the application and can be determined by means of a static timing analysis. They can be even set at run time if needed, by controlling the two DCDLs shown in the block diagram.
  • the delay is changed only if the conflict detector finds a number of consecutive clock cycles with unsafe relative phases. Since the phase drift is typically slow, metastability in the conflict detector is solved with a standard synchronizer.
  • the data transfer from the TCLK to the RCLK domain is instead performed by a safe synchronizer.
  • the conflict detector detects an unsafe relative phase between TCLK and RCLK
  • the first flip flop (FF) in the safe synchronizer shifts its sampling point by means of a DCDL .
  • the clock at the FF clock input pin normally has a certain phase, i.e. DCDL set to 0, but when the conflict detector asserts the AVOID signal, the DCDL is set to t ko (keep-out time interval) in order to shift the clock to a safe phase.
  • This conflict detector can use a DCDL according to the invention for the synchronization.
  • a keep-out mechanism is similar to the one described before, could be applied when synchronizing unrelated clock domains. In this case more care is needed in order to ensure that the phase drift between the clocks is sufficiently slow to allow the conflict detector enough time to determine an unsafe condition. Being clocks periodic, if the clock frequencies are stable, it is also possible to predict such conflicts in advance.
  • the first FF of the safe synchronizer has a shiftable setup/hold timing window (and clock to output delay) . This capability can be very useful for 10 logic in digital ASICs, in order to adapt to timing constraints from/toward external logic.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne une architecture d'un oscillateur à commande numérique qui est nativement numérique et, par conséquent, non dépendante d'un processus technologique particulier pour sa fabrication, et qui comprend fondamentalement : une chaîne d'éléments de retard ayant chacun trois entrées et une sortie, une première entrée commandée par la sortie de l'élément précédent et utilisée pour la propagation dans la ligne, une deuxième entrée pour l'injection d'un signal dans la ligne et une troisième entrée ou des entrées pour la sélection du comportement de chaque élément de retard ; et un réseau de sortance élevée pour commander avec des retards équilibrés l'entrée d'injection desdits éléments de retard, ledit réseau de sortance élevée étant basé sur un arbre d'horloges qui distribue le signal d'entrée à la deuxième entrée de chaque élément de retard.
PCT/IB2015/058390 2014-11-03 2015-10-30 Architecture d'un oscillateur à commande numérique (dco) WO2016071813A2 (fr)

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CN116667796A (zh) * 2023-07-28 2023-08-29 成都世源频控技术股份有限公司 一种提高参考时钟信号抗干扰的功分放大电路及方法

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Publication number Priority date Publication date Assignee Title
CN107222210A (zh) * 2017-06-07 2017-09-29 中国电子科技集团公司第二十四研究所 一种可由spi配置数字域时钟相位的dds系统
CN116667796A (zh) * 2023-07-28 2023-08-29 成都世源频控技术股份有限公司 一种提高参考时钟信号抗干扰的功分放大电路及方法
CN116667796B (zh) * 2023-07-28 2023-10-13 成都世源频控技术股份有限公司 一种提高参考时钟信号抗干扰的功分放大电路及方法

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