WO2016061879A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2016061879A1
WO2016061879A1 PCT/CN2014/093387 CN2014093387W WO2016061879A1 WO 2016061879 A1 WO2016061879 A1 WO 2016061879A1 CN 2014093387 W CN2014093387 W CN 2014093387W WO 2016061879 A1 WO2016061879 A1 WO 2016061879A1
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WO
WIPO (PCT)
Prior art keywords
lead
leads
connection
cof
display device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/093387
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English (en)
French (fr)
Inventor
韩丙
罗时勲
王金杰
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/416,788 priority Critical patent/US20160372442A1/en
Publication of WO2016061879A1 publication Critical patent/WO2016061879A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10681—Tape Carrier Package [TCP]; Flexible sheet connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/232—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to the field of display technology, and in particular to a display device.
  • liquid crystal displays have become the most common flat panel display devices.
  • each pixel is controlled by a grid line and a data line which are criss-crossed on the substrate to realize display of an image.
  • the gate driving signal and the data signal are emitted from a control chip in the liquid crystal display, and the gate driving signal and the data signal are generally transmitted to the gate lines and the data lines on the substrate by using a chip on film (Chip On Film, COF for short). .
  • a COF is connected to a set of fanouts on the substrate through a set of bounding leads, and then connected to gate lines or data lines of the ative area.
  • a set of connecting leads includes a plurality of rectangular leads, each of which corresponds to one of the fan leads. Because the fan-lead is generally fan-shaped, the length of the wire at the ends of the fan-shaped lead is much longer than the wire in the middle of the fan-shaped lead, so the resistance of the wires at both ends is much larger than the resistance of the intermediate wire, resulting in transmission on the wires at both ends. The waveform of the gate drive signal or the data signal is severely distorted, and a color shift is generated, so that the pixels controlled by the two ends of the wires exhibit a bright spot or a dark spot, which affects the display effect of the liquid crystal display.
  • the invention provides a display device comprising a substrate and a flip chip COF, the COF being connected by a connection lead a fan-shaped lead on the substrate, the connecting lead comprising a plurality of parallel leads;
  • connection lead In the connection lead, the area of each of the leads is gradually reduced from the leads located at both ends of the connection lead to the leads located in the middle of the connection leads.
  • the lead wire is rectangular;
  • connection lead the length of each of the leads is gradually reduced from the leads located at both ends of the connection lead to the leads located in the middle of the connection leads; the widths of the respective leads are equal.
  • the COF is a COF for transmitting a data signal.
  • the COF is a COF for transmitting a gate drive signal.
  • the display device includes at least two COFs for transmitting gate driving signals, each of the COFs being connected to the sector leads on the substrate through a set of the connecting leads;
  • the average area of each lead in the former set of connecting leads is smaller than the average area of each lead in the latter set of connecting leads.
  • the number of leads in the adjacent two sets of connecting leads is n, and the area of the i-th lead in the previous set of connecting leads is smaller than the area of the i-th lead in the latter set of connecting leads;
  • the area of the lead wires located at both ends of the connecting lead is the largest, and the closer to the middle of the connecting lead, the smaller the area of the lead wire. Because the contact area between the lead and the COF is larger, the resistance of the lead is smaller, so the resistance of the lead at both ends of the connecting lead is the smallest, and the closer to the middle of the connecting lead, the larger the resistance of the lead.
  • the resistance of the wires at both ends of the fan-shaped leads is the largest, and the closer to the middle of the fan-shaped leads, the smaller the resistance of the wires.
  • the embodiment of the present invention solves the technical problem that the pixels controlled by the wires at the two ends of the fan-shaped lead are bright or dark (fanout mura) under the premise that the substrate space is limited and the structure of the fan-shaped lead is not changed. Display the display effect of the device.
  • FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention.
  • Figure 2 is a partial schematic view of the connecting lead portion of Figure 1;
  • FIG. 3 is a schematic diagram of a display device according to Embodiment 2 of the present invention.
  • Figure 4 is a partial schematic view of the connecting lead portion of Figure 3.
  • a display device provided by an embodiment of the invention includes a substrate and a flip chip (COF), and the COF is connected to a fanout on the substrate through a bounding lead.
  • the connecting lead includes a plurality of parallel leads. In the connection leads, the area of each lead is gradually reduced from the leads located at both ends of the connection leads to the leads located in the middle of the connection leads.
  • the area of the lead located at both ends of the connecting lead is the largest, and the closer to the middle of the connecting lead, the smaller the area of the lead. Because the contact area between the lead and the COF is larger, the resistance of the lead is smaller, so the resistance of the lead at both ends of the connecting lead is the smallest, and the closer to the middle of the connecting lead, the larger the resistance of the lead.
  • the resistance of the wires at both ends of the fan-shaped leads is the largest, and the closer to the middle of the fan-shaped leads, the smaller the resistance of the wires.
  • the embodiment of the present invention solves the technical problem that the pixels controlled by the wires at the two ends of the fan-shaped lead are bright or dark (fanout mura) under the premise that the substrate space is limited and the structure of the fan-shaped lead is not changed. Display the display effect of the device.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the COF in this embodiment is a COF for transmitting a data signal.
  • the COF 2 is connected to the sector lead 4 on the substrate 1 through the connection lead 3, and is connected to the respective data lines of the display region 5.
  • Connecting lead 3 A plurality of parallel leads 30 are included. In the connection lead 3, the area of each lead 30 is gradually reduced from the lead 30 located at both ends of the connection lead 3 to the lead 30 located in the middle of the connection lead 3.
  • the lead wires 30 have a rectangular shape. From the lead wires 30 located at both ends of the connection lead 3 to the lead wires 30 located at the center of the connection lead wires 3, the width of each of the lead wires 30 is gradually reduced, and the lengths of the respective lead wires 30 are equal.
  • the resistance of the lead 30 located at both ends of the connection lead 3 is the smallest, and the closer to the middle of the connection lead 3, the larger the resistance of the lead 30 is.
  • the resistance of the wires at both ends of the sector lead 4 is the largest, and the closer to the middle of the sector lead 4, the smaller the resistance of the wire.
  • the sum of the resistances of the leads 30 in the connecting leads 3 and the wires in the sector leads 4 can be made closer or even equal, so that the degree of color shift is also closer.
  • the substrate 1 has limited space and the structure of the sector lead 4 is not changed, the technical problem that the pixel controlled by the wire at the two ends of the sector lead 4 exhibits bright spots or dark spots is solved, and the display is improved.
  • the display effect of the device is improved.
  • the lead 30 also has a function of bonding and fixing the COF 2 to the substrate 1.
  • the bonding strength of the lead 30 mainly depends on the length of the lead 30, so that the length of each lead 30 is equal, so that the bonding strength of each lead 30 can be made equivalent.
  • the adhesion and fixation of COF2 on the substrate 1 is relatively uniform and stable.
  • each lead may be an oblong shape, a trapezoidal shape, or the like, as long as the resistance of the lead at both ends of the connecting lead is minimized, and the resistance of the lead is closer to the middle of the connecting lead. The bigger it is.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment is basically the same as the first embodiment except that the COF in this embodiment is a COF for transmitting a gate driving signal.
  • the COF 2 is connected to the sector lead 4 on the substrate 1 through the connection lead 3, and is connected to the respective gate lines of the display region 5.
  • the connection lead 3 includes a plurality of parallel leads 30. In the connection lead 3, the area of each lead 30 is gradually reduced from the lead 30 located at both ends of the connection lead 3 to the lead 30 located in the middle of the connection lead 3.
  • the resistance of the lead 30 located at both ends of the connection lead 3 is the smallest, and the closer to the middle of the connection lead 3, the larger the resistance of the lead 30 is.
  • the resistance of the wires at both ends of the sector lead 4 is the largest, and the closer to the middle of the sector lead 4, the smaller the resistance of the wire.
  • the sum of the resistances of the leads 30 in the connecting leads 3 and the wires in the sector leads 4 can be made closer or even equal, so that the degree of color shift is also closer.
  • the substrate 1 has limited space and the structure of the sector lead 4 is not changed, the technical problem that the pixel controlled by the wire at the two ends of the sector lead 4 exhibits bright spots or dark spots is solved, and the display is improved.
  • the display effect of the device is improved.
  • the display device usually includes at least two COFs for transmitting gate driving signals, and the adjacent two COFs are connected by a Wire On Array (WOA). Since the WOA has a certain resistance value, the waveform of the gate drive signal of the latter COF output is more serious than the previous COF distortion, especially at the junction of the two COFs, that is, the last gate line of the previous COF. The difference in waveform of the gate drive signal on the first gate line of the latter COF is particularly obvious, resulting in a weak line of the liquid crystal display, that is, a horizontal block defect (H-block), which affects the display of the liquid crystal display. effect.
  • H-block horizontal block defect
  • the embodiment of the present invention provides the following technical solutions:
  • two COFs are taken as an example.
  • two adjacent COF2s are connected by WOA6, and each COF2 is connected to the sector on the substrate 1 through a set of connecting leads 3.
  • Lead 4 Among the adjacent two sets of connecting leads, the average area of each lead 30a in the former set of connecting leads 3a is smaller than the average area of each lead 30b in the latter set of connecting leads 3b.
  • the number of leads in each set of connecting leads is generally equal.
  • the number of the leads 30 in the adjacent two sets of connection leads 3 is n
  • the area of the i-th lead in the previous set of connection leads 3a is smaller than the i-th in the latter set of connection leads 3b.
  • each lead 30b in the latter set of connection leads 3b is larger than the lead 30a at the corresponding position in the previous set of connection leads 3a, the resistance of the lead 30b in the latter set of connection leads 3b is smaller, so that The sum of the resistance of the lead 30b in the set of connecting leads 3b and the resistance of the WOA6 can be close to or even equal to the resistance of the lead 30a in the previous set of connecting leads 3a, thereby solving the horizontal block caused by the resistance of the WOA6. Poor technical problems have improved the display effect of the display device.
  • the leads in the two sets of connecting leads cannot be one-to-one, but as long as the average area of the leads in the previous set of connecting leads is smaller than that of the leads in the latter set of connecting leads
  • the average area is such that the sum of the resistance of the leads in the latter set of connecting leads and the resistance of the WOA can be close to, or even equal to, the resistance of the leads in the previous set of connecting leads.
  • Embodiment 1 and Embodiment 2 can also be implemented in combination with each other, that is, in a display device, a COF for transmitting a data signal, and a COF for transmitting a gate driving signal, both adopt the present invention.
  • a display device a COF for transmitting a data signal
  • a COF for transmitting a gate driving signal both adopt the present invention.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示装置，属于显示技术领域，解决了位于扇形引线（4）两端的导线所控制的像素呈现亮斑或暗斑（fanout mura）的技术问题。显示装置包括基板（1）和覆晶薄膜COF（2），COF（2）通过连接引线（3）连接至基板（1）上的扇形引线（4），连接引线（3）包括多条平行的引线（30）；在连接引线（3）中，从位于连接引线（3）两端的引线（30）至位于连接引线（3）中间的引线（30），各条引线（30）的面积逐渐减小。可用于液晶电视、液晶显示器等显示装置。

Description

显示装置
本申请要求享有2014年10月20日提交的名称为“显示装置”的中国专利申请CN201410557552.2的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种显示装置。
背景技术
随着显示技术的发展，液晶显示器已经成为最为常见的平板显示装置。
在液晶显示器中，由基板上纵横交错的栅线和数据线控制各个像素，以实现图像的显示。栅极驱动信号和数据信号是从液晶显示器中的控制芯片发出的，通常利用覆晶薄膜(Chip On Film，简称COF)将栅极驱动信号和数据信号分别传输至基板上的栅线和数据线。
具体的，一个COF通过一组连接引线(bounding lead)连接至基板上的一组扇形引线(fanout)，再连接至显示区域(ative area)的栅线或数据线。现有技术中，一组连接引线包括多条长方形的引线，每条引线对应扇形引线中的一条导线。因为扇形引线的整体呈扇形，位于扇形引线两端的导线的长度会比位于扇形引线中间的导线长很多，所以两端导线的阻值比中间导线的阻值大很多，导致两端导线上所传输的栅极驱动信号或数据信号的波形严重失真，产生色偏，使该两端导线所控制的像素呈现亮斑或暗斑(fanout mura)，影响了液晶显示器的显示效果。
发明内容
本发明的目的在于提供一种显示装置，以解决位于扇形引线两端的导线所控制的像素呈现亮斑或暗斑(fanout mura)的技术问题。
本发明提供一种显示装置，包括基板和覆晶薄膜COF，所述COF通过连接引线连接 至所述基板上的扇形引线，所述连接引线包括多条平行的引线；
在所述连接引线中，从位于所述连接引线两端的引线至位于所述连接引线中间的引线，各条所述引线的面积逐渐减小。
优选的，所述引线呈长方形；
在所述连接引线中，从位于所述连接引线两端的引线至位于所述连接引线中间的引线，各条所述引线的长度逐渐减小；各条所述引线的宽度相等。
可选的，所述COF为用于传输数据信号的COF。
或者，所述COF为用于传输栅极驱动信号的COF。
进一步，所述显示装置中包括至少两个用于传输栅极驱动信号的COF，每个所述COF均通过一组所述连接引线连接至所述基板上的扇形引线；
相邻的两组连接引线中，前一组连接引线中各引线的平均面积，小于后一组连接引线中各引线的平均面积。
优选的，相邻的两组连接引线中引线的数量均为n个，前一组连接引线中的第i条引线的面积，小于后一组连接引线中的第i条引线的面积；
其中，1≤i≤n。
本发明带来了以下有益效果：本发明提供的技术方案中，位于连接引线两端的引线的面积最大，越靠近连接引线中间，引线的面积越小。因为引线与COF之间的接触面积越大，引线的阻值就越小，所以位于连接引线两端的引线的阻值最小，越靠近连接引线中间，引线的阻值越大。而与连接引线相连的扇形引线中，位于扇形引线两端的导线的阻值最大，越靠近扇形引线中间，导线的阻值越小。这样，就可以使各处的连接引线中的引线与扇形引线中的导线的阻值之和更加接近，甚至相等，所以各处的色偏程度也更加接近。因此，本发明实施例在基板空间有限，且不改变扇形引线的结构的前提下，解决了位于扇形引线两端的导线所控制的像素呈现亮斑或暗斑(fanout mura)的技术问题，改善了显示装置的显示效果。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是根据本发明实施例一提供的显示装置的示意图；
图2是图1中连接引线部分的局部示意图；
图3是根据本发明实施例二提供的显示装置的示意图；
图4是图3中连接引线部分的局部示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明实施例提供的显示装置包括基板和覆晶薄膜(COF)，COF通过连接引线(bounding lead)连接至基板上的扇形引线(fanout)。连接引线包括多条平行的引线。在连接引线中，从位于连接引线两端的引线至位于连接引线中间的引线，各条引线的面积逐渐减小。
本发明实施例中，位于连接引线两端的引线的面积最大，越靠近连接引线中间，引线的面积越小。因为引线与COF之间的接触面积越大，引线的阻值就越小，所以位于连接引线两端的引线的阻值最小，越靠近连接引线中间，引线的阻值越大。而与连接引线相连的扇形引线中，位于扇形引线两端的导线的阻值最大，越靠近扇形引线中间，导线的阻值越小。这样，就可以使各处的连接引线中的引线与扇形引线中的导线的阻值之和更加接近，甚至相等，所以各处的色偏程度也更加接近。因此，本发明实施例在基板空间有限，且不改变扇形引线的结构的前提下，解决了位于扇形引线两端的导线所控制的像素呈现亮斑或暗斑(fanout mura)的技术问题，改善了显示装置的显示效果。
实施例一：
本实施例中的COF为用于传输数据信号的COF。如图1和图2所示，COF2通过连接引线3连接至基板1上的扇形引线4，再连接至显示区域5的各条数据线。连接引线3 包括多条平行的引线30。在连接引线3中，从位于连接引线3两端的引线30至位于连接引线3中间的引线30，各条引线30的面积逐渐减小。
本实施例中，引线30呈长方形，从位于连接引线3两端的引线30至位于连接引线3中间的引线30，各条引线30的宽度逐渐减小，各条引线30的长度相等。
本发明实施例中，位于连接引线3两端的引线30的阻值最小，越靠近连接引线3中间，引线30的阻值越大。而位于扇形引线4两端的导线的阻值最大，越靠近扇形引线4中间，导线的阻值越小。这样，就可以使各处的连接引线3中的引线30与扇形引线4中的导线的阻值之和更加接近，甚至相等，所以各处的色偏程度也更加接近。因此，本发明实施例在基板1空间有限，且不改变扇形引线4的结构的前提下，解决了位于扇形引线4两端的导线所控制的像素呈现亮斑或暗斑的技术问题，改善了显示装置的显示效果。
引线30还具有将COF2粘合固定在基板1上的作用，引线30的粘合力度主要取决于引线30的长度，所以每条引线30的长度相等，可以使每条引线30的粘合力度相当，使COF2在基板1上的粘合固定较为均匀、稳定。
应当说明的是，在其他实施方式中，各引线的形状也可以是长圆形、梯形等其他形状，只要满足位于连接引线两端的引线的阻值最小，越靠近连接引线中间，引线的阻值越大即可。
实施例二：
本实施例与实施例一基本相同，其不同点在于，本实施例中的COF为用于传输栅极驱动信号的COF。如图3和图4所示，COF2通过连接引线3连接至基板1上的扇形引线4，再连接至显示区域5的各条栅线。连接引线3包括多条平行的引线30。在连接引线3中，从位于连接引线3两端的引线30至位于连接引线3中间的引线30，各条引线30的面积逐渐减小。
本发明实施例中，位于连接引线3两端的引线30的阻值最小，越靠近连接引线3中间，引线30的阻值越大。而位于扇形引线4两端的导线的阻值最大，越靠近扇形引线4中间，导线的阻值越小。这样，就可以使各处的连接引线3中的引线30与扇形引线4中的导线的阻值之和更加接近，甚至相等，所以各处的色偏程度也更加接近。因此，本发明实施例在基板1空间有限，且不改变扇形引线4的结构的前提下，解决了位于扇形引线4两端的导线所控制的像素呈现亮斑或暗斑的技术问题，改善了显示装置的显示效果。
进一步，显示装置中通常包括至少两个用于传输栅极驱动信号的COF，且相邻的两个COF之间通过基板走线(Wire On Array，简称WOA)连接。由于WOA具有一定的阻值，所以后一个COF输出的栅极驱动信号的波形相比于前一个COF失真较为严重，尤其是在两个COF的交界处，也就是前一个COF的最后一条栅线与后一个COF的第一条栅线上的栅极驱动信号的波形差异特别明显，导致液晶显示器在该处出现一条弱线，即水平区块不良(H-block)，影响了液晶显示器的显示效果。
针对该技术问题，本发明实施例提供了以下技术方案：
本实施例以两个COF为例进行说明，如图3和图4所示，相邻的两个COF2之间通过WOA6连接，每个COF2均通过一组连接引线3连接至基板1上的扇形引线4。相邻的两组连接引线中，前一组连接引线3a中各引线30a的平均面积，小于后一组连接引线3b中各引线30b的平均面积。
具体的，每组连接引线中引线的数量通常是相等的。本实施例中，相邻的两组连接引线3中引线30的数量均为n个，前一组连接引线3a中的第i条引线的面积，小于后一组连接引线3b中的第i条引线的面积；其中，1≤i≤n。也就是，前一组连接引线3a中的任意一条引线30a，与后一组连接引线3b中对应位置上的引线30b相比，前者的面积均小于后者。
因为后一组连接引线3b中，每条引线30b的面积均大于前一组连接引线3a中对应位置上的引线30a，所以后一组连接引线3b中的引线30b的阻值更小，使后一组连接引线3b中引线30b的阻值与WOA6的阻值之和，能够接近于，甚至等于前一组连接引线3a中引线30a的阻值，从而解决了WOA6的阻值导致的水平区块不良的技术问题，改善了显示装置的显示效果。
如果相邻两组连接引线中的引线数量不相等，两组连接引线中的引线不能一一对应，但只要前一组连接引线中各引线的平均面积，小于后一组连接引线中各引线的平均面积，就可以使后一组连接引线中引线的阻值与WOA的阻值之和，能够接近于，甚至等于前一组连接引线中引线的阻值。
应当说明的是，上述实施例一和实施例二也可以互相结合实施，也就是在一个显示装置中，用于传输数据信号的COF，和用于传输栅极驱动信号的COF，均采用本发明实施例提供的技术方案。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (6)

  1. 一种显示装置，包括基板和覆晶薄膜COF，所述COF通过连接引线连接至所述基板上的扇形引线，其中，所述连接引线包括多条平行的引线；
    在所述连接引线中，从位于所述连接引线两端的引线至位于所述连接引线中间的引线，各条所述引线的面积逐渐减小。
  2. 如权利要求1所述的显示装置，其中，所述引线呈长方形；
    在所述连接引线中，从位于所述连接引线两端的引线至位于所述连接引线中间的引线，各条所述引线的宽度逐渐减小；各条所述引线的长度相等。
  3. 如权利要求1所述的显示装置，其中，所述COF为用于传输数据信号的COF。
  4. 如权利要求1所述的显示装置，其中，所述COF为用于传输栅极驱动信号的COF。
  5. 如权利要求4所述的显示装置，其中，所述显示装置中包括至少两个用于传输栅极驱动信号的COF，每个所述COF均通过一组所述连接引线连接至所述基板上的扇形引线；
    相邻的两组连接引线中，前一组连接引线中各引线的平均面积，小于后一组连接引线中各引线的平均面积。
  6. 如权利要求5所述的显示装置，其中，相邻的两组连接引线中引线的数量均为n个，前一组连接引线中的第i条引线的面积，小于后一组连接引线中的第i条引线的面积；
    其中，1≤i≤n。
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