WO2016056889A1

WO2016056889A1 - A successive approximation analog to digital converter and method for calibrating thereof

Info

Publication number: WO2016056889A1
Application number: PCT/MY2015/050116
Authority: WO
Inventors: Kong Yew Tan
Original assignee: Mimos Bhd
Current assignee: Mimos Bhd
Priority date: 2014-10-10
Filing date: 2015-10-08
Publication date: 2016-04-14
Anticipated expiration: 2017-04-10
Also published as: MY184557A

Abstract

A Successive Approximation Analog to Digital Converter, SA-ADC (100) and a method for calibrating thereof has been disclosed. The SA-ADC (100) includes a capacitance measurement circuit (200) which performs frequency based capacitance measurement for calibrating the SA-ADC (100). The capacitance measurement circuit (200) is connected to a Digital to Analog Convertor, DAC of SA-ADC (100) once only and thereafter the frequency based capacitance value of capacitors is repeatedly used in conversion cycles. Thus, the capacitance measurement circuit (200) improves conversion rate of conventional successive approximation analog to digital converters and eliminates the need for high accuracy DAC required in conventional SA-ADC.

Description

A SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND

METHOD FOR CALIBRATING THEREOF

FIELD OF THE INVENTION

The present invention relates to a Successive Approximation Analog to Digital Converter (SA-ADC).

BACKGROUND OF THE INVENTION

A conventional Successive Approximation Analog to Digital Converter (SA-ADC) is a type of analog-to-digital converter that uses a digital to analog converter (DAC), a successive approximation register (SAR) and a comparator to perform a binary search operation to convert an analog input into its digital representation.

The DAC block used in the SA-ADC architecture includes passive elements such as an array of capacitors with binary weighted values. The performance of these passive elements might be restricted due to capacitance mismatch resulting from deviation from original manufacturing design of these elements. This mismatch impacts the accuracy of a high resolution SA-ADC. Thereby, conventional high resolution (>10 bits) SA-ADC require calibration to compensate for mismatch in the passive elements.

Currently, the SA-ADC operates in two cycles, namely a calibration cycle and a conversion cycle. In the calibration cycle, a high accuracy calibration DAC is used along with the functional DAC of the SA-ADC to convert the passive (usually capacitor) mismatch to residual voltage by pre-charging the capacitors to be calibrated and detecting residual voltage through charge redistribution. The residual voltage is then measured to compute error voltages for each of these capacitors. The error voltage is thereafter stored in digital memory. During the normal conversion cycle to remove the mismatch, the corresponding error voltage is then subtracted from the functional DAC output according to the digital input code of the functional DAC. However, the conventional technique of calibration which is performed by measuring residual voltage requires a high accuracy calibration DAC to measure the capacitance mismatch and a digital memory or storage to store the measured voltages. Moreover, as each SA-ADC operation requires two cycles, that is the calibration cycle followed by the conversion cycle and the overhead of performing mathematical calculation i.e. subtracting the error voltage from the output of the functional DAC during the conversion cycle, there is a slowdown in the conversion rate of the ADC.

In view of the above shortcomings, there is felt a need for a calibration technique for the DAC sub-block of the SA-ADC in which use of a high accuracy DAC is eliminated and the conversion rate is also improved. SUMMARY OF THE INVENTION

In accordance with the present invention there is provided a Successive Approximation Analog to Digital Converter (SA-ADC) to convert an analog signal into its equivalent digital signal. The SA-ADC includes a Digital to Analog Converter (DAC) comprising at least one array of binary weighted capacitors, wherein each capacitor of the arrays has a top plate and bottom plate; a plurality of switches coupled to each of the binary weighted capacitors; a Successive Approximation Register (SAR) control logic to control the switches to enable the DAC to switch between a calibration cycle and a conversion cycle; a comparator coupled between the DAC and the SAR control logic; and at least one capacitance measuring circuit connected to each binary weighted capacitor in the array at a time for performing frequency based capacitance measurement for calibrating the SA-ADC.

In accordance with this invention, the SAR control logic in the calibration cycle connects the capacitance measuring circuit to the array and selects at least one capacitor at a time from the array as a capacitor-under-test, and the capacitance measuring circuit detects the frequency of the output obtained by applying a constant current to individually charge and discharge each capacitor-under-test to determine a true weight of that capacitor. Further, the SAR control logic in the conversion cycle connects the comparator to the DAC array for performing a successive approximation operation to determine preliminary conversion digital bits. Still further, the SAR control logic at the end of each conversion cycle multiplies each preliminary conversion digital bit by the true weight of its corresponding capacitor to obtain an equivalent digital signal for the corresponding analog signal.

Furthermore, the capacitance measuring circuit includes at least two current sources alternately connected for each capacitor-under-test; at least two comparators, wherein each comparator has one terminal connected to the capacitor-under-test and other terminal connected to a discrete threshold voltage; and a flip flop configured to receive the output of the two comparators, wherein the two current sources alternately charge and discharge the capacitor-under-test to facilitate detection of the frequency obtained from the output of flip flop which is set and/or reset by the two comparators.

According to this invention, a calibration cycle is only activated once either when the SA- ADC circuit is powered on or during reset. The calibration cycle precedes the conversion cycle whereby during calibration the capacitance measurement circuit(s) is activated to determine true weights for each of the capacitors and to save the determined true weights for use in the conversion cycle. Subsequent to completion of a calibration cycle normal analog to digital conversion cycle is initiated which then utilizes the saved true weights of each of the capacitors for performing the conversion.

Additional aspects, features and advantages of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of preferred embodiments of the invention in conjunction with the drawings listed below.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The present invention will be fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, wherein: FIGURE 1 is a block diagram of a self-calibrating Successive Approximation Analog to Digital Converter (SA-ADC) in accordance with this invention;

FIGURE 2 is a block diagram of an exemplary design of a DAC sub-block of the SA- ADC;

FIGURE 3 is a block diagram of a capacitance measurement circuit for calibrating a SA- ADC in accordance with this invention; and FIGURE 4 is a flowchart showing the steps involved in calibrating a SA-ADC in accordance with this invention.

DETAILED DESCRIPTION OF THE INVENTION

The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments and is not intended to represent the only form in which the embodiments may be constructed and/or utilized. The description sets forth functions and sequences for constructing the exemplary embodiments. However, it is to be understood that the same or equivalent functions and sequences may be accomplished by different embodiments that are also intended to be encompassed within the scope of this disclosure.

The shortcomings of the conventional Successive Approximation Analog to Digital Converters (SA-ADC) led the present invention to provide an apparatus and a method for calibrating a SA-ADC.

In accordance with the present invention, the proposed SA-ADC performs calibration or capacitance mismatch compensation by measuring true weight of each capacitor in the DAC sub-block of the SA-ADC. The present invention does not measure the residual voltage for capacitance mismatch compensation and hence does not require a high accuracy calibration DAC. The SA-ADC of the present invention includes a capacitance measurement circuit which facilitates in measurement of true weight of capacitors in the DAC for calibrating the SA- ADC. During the calibration cycle, the capacitor based DAC block of the SA-ADC is disconnected from its normal path and connected to the capacitance measurement circuit. The capacitance measurement circuit then determines an absolute value of the true weight for each capacitor in the DAC by performing frequency based capacitance measurement. This frequency based capacitance measurement approach involves translation of sensed capacitance values to frequencies or digital pulses using oscillator circuits present in the capacitance measurement circuit.

Further, the capacitance measurement circuit converts the measured true weight as a radix and stores it in a digital format for that particular capacitor (bit). Once the true weight of all capacitors in the binary weighted sub-DAC has been determined, the capacitance measurement circuit is disengaged and the binary weighted DAC is connected back to the comparator (normal path) of the SA-ADC.

The true weight of the capacitors is then repeatedly used in the conversion cycles, consequently improving the conversion rate. Moreover, as no mathematical calculation (e.g. subtraction) is to be done for every conversion, the rate of conversion is further improved.

The following detailed description of the embodiments will now be described in accordance with the attached drawings, either individually or in combination. The embodiment herein and the various features and advantageous details thereof are explained with reference to the non-limiting embodiment in the following description. Accordingly, the description should not be construed as limiting the scope of the embodiment herein. Referring to the accompanying drawings FIGURE 1 discloses a block diagram of the self-calibrating SA-ADC (100) in accordance with this invention. The self-calibrating SA- ADC (100) includes at least one Digital to Analog Converter (DAC), a Successive Approximation Register, SAR control logic (106), a comparator (108) and at least one capacitance measuring circuit (200).

The DAC of the SA-ADC (100) is a conventional capacitor based DAC which includes at least one array of binary weighted capacitors in one or more configurations. FIGURE 2 shows a schematic of a differential capacitor based DAC circuit configured in accordance with an embodiment of the present invention. The design of the capacitor based DAC includes a first array (102) and at least a second array (104) of binary weighted capacitors. Although, the present invention is described and depicted in the figures by a differential capacitor based DAC, the scope of the present invention is not limited to a particular type or design of the capacitor based DAC. Other types or designs of capacitor based DAC circuits and devices are within the scope of this invention.

During the conversion cycle, each of the binary weighted capacitors in the arrays (102,104) is connected to a top plate and bottom plate and is further coupled to a plurality of switches. These switches are controlled by the SAR control logic (106) to enable the DAC (102, 104) to switch between a calibration cycle and a conversion cycle.

The SAR control logic (106) also controls operation of the SA-ADC along with performing a successive approximation operation for converting an analog signal into its digital representation. The comparator (108) is coupled between the DAC (102, 104) and the SAR control logic (106) and performs the binary search operation for facilitating the successive approximation operation.

To overcome the capacitance mismatch in the DAC block of the SA-ADC, during the calibration cycle the capacitance measuring circuit (200) is connected for determining the true weight of each of the capacitors in the DAC. In accordance with this invention, the calibration cycle is activated only once initially either when the SA-ADC circuit is powered on or during reset. In the calibration cycle, the SAR control logic (106) disconnects the DAC block (102, 104) from the comparator (108) and connects it to the capacitance measuring circuit (200) via interchanging the connection of the switches coupled to the DAC (102, 104). The SAR control logic (106) connects the capacitance measurement circuit (200) to the top plate of the first array (102) and the top plate of the second array (104). The SAR control logic (106) then selects at least one capacitor at a time from the arrays (102, 104) as a capacitor-under-test. The true weight of the capacitor-under-test is then determined by using frequency based capacitance measurement technique. The frequency based approach involves translation of sensed capacitance values to frequencies or digital pulses. These pulses are further converted and stored in a digital format in a register as a radix for that particular capacitor (bit). The calibration cycle is continued in this manner until the true weight of each capacitor in the arrays (102, 104) has been determined and stored in a discrete location corresponding to that capacitor in the register. Subsequently, the capacitance measuring circuit (200) is disengaged and the DAC block (102, 104) is connected to its normal path in SA-ADC (100) and the conversion cycle is initiated. In the conversion cycle, the comparator's (108) positive input is connected to the first capacitor array (102) for receiving a positive analogue signal, a negative input connected to the second capacitor array (104) for receiving a negative analogue signal for performing a binary search on the analog inputs sampled by the DAC (102, 104). The iterative results of the binary search are used by the successive approximation register to determine preliminary conversion digital bits. At the end of a conversion cycle, an accurate digital equivalent for an input analog signal is obtained by multiplying each corresponding preliminary conversion digital bit by its equivalent true binary weight (i.e. radix). In this manner, the proposed SA-ADC (100) eliminates the need for repeatedly calibrating the DAC block and thereby improves the conversion rate.

As seen in FIGURE 2, the binary-weighted capacitor array representing the DAC consists of 2^*n weighted capacitors (CNP¹ to CNP"). The present invention measures capacitance mismatch of these weighted capacitors by determining the voltages VP and VN. In accordance with this invention, these voltages are expressed in terms of capacitor weights with error term for any mismatch. According to the present invention if correct capacitor weights are determined then an accurate digital signal equivalent to the analog input can be obtained. The basis for determining true weight for overcoming capacitance mismatch for accurate conversion is provided hereinafter. Taking mismatch into account, the actual value of each pair of capacitor can be modelled as follows: wherein, C₀ is the unit capacitor and and are the deviation factors of the

capacitor. Thus, weight of each capacitor is expressed as follows:

For a SAR ADC with n bits resolution, after n times comparison and approximation, the output voltage at node VN and VP is expressed as:

By substituting value of V_in and V_ip in equation (4) we get equation (6) as seen below:

As seen in equation (6), there is only one DC shift and the signal Vip defines the weight (w) as:

wherein, if Wi represents the correct weight, the initial signal V/p can be recovered.

Referring to FIGURE 3, which discloses a block diagram of the capacitance measuring circuit (200) for performing the frequency based capacitance measurement. The capacitance measuring circuit (200) includes at least two current sources (202, 204) alternately connected for each capacitor-under-test, wherein one current source is connected for charging the capacitor-under-test and the other current source is connected to discharge the capacitor-under-test. The charging and discharging of the capacitor-under-test is implemented using transistors which represent the controlled current sources (202, 204). The capacitance value (voltage) which is measured by charging and discharging the capacitor-under-test is input to two comparators (206, 208). The two comparators include a first comparator (206) with hysteresis and an inverting input and a second comparator (208) with hysteresis and a non-inverting input. Both the comparators (206, 208) have different reference threshold voltages (V_tr_ and V_tr+). The two comparators compare potential across the capacitor-under-test with the reference threshold voltages by alternately switching the capacitor-under-test between the two current sources (202, 204). The output terminal of the comparators (206, 208) is connected to a flip flop (210) whose state is set or reset dependent upon whether the output of the comparators is high or low. In this manner, the comparators (206, 208) convert the triangular voltage across the capacitor-under-test into a square wave of output frequency at the output of the flip flop (210):

The capacitance measuring circuit (200) of the present invention maps a capacitance range of 10 f F - 100 pF to a frequency span of 300 Hz - 3 MHz.

The output frequency (f_osc ) is used to determine absolute value (real binary weights) for each capacitor used in the sub-DAC. The absolute value is converted and stored in digital format as a radix for that particular capacitor (bit) in a register (not shown in the Figures).

TABLE 1 : Shows exemplary radix values computed by the capacitance measuring circuit (200) for each capacitor (CNP¹ to CNP").

TABLE 1 shows exemplary radix values computed for each of the capacitors of the sub- DAC. At the end of the conversion cycle the radix values (which represent the true weight of a particular capacitor) as seen in TABLE 1 are multiplied with each preliminary digital conversion bit to arrive at the correct output code for that particular conversion, as seen below:

B12 x Rx[12] 2.1320164

B10 x Rx[10j 1.9397950

B09 x Rx[09] 1.9071319

B08 x Rx[08j 1.8878457

B05 x Rx[05] 1.9601931

B03 x Rx[03j 1.8499006

B02 x Rx[02] 1.8439433

Thus, sum of the above computation gives the correct value for the digital equivalent of the analog input voltage. In the above illustration, the sum is shown in decimal form however during implementation the decimal numbers are represented in 2's complement digital logic.

In accordance with the present invention, there is provided a method for self-calibrating a Successive Approximation Analog to Digital Converter, SA-ADC (100) for converting an analog signal into a digital signal, wherein the SA-ADC includes a Digital to Analog Converter, DAC; a Successive Approximation Register, SAR control logic (106) and a comparator (108). The method as seen in FIGURE 4 comprises the following steps: connecting a capacitance measuring circuit (200) to an array of binary weighted capacitors representing the DAC, (1000); selecting at least one binary weighted capacitor from the array as a capacitor-under-test, (1002); determining a true weight of the capacitor-under-test by performing frequency based capacitance measurement, (1004); disconnecting the capacitance measuring circuit (200) if the true weight of each individual capacitor in the array has been determined, (1006); connecting the comparator (108) to the array representing the DAC, (1008); performing successive approximation operation to determine preliminary conversion digital bits, (1010); and multiplying each preliminary conversion digital bit by the true weight of its corresponding capacitor to obtain an equivalent digital signal for the particular analog input, (1012). Additionally, the step of determining a true weight of the capacitor-under-test by performing frequency based capacitance measurement includes: connecting the weighted capacitors to input terminals of two comparators of the capacitance measuring circuit (200), wherein the two comparators have different threshold voltages; applying a constant current to charge or discharge each capacitor-under-test by alternatively connecting each capacitor-under-test to at least two current sources; detecting the frequency of an output obtained from a flip flop which is set or reset by the two comparators to determine the true weight of each individual capacitor; and storing the true weight as register bits corresponding to the capacitor-under-test.

Persons skilled in the art and technology to which this invention pertains will appreciate that the capacitance measuring circuit of the present invention eliminates the need for employing a high accuracy calibration DAC or tuning capacitor for measuring residual voltage to overcome capacitor mismatch errors. Moreover, the present invention requires calibration to be done initially only once and thereafter the true value of each capacitor can be used repeatedly in normal conversion mode. Furthermore, the capacitance measuring circuit of the present invention does not slow down the conversion time as no mathematical calculation (e.g. subtraction) is to be done for every conversion.

It should be appreciated that the example apparatus represents only one functionally descriptive example of many potential implementations. Accordingly, division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and/or elements for implementing these functions would be necessarily be divided, omitted, or included in embodiments of the present invention. Unless contrary to physical possibility, the inventors envision the methods described herein: (i) may be performed in any sequence and/or in any combination; and (ii) the components of respective embodiments may be combined in any manner.

Although there have been described example embodiments of this novel invention, many variations and modifications are possible without departing from the scope of the invention. Accordingly the inventive embodiments are not limited by the specific disclosure above, but rather should be limited only by the scope of the appended claims and their legal equivalents.

Claims

CLAIMS:

1. A Successive Approximation Analog to Digital Converter, SA-ADC (100) to convert an analog signal into a digital signal, comprising:

(!) a Digital to Analog Converter, DAC comprising at least one array of binary weighted capacitors;

(ii) a plurality of switches coupled to each of the binary weighted capacitors;

(iii) a Successive Approximation Register, SAR control logic (106) to control the switches to enable the DAC to switch between a calibration cycle and a conversion cycle;

(iv)a comparator (108) coupled between the DAC and the SAR control logic (106) during the conversion cycle to perform a successive approximation operation to determine preliminary conversion digital bits for each of the binary weighted capacitors; and

characterized in that:

(v) at least one capacitance measuring circuit (200) connected to the binary weighted capacitors in the array to select at least one binary weighted capacitor at a time during the calibration cycle as a capacitor-under-test for calibrating the SA-ADC (100), wherein the capacitance measuring circuit (200) determines a true weight of a capacitor-under-test by detecting frequency of output obtained by applying a constant current to the capacitor-under-test.

2. The SA-ADC (100) as claimed in claim 1 , wherein said capacitance measuring circuit (200) includes:

(i) at least two current sources (202, 204) alternately connected for each capacitor- under-test;

(ii) at least two comparators (206, 208) with hysteresis, wherein each comparator has one input connected to the capacitor-under-test and other input connected to a discrete threshold voltage; and

(iii) a flip flop (210) configured to receive output of the two comparators (206, 208) wherein the two current sources (202, 204) alternately charge and discharge the capacitor-under-test to facilitate detection of frequency obtained from output of flip flop (210) which is set or reset by the two comparators (106, 108).

3. The SA-ADC (100) as claimed in claim 1 , wherein the calibration cycle is activated in the event that the SA-ADC (100) is powered on.

4. The SA-ADC (100) as claimed in claim 1 , wherein the calibration cycle is activated in the event that the SA-ADC (100) is reset.

5. The SA-ADC (100) as claimed in claim 1 , wherein said true weight of each capacitor- under-test is stored in a discrete location in a register.

6. The SA-ADC (100) as claimed in claim 5, wherein at the end of each conversion cycle said preliminary conversion digital bits are multiplied by said true weight of their corresponding binary weighted capacitor stored in the register to provide an equivalent digital signal for the analog signal.

7. The SA-ADC (100) as claimed in claim 1 , wherein capacitance measuring circuit (200) is disconnected by the SAR control logic (106) if the true weight of each individual capacitor in the array has been determined.

8. A method for self-calibrating a Successive Approximation Analog to Digital Converter, SA-ADC (100) for converting an analog signal into a digital signal, wherein the SA-ADC includes a Digital to Analog Converter, DAC; a Successive Approximation Register, SAR control logic (106) and a comparator (108), the method comprising the following steps:

i. connecting a capacitance measuring circuit (200) to at least one array of binary weighted capacitors representing the DAC, (1000);

ii. selecting at least one binary weighted capacitor from the array as a capacitor- under-test, (1002); Hi. determining a true weight of the capacitor-under-test by performing frequency based capacitance measurement, (1004);

iv. disconnecting the capacitance measuring circuit (200) if the true weight of each individual capacitor in the array has been determined, (1006); v. connecting the comparator (108) to the array of binary weighted capacitors representing the DAC, (1008);

vi. performing successive approximation operation to determine preliminary conversion digital bits, (1010); and

vii. multiplying each preliminary conversion digital bit by said true weight of its corresponding capacitor to obtain an equivalent digital signal for the particular analog input, (1012).

9. The method as claimed in claim 8, wherein the step of determining a true weight of the capacitor-under-test by performing frequency based capacitance measurement includes:

i. connecting each capacitor-under-test to inputs of two comparators (206, 208) of the capacitance measuring circuit (200), wherein the two comparators (206, 208) have different threshold voltages;

ii. applying a constant current to charge or discharge each capacitor-under-test by alternatively connecting each capacitor-under-test to at least two current sources;

iii. detecting the frequency of an output obtained from a flip flop (210) which is set or reset by the two comparators (206, 208) to determine the true weight of each individual capacitor; and

iv. storing said true weight as register bits corresponding to the capacitor-under- test.