CN117318714A - High-precision SAR ADC based on capacitor mismatch randomization nonlinear elimination technology - Google Patents

High-precision SAR ADC based on capacitor mismatch randomization nonlinear elimination technology Download PDF

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Publication number
CN117318714A
CN117318714A CN202311108603.9A CN202311108603A CN117318714A CN 117318714 A CN117318714 A CN 117318714A CN 202311108603 A CN202311108603 A CN 202311108603A CN 117318714 A CN117318714 A CN 117318714A
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China
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bit
capacitor
unit
sar adc
module
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沈易
范靖涵
黄安吉
李昂扬
刘术彬
丁瑞雪
朱樟明
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Hangzhou Research Institute Of Xi'an University Of Electronic Science And Technology
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Hangzhou Research Institute Of Xi'an University Of Electronic Science And Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Abstract

The invention discloses a high-precision SAR ADC based on a capacitance mismatch randomization nonlinear elimination technology, which comprises the following working processes: the sampling switch circuit module collects input signals and takes the input signals as sampling signals; each bit in the high M bit capacitor and the redundant bit capacitor are quantized respectively to obtain a binary code corresponding to the bit; the SAR logic module controls the bottom polar plate of the corresponding capacitance of the bit to switch according to the binary code corresponding to the bit; finally obtaining quantized binary codes with high M bits; the digital weight average logic module converts the binary code of the high M bit into a thermometer code, randomly points to the Z unit capacitor by using an internal DWA pointer, and selects 2 with the Z unit capacitor as the initial capacitor M The unit capacitors are switched again; and quantizing the residual bit number of the SAR ADC to obtain a complete quantized code of the SAR ADC.

Description

High-precision SAR ADC based on capacitor mismatch randomization nonlinear elimination technology
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a high-precision SAR ADC based on a capacitance mismatch randomization nonlinear elimination technology.
Background
With the rapid development of modern electronic communication technology, the demand for electronic devices such as low-power meters, portable medical imaging devices and the like is rapidly increasing. The analog-to-digital converter (ADC) is used as a bridge connecting the real analog world and the virtual digital world, and the performance of the ADC directly determines the performance of the whole electronic system. The ADC converts analog signals with continuous time and amplitude into corresponding discrete digital signals, so that the processing, storage and transmission of subsequent information are facilitated. Realizing low power consumption, high speed, high accuracy ADCs has become a major trend in current designs.
The successive approximation type analog-to-digital converter (SAR ADC) has a simple structure and lower power consumption, and along with the continuous progress of the CMOS process, the transistor size is smaller and smaller, the speed is obviously increased, and the SAR ADC gradually becomes a mainstream architecture of the middle-high precision middle-speed ADC. However, non-ideal factors of the capacitor array, such as capacitor mismatch, can have a larger influence on the linearity of the overall ADC, and become important factors that influence the SAR ADC to achieve higher accuracy.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a high-precision SAR ADC based on a capacitance mismatch randomization nonlinear cancellation technology. The technical problems to be solved by the invention are realized by the following technical scheme:
a high-precision SAR ADC based on a capacitance mismatch randomized nonlinear cancellation technique, comprising:
the system comprises a sampling switch circuit module, a CDAC array module, a comparator module, an SAR logic module and a digital weight average logic module; the CDAC array module comprises: a P-terminal capacitor array and an N-terminal capacitor array; the high-M-bit capacitor of the CDAC array module is split into: in the high M-bit capacitorThe sum unit capacitance of the weight coefficient corresponding to each bit and 1 redundant bit capacitance C M In total 2 M Each unit capacitor has a capacitance value of C M The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the weight coefficient corresponding to each bit represents the number of unit capacitors split by the bit; the SAR ADC is an N-bit SAR ADC;
the SAR ADC working process comprises the following steps:
sampling: the sampling switch circuit module samples an input signal to a top plate of the CDAC array module through a bottom plate sampling technology and outputs the input signal as a sampling signal;
a first quantization stage: the comparator module quantizes the sampling signal through each bit in the high M-bit capacitor and the redundant bit capacitor to obtain a binary code corresponding to the bit, and the SAR logic module controls a bottom polar plate of the corresponding capacitor of the bit to switch according to the binary code corresponding to the bit; if the bit is one of the high M bit capacitors, the bit corresponding capacitor is a unit capacitor obtained by splitting the bit, otherwise, the bit corresponding capacitor is the redundant bit capacitor, and finally, a quantized high M bit binary code with the bit number of M+1 is obtained and sent to the digital weight average logic module;
a second quantization stage: the digital weight average logic module converts the binary code of the high M bit into a thermometer code, randomly points to a Z-th unit capacitor by using an internal DWA pointer, and selects 2 with the Z-th unit capacitor as an initial capacitor according to the thermometer code M Switching the unit capacitors;
third quantization stage: quantizing the residual bit number of the SAR ADC to obtain a complete quantized code of the SAR ADC;
wherein, three quantization phases form a quantization period; the initial capacitor selected in the second quantization stage in the post-quantization period is re-selected according to the preset relationship.
In one embodiment of the present invention, the weight coefficient corresponding to each bit in the high M-bit capacitor is: 2 i-1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein i represents the bit number of the current bit in the high M-bit capacitor, and i is an integer between 1 and M; weights of the redundant bit capacitancesThe weight coefficient is 1.
In one embodiment of the present invention, the sampling switch circuit module samples an input signal to the top plate of the CDAC array module through a bottom plate sampling technique, and the working process of outputting the sampled signal includes:
the sampling switch circuit module connects the input signal to the bottom polar plate of the CDAC array to control the common mode voltage V CM The common mode voltage V of the top polar plate connected to the CADC array is firstly disconnected after a period of time is passed after the top polar plate is connected to the CDAC array CM At this time, the top polar plate is in a suspended state, and then the input signal of the bottom polar plate of the CADC array is disconnected and changed into the common mode voltage V CM The method comprises the steps of carrying out a first treatment on the surface of the According to the law of conservation of charge, the voltage on the top electrode plate of the CDAC becomes the reverse signal of the input signal at this time, sampling is completed, and the voltage on the top electrode plate of the CDAC is output as a sampling signal.
In one embodiment of the present invention, the comparator module quantizes the sampling signal through each bit of the high M bit capacitor and the redundant bit capacitor to obtain a binary code corresponding to the bit, and the method includes:
when the input voltage V of the positive input end of the comparator module P >Input voltage V at negative input N When the binary code corresponding to the current bit is obtained as 1;
when the input voltage V of the positive input end of the comparator module P <Input voltage V at negative input N When the binary code corresponding to the current bit is obtained to be 0;
wherein the input voltage V of the positive input end of the comparator module P The input voltage V of the negative input end is the voltage on the P end top polar plate of the CDAC N Is the voltage on the N-terminal top plate of the CDAC.
In one embodiment of the present invention, 2 is selected based on the thermometer code, wherein the Z-th unit capacitor is used as the initial capacitor M The switching of the unit capacitors comprises:
when X+Z-1 is less than or equal to 2 M When the Z-th to X+Z-1-th P terminal is singly arrangedThe bottom electrode plate of the bit capacitor is switched to GND, and the bottom electrode plates of the remaining Y P-end unit capacitors are switched to V REF The bottom polar plate of the Z-th to X+Z-1-th N-terminal unit capacitors is switched to V REF Switching bottom polar plates of the remaining Y N-terminal unit capacitors to GND; wherein, in the quantized high M-bit binary codes, the binary code of each bit is multiplied by a weight coefficient corresponding to the binary code, and the result obtained by summation is equal to the number of 1 in the thermometer code; y=2 M -X。
In one embodiment of the present invention, 2 is selected based on the thermometer code, wherein the Z-th unit capacitor is used as the initial capacitor M The unit capacitors are switched, and the method further comprises the following steps:
when X+Z-1>2 M At the time, the Z-2 th M The P end unit capacitance and the 1 st to X+Z-2 th M -1 bottom plate of the P-terminal unit capacitor is switched to GND, and the bottom plates of the remaining Y P-terminal unit capacitors are switched to V REF Z is from the th to the 2 nd M N-terminal unit capacitor and 1 st to X+Z-2 th M -1 bottom plate of N-terminal unit capacitor is switched to V REF The bottom plates of the remaining Y N-terminal unit capacitors are switched to GND.
In one embodiment of the present invention, the preset relationship includes:
the next unit capacitor of the last unit capacitor selected in the second quantization stage in the previous quantization period is the first unit capacitor selected in the second quantization stage in the next quantization period.
In one embodiment of the invention, the comparator module comprises: a pre-amplifier and a latch; the pre-amplifier is used for amplifying the differential voltage at the input end of the comparator module, and the latch latches the amplified voltage through a positive feedback structure and outputs the voltage to the SAR logic module.
The invention has the beneficial effects that:
in the scheme provided by the embodiment of the invention, the high M-bit capacitor of the CDAC array module is split through the weight coefficient to obtain the number of the unit capacitors corresponding to each bit, and after the capacitance value is the redundant bit capacitor, the high M-bit capacitor array is controlled to be switched again through the thermometer code output by the digital weight average logic module. After quantization of a large number of periods, the mismatch of each bit of weight capacitor is averaged to each quantization, so that the mismatch of each weight capacitor is randomized, the nonlinearity of an ADC system is improved, the spurious-free dynamic range of the SAR ADC is improved, and the first-order shaping of output signals is realized, so that the nonlinearity problem caused by the mismatch of high-order capacitors in a capacitor array is improved.
Drawings
Fig. 1 is a schematic diagram of a basic structure of a high-precision SAR ADC based on a capacitor mismatch randomization nonlinear cancellation technique according to an embodiment of the invention;
fig. 2 is a schematic diagram of a capacitor array and specific operation after splitting high M-bit capacitors of a high-precision SAR ADC based on a capacitor mismatch randomizing nonlinear cancellation technique according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Fig. 1 is a schematic diagram of a basic structure of a high-precision SAR ADC based on a capacitor mismatch randomization nonlinear cancellation technique according to an embodiment of the invention.
The embodiment of the invention provides a high-precision SAR ADC based on a capacitance mismatch randomization nonlinear elimination technology, which comprises the following steps:
the system comprises a sampling switch circuit module, a CDAC array module, a comparator module, an SAR logic module and a digital weight average logic module; the CDAC array module includes: a P-terminal capacitor array and an N-terminal capacitor array; the high M-bit capacitance of the CDAC array module is pre-split into: the sum unit capacitor of the weight coefficient corresponding to each bit in the high M bit capacitor and 1 redundant bit capacitor C M In total 2 M Each unit capacitor has a capacitance value of C M The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the weight coefficient corresponding to each bit represents the number of unit capacitors split by the bit; the SAR ADC is an N-bit SAR ADC;
the SAR ADC working process comprises the following steps:
sampling: the sampling switch circuit module samples an input signal to a top plate of the CDAC array module through a bottom plate sampling technology and outputs the input signal as a sampling signal;
a first quantization stage: the comparator module quantizes the sampling signal through each bit in the high M-bit capacitor and the redundant bit capacitor to obtain a binary code corresponding to the bit, and the SAR logic module controls the bottom polar plate of the corresponding capacitor of the bit to switch according to the binary code corresponding to the bit; if the bit is one of the high M bit capacitors, the bit corresponding capacitor is a unit capacitor obtained by splitting the bit, otherwise, the bit corresponding capacitor is a redundant bit capacitor, and finally, a quantized high M bit binary code with the bit number of M+1 is obtained and sent to a digital weight average logic module;
a second quantization stage: the digital weight average logic module converts the binary code with high M bits into thermometer code, the inside DWA pointer is utilized to randomly point to the Z unit capacitor, and 2 with the Z unit capacitor as the initial capacitor is selected according to the thermometer code M Switching the unit capacitors to obtain a high M-bit quantization code of the SAR ADC;
third quantization stage: quantizing the residual bit number of the SAR ADC to obtain a complete quantized code of the SAR ADC;
wherein, three quantization phases form a quantization period; the initial capacitor selected in the second quantization stage in the post-quantization period is re-selected according to the preset relationship.
The following will explain the present invention in detail.
Optionally, the comparator module includes: a pre-amplifier and a latch; the pre-amplifier amplifies the differential voltage at the input end of the comparator module, and the latch latches the amplified voltage through a positive feedback structure and outputs the voltage to the SAR logic module.
Before the SAR ADC of the embodiment of the invention works, the high M-bit capacitor of the CDAC array module is split in advance according to the weight coefficient corresponding to each bit. The capacitance value of the redundant bit capacitor in the high M bit capacitor is equal to the capacitance value of the split unit capacitor. The redundant bit capacitance also serves as a unit capacitance.
Optionally, the weight coefficient corresponding to each bit in the high M-bit capacitor is: 2 i-1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein i represents the bit number of the current bit in the high M bit capacitor, and i is an integer between 1 and M; the weight coefficient of the redundant bit capacitor is 1. Wherein, the value of i starts from M, from big to small and up to 1.
As shown in fig. 2, the high M-bit capacitors are split according to the weight coefficient corresponding to each bit, the weight coefficient is the number of unit capacitors corresponding to each split bit, and the split unit capacitors comprise redundant bit capacitors, which are 2 in total M And each.
And splitting and recombining the high M-bit capacitors of the CDAC array module through the weight coefficients to obtain unit capacitors and redundant bit capacitors corresponding to each bit, wherein each bit capacitor in the high M-bit capacitors is a weight capacitor, and the respective capacitance weight is the total number of the weight coefficients/the split unit capacitors.
The operation of the SAR ADC is described in detail below.
For sampling phase
Optionally, the sampling switch circuit module samples the input signal to the top plate of the CDAC array module through a bottom plate sampling technology, and the working process of outputting the sampled signal includes:
the sampling switch circuit module connects the input signal to the bottom polar plate of the CDAC array to control the common mode voltage V CM Connected to the top plate of the CDAC array, and after a period of time, the common-mode voltage V of the top plate connected to the CADC array is disconnected CM At this time, the top polar plate is in a suspended state, and then the input signal of the bottom polar plate of the CADC array is disconnected and changed into a common mode voltage V CM The method comprises the steps of carrying out a first treatment on the surface of the According to the law of conservation of charge, the voltage on the top plate of the CDAC becomes the inverse signal of the input signal, the sampling is completed, and the voltage on the top plate of the CDAC is output as the sampling signal.
Sampling signal V obtained by N-terminal CDAC capacitor array N ＝V CM -V IN ＝V IP . Sampling signal V obtained by P-end CDAC capacitor array P ＝V CM -V IP ＝V IN . Wherein V is IN Signal sum V at N-terminal for input signal IP The signal of the input signal at the P terminal.
For the first quantization stage
The comparator module quantizes the sampling signal through each bit in the high M-bit capacitor and the redundant bit capacitor to obtain a binary code corresponding to the bit, and the comparator module comprises:
when the input voltage V of the positive input end of the comparator module P >Input voltage V at negative input N When the binary code corresponding to the bit is obtained to be 1;
when the input voltage V of the positive input end of the comparator module P <Input voltage V at negative input N When the binary code corresponding to the bit is obtained to be 0;
wherein the input voltage V of the positive input end of the comparator module P The voltage on the P-terminal top plate of CDAC, the input voltage V of the negative input terminal N Voltage on top plate of N-terminal of CDAC . 。
After the SAR logic module obtains the binary code corresponding to the bit, the SAR logic module controls the bottom polar plate of the corresponding capacitance of the bit to switch according to the binary code corresponding to the bit; if the bit is one of the high M bit capacitors, the bit corresponding capacitor is a unit capacitor obtained by splitting the bit, otherwise, the bit corresponding capacitor is a redundant bit capacitor. The process specifically comprises the following steps:
1) When the bit is one of the high M bit capacitors:
if the binary code corresponding to the bit is 1, the SAR logic module controls the bottom plate of the P-end unit capacitor to be connected with GND and the bottom plate of the N-end unit capacitor to be connected with V in the unit capacitor obtained by splitting the bit REF ；
If the binary code corresponding to the bit is 0, the SAR logic module controls the bottom polar plate of the P-end unit capacitor to be connected with V in the unit capacitor obtained by splitting the bit REF The bottom electrode plate of the N-end unit capacitor is connected with GND.
2) When the bit is a redundant bit capacitance:
if the binary code corresponding to the bit is 1, the SAR logic module controls the bottom plate of the P-end unit capacitor to be connected with GND and the bottom plate of the N-end unit capacitor to be connected with V in the redundant bit capacitor REF ；
If the binary code corresponding to the bit is 0, the SAR logic module controls the bottom plate of the P-end unit capacitor in the redundant bit capacitor to be connected with V REF The bottom electrode plate of the N-end unit capacitor is connected with GND.
And finally obtaining quantized binary codes with M+1 digits in the M+1 digits by M+1 times of processes from the upper digits to the lower digits, and sending the binary codes to the digital weight average logic module.
In respect of the second quantization stage,
the digital weight average logic module converts the high M binary code into a thermometer code, a technique that is conventional in the art and is not described herein, see the prior art for details.
The digital weight average logic module randomly points to 2 by using an internal DWA pointer through pseudo-random codes M The Z-th unit capacitor of the unit capacitors.
Optionally, selecting 2 with the Z unit capacitor as the initial capacitor according to the thermometer code M The switching of the unit capacitors comprises:
when X+Z-1 is less than or equal to 2 M When the bottom electrode plates of the Z-th to X+Z-1-th P-terminal unit capacitors are switched to GND, the bottom electrode plates of the remaining Y P-terminal unit capacitors are switched to V REF The bottom polar plate of the Z-th to X+Z-1-th N-terminal unit capacitors is switched to V REF Switching bottom polar plates of the remaining Y N-terminal unit capacitors to GND; wherein, in the binary codes of the high M bits after X=quantization, the binary code of each bit is multiplied by the weight coefficient corresponding to the binary code, and then the result obtained by summation=the number of 1 in the thermometer code; y=2 M -X。
The Z-th unit capacitor is randomly selected as the initial capacitor in the first quantization period, and when X unit capacitors are selected for switching, X+Z-1 exceeds the number of the unit capacitors by 2 M Or after the first quantization periodThis is now the case.
Thus, alternatively, 2 is selected based on the thermometer code, with the Z-th unit capacitance as the starting capacitance M The unit capacitors are switched, and the method further comprises the following steps:
when X+Z-1>2 M At the time, the Z-2 th M The P end unit capacitance and the 1 st to X+Z-2 th M -1 bottom plate of the P-terminal unit capacitor is switched to GND, and the bottom plates of the remaining Y P-terminal unit capacitors are switched to V REF Z is from the th to the 2 nd M N-terminal unit capacitor and 1 st to X+Z-2 th M -1 bottom plate of N-terminal unit capacitor is switched to V REF The bottom plates of the remaining Y N-terminal unit capacitors are switched to GND.
Starting the serial number of the initial capacitor selected in the current period until the 2 nd M After that, the first bit is selected again until the selected unit capacitance number=x.
In respect of the third quantization stage,
third quantization stage: and quantizing the residual bit number of the SAR ADC to obtain a complete quantized code of the SAR ADC. This step is conventional in the art and is not described in detail for the sake of brevity, and reference is made to the prior art.
The three quantization phases form a quantization period; the initial capacitor selected in the second quantization stage in the post-quantization period is re-selected according to the preset relationship.
Optionally, the preset relationship includes:
the next unit capacitor of the last unit capacitor selected in the second quantization stage in the previous quantization period is the first unit capacitor selected in the second quantization stage in the next quantization period.
Through the round selection mode, after a large number of quantization periods, the mismatch of each bit of weight capacitor is averaged to each quantization, so that the mismatch of each weight capacitor is randomized, the nonlinearity of an ADC system is improved, the spurious-free dynamic range of the SAR ADC is improved, the first-order shaping of an output signal is realized, and the nonlinearity problem caused by the mismatch of high-order capacitors in a capacitor array is solved.
Example 2
For convenience of description below to employ V CM The working principle of the invention is illustrated by way of example for an 8-bit SAR ADC with base timing.
The 8-bit SAR ADC mainly comprises: sampling switch circuit, CDAC capacitor array, comparator, SAR logic and digital weight average logic module. Wherein C is 3a The high four-bit capacitor C of the CDAC capacitor array is used as the redundant bit capacitor 6 、C 5 、C 4 、C 3b And C 3a Splitting into 16 capacity values C according to binary weights of 8, 4, 2, 1 and 1 3a "unit capacitance" of (a).
The working process comprises sampling input signal via sampling switch circuit module, switching on sampling switch, connecting input signal with capacitor array top plate, and connecting capacitor array bottom plate with V CM And (3) sampling an input signal onto a top polar plate of the capacitor, then switching off a sampling switch, ending the sampling phase and starting a quantization phase. Quantization in one period is divided into three phases. The first quantization stage quantizes the first 4 bits of the SAR ADC, and if V P >V N The first binary code '1' is obtained, otherwise '0' is obtained, and the first 8 capacitance values are C after SAR logic control 3a The bottom plate of the unit capacitor is connected with VREF/GND. And continuing to conduct second bit quantization, wherein the obtained binary code controls the 9 th to 12 th unit capacitors to conduct switching, then conduct third bit quantization, the obtained binary code controls the 13 th to 14 th unit capacitors to conduct switching, then conduct fourth bit quantization, the obtained binary code controls the 15 th unit capacitor to conduct switching, finally conduct quantization of redundant bit capacitors, the obtained binary code controls the 16 th unit capacitor to conduct switching, finally conduct quantization to obtain the binary code with 5 bits and high 4 bits, firstly conduct no quantization of the rest bits, input the 5 bits of binary codes into a digital weight average logic module, and the first quantization stage is ended, and the second quantization stage is conducted.
The second quantization stage DWA algorithm specifically operates as follows: converting the binary code with 5 bits into thermometer code, and controlling the unit capacitor after splitting the high four-bit capacitor to performAnd (5) re-switching. For example: the 5-bit binary code outputted in the first quantization stage is 10110, and then 8+2+1=11 bottom plates of the unit capacitors are required to be switched to GND, and 5 bottom plates of the unit capacitors are required to be switched to V REF . The digital weight average logic module randomly points to the Z-th unit capacitor by using an internal DWA pointer, taking the 3 rd unit capacitor as an example, and controlling the P-end high-order capacitor to split by using a thermometer code, wherein 11 unit capacitors from the DWA pointer position are connected with GND, namely the 3 rd to 13 th unit capacitors are connected with GND, and the rest 5 unit capacitors are connected with V REF Of the 16 unit capacitors at the N end, the 3 rd to 13 th unit capacitors are connected with V REF The remaining 5 unit capacitors are connected to GND. Since the voltage of the top-level plate of the capacitor is not changed, no redundant capacitor switching power consumption is generated. The second quantization phase ends and a third quantization phase is performed.
And the third quantization stage is used for completing normal quantization of the residual digits, and finally obtaining the binary code corresponding to the complete 8-bit SAR ADC.
It should be noted that, during the second quantization phase of the second quantization period, the DWA pointer in the digital weight average logic module points to the 14 th unit capacitor. If the 5-bit binary code obtained in the first quantization stage is 11011, the digital weight average logic module controls the 14 th to 16 th bit and 1 st to 11 th bit unit capacitors of the 16 unit capacitors split by the P-end high-order capacitor to be connected with GND through the DWA pointer and the thermometer code, and the rest unit capacitors are connected with V REF The 14 th to 16 th unit capacitors in the 16 unit capacitors at the N end are connected with the V from the 1 st to 11 th unit capacitors REF The rest unit capacitors are connected to GND, and the DWA pointer points to the 12 th bit unit capacitor in the second quantization stage of the next period, and so on.
Because in a typical SAR ADC the weight capacitance mismatch for each bit is fixed, the mismatch after multiple quantization is still fixed. The embodiment of the invention uses a digital weight average logic algorithm, the capacitors to be split are split and recombined by calculating the actual weight coefficient, and after a large number of periods of quantization, the mismatch of each bit of weight capacitor is averaged to each quantization, so that the mismatch of each weight capacitor is randomized, and the nonlinearity of an ADC system is improved. Unlike the mapping ADC, the detection-skip algorithm is completed with only one ADC, saving the area of one coarse ADC.
It should be noted that, in the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (8)

1. A high-precision SAR ADC based on a capacitance mismatch randomization nonlinear cancellation technique, comprising:
the system comprises a sampling switch circuit module, a CDAC array module, a comparator module, an SAR logic module and a digital weight average logic module; the CDAC array module comprises: a P-terminal capacitor array and an N-terminal capacitor array; the high-M-bit capacitor of the CDAC array module is split into: the sum unit capacitor of the weight coefficient corresponding to each bit in the high M bit capacitor and 1 redundant bit capacitor C M In total 2 M Each unit capacitor has a capacitance value of C M The method comprises the steps of carrying out a first treatment on the surface of the Wherein, the weight coefficient corresponding to each bit represents the number of unit capacitors split by the bit; the SAR ADC is an N-bit SAR ADC;
the SAR ADC working process comprises the following steps:
sampling: the sampling switch circuit module samples an input signal to a top plate of the CDAC array module through a bottom plate sampling technology and outputs the input signal as a sampling signal;
a first quantization stage: the comparator module quantizes the sampling signal through each bit in the high M-bit capacitor and the redundant bit capacitor to obtain a binary code corresponding to the bit, and the SAR logic module controls a bottom polar plate of the corresponding capacitor of the bit to switch according to the binary code corresponding to the bit; if the bit is one of the high M bit capacitors, the bit corresponding capacitor is a unit capacitor obtained by splitting the bit, otherwise, the bit corresponding capacitor is the redundant bit capacitor, and finally, a quantized high M bit binary code with the bit number of M+1 is obtained and sent to the digital weight average logic module;
a second quantization stage: the digital weight average logic module converts the binary code of the high M bit into a thermometer code, randomly points to a Z-th unit capacitor by using an internal DWA pointer, and selects 2 with the Z-th unit capacitor as an initial capacitor according to the thermometer code M Switching the unit capacitors;
third quantization stage: quantizing the residual bit number of the SAR ADC to obtain a complete quantized code of the SAR ADC;
wherein, three quantization phases form a quantization period; the initial capacitor selected in the second quantization stage in the post-quantization period is re-selected according to the preset relationship.
2. The high-precision SAR ADC based on the capacitor mismatch randomization nonlinear cancellation technique of claim 1, wherein the weight coefficient corresponding to each bit in the high M-bit capacitor is: 2 i-1 The method comprises the steps of carrying out a first treatment on the surface of the Wherein i represents the bit number of the current bit in the high M-bit capacitor, and i is an integer between 1 and M; the weight coefficient of the redundant bit capacitor is 1.
3. The high-precision SAR ADC based on the capacitor mismatch randomization nonlinear cancellation technique according to claim 1, wherein the sampling switch circuit module samples the input signal to the top plate of the CDAC array module by bottom plate sampling technique, and the operation of outputting the sampled signal comprises:
the sampling switch circuit module connects the input signal to the bottom polar plate of the CDAC array to control the common mode voltage V CM The common mode voltage V of the top polar plate connected to the CADC array is firstly disconnected after a period of time is passed after the top polar plate is connected to the CDAC array CM At this time, the top polar plate is in a suspended state, and then the input signal of the bottom polar plate of the CADC array is disconnected and changed into the common mode voltage V CM The method comprises the steps of carrying out a first treatment on the surface of the According to the law of conservation of charge, the voltage on the top electrode plate of the CDAC becomes the reverse signal of the input signal at this time, sampling is completed, and the voltage on the top electrode plate of the CDAC is output as a sampling signal.
4. A high-precision SAR ADC based on a capacitor mismatch randomization nonlinear cancellation technique according to claim 3, wherein said comparator module quantizes said sampled signal with each of said high M-bit capacitor and redundant bit capacitor to obtain a binary code corresponding to that bit, comprising:
when the input voltage V of the positive input end of the comparator module P >Input voltage V at negative input N When the current position is obtainedThe corresponding binary code is 1;
when the input voltage V of the positive input end of the comparator module P <Input voltage V at negative input N When the binary code corresponding to the current bit is obtained to be 0;
wherein the input voltage V of the positive input end of the comparator module P The input voltage V of the negative input end is the voltage on the P end top polar plate of the CDAC N Is the voltage on the N-terminal top plate of the CDAC.
5. The high-precision SAR ADC based on a capacitor mismatch randomization nonlinear cancellation technique according to claim 1, wherein said selecting 2 with said Z-th unit capacitor as a starting capacitor according to said thermometer code M The switching of the unit capacitors comprises:
when X+Z-1 is less than or equal to 2 M When the bottom electrode plates of the Z-th to X+Z-1-th P-terminal unit capacitors are switched to GND, the bottom electrode plates of the remaining Y P-terminal unit capacitors are switched to V REF The bottom polar plate of the Z-th to X+Z-1-th N-terminal unit capacitors is switched to V REF Switching bottom polar plates of the remaining Y N-terminal unit capacitors to GND; wherein, in the quantized high M-bit binary codes, the binary code of each bit is multiplied by a weight coefficient corresponding to the binary code, and the result obtained by summation is equal to the number of 1 in the thermometer code; y=2 M -X。
6. The high-precision SAR ADC based on a capacitor mismatch randomization nonlinear cancellation technique according to claim 5, wherein said selecting 2 with said Z-th unit capacitor as a starting capacitor according to said thermometer code M The unit capacitors are switched, and the method further comprises the following steps:
when X+Z-1>2 M At the time, the Z-2 th M The P end unit capacitance and the 1 st to X+Z-2 th M -1 bottom plate of the P-terminal unit capacitor is switched to GND, and the bottom plates of the remaining Y P-terminal unit capacitors are switched to V REF Z is from the th to the 2 nd M N-terminal unit capacitor and 1 st to X+Z-2 th M -1NThe bottom polar plate of the end unit capacitor is switched to V REF The bottom plates of the remaining Y N-terminal unit capacitors are switched to GND.
7. The high-precision SAR ADC based on the capacitive mismatch randomized nonlinear cancellation technique according to claim 1, wherein said predetermined relationship comprises:
the next unit capacitor of the last unit capacitor selected in the second quantization stage in the previous quantization period is the first unit capacitor selected in the second quantization stage in the next quantization period.
8. The high-precision SAR ADC based on the capacitive mismatch randomized nonlinear cancellation technique according to claim 1, wherein said comparator module comprises: a pre-amplifier and a latch; the pre-amplifier is used for amplifying the differential voltage at the input end of the comparator module, and the latch latches the amplified voltage through a positive feedback structure and outputs the voltage to the SAR logic module.
CN202311108603.9A 2023-08-30 2023-08-30 High-precision SAR ADC based on capacitor mismatch randomization nonlinear elimination technology Pending CN117318714A (en)

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