TWI253235B - Background-calibrating pipelined analog-to-digital converter - Google Patents

Abstract

A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

Description

1253235 Case No.: 093107452 Revised July 5, 1994 玖, Invention Description: TECHNICAL FIELD OF THE INVENTION The present invention provides a digital electronic device, and more particularly to a pipeline analog to digital converter capable of background correction. [Prior Art] A pipeline analog-to-digital converter (hereinafter referred to as a pipelined ADC) is commonly used in video image systems, digital subscriber loops, and billions of bits. Gigabit Ethernet transceiver, or an important component in wireless communication systems. Pipeline analog to digital conversion (A/Dconversion, hereinafter referred to as A/D conversion) can achieve a good balance between power, speed, and integrated circuit chip area, so it can be used to achieve sampling frequency in the megahertz class. South resolution ADC operation. FIG. 1 is a schematic diagram of a conventional pipelined ADC. The ADC 10 in FIG. 1 includes an encoder 18 and a plurality of serially multiplying digital-to-analog converter stages (hereinafter referred to as MDAC stages) 12, 14, and 16 (the three levels may be The same, can also be different). The first MDAC stage 12 can receive a type of analog signal Vi according to a predetermined precision and output a digital code Di representing the analog signal Vi. Subsequent MDAC stages 14, 16 may output digital code D2, D3 depending on the residual signal %, V3 amplified by the first stage 12 or the second stage 14, respectively. In other words, each subsequent level digitizes the remaining value of the previous level. Therefore, the digital output Di of the first stage 12 contains the most significant bits (MSBs). As for the last level 16 digital output Dp will contain the least significant bits (LSBs). The encoder 18 is arranged to arrange the outputs D!, D2, D3 of the above-mentioned series of different stages 12, 14, 16 to generate a digital signal D 对应 corresponding to the analog signal R. I253235 Case No.: 093107452 Revised July 5, 1994 Figure 2 is a schematic diagram of a conventional technique, MDAC. The MDAC 20 shown in Figure 2 can be used as the MDAC stage 12, 14, 16 in Figure 1. The MDAC 20 includes an internal ADC 22, a digital-to-analog converter (DAC) 24, an adder 26, and an amplifier 28. Operationally, a type of analog input Vj is received from the previous stage (or Vj itself is the initial input signal), quantized via ADC 22 to produce an estimate of Vj, i.e., a digital code Dj. Next, DAC 24 produces a relative analog signal Vjda (Dj), and the adder subtracts Vi from Di (Di). The remaining value rotated by adder 26 is amplified by amplifier 28 in accordance with a gain factor & The output Vi+i of the MDAC 20 can be expressed using the following equation: (1) Thus the input of the pipelined ADC 10 in Figure 1 can be expressed as:

Gi GxG2 ... Gp] (2) where Q = Vph / (GiG2...Gp) is the quantization error during the entire a/D conversion process. Encoder 18 in Figure 1 can subtract q from V1 to derive digital output D. . It should be noted here that the 'signal generation and gain 仏· are all design parameters. In addition, the conversion characteristics of the ADC22 in the 级 line level 20 do not affect the digital output D〇. In CMOS technology applications, most A/d pipeline stages are implemented using switched-capacitor (SC) MDACs, which include components such as comparators, op amps, switches, and capacitors. . Figure 3 is a schematic diagram of a conventional radix-2 1.5-bit switched capacitor MDAC30 with conversion characteristics as shown in Figure 4. The MDAC 30 includes a comparator 32' 34, an encoder 36, a switch block 38, first and second capacitors 40, 42 (capacitance values Cf & Cs, respectively), and an operational amplifier 44. If it is in a sampie phase, when the first clock is in the high power 7 1253235 case number: 093107452, the July 5 曰 correction bit, the switch group 38 only indicates '1, the switch is off. The signal % will be sampled 'in the first and second capacitors 40, 42. Comparators 32 and 34 are used to compare V" and +〇. 25Vr and -0.225Vr, respectively, and output a digital code which can be -丨, 〇, or +1 depending on the result of the comparison. On the other hand, if it is in a hold phase, when a second clock is at a high level, only the switch is set to '2, and the switch is turned off. Therefore, during the hold phase, the output signal Vj+ Ι can be expressed as:

K-Dl (3) where 's assuming a linear capacitance 4 〇, 42 in Figure 3, and an ideal operational amplifier 44 (with infinite DC gain and zero input bias). As for the implementation, it is desirable that the capacitors 4A, 42 have the same capacitance values Cf, Cs. However, since there is a case where the capacitance value does not match (i.e., Cf is not equal to Cs), and the operational amplifier 44 has an input bias, the pipelined ADC1 must be calibrated to obtain a more accurate operation result. In the calibration, the ADC's operation speed and accuracy have different trade-offs, and it varies according to the matching characteristics between devices (such as M〇SFETs, capacitors, etc.). The accuracy of an MDAC is expressed as the input bias of the comparator and op amp, and the exact value of the capacitance ratio. In order to overcome the above trade-off between accuracy and accuracy, there are several automatic corrections (self_calibrati〇n) techniques that are summed up: out. Although corrections can be performed on the analogy domain (anal〇gd〇main), the preferred method is digital because of the cost reduction and digital circuit considerations in deep sub-micron technologies. The way to correct the work. In addition, in the digital automatic correction scheme, the original ^^1^(: necessary modification is negligible, and therefore, only a slight performance degradation effect is affected on the transmission path of the analog signal. 1253235 No.: 093107452 July 5, 1994 Revised the traditional automatic correction scheme must reconfigure the MDAC, however this will inevitably affect the normal A/D conversion. Therefore, it can withstand a little idle time ( Idle time), the calibration of the ADC will only be performed when the initial power supply is turned on. However, since the temperature of the test will change, the calibration jade that is performed when the power is turned on will lose the result. Solving this problem also produced a number of different background corrections (backgr〇und calibrati schemes that allow an ADC to continuously calibrate the internal MDAC to keep up with changes in the environment while performing normal conversions Without being affected by the reduced resolution in the background correction technique, there are many algorithms that are widely known. For example, The skip-and-fill algorithm can randomly skip the a/D period to right-weight the MDAC' and fill it in with a nonlinear internal difference (η〇ηηnear interp〇iati〇n) For the value of this algorithm, please refer to rU K. M〇〇nandB s. Song, Background digital calibration techniques for pipelined ADC s" , IEEE Trans. Circuits Syst. IL vol.44, pp. 102-109,

February 1997" and "SU·Kwak, BS· Song, and K. Bacrania, "A 15-b, 5-Msample/s low-spurious CMOS ADCM, IEEE J. Solid-State vol· 32, pp·1866-1875 , December 1997". However, in order for the interferometer to achieve better results, the bandwidth of the input signal must be limited. In addition, if a multi-bit MDAC is used in the pipeline stage, the MDAC mismatch pattern can be used to estimate the conversion errors of the MDAC in normal a/D operations. However, if you do not know the gain error message of MDAC, the above method is only applicable to the pipeline stage with high gain. Another way to implement background correction is to replace the MDAC being corrected with an additional MDAC' such as "J. M. Ingino and B. A. Wooley, "A continuously calibrated 12-b, 10-MS/s , 3.3 VA/D converter", IEEE J. Solid-State Circuits ^ vol. 33, pp. 1920-1931, December 1253235 Case No.: 093107452 July 5, 1994 Revision 1998. However, the complexity of the required analog switching scheme reduces the speed of the operation on the analog signal transmission path. Another solution is "J. Ming and SH Lewis," An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration, IEEE J. Solid-State Circuits, vol. 36, pp·1489 -1497, October 2001", which is hereby incorporated by reference, can be used to correct gain errors only when a large number of analog and digital hardware are added. Finally, a self-calibrating reversible pipeline ADC/DAC is also disclosed in the U.S. Patent No. 5,929,796. In summary, for the background correction scheme of the prior art, a feasible improvement scheme must be proposed by the nonlinear effects caused by mdac gain error, input bias, and output error in A/D conversion. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an MDAC stage, a pipelined ADC that can be background corrected, and a related method to solve the problems faced by the above-described prior art. Briefly, an MDAC stage disclosed in the present invention includes: a sub-ADC for converting a analog signal received from an input node into a digital code; an amplifier; and a first capacitor selectively coupled to The input node is coupled between the input of the amplifier and the input of the amplifier and the output of the amplifier. In addition, the MMC stage further includes a plurality of second capacitors connected in parallel, selectively connected between the input node and the input of the amplifier, and between the plurality of corresponding digital reference signals and the input of the amplifier. The 1253235 case number: 093107452 July 5, 1994 Correction The digital reference signal includes a digital signal corresponding to the digital code and a first correction signal. During a sampling phase, the first capacitor is coupled between the input node and the input of the amplifier; and the second capacitor is coupled between the input node and the input of the amplifier. The first capacitor is coupled between the input of the amplifier and the output of the amplifier during a hold phase; the second capacitor is coupled between the digital reference signal and the input of the amplifier. According to a patent application of the present invention, a pipelined ADC is disclosed comprising: a plurality of MDAC stages connected in series; and a multiplier coupled to the output of the MDAC stage of the last stage. The multiplier determines a product of the MDAC stage of the last stage multiplied by a product of a second correction signal, wherein the second correction signal corresponds to a first correction signal. There is also a low pass filter connected to the multiplier for filtering the output of the multiplier to output as it is, and an encoder for receiving the outputs of the MDAC stages to generate a digital output signal And compensating the digital output signal with the DC component. According to another patent application of the present invention, a method is disclosed, including: sampling an input analog signal in a first capacitor and a plurality of second capacitors in an MDAC stage during a sampling phase; And applying a first correction signal to the second capacitor in the gradation level; and filtering the first correction signal from the pipelined digital output. An advantage of the present invention is that by using the second capacitors and the first correction signal, the correcting operation can be performed without affecting the normal A/D conversion. Another advantage of the present invention is that the second capacitance does not cause too much additional capacitive load, so the operating speed is not reduced. The invention also has the advantage that non-linear effects are not caused by gain errors, input bias, and output errors in the conversion can be reduced more than conventional techniques. 11 1253235 Case No.: 093107452 Revised on July 5, 1994 [Embodiment] Please refer to FIG. 5 , which is a schematic diagram of an embodiment of the MDAC of the present invention. The MDAC 50 in Figure 5 is a two-base (radix-2) 1.5-bit switched capacitor MDAC. However, this is for illustrative purposes only, and the invention can be used in other types of pipeline stages ( For example, in a multi-bit operation that does not have a switched capacitor). The MDAC 50 of this embodiment includes a sub-ADC 52 for converting an input analog signal Vj into a digital code team. Sub-ADC 52 includes comparators 54, 56 and an encoder 58 for using a reference voltage Vr to produce an output of 1.5 bits (e.g., '(10), 01, or '1〇'). As for the detailed design and operation principle of the sub-ADC 52, it is well known to the skilled person, and will not be repeated here. The MDAC 5 further includes a switch group 6 〇 (containing a plurality of switches). The wire is selectively connected to the n capacitor 62. The third capacitor 64, 66, 68 is between the sub ADC 52, the input analog signal Vj, and the amplifier 7A. The second capacitors, 66, 68 are connected in parallel with each other and can share the same input and output. The switch group 6〇 can be implemented with a conventional switching element (such as a transistor), and its opening and closing is determined according to the operation stage of the MDAC 50. That is, in the sampling phase, only the switch labeled 1 in Figure 5 will be closed; in the hold phase, only the switch labeled 〇 in Figure 5 will be closed. The capacitance value of the first capacitor 62 is G, and the capacitance values of the second capacitors 64, 66, 68 are Ch, Csqα N, respectively. Note that although two second capacitors 64, (10) (10) are mentioned in the present embodiment, the present invention can actually use more than two φ, to any feasible number of capacitors. In the leg C5 wipes, the total capacitance of all of the second capacitors, 66, 68 must be substantially equal to the capacitance of the first capacitor 62, such that ·· ci +c,, 2 + · (4) As for the operation, During the sampling phase, the switch group 6 is configured such that all capacitors, materials, and 66' 68 are connected to the input intercept and sampled. Conversely, in the hold phase, the switch group 60 causes the second capacitor 64, 68 to be connected to the reference voltage % multiplied by the determined digit code D], and a selected second capacitor 66 is connected to a first correction signal. Among them, 12 Ϊ 253235 Case No.: 093107452 July 5, 1994 Correction of the first correction signal is the reference voltage Vr multiplied by a pseudo-random digital binary-valued sequence Q (pseudo-random digital binary-valued sequence). As to which of the first capacitors will receive the first correction signal, it depends on which capacitor is corrected by the system. The selection of the second capacitor to receive the first correction signal can be determined by design principles, or can be determined in a more convenient manner, since all of the second capacitors must ultimately receive the first correction signal by themselves. The sequence q will vary between +1 and 〇, or between -1 and 0, depending on whether the value of the output digit code Dj is 丨 or 丨. For its part, the Vj+1 output by MDAC50 can be expressed as: x \Vj " Vja (Dj) ^V^D^^-V^q] (5)

The true gain of the amplifier 70 is ό广 i + Cs/Cf, Ct , and the analog signal generated according to the digital code Dj is: (6) How the random signal q can be applied to the second capacitor 64, 66, 68 For background correction, see Figure 6. Figure 6 is a simplified schematic of an ADC80 with a jjDAC stage 50. When a plurality of MDAC stages 50 are serially connected to an ADC (e.g., ADC1 in Figure 1), the subsequent LSB stages can be reduced to a single whole when considering the operation of a particular stage. Therefore, the ADC 80 includes an MDAC 50; - the z-ADC 82C represents an LSB level that is reduced to one); a multiplier 89 is used to combine the output Dz with a second correction signal q, (the second correction signal q' corresponds to The first correction signal q); a low pass filter 86 for obtaining a DC component of the q, .Dz output by the multiplier 89; and an encoder 88. Generally, in operation, the random correction signal q is fed into the second capacitor 64, 66, 68 of the MDAC 50, and then removed by the encoder 88 from the Dj output from the MDAC 50 and the Dz output from the z-ADC 82. . This is mainly by selecting the random sequence q' of the waveform pattern corrected by the same as the random correction sequence q 13 : 253235 Case number: 093107452 July 5, 1994. However, q' mainly changes to + Between 1 and -1 (ie, without DC component). y MDAC50 and ADC80 can perform the mathematical operations described below, and the following description should be made to gain a deeper understanding of the present invention. 0j(csi/ct)vr in equation (5) is estimated by z^ADC, 82 in the form of quantizing Vj+i, and then low-pass filter 86 is low-passed in the digital domain^ on q'.Dz Filtering. If the signal q has an average value close to 〇 and does not have a correlation with ^, then the DC component of q'·Ι)Ζ will correspond to the gain error of z-ADC 82, where: z (7) (8) Δ/ ^-qqxG ^Lyr ^ΐ-FJ ct r 2 7 C Widely integrate the above equations (6) and (7) to obtain: τΛ^) DAD) ~G~ (9) The normal A/D operation of ADC80 is shown below: In other words, the digital output of encoder 88 is D. Is Djz, such as digital output = /) 7Z = T; (Z) y).

G (10) Jing Zhusi z-ADC 82's initial digit output packet item, ^ will depend on these two items: cut the base line =) the last two Δ / item of the towel begins to converge, the above noise" / /, to light (7), you can calculate the 1253235 case number with good accuracy: 093107452, July 2, July 5, 1994, revised the province of the province _ mathematical description 'for the sake of simplicity' =: work: These I-informed equations, however, these omitted parts should be well understood by the familiarity of the digital technology, so there is no more information here. Therefore, according to the present invention, the final output of the voltage distribution range of vj+1 can be Expressed as:

(11) Assume that the comparators 54, 56 in Figure 5 are ideal and that the input Vj is between the flavors. When the background correction device of the present invention adds the random signal q, the equation (ιι) pressure distribution surface must add the item Cs, i/Gf of the meal. Therefore, a preferred solution is to combine the second capacitors 64, 66, 68 into a smaller capacitance value Cs or to use a larger number of second capacitors. Please refer to Figure 7. Figure 7 is a schematic diagram of another embodiment of the ADC of the present invention. The side turns include a plurality of series connected MDAC stages 92, 94, 96, and these MDAC stages are identical to the aforementioned MDAC stage 50. Similar to the ADC 80, the ADC 9A in this embodiment also includes a multiplier 97, a low pass filter 98, and an encoder 1A. In addition, AI)C9〇 further includes a pseudo-random signal generator 102 for generating signals q and Q, and including a memory 1〇4 for storing the multiplier 97. The DC component of the output '. Although three MDAC stages 92, 94, and 96 are shown in the figure, it is feasible to use more or less MDACs. During the A/D conversion of the ADC 90, an external analog signal % is input to the first MDAC stage 92. The first MDAC stage 92 can generate a corresponding digital code Di and output a residual analog number V2 to a first MDAC stage 94. Such a process is repeatedly performed in accordance with the sampling and holding phases of each of the jjDAC stages 92, 94, 96, and the digits 仏, h, and Dp corresponding to the analog signal % are output to the encoder 1〇〇. As for the work for correction, the pseudo-random signal generator 1〇2 will generate the required random correction sequence^ and increment 15 1553235. Case number: 09 is 7452 July 5, 5_ positive (progressively) input to MDAC level 92 The second capacitors 64, 66, 68 (refer to FIG. 5) in 94, 96 are corrected from the MDAC of the least significant bit, and then sequentially corrected to the MDAC of the most significant bit. As for the order in which the second capacitors 64, 66, 68 receive the signal q, it is not important, however, the order of correction of the MDAC stages 92, 94, 96 from the least significant bit to the most significant bit must be followed. As for the compensation of the random first correction signal q, the pseudo random signal generator 102 can also apply the corresponding second correction signal q to the output of the last stage 96 of the ADC 90. The subsequent DC component Δ) is then generated by the low pass filter 98, and the DC component A is output to the encoder 1 and the memory 1〇4. Finally, the encoder 100 can remove the trajectory of the input random correction sequence ^ by using the data stored in the memory 104 to output the corrected digital signal D〇. Figure 8 shows a schematic diagram of the effect of extracting Δ from the white noise W in the low pass filters 86, 98 of Figures 6 and 7 under appropriate design. The low pass filters 86, 98 may be designed in a conventional manner or may be a decimal filter as long as they are compatible with the above description of the present invention. The simulation results of the background correction of the present invention will be briefly described below, and the present invention can be more clearly shown to be superior to the prior art. Referring again to Figure 6, an analog pipeline ADC is placed in the MDAC stage 50 and subsequently connected to an ideal 17-bit z-ADC82. The MDAC stage 50 has an undesirable capacitance ratio: Cs/Cf two 0.98 (i.e., 2% mismatch) and a bias voltage VGS = 0.01 Vr. The MDAC stage 50 contains four equal second capacitances (i.e., and 4). The input signal Vj is a sinusoidal signal with an amplitude of 0.5Vr and a frequency equal to about 2/5 times the sampling frequency. Before the MDAC50 has not been corrected, the signal-to-noise-and-distortion ratio (SNDR) is 43·4 dB, and the spurious-free dynamic range (SFDR) is 47. 2 dB, so the effective number of bits (ENOB) is 6.9 bits. However, after using the background correction disclosed in the present invention (with a properly designed low-pass filter 86, μ = 2^), the signal-to-noise ratio becomes 92. 7 dB, and the false signal-free dynamic response becomes 99. 6 dB, so EN0B will be 15.1 bits. As for the low-pass filter 86 different 1253235 July 5, 1994, Amendment No.: 093107452, the μ value corresponds to different transient behavior as shown in Figure 9, the smaller the _ (the better the resolution can be obtained Long (four) coffee. As for the use of - the appropriate design of the decimal wave (M = 2) as the above filter, the obtained signal-to-noise ratio will be 咫川仙, no false signal dynamic response will be 90· 2dB, EN0B will be 14.3 bits.

Figure 10 shows the variation of the signal-to-noise ratio of the analog ADC output at different input frequencies. As for the ADC, the low-pass filter and the decimal filter are respectively corrected, and the corresponding curves are 11 〇 and 112, respectively. " U Compared to the prior art, the MDAC of the present invention includes a plurality of second capacitors and provides a random correction signal to the dedicated first capacitor. The MDAC, ADC, and related methods of the present invention can perform the work of calibration and the work of A/D conversion simultaneously. In practice, the present invention only needs to make some modifications to the path of the analog signal, and does not reduce the operation speed, and can reduce the nonlinear effect caused by the capacitor mismatch, the DC bias, and the inaccurate reference voltage. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be covered by the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional pipeline-type ADC. Figure 2 is a schematic diagram of a conventional technique for the MDAC in the ADC of Figure 1. FIG. 2 is a schematic diagram of a conventional one-to-one quinary switched capacitor MDAC. Figure 4 is a schematic diagram showing the conversion characteristics of a conventional one-two base 1.5-bit switched capacitor MDAC. FIG. 5 is a schematic diagram of an embodiment of a two-base 1.5-bit switched capacitor MDAC according to the present invention. FIG. 6 is a schematic diagram of an embodiment of the pipelined MDAC of FIG. 17 1253235 Case No.: 093107452 July 5, 1994 Revision Figure 7 is a schematic diagram of an embodiment of a pipelined ADC of the present invention. Figure 8 is a schematic illustration of the effects of the low pass filter in Figures 6 and 7. Figure 9 is a schematic diagram of the transient behavior of the low pass filter design of the present invention. Figure 10 is a schematic diagram of the signal-to-noise ratio of the ADC output of the present invention at different input frequencies. Symbols of the diagram illustrate 10 pipelined analog to digital converters 12, 14, 16, 20, 30, 50, 92, 94, 96 multiplicative digits to analog converters 18, 36, 58, 88, 100 encoding is 22, 80, 90 analog to digital converter 24 digital to analog converter 26 adder 28, 70 amplifier 32, 34, 54, 56 comparator 38, 60 switch group 40, 62 first capacitor 42, 64, 66, 68 second Capacitor 44 Operational Amplifier 52 Sub-Analog to Digital Converter 82 z-Analog to Digital Converter 86, 98 Low-Passing Waver 89, 97 Multiplier 102 Pseudo-random Signal Generator 104 Memory

18

Claims (1)

1253235 Pickup, patent application scope: 】· Kind of multiplier to analog converter level (MDAC stage) in a pipeline analog to digital converter (pipelinedADC), the multiplier to analog converter level contains: An input node for receiving a analog signal; a sub-analog to a digital converter for converting the analog signal into a digital code; an amplifier; a first capacitor selectively coupled to the input node and the amplifier Between the input terminals, and between the input of the amplifier and the output of the amplifier; and a plurality of parallel second capacitors selectively coupled between the input node and the amplification rider' a plurality of digital reference signals and a predetermined (four) 胄9 input terminal; wherein the digital reference signals include a digital signal corresponding to the digital code and a first correction signal; wherein during the sampling phase, the a first capacitor is connected between the input node and an input end of the amplifier, and the two capacitors are connected in parallel to the input node and the input end of the amplifier. The first capacitor is connected between the input end of the amplifier and the output end of the amplifier is, and the second capacitor is connected in parallel between the digit reference signal and the input end of the amplifier. . 2. The multiplicative digital to analog converter stage of claim 1, wherein the sum of the φ φ two capacitors is substantially equal to the first capacitance. 3. A tube, line analog to digital converter comprising a multiplicative digital to analog converter stage as described in claim i. 4. If the application is as follows: the pipeline analog to digital converter described in item 3, which further includes: The multiplier is connected to the 4th line analog to the digital converter towel. The rounding end of the analog converter stage, the multiplier is used to determine the product of the last stage multiplied digit to the analog converter stage multiplied by a second correction signal multiplied by 19 1253235, wherein the second corrected signal system Corresponding to the first correction signal; a low pass filter connected to the multiplier for filtering the multiplier output and outputting a DC component; and an encoder 'for receiving the multiplication The digital to analog converter stage rotates and produces a digital output signal, and the digital component is used to compensate for the digital output signal. 5. The pipeline analog to digital converter of claim 4, wherein the first and the first positive signal are random number binary sequences having the same waveform. 6. The pipeline analog to digital converter of claim 4, further comprising a pseudo random number generating 'for generating the first and second correction signals. 7. The pipeline analog to digital converter of claim 4, further comprising a 5 memory for storing the DC component, wherein the encoder can perform the memory operation. 8. A method for background correction (backgr〇und calibration) of a pipeline analog to digital converter, the pipeline analog to digital converter comprising a plurality of serially multiplied digits to an analog converter stage, The method includes: sampling, at a sampling stage, an input analog signal in a multiplicative bit to a first capacitor and a plurality of second capacitors in the analog converter stage; and in a hold phase, a first correction signal is used Using the multiplier to a second capacitor in the analog converter stage; combining the pipeline analog to the last digit of the digitizer to the analog converter stage and combining a second correction signal The second correction signal corresponds to the first correction signal; and the second correction signal is filtered out from the pipeline analog to the digital output of the digital converter. 0 20 1253235 9. As claimed in the eighth item The method further includes: sequentially using the first correction signal to a corresponding multiplicative digit to an analog converter during a corresponding hold phase The second capacitor of the stage t, wherein the order is in the order of increasing the number of significant bits of the multiplicative bit to the analog converter stage 曰 10. The eighth aspect of the patent application is equal to the first capacitor. The method of claim 2, wherein the sum of the second capacitors is substantially the same as the method of claim 8, wherein the first and second digits are binary digit sequences having the same waveform. 4 positive signal system twenty one