200533081 玫、發明說明： 【發明所屬之技術領域】 本發明提供一種數位電子裝置，尤指一種可進行背景校正的管線 式類比至數位轉換器。 【先前技術】 管線式類比至數位轉換器（pipelined analog-to-digital converter，以下簡稱管線式ADC)是一種常使用於視訊影像系統、數 位用戶迴路（digital subscriber loop)、十億位元乙太網路收發機 (Gigabit Ethernet transceiver)、或者是無線通訊系統中的一種 重要元件。管線式的類比至數位轉換（A/Dconversion，以下簡稱A/D 轉換）可以在功率、速度、積體電路晶片面積上取得不錯的平衡點， 故可以用來實現取樣頻率在百萬赫茲等級的高解析度ADC運算之中。 圖一為習知技術一管線式ADC的示意圖。圖一中的ADC1〇包含有 一編碼器18，以及複數個串聯的相乘數位至類比轉換器級200533081 Description of the invention: [Technical field to which the invention belongs] The present invention provides a digital electronic device, particularly a pipeline analog-to-digital converter capable of performing background correction. [Prior technology] A pipelined analog-to-digital converter (hereinafter referred to as a pipelined ADC) is a commonly used video video system, digital subscriber loop, and a billion-bit Ethernet Gigabit Ethernet transceiver, or an important element in wireless communication systems. The pipeline analog-to-digital conversion (A / Dconversion, hereinafter referred to as A / D conversion) can achieve a good balance in power, speed, and integrated circuit chip area, so it can be used to achieve sampling frequencies in the megahertz level. High-resolution ADC operation. FIG. 1 is a schematic diagram of a conventional pipeline ADC. The ADC10 in FIG. 1 includes an encoder 18 and a plurality of serially multiplied digital-to-analog converter stages.
(multiplying digital-to-analog converter stage，以下簡稱MDAC 級）12、14、16 (這二級可以是相同的，亦可以是不同的）。第一 mdac 級12可以依據一預設的精確度（precisi〇n)，接收一類比訊號％， 並輸出代表類比訊號V!的一數位碼h。後續的MDAC級14、16可以分 別依據被第一級12或第二級14所放大的剩餘訊號（residual signal) V2、V3輸出數位碼D2、D3。換句話說，就是每一個後續的級會將前一級 的剩餘值（residue)數位化（digitize)，因此，第一級12的數位 輸出仏會包含有最有效位元（m〇st significant此，MS]gs)，至於 最後-級16的數位輸出仏則會包含有最無效位元⑴紐細他㈣ bits’LSBs)。編碼器18係用來安排上述一連串不同級12、14、16 的輸出h、D2、Ds以產生對應於類比訊號Vi的一數位訊號D〇。 200533081 、圖一係為習知技術一 MDAC的示意圖。圖二所示的MDAC2〇可用來 作為圖一中的MDAC級12、14、16。MDAC20包含有一内部的ADC22，一 數位至頒比轉換為（dighai_t〇—anai〇g c〇nverter，以下簡稱⑽。） 24 ’ 一加法為26，以及一放大器28。在操作上，一類比輸入Vj係自前 級接收得來（或是Vj本身即為最初的輸入訊號），經由ADC22進行 量化以產生Vj的估計值，即一數位碼Dj。接下來，DAC24產生一相對的 類比吼號Vjda (Dj)，而加法器則將ν』減去v/a (Dj)。加法器26所輪 出的剩餘值會透過放大器28、依據一增益因數仏進行放大。MDAC2〇的 輪出Vj+l可以使用以下方程式表示： (1) 因此，圖一中之管線式ADC1〇的輸入可以表示成 (2) G1G2 G\G2 'GP-\ 其中’ Q = Vm/ (G&2…Gp)係為整個a/D轉換過程中的量化錯誤 (quantizing error)。圖一中的編碼器18可以將％減去Q以得出數 位輸出D〇。此處需注意的是，訊號c和增益Gj皆為設計參數，另外， 管線級 20 中的 ADC22 的轉換特性（conversi〇n characteristics)並 不會對數位輸出D〇造成影響。 在CMOS技術的應用當中，大多數的A/d管線級皆是使用切換式電 容（switched-capacitor，SC) MDAC來實施，其包含有比較器、運算 放大器（opamp)、開關、以及電容等元件。圖三係為一習知技術的二 基數（radix-2) 1.5位元切換式電容mdAC30的示意圖，其轉換特性則 如圖四所示。MDAC30包含有比較器32、34，編碼器36，開關組38， 第一及第二電容40、42 (電容值分別為Cf&Cs)，以及一運算放大器 44。若處於一取樣階段（sampie pj^%)時，當一第一時脈處於高電 11 200533081 位時，開關組38中僅有標示了 T開關是關閉的，訊號％會被取樣 於第一及第二電容40、42。比較器32、34分別用來比較Vj與+0.251 及-0· 25Vr，並依據比較的結果輸出可以是-1、〇、或+1的數位碼。反 之，若處於一保持階段（hold phase)時，當一第二時脈處於高電位 時，開關組38中僅有標示了 ‘2’開關是關閉的，故於保持階段時， 輸出訊號Vj+l可以表示為： 其中，係假設圖三中具有線性的電容40、42，以及理想的運算放大器 44 (具有無限大的直流增益以及零輸入偏壓）。 至於在實作上，較理想的情形是電容4〇、42具有相同的電容值Cf、 Cs。然而，由於會有電容值不匹配的情形（即Cf不等於匕），且運算放 大器44具有輸入偏壓存在，故必須對管線式八^⑺進行校調，才能得 出更正確的運算結果。 b 在校調時，ADC的運算速度與精確度會有不同的折衷方案 (trade-off )存在，且會根據裴置（例如M〇SFET、電容等元件）間的 匹配特性而產生魏。-MDAC的精確度（accuraey)係以比較器和運 算放大器的輸入偏壓、以及電容比的精確值表示。為了要克服上述在 運算速度與精確度間的折衷，有幾種自動校正（self—calibrati〇n) 技術陸續被提出。5隹然可以在類比領域（anaiQg dQmain)上進行校正 , (deep sub-micron technologies) 中降低成本及增加數位電路的考量，健的方輯是崎位的方式進 行校正的工作。另外，在數位的自動校正方案中，原先對霞必須的 修飾變得微不足道’因此’在類比訊號的傳送路徑上僅會受到些許的 效能降低（performance degradation)的影響。 日 一 12 200533081 傳統的自動校正方案皆須對MDAC進行重新配置 (reconfiguration)，然而這勢必會影響到正常的A/D轉換。因此， 在可以，受些許閒置時間（idle time)的應用中，只有在一初始電源 =啟狀態時才會進行ADC的校正工作。但是由於電壓與溫度會產生改 變，在電源開啟時進行的校正工作稍後就都會失去效果。為了解決此 問題’亦發產出了許多不同的背景校正（backgr〇und calibrati〇n) 方案，其可以使得一 ADC持續對内部的MDAc進行校正，以跟上環境的 改變，且同時可以執行正常的轉換工作，而不會受到解析度降低的影 響。 在背景校正技術中，有很多種演算法是廣為人知的。舉例來說， 「略過-填充」（skip-and-fin)演算法可以隨機地略過A/D週期以 對MDAC進行校正’並使用非線性内差（n〇niinear 的方式填充入遺失的值，關於此一演算法請參閱rU K. M〇onandB.S. Song， Background digital calibration techniques for pipelined ADC sJ, , IEEE Trans. Circuits Syst. //, vol.44, pp. 102-109,(multiplying digital-to-analog converter stage (hereinafter referred to as MDAC stage)) 12, 14, 16 (the two stages can be the same or different). The first mdac stage 12 can receive an analog signal% and output a digital code h representing the analog signal V! According to a preset accuracy (precision). Subsequent MDAC stages 14, 16 can output digital codes D2, D3 based on the residual signals V2, V3 amplified by the first stage 12 or the second stage 14, respectively. In other words, each subsequent stage digitizes the residual value of the previous stage. Therefore, the digital output of the first stage 12 will contain the most significant bits (m0st significant this, MS] gs), as for the last-stage 16 digital output, it will contain the least significant bits (bits'LSBs). The encoder 18 is used to arrange a series of outputs h, D2, and Ds of different stages 12, 14, and 16 to generate a digital signal D0 corresponding to the analog signal Vi. 200533081, Figure 1 is a schematic diagram of the conventional technology MDAC. The MDAC20 shown in Figure 2 can be used as the MDAC stages 12, 14, 16 in Figure 1. MDAC20 includes an internal ADC22, a digital-to-analog converter (dighai_t0-anai0gconverter, hereinafter abbreviated as ⑽). 24 ′ A 26 is added, and an amplifier 28. In operation, an analog input Vj is received from the previous stage (or Vj itself is the initial input signal), and quantized by ADC22 to generate an estimated value of Vj, which is a digital code Dj. Next, the DAC 24 generates a relative analog howl Vjda (Dj), and the adder subtracts v / a (Dj) from ν ′. The residual value rounded by the adder 26 is amplified by the amplifier 28 according to a gain factor 仏. The rotation output Vj + l of MDAC2〇 can be expressed by the following equation: (1) Therefore, the input of pipeline ADC1〇 in Figure 1 can be expressed as (2) G1G2 G \ G2 'GP- \ where' Q = Vm / ( G & 2 ... Gp) is a quantizing error during the entire a / D conversion process. The encoder 18 in Figure 1 can subtract% from Q to obtain the digital output D0. It should be noted here that the signal c and the gain Gj are design parameters. In addition, the conversion characteristics of the ADC22 in the pipeline stage 20 will not affect the digital output D0. In the application of CMOS technology, most A / d pipeline stages are implemented using switched-capacitor (SC) MDACs, which include components such as comparators, opamps, switches, and capacitors. . Figure 3 is a schematic diagram of the radix-2 1.5-bit switching capacitor mdAC30 of a conventional technology, and its conversion characteristics are shown in Figure 4. The MDAC 30 includes a comparator 32, 34, an encoder 36, a switch group 38, first and second capacitors 40 and 42 (capacitance values are Cf & Cs, respectively), and an operational amplifier 44. If it is in a sampling phase (sampie pj ^%), when a first clock is at the high power 11 200533081 position, only the T switch in the switch group 38 is marked off, and the signal% will be sampled at the first and第二 Capacitors 40 and 42. The comparators 32 and 34 are respectively used to compare Vj with +0.251 and -0.25Vr, and output digital codes that can be -1, 0, or +1 according to the comparison result. Conversely, if it is in a hold phase, when a second clock is at a high potential, only the switch labeled “2” in the switch group 38 is closed. Therefore, during the hold phase, the output signal Vj + l can be expressed as: Among them, it is assumed that there are linear capacitors 40 and 42 in FIG. 3 and an ideal operational amplifier 44 (having infinite DC gain and zero input bias voltage). As for implementation, the ideal situation is that the capacitors 40 and 42 have the same capacitance values Cf and Cs. However, since there may be a case where the capacitance values do not match (that is, Cf is not equal to dagger), and the operational amplifier 44 has an input bias voltage, it is necessary to adjust the pipeline type ⑺ to obtain a more accurate operation result. b During the calibration, there will be different trade-offs between the operation speed and accuracy of the ADC, and Wei will be generated according to the matching characteristics of Pei Chi (such as MOSFET, capacitor and other components). -Accuracy of MDAC is expressed in terms of the input bias voltage of the comparator and operational amplifier, and the exact value of the capacitance ratio. In order to overcome the above trade-off between speed and accuracy, several self-calibration (self-calibration) techniques have been proposed one after another. 5 It is possible to perform corrections in the analog domain (anaiQg dQmain). (Deep sub-micron technologies) reduce the cost and increase the consideration of the digital circuit. The robust square is a correction method in a rugged manner. In addition, in the digital automatic correction scheme, the original modification of Xia has become negligible. Therefore, the analog signal transmission path will only be affected by a small amount of performance degradation. January 12 200533081 Traditional auto-calibration schemes must reconfigure MDAC, but this will inevitably affect normal A / D conversion. Therefore, in an application that can be subjected to a little idle time, the ADC calibration work will only be performed when the initial power supply is on. However, due to changes in voltage and temperature, corrections performed while the power is on will lose effect later. In order to solve this problem, many different background correction (backgrundund calibration) solutions have also been developed, which can enable an ADC to continuously correct the internal MDAc to keep up with changes in the environment, and at the same time can perform normal Conversion works without being affected by the reduced resolution. In background correction technology, there are many kinds of algorithms that are widely known. For example, the "skip-and-fin" algorithm can randomly skip the A / D period to correct the MDAC 'and use the non-linear internal difference (n0niinear) to fill the missing Value, please refer to rU K. MoonandB.S. Song, Background digital calibration techniques for pipelined ADC sJ,, IEEE Trans. Circuits Syst. //, vol.44, pp. 102-109,
February 1997」以及「S.U· Kwak, B.S. Song, and L Bacrania, “A 15-b, 5~Msample/s low-spurious CMOS ADC" , IEEE J. Solid-State Ora/iis; vol· 32，pp· 1866-1875，December 1997」。然而，為了要 使内差器可以得到較佳的結果，輸入訊號的頻寬必須收到限制。另外， 若在管線級内使用了一多位元的MDAC，可以使用MDAC的不匹配型態 (mismatch pattern)來估計在正常A/D運算中MDAC的轉換錯誤 (conversion errors)。但是，若不知道MDAC的增益錯誤訊息，則 上述的作法只適用於具有高增益的管線級之中。 還有一種可以實施背景校正的方法，就是使用一額外的MDAC取代 正在校正中的 MDAC，如「J.M· Ingino and B. A· Wooley， “A continuously calibrated 12-b， 10-MS/s， 3.3V A/D converter” ， IEEE J. Solid-State Circuits, vol. 33, pp. 1920-1931, December 13 200533081 1998」所述。然而，所需的類比切換方案的複雜度卻會降低在類比訊 號傳送路徑上的運算速度。 另一種解決方案則如「J·Ming and S.H· Lewis， “An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration, ” IEEE J. Solid-State Circuits, vol. 36, pp· 1489-1497，October 2001」所述，在此提出以供參考，僅能在增 加大量的類比及數位硬體的情形下，對增益錯誤進行校正。 最後’在美國第5, 929, 796號的專利案件中亦揭露了一種自動校 正的可逆管線 ADC/DAC (self-calibrating reversible pipeline ADC/DAC) ’在此提出以供參考。 絲上所述，對於習知技術的背景校正方案，由姐^AC之增益錯誤、 輸入偏壓、以及在A/D轉換中的輸出錯誤所造成的非線性效應，必須 提出可行的改良方案。 " ' 【發明内容】 因此本發個目的在於提供—種麗級，—種可進行背景校 正的管線式ADC，以及-種相關的方法，以解決上述習知技術所面臨的 簡單地說，本發明所揭露的一 _級包含有：一子规，將 接收自-輸人節闕-類比峨轉換成__數位碼；— ==1生，_輸入節點與該放大器輸入端二以及 數個並_二電容，轉二另包含有複 間乂及複數個相對應的數位參考訊號與該放大器輸入端之間。該 14 200533081 等數位參考訊號包含有對應於該數位碼的數位訊號以及一第一校正訊 號。於一取樣階段時，該第一電容係連接於該輸入節點與該放大器輸 入端之間；該等第二電容則並聯於該輸入節點與該放大器輸入端之 ，。於_保_段時，該第—電容係連接於紐以輸人端與該放大 器輸出端之間·’該等第二電容則並聯於該等數位參考訊號與該放大器 輸入端之間。 根據本發明一申請專利範圍，係揭露一種管線式ADC，包含有：複 數個串聯_DAC級；-乘法器，連接於最後一級級的輸出端。 該乘法器可決定出最後-級的MDAC級的輸出乘上一第二校正訊號的一 乘?、，其中該第二校正訊號係對應於一第一校正訊號。還有一低通;慮 · ，器連接於該乘法ϋ，用來對該乘法器的輸出進行渡波，以輸出一直 /瓜，^，以及一編碼益，用來接收該等Mdac級的輸出，產生一數位輸 出Λ號，並以s亥直流成分對該數位輸出訊號進行補償。 根據本發明另_巾請專利範圍，係揭露_種方法，包含有：於一 段’將—輸人類比訊棘胁—聽級中的—第—電容以及複 中沾-:電’於—麟階段，將—第—校正訊號制於該MDAC級 出中電容上；以及將該第—校正訊號自該管線式ADC的數位輸 本^的—個優點在於，藉由制該等第二電容以及該第一校正 减，可財不辟正常的A/D轉換的情形τ，進行校正的工作。 電容ΪΓΓ另—個優點在於，該等第二電容並不會造成太多額外的 電負载（capacitive load)，故運算速度並不會因而降低。 輸入偏壓而造成 降低。 本發明還有一個優點，就是不會因為 非、__，職⑽織可 15 200533081 【實施方式】 請參閱圖五，圖五為本發明之MDAC的一實施例示意圖。圖五中的 MDAC 50係為二基數（radix-2) 1_ 5位元切換式電容MDAC，然而，這 僅用做舉例說明，本發明亦可以使用在其他種類的管線級（pipeUne stage)之中（例如不具有切換式電容的多位元運算之中）。 本實施例的MDAC50包含有一子ADC52，用來將一輸入類比訊號％ 轉換成一數位碼Dj。子ADC52包含有比較器54、56以及一編碼器58， 可用來使用一參考電壓Vr以產生丨· 5位元的輸出（例如、 01 、或10 )。至於子ADC52詳細的設計及運算原理則是習知 技，者所熟知的，在此不多做贅述。MDAC50另包含有一開關組6〇 (内 含複數個開關），用來選擇性地連接一第一電容62，第二電容64、66、 68於子ADC52、輸入類比訊號Vj、以及放大器7〇之間。第二電容料、 66、68係相互並聯，且可以共用相同的輸入與輸出。開關組6〇可以以 傳統的開關元件（如電晶體）來實施，至於其開啟與關閉則是依據 MDAC50的操作階段決定。亦即，於一取樣階段時，圖五中僅有標示 了，1’的開關會是關閉的；於一保持階段時，圖五中則僅有標示 了，〇’的開關會是關閉的。第一電容62的電容值為G，第二電容64、 66、68的電容值則分別為^l、Cs，N。請注意，雖然在本實施例 中只提到了三㈣二電容64、66、68，然而本發明實際上可以使用雨 個以上，至任何可行數目的電容。在MDAC50中，所有的第二電容料、 66、68的總電容值必須實質上等於第一電容62的電容值，使得： + (4) 至於在操作上，於取樣階段，開關組60係使得所有的電容肋、64、 66、68皆連接於輸入訊號％並對其進行取樣。相反的，於保持階段， 開關組60則使得第二電容64、68連接至參考電壓％乘上決定^數 位碼认，至於一個選定的第二電容66則連接至一第一校正訊號，其中 16 200533081 該第一校正訊號係為參考電壓Vr乘上一偽隨機數位二元序列q (pseudo-random digital binary-valued sequence)。至於是哪一 個第二電容會接收到該第一校正訊號則視系統在對哪一個電容進行校 正所決定。選擇那個第二電容來接收第―校正訊號可以以設計的原^ 所决疋，抑或可以以較為方便的方式決定，因為所有的第二電容最終 都必須獨自接收该第一校正訊號。序列q會在與〇之間變動、或是 在1兵0之間、义動，這疋依據輸出數位碼认的值是1或—1所決定。就 其本身而論’ MDAC50所輸出的vH1可以表示為：February 1997 "and" SU · Kwak, BS Song, and L Bacrania, "A 15-b, 5 ~ Msample / s low-spurious CMOS ADC ", IEEE J. Solid-State Ora / iis; vol · 32, pp · 1866-1875, December 1997. " However, in order to get better results from the internal difference, the bandwidth of the input signal must be limited. In addition, if a multi-bit MDAC is used in the pipeline stage, the MDAC mismatch pattern can be used to estimate MDAC conversion errors in normal A / D operations. However, if you do not know the MDAC gain error message, the above method is only applicable to pipeline stages with high gain. Another way to implement background correction is to replace the MDAC being corrected with an additional MDAC, such as "JM · Ingino and B. A · Wooley," A continuously calibrated 12-b, 10-MS / s, 3.3 VA / D converter ", IEEE J. Solid-State Circuits, vol. 33, pp. 1920-1931, December 13 200533081 1998". However, the complexity of the required analog switching scheme will reduce the operation speed on the analog signal transmission path. Another solution is "J · Ming and SH · Lewis," An 8-bit 80-Msample / s pipelined analog-to-digital converter with background calibration, "IEEE J. Solid-State Circuits, vol. 36, pp · 1489-1497, October 2001 ", which is proposed here for reference, and only when a large number of analog and digital hardware are added, the gain error can be corrected. Finally, a self-calibrating reversible pipeline ADC / DAC (Auto-calibrating reversible pipeline ADC / DAC) is also disclosed in US Patent No. 5,929,796, which is hereby incorporated by reference. As mentioned above, for the background correction scheme of the conventional technology, the non-linear effects caused by the gain error of the AC, the input bias, and the output error in the A / D conversion must be put forward a feasible improvement scheme. " 'Summary of the Invention' Therefore, the purpose of the present invention is to provide-a beautiful class,-a pipeline ADC that can perform background correction, and-a related method, in order to solve the above-mentioned conventional technology, simply, The first stage disclosed in the present invention includes: a sub-rule that converts the received from-input festival 阙 analogy into __ digital code;-== 1 students, _ input node and the amplifier input two and several The parallel and two capacitors, the second and the third capacitors, further include a complex circuit and a plurality of corresponding digital reference signals and the input terminal of the amplifier. The 14 200533081 and other digital reference signals include a digital signal corresponding to the digital code and a first calibration signal. During a sampling phase, the first capacitor is connected between the input node and the amplifier input; the second capacitors are connected in parallel between the input node and the amplifier input. During the _guaranteed period, the first capacitor is connected between the input terminal of New York and the amplifier output terminal. The second capacitors are connected in parallel between the digital reference signal and the input terminal of the amplifier. According to the scope of a patent application of the present invention, a pipeline ADC is disclosed, comprising: a plurality of series-DAC stages; and a multiplier connected to the output terminal of the last stage. The multiplier can determine the output of the last-stage MDAC stage multiplied by a multiplier of a second correction signal, where the second correction signal corresponds to a first correction signal. There is also a low-pass filter, which is connected to the multiplier 用来 and is used to cross the output of the multiplier to output a constant / melon, and a coding benefit, which is used to receive the output of these Mdac stages to produce A digital output Λ number, and the digital output signal is compensated by the sine DC component. According to the present invention, the scope of patent claims is to disclose a method, which includes: in a paragraph of "will-lose humans than information threat-hearing level-the first-capacitor and complex in the-: electricity" Yu-Lin Phase, the first correction signal is controlled on the MDAC output capacitor; and the first correction signal is transmitted from the digital input of the pipeline ADC. One advantage is that by making the second capacitors and This first correction is subtracted, so that the normal A / D conversion situation τ can be avoided, and the correction work can be performed. Another advantage of the capacitors ΪΓΓ is that the second capacitors will not cause too much additional capacitive load, so the operation speed will not be reduced accordingly. Input bias causes a reduction. Another advantage of the present invention is that it is not because of non-, __, vocational and technical cooperation. 15 200533081 [Embodiment] Please refer to FIG. 5. FIG. 5 is a schematic diagram of an MDAC according to an embodiment of the present invention. The MDAC 50 shown in Figure 5 is a two-radix (radix-2) 1- to 5-bit switched capacitor MDAC. However, this is only used as an example, and the present invention can also be used in other types of pipeline stages. (Such as in multi-bit operations without switched capacitors). The MDAC 50 of this embodiment includes a sub-ADC 52 for converting an input analog signal% into a digital code Dj. The sub-ADC 52 includes comparators 54, 56 and an encoder 58, which can be used to generate a 5-bit output (eg, 01, or 10) using a reference voltage Vr. As for the detailed design and operation principle of the sub-ADC52, it is well-known technology, and those who are familiar with it will not go into details here. The MDAC50 also includes a switch group 60 (containing a plurality of switches) for selectively connecting a first capacitor 62, second capacitors 64, 66, 68 to the sub-ADC 52, the input analog signal Vj, and the amplifier 70. between. The second capacitors 66 and 68 are connected in parallel with each other and can share the same input and output. The switch group 60 can be implemented with a traditional switching element (such as a transistor), and its opening and closing are determined according to the operating stage of the MDAC50. That is, during a sampling phase, only the switch labeled 1 'will be closed in Fig. 5; during a hold phase, only the switch labeled' 0 'will be closed, and the switch' 0 'will be closed. The capacitance value of the first capacitor 62 is G, and the capacitance values of the second capacitors 64, 66, 68 are ^ 1, Cs, N, respectively. Please note that although only three or two capacitors 64, 66, 68 are mentioned in this embodiment, the present invention can actually use more than one capacitor to any feasible number of capacitors. In MDAC50, the total capacitance of all the second capacitors 66, 68 must be substantially equal to the capacitance of the first capacitor 62, so that: (4) As for operation, during the sampling phase, the switch group 60 is such that All capacitor ribs, 64, 66, 68 are connected to the input signal% and sampled. Conversely, during the holding phase, the switch group 60 causes the second capacitors 64 and 68 to be connected to the reference voltage% multiplied by the decision code, and a selected second capacitor 66 is connected to a first correction signal, of which 16 200533081 The first correction signal is a reference voltage Vr multiplied by a pseudo-random digital binary-valued sequence q. As for which second capacitor will receive the first correction signal, it depends on which capacitor the system is correcting. Which second capacitor is selected to receive the first correction signal can be determined by the original design, or can be determined in a more convenient way, because all the second capacitors must ultimately receive the first correction signal alone. The sequence q will change between 0 and 0, or between 1 soldier and 0, which will be determined by the value recognized by the output digital code as 1 or -1. For its part, vH1 output by MDAC50 can be expressed as:
Vj.i-Gjx + 1 (5) i c, 其中放大H 70真正的增益係為0j=1+Cs/Cf Ct =Cs+Cf，依據數位瑪认 所產生的類比訊號則為： (6) 乂至於隨機訊號q可以如何應用在第二電容64、66、68上以進行背 景校正則請參閱圖六。圖六為_ AD⑽的簡單示意圖，包含有一舰c =50。當複數個_c級5〇串連成為一 ADC時（例如圖一中的仙⑽）， §考慮一特定級的運作時，後續❸LSB級可以簡化為-個單-的整體。 =此A^C8〇包含有一敝5〇; 一 z—侧2(代表了簡化為一的⑽級）； 一乘法器89’用來合成Z’C82所輸出的匕與一第二校正訊號q，（第 訊號q’係對應於第—校正訊?細）；_低通濾波器86，用來得 出乘法器89所輸出q，.Dz的直流成分；以及—編碼器犯。 又來祝’在操作時，隨機校正訊號q係被送人腿c5〇的第二電 二4、66、68中，然後被編碼器88從·5〇所輸出的D以及z—刪2 剧出的Dz巾移除。$主要是藉由獅出與隨機校正序列卩具有相同 17 200533081 的波形型態（wavef〇rm pattern)的隨機序列q’ ，然而，q’主要變 動於+1與-1之間（亦即不具有直流成分）。 ^ MDAC50與ADC80可執行以下所述的數學運算，看過以下的的描述 後應可對本發明有更深的瞭解。方程式（5)中的系藉由 z-ADC，82以量化乂川的方式估計得出，然後低通濾波器86於數位^域 上對q ·Ι)ζ進行低通濾波。若訊號q’具有接近於〇的平均值，且與 V]不具有相關性存在’則q’ ·])ζ的直流成分就會以2)δ==Άζ/(^的方式 對應於z-ADC 82的增益錯誤，其中： ζ 2 工 (7) 綜合上述的方程式（6)和（7)可以得出 (8) 然後’在方程式（8)中，對應於所有Dj值的6jV广(Dj)皆得出之後， 所需的結果Tj (Dj)就會如以下方程式所示·· W.) ρ2Φ}) G, (9) 係為Djz ’如 對於ADC80正常的A/D運算而言，編碼器88的數位輸出D〇 下所示： 數位輸出Vj.i-Gjx + 1 (5) ic, where the real gain of the amplified H 70 is 0j = 1 + Cs / Cf Ct = Cs + Cf, according to the digital signal generated by the analog signal: (6) 乂As for how the random signal q can be applied to the second capacitors 64, 66, 68 for background correction, please refer to FIG. Figure 6 is a simple schematic diagram of _ AD⑽, including a ship c = 50. When multiple _c stages 50 are connected in series to form an ADC (such as the fairy in Figure 1), § considering the operation of a specific stage, the subsequent ❸LSB stage can be reduced to a single unit. = This A ^ C8〇 contains a 敝 50; a z-side 2 (representing a ⑽ simplified to one); a multiplier 89 'used to synthesize the dagger output by Z'C82 and a second correction signal q , (The signal q ′ corresponds to the first correction signal); a low-pass filter 86, which is used to obtain the DC component of q, .Dz output by the multiplier 89; and the encoder commits. Let ’s wish again ”During operation, the random correction signal q is sent to the second electric cell 4, 66, 68 of the leg c50, and then the D and z output from the encoder 88 from · 50 are deleted. Remove the Dz towel. The $ is mainly a random sequence q 'with the same wave pattern of 17 200533081 as the random correction sequence 卩. However, q' mainly changes between +1 and -1 (that is, not With DC component). ^ MDAC50 and ADC80 can perform the mathematical operations described below. After reading the following description, you should have a deeper understanding of the present invention. The system in equation (5) is estimated by z-ADC, 82 in a quantized way, and then a low-pass filter 86 performs low-pass filtering on q · 1) ζ over the digital domain. If the signal q 'has an average value close to 0, and there is no correlation with V], then the DC component of q' ·]) ζ will correspond to z- in the manner of 2) δ == Άζ / (^ The gain of ADC 82 is wrong, where: ζ 2 ((7) The above equations (6) and (7) are combined to get (8). Then in equation (8), 6jV wide (Dj) corresponding to all Dj values ) Are obtained, the required result Tj (Dj) will be as shown in the following equation ... W.) ρ2Φ}) G, (9) is Djz 'For normal ADC operation of ADC80, Digital output D0 of encoder 88 is shown below: Digital output
D G (10) 凊注意z-ADG 82的初始數位輸出Dz包含有方料 ^ 項次，Dz必須減掉這兩個項次以對〜進行計算。只要、，後兩個 '項次開始收斂’上述兩個噪音項次就可以以不錯的精‘度 18 200533081 示成： 故依據本發明，最終輪出之Vw的碰分佈範圍可以表 (C」—+Cf C. \ (11) 4Cf cf 假设圖五中的比較ϋ 54、56是理想的且輸人的I係介於抓。冬 本發明的背景校正裝置將隨機訊號q加入v川時，方程式⑴）中: 壓分佈範圍必須加入額外的項次Cs，i/Cf。因此，較佳的方綠選擇^ 第二電容64、66、68組合成較小的電容值Cs，或是使用較多數 二電容。 弟 請參閱圖七。圖七為本發明ADC的另一實施例示意圖。ADC90包含 有複數個串聯的MDAC級92、94、96，而這些腿C級皆相同於前述的 MDAC級50。相似於ADC80，本實施例中的ADC90亦包含有一乘法器97， 一低通濾波器98，以及一編碼器1〇〇。除此之外，ADC90另包含有一偽 隨機訊號產生器（pseudo-random signal generator) 102，用來產生 sfL號q、Q ’以及包含有一心丨思體104 ’用來儲存乘法器97所輸出 的直流成分。雖然在圖中顯示了三個MDAC級92、94、96，但實施上更 多或更少的MDAC及皆是可行的作法。 於ADC90的A/D轉換過程中，一外部的類比訊號Vi係被輸入至第 一 MDAC級92。第一 MDAC級92可產生一相對應的數位碼Di，並輸出一 剩餘類比訊號V2至第二MDAC級94。這樣的過程會依據每一個MDAC級 92、94、96的取樣及保持階段重複地執行，對應於類比訊號W的數位 碼D!、D2、Dp則被輸出至編碼器100。至於為了進行校正的工作，偽隨 機訊號產生器102會產生所需的隨機校正序列q並遞增地 19 200533081 fi(/rie=ly)輪入至MDAC 級92、94、96 内的第二電容64、66、 “考圖五），從最無效位元的MDACS校正起，然後依序校正 為止。至於第二電容64、66、__ _序 則疋不重要的，然而，MDAC級92、94、96從最I效位 位元的校，賴是必賴漏。至㈣賴第_校正棘q == 方面，偽隨機《產生II⑽亦可轉相對應的第二校正訊號應用 在ADC9G的最後-級96的輸出上。再由低通紐98產生後續的直 流成分/)△，並將直流成分&輸出至編碼器1〇〇以及記憶體1〇4。最後， 編碼器100可藉由儲存於記憶體1〇4巾的資料，將輸入隨機校正序· 的執跡給移除掉，以輸出校正過的數位訊號D〇。 圖八顯示了在適當的設計下，圖六與圖七中的低通遽波器祁、⑽ 用來自白，音（Whitenoise)W中擷取（extract) △之效應的示意圖。 低通濾波态86、98可以使用一般的方式設計，亦可以是十進制濾波器 (decimation filter)，只要可以與上述對本發明的描述相容即可。 以下將簡述對本發明背景校正的模擬結果，可以更清楚的顯示出 本發明優於習知技術之處。請再次參考圖六，一模擬管線式ADC係設 置於MDAC級50之中’後續則連接至一理想的η位元z—胤82。MDAC 級50具有不理想的電容比：Q/Cf = 〇·98 (亦即2%的不匹配）以及偏 壓VGS = 0· OlVr。MDAC級50包含有四個相等的第二電容（即ν=4)。 輸入訊號Vj係為一弦波訊號（sinusoidal signal)，具有〇.5Vr的振 幅，頻率則約等於取樣頻率的2/5倍。在MDAC50尚未被校正前，訊雜 失真比（signal-to-noise-and-distortion ratio，SNDR)係為 43. 4 dB ’ 無假信號動恶響應（spurious-free dynamic range，SFDR)係為 47· 2 dB，故有效位元數（effective number 〇f bits，ENOB)係為 6. 9 位元。而在使用了本發明所揭露的背景校正後（配合一適當設計的低 通濾波器86，μ = 2-28)，訊雜失真比會變成92. 7dB，無假信號動態響 應則變為99· 6 dB，故EN0B會是15.1位元。至於低通濾波器86不同 20 200533081 的U值所對應到不同的暫態行為如圖九所示，越小咖值（可得 的解析度）需要越長的彳後時間。至於當使用—適當設計 波為（Μ = 228)來作為上述的濾、波器時，得到的訊雜失真比會是幼屬二、 無假信號動態響應會是9〇· 2dB，ΕΝ0Β就會是14. 3位元。 圖十為上述模擬ADC輸出的訊雜失真比在不同輸入頻率下的變化 f月形。至於ADC則分別藉由上述的低通濾波器以及十進制淚 校正，對應到的曲線分別為110和112。 w °進订 相較於習知技術，本發明的MDAC包含有複數個第二電容，並對嗲 專第一電谷提供一隨機校正訊號。本發明的MDAC、ADC以及相關的方 法可以同步進行校正的工作以及A/D轉換的工作。在實施上，本發明 僅需對類比訊號的路徑做些許的修改，且不會降低運算速度，並可降 低由電容不匹配、直流偏壓、及不精準的參考電壓所造成的非線性效 應。 > 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所 做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 圖式之簡單說明 圖一為習知技術一管線式ADC的不意圖。. 圖二為習知技術用於圖一之ADC中的MDAC的示意圖。 圖三為習知技術一二基數1· 5位元切換式電容MDAC的示意圖。 圖四為習知技術一二基數1 _ 5位元切換式電容MDAC轉換特性的示意圖。 圖五為本發明二基數1· 5位元切換式電容MDAC的一實施例示意圖。 圖六為圖五中管線式MDAC的一實施例示意圖。 21 200533081 圖七為本發明管線式adc的一實施例示意圖。 圖八為圖六與圖七中低通濾波器之效應的示意圖。 ，九為本發明對低通濾波器設計時的暫態行為的示意圖。 圖十為於不同輸入頻率下本發明ADC輸出之訊雜^比的示意圖 圖式之符號說明D G (10) 凊 Note that the initial digital output Dz of z-ADG 82 contains the square ^ term, and Dz must subtract these two terms to calculate ~. As long as, the last two 'terms start to converge' The above two noise terms can be expressed with good precision 18 200533081 as follows: Therefore, according to the present invention, the collision distribution range of the final round of Vw can be expressed as (C ” — + Cf C. \ (11) 4Cf cf Assume that the comparisons in Figure 5 ϋ 54 and 56 are ideal and the losing I system is between grasping. When the background correction device of the present invention adds a random signal q to v, In equation ⑴): the pressure distribution range must add additional terms Cs, i / Cf. Therefore, a better square green option ^ The second capacitors 64, 66, 68 are combined to form a smaller capacitor value Cs, or a larger number of capacitors are used. Brother Please refer to Figure 7. FIG. 7 is a schematic diagram of another embodiment of the ADC of the present invention. The ADC90 includes a plurality of MDAC stages 92, 94, 96 connected in series, and these leg C stages are the same as the aforementioned MDAC stage 50. Similar to ADC80, ADC90 in this embodiment also includes a multiplier 97, a low-pass filter 98, and an encoder 100. In addition, ADC90 also includes a pseudo-random signal generator 102, which is used to generate sfL signals q, Q ', and contains a mind conscious body 104', which is used to store the output of multiplier 97. DC component. Although three MDAC stages 92, 94, 96 are shown in the figure, more or fewer MDACs are implemented and all are possible. During the A / D conversion of ADC90, an external analog signal Vi is input to the first MDAC stage 92. The first MDAC stage 92 can generate a corresponding digital code Di and output a residual analog signal V2 to the second MDAC stage 94. Such a process is repeatedly performed according to the sampling and holding phases of each MDAC stage 92, 94, 96, and the digital codes D !, D2, Dp corresponding to the analog signal W are output to the encoder 100. As for the correction work, the pseudo-random signal generator 102 will generate the required random correction sequence q and increment it 19 200533081 fi (/ rie = ly) into the second capacitor 64 in the MDAC stages 92, 94, and 96. , 66, "Test Figure 5), starting from the least significant bit of MDACS correction, and then sequentially correction. As for the second capacitor 64, 66, __ _ sequence is not important, however, MDAC level 92, 94, 96 From the calibration of the most effective bit, it is necessary to omit it. To the first _correction spin q == aspect, the pseudo-random "Generate II ⑽ also can be converted to the corresponding second correction signal is applied at the end of ADC9G- The output of the stage 96. The subsequent DC component /) △ is generated by the low-pass button 98, and the DC component & is output to the encoder 100 and the memory 104. Finally, the encoder 100 can be stored by Based on the data in the memory 104, the input of the random correction sequence · is removed to output the corrected digital signal D0. Figure 8 shows the appropriate design, Figure 6 and Figure 7 Low-pass chirp wave filter Qi, ⑽ Use the effect of extracting △ from Whitenoise W Figure. The low-pass filter states 86, 98 can be designed in a general way, or they can be decimal filters, as long as they are compatible with the above description of the present invention. The simulation of the background correction of the present invention will be briefly described below. As a result, it can be more clearly shown that the present invention is superior to the conventional technology. Please refer to FIG. 6 again. An analog pipeline ADC is set in the MDAC stage 50. 'Subsequently, it is connected to an ideal η bit z-胤 82. The MDAC stage 50 has an undesired capacitance ratio: Q / Cf = 0.98 (that is, a 2% mismatch) and a bias voltage VGS = 0 OlVr. The MDAC stage 50 contains four equal second capacitors (That is, ν = 4). The input signal Vj is a sinusoidal signal, with an amplitude of 0.5Vr, and the frequency is approximately 2/5 times the sampling frequency. Before the MDAC50 has not been corrected, the noise is distorted. The signal-to-noise-and-distortion ratio (SNDR) is 43.4 dB. The spurious-free dynamic range (SFDR) is 47.2 dB, so the number of effective bits ( effective number 〇f bits (ENOB) is 6.9 bits. After the background correction disclosed by the present invention (with a suitably designed low-pass filter 86, μ = 2-28), the noise-to-noise and distortion ratio will be 92.7 dB, and the dynamic response without false signals will be 99.6 dB Therefore, EN0B will be 15.1 bits. As for the low-pass filter 86, the different U-values of 2005200581 correspond to different transient behaviors, as shown in Figure 9. The smaller the value (the available resolution), the longer the postponement time. As for using the appropriate design wave (M = 228) as the above-mentioned filter and wave filter, the obtained signal-to-noise and distortion ratio will be young, and the dynamic response without false signals will be 90.2dB, and Ν0Β will It is 14. 3 bits. Figure 10 shows the change in the noise-to-noise ratio of the analog ADC at different input frequencies. As for the ADC, the above-mentioned low-pass filter and decimal tear correction are used respectively, and the corresponding curves are 110 and 112, respectively. w ° ordering Compared with the conventional technology, the MDAC of the present invention includes a plurality of second capacitors, and provides a random correction signal to the first specialized valley. The MDAC, ADC and related methods of the present invention can simultaneously perform the work of correction and the work of A / D conversion. In practice, the present invention only needs to modify the analog signal path slightly, without reducing the operation speed, and can reduce the non-linear effect caused by the capacitor mismatch, DC bias, and inaccurate reference voltage. > The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the patent of the present invention. [Brief description of the diagram] Brief description of the diagram Figure 1 is the intention of the conventional technology-pipeline ADC. Figure 2 is a schematic diagram of the conventional technology used in the MDAC in the ADC of Figure 1. FIG. 3 is a schematic diagram of a conventional base-to-two 1.5-bit switched capacitor MDAC. FIG. 4 is a schematic diagram of the conversion characteristics of a conventional radix 1- to 5-bit switched MDAC capacitor. FIG. 5 is a schematic diagram of an embodiment of a two-based 1.5-bit switched capacitor MDAC according to the present invention. FIG. 6 is a schematic diagram of an embodiment of the pipeline MDAC in FIG. 5. 21 200533081 FIG. 7 is a schematic diagram of an embodiment of the pipeline adc of the present invention. FIG. 8 is a schematic diagram of the effects of the low-pass filter in FIGS. 6 and 7. Nine is a schematic diagram of the transient behavior of the present invention when designing a low-pass filter. Figure 10 is a schematic diagram of the signal-to-noise ratio of the ADC output of the present invention at different input frequencies.
Z-類比至數位轉換器 低通渡波器 乘法器 _ 偽隨機訊號產生器Z-Analog-to-Digital Converter Low-pass Transponder Multiplier _ Pseudo-random Signal Generator
記憶體 22 104Memory 22 104