WO2016046980A1

WO2016046980A1 - Semiconductor storage device

Info

Publication number: WO2016046980A1
Application number: PCT/JP2014/075710
Authority: WO
Inventors: 健三黒土; 笹子　佳孝
Original assignee: 株式会社日立製作所
Priority date: 2014-09-26
Filing date: 2014-09-26
Publication date: 2016-03-31
Also published as: JPWO2016046980A1

Abstract

The present invention enhances read operation reliability without being influenced by the resistance variation of a bit line and unselected memory cells. A semiconductor storage device is provided with a read circuit 101 for reading out data stored in a plurality of memory chains for storing information. To determine readout data, the read circuit 101 compares a reference current flowing through the memory chains as a result of a first readout mode and a cell read current flowing through the memory chains as a result of a second readout mode. In the first readout mode, a precharge voltage is supplied to the memory chains with all of the phase-change elements of the memory chains unselected. In the second readout mode, the precharge voltage is supplied to the memory chains with the phase-change elements of the memory chains selected.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and particularly to an electrically rewritable nonvolatile memory such as a phase change memory, a ReRAM (resistance change memory), and an STT-MRAM (spin injection magnetization reversal resistance change memory). It relates to effective technology.

As background art in this technical field, for example, there is JP-A-2005-327409 (Patent Document 1). In this publication, there is a problem of “providing a semiconductor memory device having a highly reliable data read mode in which the possibility of erroneous reading is reduced”, and further, as a solving means, “the two ends of the memory cells connected in series are Each memory cell unit is connected to a data transfer line and a reference potential line via a selection transistor, and a read voltage that turns the memory cell on or off according to the data is applied to the selected memory cell in the memory cell unit Then, a pass voltage that turns on the memory cell regardless of the data is applied to the remaining non-selected memory cells, the selection transistor is turned on, and whether or not there is a current between the data transfer line and the reference potential line Has a data read mode in which the data of the selected memory cell is determined by detecting (see the summary).

Further, the re-published WO2009 / 041187 (Patent Document 2) states that “in a memory cell in which data is stored by accumulating or removing charges and read by current, when threshold voltage variation increases. Another object of the present invention is to provide a semiconductor memory device and a data discriminating method capable of accurately discriminating data, including a memory cell 1 for storing data by accumulating or removing electric charges and reading data by electric current. The circuit 2 writes intermediate data in the cell itself from which normal data is read, and generates and determines a reference current for determining normal data by reading the intermediate data (summary). reference).

Further, in Japanese Patent Laid-Open No. 2006-202383 (Patent Document 3), “a dummy cell 109 or 110 to which stress is applied according to the number of times of reading / writing is provided, and a change in resistance value of a phase change element of the dummy cell is compared. 111, 112 "(see summary).

Also, a technique for manufacturing a large-capacity semiconductor memory device by using a phase change memory as a nonvolatile memory and connecting a plurality of bits in series in a chain shape is known (see, for example, Patent Document 4).

This publication states that "in a semiconductor memory in which a diode and a transistor are connected in series, there is a problem that the characteristics of the transistor deteriorate due to carriers entering the transistor from the diode" (see summary). Further, paragraph 0044 states that “the following operation is performed in a cell in which a memory cell in which such a transistor and a phase change element are connected in parallel, ie, a chain cell, is connected”. Yes.

JP 2005-327409 A Republished WO2009 / 041187 JP 2006-202383 A JP 2012-69830 A

The inventor examined the circuit configuration of the resistance change type memory, particularly the phase change memory in detail, and found the following knowledge.

A peripheral circuit including a read circuit section having a sense amplifier for reading is provided around the memory array. Here, in order to realize a large-capacity semiconductor nonvolatile memory, it is necessary to improve the ratio of the memory array area to the memory chip. That is, it is necessary to reduce the number of memory arrays and to reduce the area of peripheral circuits other than the memory array.

However, if the number of memory arrays is reduced, the length of the bit line connecting the memory cell and the sense amplifier becomes longer, resulting in a problem that the resistance of the bit line increases. Furthermore, since there is a certain resistance variation in the wiring resistance, it is difficult to read out the resistance of the phase change element.

The phase change element has an amorphous (amorphous) state, a low resistance crystal state, and a high resistance, and uses a difference in electrical resistance. For example, the high resistance state is set to “0” and the low resistance state is set to “1”. Record information. A change from '1' to '0' is a write or reset operation, and a change from 0 'to' 1 'is an erase or set operation.

The phase change element has a phenomenon called resistance drift in which the element resistance gradually increases with time after writing. It is said that the cause of the resistance drift is the structural relaxation of the phase change material that occurs after writing. This resistance drift is characterized in that the resistance value is likely to increase as the element resistance increases.

Incidentally, in the erase operation of the phase change element, there is a certain variation in the resistance value of the phase change element after erasure. Therefore, in order to perform data retention with high reliability, it is desirable to perform a read operation after performing the erase operation of the phase change element to confirm that the resistance of the phase change element is sufficiently low.

However, the reduction in the number of memory arrays accompanying an increase in capacity increases the bit line resistance, and further increases the variation thereof, making it difficult to confirm that the resistance of the phase change element is sufficiently low.

For this reason, it cannot be confirmed that the resistance of the phase change element is sufficiently low, and data inversion in which the value of the phase change element changes from '1' to '0' due to resistance drift occurs, resulting in phase change. There is a problem that the reliability of the memory is lowered.

An object of the present invention is to provide a technique capable of improving the reliability of a read operation without being affected by variations in resistance of read bit lines and non-selected memory cells.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

That is, a typical semiconductor memory device includes a memory array having a plurality of storage units for storing information, and a read circuit that reads out data stored in the storage unit, and includes a first read mode and a second read mode. And having. The storage unit includes at least one memory cell.

The memory cell includes a storage element and a selection element. The memory element has at least a first memory state and a second memory state due to a difference in electrical resistance. The selection element selects a storage element.

The first read mode is a mode in which all the storage elements of the storage unit are not selected and a precharge voltage is supplied to the storage unit. The second read mode is a mode in which a memory element of the memory unit is selected and a precharge voltage is supplied to the memory unit.

The read circuit determines read data by comparing the reference current flowing in the storage unit in the first read mode with the cell read current flowing in the storage unit in the second read mode.

In particular, the read circuit acquires the read current and the reference current from the same bit line to which the selected storage unit is connected in the first read mode and the second read mode, respectively.

The reliability of data reading in the semiconductor memory device can be improved.

4 is an explanatory diagram illustrating an example of a partial circuit configuration of a memory array 202 included in the semiconductor memory device according to the first embodiment; FIG. FIG. 2 is an explanatory diagram illustrating an example of a configuration of a read circuit provided in a peripheral portion of the memory array in FIG. 1. It is explanatory drawing which shows an example of the layout in the semiconductor memory device which this inventor examined. It is explanatory drawing which shows the other example of the layout in the semiconductor memory device which this inventor examined. It is explanatory drawing which showed an example of the change of the elapsed time after writing, and phase change element resistance. FIG. 2 is an explanatory diagram showing an example of an on / off state of a Z selection transistor when a cell read current flows in the memory array of FIG. 1. FIG. 3 is an explanatory diagram showing an example of an on / off state of a MOS when a cell read current is passed in the read circuit of FIG. 2. 3 is a timing chart showing an example of a read operation by the read circuit of FIG. 2. It is explanatory drawing which shows an example of the breakdown of the resistance read by a sense amplifier at the time of a read. It is explanatory drawing which shows the example of a structure of the read circuit used as the object of a comparison with FIG. 1 which this inventor examined. 11 is a timing chart illustrating an operation example of the read circuit in FIG. 10. FIG. 3 is an explanatory diagram showing an example of a configuration in a semiconductor memory device having the read circuit of FIG. 2. FIG. 2 is an explanatory diagram illustrating an example of operations during writing and erasing in the phase change element of FIG. 1. FIG. 10 is an explanatory diagram showing a partial circuit configuration example of a memory array included in a semiconductor storage device according to a second embodiment; FIG. 15 is an explanatory diagram enlarging a part of the memory array of FIG. 14. FIG. 16 is a schematic diagram illustrating a cross section taken along the line D-D ′ of FIG. 15. 17 is a timing chart showing an operation example of a read circuit provided in a semiconductor memory device having the memory array of FIG. FIG. 10 is an explanatory diagram illustrating an example of a partial circuit configuration of a memory array according to a third embodiment. 19 is a timing chart illustrating an operation example of a read circuit provided in a semiconductor memory device having the memory array of FIG. It is explanatory drawing which shows an example of a structure of the read circuit by this Embodiment 4. It is explanatory drawing which shows an example of a structure of the read circuit by this Embodiment 5.

In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., the shape of the component is substantially the case unless it is clearly specified and the case where it is clearly not apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

In all the drawings for explaining the embodiments, the same members are, in principle, given the same reference numerals, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

Hereinafter, embodiments will be described in detail.

(Embodiment 1)
<Configuration of semiconductor memory device>
The semiconductor memory device has, for example, a 1T-1R type (1 transistor-1 resistance element) parallel type memory cell. In this semiconductor memory device, an example of a semiconductor memory device that performs a determination of “0” and “1” at the time of reading by flowing a reference current using the same path as the cell read current except for the selected memory cell will be described.

FIG. 1 is an explanatory diagram showing an example of a partial circuit configuration of a memory array 202 included in the semiconductor memory device according to the first embodiment.

The memory array 202 is composed of a plurality of memory chains MC. The memory chain MC serving as a storage unit includes a selection element XMOS and at least one memory cell CELL. The memory cell has a configuration in which one phase change element PCM which is a storage element and a Z selection transistor ZMOS which is one Z selection element are connected in parallel.

Here, an example in which one phase change element PCM and one Z selection transistor ZMOS are connected in parallel will be described. However, one phase change element PCM and a plurality of Z selection transistors ZMOS are connected in parallel. It goes without saying that it is possible to connect to. Alternatively, a plurality of phase change elements PCM and one Z selection transistor ZMOS can be connected in parallel, or a plurality of phase change elements PCM and a plurality of Z selection transistors ZMOS can be connected in parallel. Needless to say.

The Z direction is a direction orthogonal to the silicon substrate which is a semiconductor substrate, and the X direction and the Y direction are preferably orthogonal to the Z direction and orthogonal to each other. In this way, a plurality of memory cells existing in the Z direction can be collectively formed by a single drilling process, and the manufacturing cost can be reduced.

It is desirable that the gate electrodes of the Z selection transistor ZMOS are connected to each other for each layer between the plurality of memory chains MC. For example, the potential of the Z selection line Z0 connected to the gate of the zeroth layer Z selection transistor ZMOS is the same in any memory chain MC.

With such a configuration, there is an effect that the chip area of the semiconductor memory device 201 can be reduced by reducing the area of the gate electrode of the Z selection transistor ZMOS, and an inexpensive semiconductor memory device 201 can be provided.

It goes without saying that the Z selection line Z connected to the gate of the Z selection transistor can be separated for each bit line and the potential can be individually controlled. It goes without saying that the Z selection line Z can be separated for each X selection line X and the potential can be individually controlled. In this case, since the optimum gate potential of the Z selection transistor ZMOS can be controlled for each location, the gate breakdown voltage of the Z selection transistor ZMOS can be reduced, and the reliability of the semiconductor memory device 201 is improved.

The Z selection transistor ZMOS is preferably a vertical GAA-NMOSFET (Gate All Around n-channel MOSFET). By using an NMOSFET having a higher current driving capability than a PMOSFET, the number of phase change elements PCM included in the memory chain MC can be increased, and a large-capacity semiconductor memory device 201 can be realized. Of course, it goes without saying that a PMOS can be used.

Since the size of the transistor can be reduced by using the vertical MOSFET as compared with the case of using 4F2 (F is the minimum processing size) and a planar MOS, the capacity can be increased.

By using the GAA structure, the gate width can be increased compared to the case of using a planar MOS, the MOS driving power is improved, the number of memory cells included in the memory chain MC is increased, and Capacitance can be achieved.

When the PMOS is used, the voltage applied to the gate electrode of the non-selected Z selection transistor can be lowered as compared with the case where the NMOS is used. Therefore, the gate breakdown voltage of the Z selection transistor ZMOS can be reduced, and the reliability of the semiconductor memory device 201 The effect is improved.

As a part of the material of the phase change element PCM, for example, a chalcogenide material, particularly a GeSbTe alloy (germanium-antimony-tellurium alloy) can be used. The chalcogenide material can take two metastable states, an amorphous (amorphous state) and a crystalline state, and the electric resistance values in the respective states are different. That is, in the case of amorphous, the resistance is high, and in the crystalline state, the resistance is low. By utilizing the difference in electrical resistance, the values “0” and “1” can be stored.

‘0’ for the amorphous state and ‘1’ for the crystalline state. Rewriting from '0' to '1' is erasing or setting operation, and rewriting from '1' to '0' is writing or resetting operation.

Rewriting is performed by passing current through the phase change element PCM and generating Joule heat. In order to erase, the phase change element is crystallized by holding at a temperature equal to or higher than the crystallization temperature for a certain period of time. In order to write, it is made amorphous (vitrified) by heating above the melting point and rapidly cooling. Needless to say, the phase change element PCM can take a value of three or more.

By using a phase change element that has already been applied to a product as a memory element, the development period can be shortened, and the semiconductor memory device 201 can be shipped in a short period of time. In this embodiment, an example of a phase change element that performs a crystal-amorphous phase change will be described. However, it is needless to say that a phase change element of crystal A-crystal B can be used. Absent. Here, the crystal A and the crystal B are crystals having different crystal structures.

Note that in this embodiment, a case where a phase change element is used as a memory element is described as an example. However, it is needless to say that ReRAM or STT-MRAM (spin injection MRAM) can be used as the memory element. Yes.

By using ReRAM with a small rewrite current, it is possible to increase the number of memory elements included in one memory chain MC, and there is an effect that a large-capacity semiconductor memory device 201 can be realized. In addition, there is an effect that the semiconductor memory device 201 having a high write data rate can be realized by using the STT-MRAM having a high rewrite speed.

<Configuration and operation of lead circuit>
Hereinafter, a case where a phase change element is used as a memory element will be described.

FIG. 2 is an explanatory diagram showing an example of the configuration of the read circuit 101 provided in the peripheral portion of the memory array 202 of FIG.

A read circuit 101 and a write / erase selection switch PROGS are connected to the bit line BL. Needless to say, the memory array 202 includes a plurality of bit lines BL. A write / erase selection switch PROGS is provided between the write / erase circuit 102 and the bit line BL.

The read circuit 101 as a read circuit includes a reference resistor REFR, a cell read current selection switch CELLS, a reference current selection switch REFS, a discharge switch DISS, a precharge switch PRES, a sense amplifier activation switch SA_ENS, a sense amplifier SA, a data output DOUT, a cell read. It has a voltage holding capacitor C _CELL and a reference voltage holding capacitor C _REF .

It is desirable that the value of the reference resistor REFR is a read threshold value used for determining “0” and “1” at the time of reading. For example, 1 MΩ. The reference resistor REFR can be formed using, for example, a diffusion layer resistor.

The cell read current selection switch CELLS is turned on based on the cell read current selection signal CES when generating the cell read current. The reference current selection switch REFS is turned on based on the reference current selection signal RFS when generating the reference current.

Further, the discharge switch DISS is turned on based on the discharge signal DIS when the cell read voltage V _CELL and the reference voltage V _REF are discharged to 0V, for example.

The precharge switch PRES is turned on based on the precharge signal PRE when the cell read voltage V _CELL and the reference voltage V _REF are set to a precharge voltage V _PRE , for example, 1V. The sense amplifier activation switch SA_ENS is turned on based on the sense amplifier activation signal SA_ENS when the cell read voltage V _CELL and the reference voltage V _REF are input to the sense amplifier SA.

The sense amplifier SA differentially amplifies the input signal and outputs the result to the data output line DOUT. The cell read voltage holding capacitor C _CELL and the reference voltage holding capacitor C _REF are used to hold the cell read voltage V _CELL and the reference voltage V _REF . The capacitor can be manufactured using, for example, a gate insulating film capacitor.

The write / erase circuit 102 is used for writing or erasing the phase change element PCM included in the memory cell CELL. As described above, it is desirable to amplify the voltage difference in order to reduce the circuit area, but it goes without saying that other means, for example, means for comparing with the amount of current can be taken.

FIG. 1 shows the on and off states of the MOS when a reference current is passed. The reference voltage holding capacitor C _REF holds the precharge voltage V _PRE in advance. The precharge switch PRES is turned on in advance to set the reference voltage _VREF to the precharge voltage _VPRE . Then, the voltage is held using the reference voltage holding capacitor C _REF .

The electric charge held in the reference voltage holding capacitor C _REF flows to the source electrode SL through the reference resistor REFR, the bit line BL, and the memory chain MC0 when the reference current selection switch REFS is turned on. The current flowing at this time is used as a reference current.

Compared to the write state in which the value “0” of the phase change element PCM is recorded and the erase state in which the value “1” is recorded, the resistance of the Z selection transistor ZMOS in which the Z selection transistor ZMOS is on is Low is desirable. For example, the resistance value is 33 kΩ.

As a result, in the memory cell CELL in the non-selected state, the current flows mainly through the Z selection transistor ZMOS, and the current flowing through the phase change element PCM can be reduced, thereby realizing a highly reliable semiconductor memory device 201. be able to.

In the state shown in FIG. 1, the Z selection transistor ZMOS is turned on by Z selection lines Z0, Z1, Z2, and Z3 selected by a Z selection line driving circuit (not shown) disposed in the vicinity of the memory array 202. . Therefore, the reference current mainly passes through the selection element XMOS0 and the four Z selection transistors ZMOS in the memory chain MC0.

Note that the selected memory cell to be read is the memory cell CELL2, and the non-selected memory cells that are not to be read are the memory cells CELL0, CELL1, and CELL3.

Next, the operation of each MOS when a cell read current is passed will be described.

FIG. 6 is an explanatory diagram showing an example of an on / off state of the Z selection transistor ZMOS when a cell read current is allowed to flow in the memory array 202 of FIG. FIG. 7 is an explanatory diagram showing an example of the on / off state of the MOS when a cell read current is passed in the read circuit 101 of FIG.

The cell read voltage holding capacitor C _CELL holds the precharge voltage V _PRE . The precharge switch PRES is turned on in advance to set the cell read voltage V _CELL to the precharge voltage V _PRE , and this voltage is set using the cell read voltage holding capacitor C _CELL .

The charge held in the cell read voltage holding capacitor C _CELL flows to the source electrode SL through the bit line BL and the memory chain MC0 when the cell read current selection switch CELLS is turned on. The current flowing at this time is defined as a cell read current.

The Z selection transistors ZMOS of the non-selected memory cells CELL0, CELL1, and CELL3 are turned on by the Z selection lines Z0, Z1, and Z3. Therefore, the current flows mainly through the Z selection transistor ZMOS, not the phase change element PCM.

Since the Z selection transistor ZMOS of the selected memory cell CELL2 to be read is turned off by the Z selection line Z2, the current flows mainly through the phase change element PCM, not the Z selection transistor ZMOS. It is desirable that the off-resistance of the Z selection transistor ZMOS is higher than the resistance of the phase change element PCM in the write state and the erase state.

In this way, the resistance of the phase change element PCM can be read with higher accuracy, and a highly reliable semiconductor memory device 201 can be realized. To repeat, in the memory chain MC0, the cell read current mainly passes through the three Z selection transistors ZMOS in the selection element XMOS0 and the memory cells CELL0, CELL1, and CELL3, and mainly passes through the phase change element in the memory cell CELL2. ing.

As described above, some of the charges accumulated in the reference voltage holding capacitor C _REF and the cell read voltage holding capacitor C _CELL move to the source electrode as the reference current and the cell read current.

As a result, the cell read voltage V _CELL and the reference voltage V _REF that were initially the precharge voltage V _PRE are lowered. The cell read voltage V _CELL and the reference voltage V _REF after flowing the reference current and the cell read current for a certain time are input to the sense amplifier SA by turning on the sense amplifier activation switch SA_ENS, and are differentially amplified.

It is desirable that the time for supplying the reference current and the time for supplying the cell read current are the same. By making the same, the design of the read circuit can be simplified, and the time required for designing the semiconductor memory device 201 can be shortened.

If the selected memory cell CELL2 is “0” in the high resistance state, the cell read current is smaller than the reference current, and the cell read voltage V _CELL is higher than the reference voltage V _REF . By amplifying this voltage difference with the sense amplifier SA, it can be read that the value of the memory cell CELL2 is “0”.

On the other hand, if the selected memory cell CELL2 is “1” in the low resistance state, the cell read current is larger than the reference current, and the cell read voltage V _CELL is lower than the reference voltage V _REF . By amplifying this voltage difference by the sense amplifier SA, it can be read that the value of the memory cell CELL2 is “1”.

<Detailed operation of lead circuit>
Further detailed description will be given with reference to FIG.

FIG. 8 is a timing chart showing an example of a read operation by the read circuit 101 of FIG. In FIG. 8, from the upper side to the lower side, the cell read voltage V _CELL , the reference voltage V _REF , the Z selection line Z2, the Z selection lines Z0, Z1, Z3, the discharge switch DISS, the cell read current selection switch CELLS, the reference current selection switch REFS, Signal timings in the precharge switch PRES and the sense amplifier activation switch SA_ENS are respectively shown.

By turning off the discharge switch DISS and turning on the precharge switch PRES (timing 601 in FIG. 8), the precharge voltage V _PRE is applied to the reference voltage holding capacitor C _REF and the cell read voltage holding capacitor C _CELL . It is desirable to perform precharging simultaneously with respect to the reference voltage and the read voltage. By carrying out simultaneously, it becomes possible to shorten precharge time to half time compared with the case where each precharge is performed, and the high-speed semiconductor memory device 201 can be realized. Needless to say, it can be charged individually.

Furthermore, it is desirable that the read voltage and the precharge voltage of the reference voltage be the same. By doing so, the design becomes easy and the design period can be shortened. Needless to say, the precharge voltages can be different from each other. By increasing the precharge voltage of the reference voltage, the precharge time can be shortened, and the semiconductor memory device 201 having a high read speed can be realized.

Subsequently, the precharge switch PRES is turned off and the reference current selection switch REFS is turned on (timing 602 in FIG. 8), thereby causing a reference current to flow. This operation is the first read mode. Reference current, the reference voltage holding capacitor C _REF from the bit line BL, and through the memory chain MC 0, flows to the source electrode SL. Since the Z selection line Z2 is turned on, the current mainly passes through the Z selection transistor ZMOS in the memory cell CELL2 of the memory chain MC0. At this time, it goes without saying that a slight current flows through the non-selected memory chain MC1 and the like. However, the transistor characteristics of the X selection element XMOS are adjusted so that the leakage current is relatively smaller than the current flowing through the memory chain MC0, and the off-current is reduced.

Further, the cell read current is caused to flow by turning off the reference current selection switch REFS and the Z selection line Z2 and turning on the cell read current selection switch CELLS. This operation is the second reading mode. The cell read current flows from the cell read voltage holding capacitor C _CELL through the bit line BL and the memory chain MC0 to the source electrode SL. Since Z selection line Z2 is turned off, current mainly passes through phase change element PCM in memory cell CELL2 of memory chain MC0.

Then, the cell read current selection switch CELLS is turned off, and the sense amplifier activation switch SA_ENS is turned on (timing 604 in FIG. 8). As a result, the potential difference between the cell read voltage V _CELL and the reference voltage V _REF is amplified by the sense amplifier SA. Using this amplified voltage, it is determined whether the value of the memory cell is “0” or “1”.

<About issues>
Here, the problem of deterioration of the reliability of the phase change memory due to the resistance drift described in the prior art will be reviewed using specific numerical values.

FIG. 3 is an explanatory diagram showing an example of the layout in the semiconductor memory device examined by the present inventors. FIG. 4 is an explanatory diagram showing another example of the layout in the semiconductor memory device examined by the present inventors.

As shown in FIG. 3, the size of the semiconductor chip CH of the semiconductor memory device is, for example, 10 mm × 11 mm, and its area is 110 mm ² . The number of memory arrays MRY is four, the size of the memory array MRY is 4 mm square, and the area of the memory array MRY is 16 mm ² . It is assumed that a sense amplifier is located on one side of the memory array MRY. In this case, the distance from the memory cell to the sense amplifier, that is, the length of the bit line is about 4 mm at the maximum. The short sides of the read circuit 501 and the column decoder 502 are assumed to be about 1 mm.

The column decoder 502 includes a write circuit and an erase circuit in addition to the column selection control circuit. The short side of the row decoder 503 is set to 0.5 mm. The pad unit 504 is used for connecting the semiconductor memory device to an external controller. For example, when the semiconductor storage device is used for an SSD (Solid State Drive), the external controller becomes an SSD controller. Needless to say, the power supply voltage VDD and the ground voltage VSS are supplied.

FIG. 4 shows a case where the number of memory arrays is larger than that in FIG. In the semiconductor memory device of FIG. 4, the size of the semiconductor chip CH is 10 mm × 11 mm and the area is 110 mm ² as in FIG. 3, but the number of memory arrays MRY is 16.

The size of the memory array MRY is 1.5 mm × 1.75 mm, its area is 2.625 mm ^2, and when the sense amplifier is located on one side of the memory array MRY, the memory cell MRY is changed to the sense amplifier. Distance, that is, the length of the bit line is 1.5 mm at the maximum.

It should be noted that 1 mm each is assigned vertically and horizontally as a scribe portion and a pad portion 504 required when manufacturing a semiconductor memory device. The scribe part is a part that becomes a cutting part when the semiconductor wafer 201 is manufactured by cutting a silicon wafer with a diamond cutter.

Also, even if the number of memory arrays changes, the circuit configuration of the column decoder and row decoder does not change greatly, and the width of the short side is almost the same. Therefore, as the number of memory arrays increases, the ratio of the memory array MRY to the semiconductor memory device decreases. For example, when the number of memory arrays MRY shown in FIG. 3 is 4, the occupation ratio 1 occupied by the memory array MRY in the semiconductor memory device is expressed by the following equation (1).

Memory array occupation ratio 1 = 16 mm ² × 4/110 mm ² = 58% (1)
On the other hand, when the number of memory arrays MRY shown in FIG. 4 is 16, the occupation ratio 2 occupied by the memory array MRY in the semiconductor memory device 201 is expressed by the following equation (2).

Memory array occupancy ² = 2.625mm 2 × 16 pieces ^{/ 110mm 2 = 38% (2} )
That is, the smaller the number of memory arrays, the higher the memory array occupancy rate, and a large-capacity semiconductor memory device can be realized.

On the other hand, consider the resistance of the bit line connecting the memory cell and the sense amplifier.

Assuming that the bit line width is the minimum processing dimension F = 32 nm, the bit line material is tungsten, and the sheet resistance is 3Ω / □, when the memory array MRY shown in FIG. The maximum resistance RBL1 is expressed by the following equation (3).

RBL1 = 3Ω × 4 mm / 32 nm = 375 kΩ (3)
On the other hand, when the number of memory arrays MRY shown in FIG. 4 is 16, the maximum resistance RBL1 of the bit line having a maximum length of 1.5 mm is expressed by the following equation (3).

RBL2 = 3Ω × 1.5 mm / 32 nm = 141 kΩ (4)
That is, the smaller the number of memory arrays, the higher the bit line resistance. Further, since the bit line resistance is high, it is strongly influenced by the resistance variation. The wiring resistance is, for example, about 10% to 40%. For example, assuming that the bit line resistance varies by 30%, the resistance varies by about 113 kΩ when the number of memory arrays MRY shown in FIG. 3 is four. On the other hand, when the number of memory arrays MRY shown in FIG. 4 is 16, the resistance variation is about 42 kΩ, and the variation amount is small. Needless to say, the wiring width also varies.

Subsequently, the resistance drift will be described in more detail.

FIG. 5 is an explanatory diagram showing an example of a change between the elapsed time after writing and the phase change element resistance. In FIG. 5, the horizontal axis represents the elapsed time after writing or erasing, and the vertical axis represents the resistance of the phase change element. The graph is shown as a log-log plot.

Lines

401, 403, and 404 respectively indicate resistance changes after the erase operation. On the other hand, the line 402 shows the resistance change after the write operation. Assume that after erasing and writing, a read operation is performed to check whether erasing and writing are successful. The lead for confirmation is the verify lead.

A line 401 is an example in the case where erasing can be performed to a sufficiently low resistance, and the resistance becomes sufficiently lower than an erase verify threshold, for example, 300 kΩ, at the time of verify read after erasure, for example, 20 us (microseconds) after erasure. ing. Furthermore, the resistance is lower than the read threshold, for example, 1 MΩ, even when data retention must be guaranteed (assumed as a guarantee period), for example, after 5 years. Therefore, even if reading is performed at the time of the guarantee period, it can be read that the value is “1” correctly.

Next, a line 402 is an example in the case where the write is successful. The resistance is higher than a write verify threshold, for example, 3 MΩ at the time of the verify read after the write, and the resistance is higher than the read threshold even in the guarantee period. High resistance. Therefore, even if reading is performed after the guarantee period from writing, it can be read that the value is “0” correctly.

On the other hand, a line 403 is an example in which the resistance at the time of erasing is relatively high, and the value of the phase change element resistance is slightly below the read threshold value during the guarantee period. In this case, the increase in resistance with time is greater than that of line 401.

Furthermore, line 404 is an example in which the resistance at the time of erasing is higher, and the value of the phase change element resistance exceeds the read threshold value during the guarantee period. The increase in resistance with time is further increased, and if it is read from the write after the guarantee period, it is determined to be “0”, and the original value cannot be read correctly.

In this way, in order to prevent the resistance after erasure from increasing and to realize a highly reliable phase change memory, the erase verify is performed so that the resistance read by the verify read after erasure exceeds the erase verify threshold. Set the threshold.

When the line 404 is erased, when verify read after erasure is performed, it is determined that the phase change element resistance is equal to or greater than the erase verify threshold value, and erasure must be performed again.

For this reason, it is necessary to improve the reliability of the phase change element by accurately reading whether the element resistance is higher or lower than the erase verify threshold. On the other hand, when the capacity is increased, the resistance of the bit line and its variation increase, making it difficult to read the phase change element resistance. That is, as the capacity increases, the bit line resistance increases, making it difficult to ensure the reliability of the phase change element.

FIG. 9 is an explanatory diagram showing an example of the breakdown of the resistance read by the sense amplifier SA at the time of reading.

In this embodiment, description will be made assuming that the number of memory arrays is 4, the size of the memory array is 4 mm square, and the area is 16 mm ² . The maximum length of the bit line BL is 4 mm. The phase change element resistance in the erased state is, for example, 100 kΩ. The maximum resistance of the bit line is, for example, 375 kΩ as described in the problem. The resistance of the non-selected memory cell is 100 kΩ, for example. Other resistors including the resistance of the X selection MOS and the on-state MOS in the read circuit are, for example, 30 kΩ. As can be seen from the breakdown, the resistance read by the sense amplifier may include a relatively large bit line resistance in addition to the resistance of the phase change element desired to be read. This high bit line resistance may make it difficult to read the phase change element resistance.

On the other hand, in the read circuit 101 of the present embodiment, the same bit line BL is used both when a reference current is passed and when a cell read current is passed. Therefore, stable phase change element resistance reading can be performed without being affected by the resistance variation of the bit line BL.

FIG. 10 is an explanatory diagram showing an example of the configuration of a read circuit to be compared with FIG. 1 examined by the present inventors.

The read circuit of FIG. 10 differs from the read circuit of FIG. 1 in that it has a reference voltage source V _FREF having a fixed voltage value, and is controlled by a reference current selection switch REFS and a sense amplifier activation switch SA_ENS. It is connected to the sense amplifier SA via the element.

FIG. 11 is a timing chart showing an operation example of the read circuit of FIG.

First, by turning off the discharge switch DISS and turning on the precharge switch PRES (timing 901 in FIG. 11), the precharge voltage V _PRE is applied to the cell read voltage holding capacitor C _CELL .

Next, turn off the precharge switch PRES, (timing 902 of FIG. 11) the reference current selection switch REFS is turned on, the reference voltage V _REF to a fixed reference voltage V _FREF. By turning on the cell read current selection switch CELLS, a cell read current flows (timing 903 in FIG. 11).

The cell read current flows from the cell read voltage holding capacitor C _CELL through the bit line BL and the memory chain MC0 to the source electrode SL. Since Z selection line Z2 is turned off, current mainly passes through phase change element PCM in memory cell CELL2 of memory chain MC0.

Subsequently, the cell read current selection switch CELLS is turned off and the sense amplifier activation switch SA_ENS is turned on (timing 604 in FIG. 11). As a result, the potential difference between the cell read voltage V _CELL and the reference voltage V _REF is amplified by the sense amplifier SA. Using this amplified voltage, it is determined whether the value of the memory cell is “0” or “1”.

In the configuration example of FIG. 10, when the cell read current is allowed to flow, the bit line BL is used, but the reference voltage V _REF uses the fixed reference voltage V _FREF and does not change depending on the resistance of the bit line BL. Therefore, it is affected by the resistance variation of the bit line BL, and it becomes impossible to read the phase change element resistance stably.

For example, the resistance of the bit line BL varies 113 kΩ. It is higher than 100 kΩ, which is an example of the resistance of the phase change element in the erased state. Due to this resistance variation, it becomes difficult to determine the resistance of the phase change element from the resistance read by the sense amplifier. It becomes impossible to determine whether the state of the element is “0” or “1” with high reliability.

Write and erase are performed by generating Joule heat by supplying a write current to the phase change element PCM. The write current is 40 μA, for example, and the erase current is 20 μA, for example. Note that writing or erasing can also be performed by generating Joule heat by passing a current through the adjacent Z selection transistor ZMOS.

It is desirable that the potential of the source electrode SL is maintained at approximately 0V. Strictly speaking, it goes without saying that the potential of the source electrode is slightly higher than about 0 V, which is the potential of the GND terminal, due to a voltage drop caused by a current flowing from the source electrode to the GND (ground) terminal. By maintaining the voltage at approximately 0 V, it is possible to avoid an increase in power consumption caused by driving a source electrode having a large parasitic capacitance.

<Configuration example of semiconductor memory device>
FIG. 12 is an explanatory diagram showing an example of the configuration of the semiconductor memory device 201 having the read circuit 101 of FIG. In FIG. 12, only one memory array 202 is shown for simplicity.

The semiconductor memory device 201 is supplied with the power supply voltage VDD and the ground voltage VSS from the outside of the semiconductor chip, and communicates control signals and the like through the data signal line DQ.

Examples of the input control signal include a chip valid signal CE, a command latch valid signal CLE, an address latch valid signal ALE, a clock signal CLK, a read / write valid signal W / R #, and a write protect signal WP #.

As an input / output control signal, for example, there is a data strobe DQS, and as an output control signal, for example, there is a read busy signal R / B #. In addition, an I / O signal power supply VCCQ, an I / O signal ground source VSSQ, and the like can be supplied.

The semiconductor memory device 201 includes a row system circuit 1001, a column system circuit 1002, a control system circuit 1003, a power supply circuit 1004, a memory array 202, and the like. The row circuit 1001 includes a bit line selector, a sense amplifier, and the like. The column system circuit 1002 includes a row decoder, a word line driver, and the like. The control system circuit 1003 includes a command decoder, a control circuit, a buffer device, and the like.

From the power supply circuit 1004, power is supplied to the row system circuit 1001, the column system circuit 1002, and the control system circuit 1003. A part of the voltage is stepped up or stepped down, and the remaining voltage is supplied with the power supply voltage VDD as it is.

<Write / erase phase change element>
Subsequently, writing and erasing of the phase change element PCM will be described.

FIG. 13 is an explanatory diagram showing an example of operations at the time of writing and erasing in the phase change element PCM of FIG.

Write is performed by causing a reset pulse to flow through the phase change element PCM and generating Joule heat. The phase change element PCM is heated to the melting point or higher by the reset pulse, and is brought into an amorphous state by being rapidly cooled. The application time of the reset pulse is about 8 ns, for example.

Erasing is performed by causing a set pulse to flow through the Z selection transistor ZMOS (FIG. 1) and generating Joule heat.

The phase change element PCM is held for a certain time, for example, 500 ns above the crystallization temperature by the set pulse. Thus, phase change element PCM enters a crystalline state. The crystalline state has a lower resistance than the amorphous state, and by utilizing the difference in resistance, information can be recorded, for example, by setting the low resistance state to “1” and the high resistance state to “0”.

As described above, since the read circuit 101 uses the same bit line BL when supplying the reference current and when supplying the cell read current, the influence of the resistance variation of the bit line BL can be reduced. As a result, stable phase change element resistance reading can be performed, and the reliability of the semiconductor memory device can be improved.

(Embodiment 2)
<Overview>
In the second embodiment, a semiconductor memory device having a light plate electrode WR will be described. With the configuration having the light plate electrode WR, the write data rate and the erasing speed can be increased.

<Configuration of memory array>
FIG. 14 is an explanatory diagram showing a circuit configuration example of a part of the memory array 202 included in the semiconductor memory device according to the second embodiment.

The memory array 202 includes a plurality of memory chains MC as shown in FIG. The memory chain MC is configured by connecting a plurality of memory cells CELL in series. Here, it is assumed that the memory chain MC is composed of eight memory cells CELL.

The memory cell CELL is configured by connecting one phase change element PCM and one Z selection transistor ZMOS in parallel. Here, an example in which one phase change element PCM and one Z selection transistor ZMOS are connected in parallel will be described, but one phase change element PCM and a plurality of Z selection transistors ZMOS are connected in parallel. It goes without saying that it is possible to connect to. Further, a plurality of phase change elements PCM and one Z selection transistor ZMOS can be connected in parallel, or a plurality of phase change elements PCM and a plurality of Z selection transistors ZMOS can be connected in parallel. Needless to say.

In FIG. 14, description will be made assuming that the read bit line is extended in the X direction and parallel to the Y selection line. An example in which the memory chain is stacked in four layers is taken as an example.

In this case, the number of stacked memory cells is 8 × 4, 32 layers. It goes without saying that it is possible to stack more than four layers or to have a number of layers less than four. There is an advantage that the memory capacity can be increased by increasing the number of stacked layers. There is an advantage that manufacturing is facilitated by reducing the number of stacked layers.

Further, in FIG. 14, the memory chain of the X address I and the Y address J of the H layer is represented as MC (H)-(I)-(J). The plurality of read bit lines RBL are assumed to be extended in the X direction. The read bit line of the Y address J of the H layer is indicated as RBL (H)-(J).

The X selection MOS and the Y selection MOS are double gate MOSs, and there are two gate electrodes for each MOS. Further, since the channel thickness of the MOS is thin, the MOS is turned on only when an on-voltage is applied to the two gate electrodes. The Y selection line is driven by a Y driver YDR.

FIG. 15 is an explanatory diagram enlarging a part of the memory array of FIG.

The memory chain MC is arranged at 2F intervals as shown in FIG. The X selection destination is extended in the Y direction.

FIG. 16 is a schematic diagram showing a D-D ′ section of FIG. 15. FIG. 16 shows a part of the memory chain MC, and shows a plurality of Z selection transistors ZMOS and a phase change element PCM.

The Z selection transistor ZMOS and the phase change element PCM include a silicon oxide film 1406, a gate oxide film 1403, a silicon channel 1404, a phase change material 1405, a Z selection transistor gate electrode 1401, an interlayer insulating film 1402, and the like.

The Z selection transistor ZMOS is preferably a vertical GAA-NMOSFET (Gate All Around n-channel MOSFET). By using an NMOSFET having a higher current driving capability than a PMOSFET, the number of phase change elements PCM included in the memory chain MC can be increased, and a large-capacity semiconductor memory device can be realized. Of course, it goes without saying that a PMOS can be used.

By using the vertical MOSFET, the size of the transistor can be reduced as compared with the case of using 4F2 and a planar MOS, so that the capacity can be increased. By using the GAA structure, it becomes possible to widen the gate width as compared with the case of using a planar MOS, improving the driving power of the MOS, and increasing the number of memory cells CELL included in the phase change chain MC. The capacity can be increased.

When the PMOS is used, the voltage applied to the gate electrode of the non-selected Z selection transistor ZMOS can be made lower than when the NMOS is used, so that the gate breakdown voltage of the Z selection transistor ZMOS can be reduced. This has the effect of improving the reliability.

It is desirable to use a double gate NMOSFET as the X selection element XMOS. By using a double gate MOSFET, the gate width of the MOSFET can be increased compared to the case of using a planar MOSFET. Thereby, it becomes easy to secure a current necessary for writing phase change element PCM. As a result, there is an advantage that the yield of the semiconductor memory device 201 can be improved.

Further, since the driving power of the MOSFET is improved, the number of memory cells included in the memory chain MC can be increased. Furthermore, since the cell area of the memory chain MC can be reduced to 4F2 (F is the minimum processing dimension), which is 6 to 8F2 when the planar MOSFET is used, a large-capacity semiconductor memory device can be realized. it can.

The double-gate NMOSFET has two gate electrodes, and when an on-voltage is applied to both gate electrodes, the MOS is turned on (that is, in a low resistance state). When an on voltage is applied only to one of the gate electrodes, or when an off voltage is applied to all the gate electrodes, the MOS is turned off (that is, a high resistance state is set).

<Application example of double-gate NMOSFET>
Hereinafter, a case where a double gate NMOSFET is used will be described.

The light plate electrode WR is used to supply a write current and an erase current used for writing and erasing. By using the light plate electrode WR having a wide wiring width, a large current required for writing and erasing can be stably supplied, and a highly reliable semiconductor memory device can be realized.

<Operation of lead circuit>
Subsequently, the operation of the read circuit 101 will be described. In the second embodiment, the configuration of the read circuit 101 is the same as that of the read circuit 101 in FIG. 1 of the first embodiment.

FIG. 17 is a timing chart showing an operation example of the read circuit 101 provided in the semiconductor memory device having the memory array 202 of FIG.

In FIG. 17, from the top to the bottom, the cell read voltage V _CELL , reference voltage V _REF , Z selection line Z0-0, Z selection lines Z0-1 to Z0-7, discharge switch DISS, cell read current selection switch CELLS, reference current Signal timings on the selection switch REFS, precharge switch PRES, sense amplifier activation switch SA_ENS, Y selection lines Y0-0, Y0-1, X selection lines X0-0, X0-1, and X selection line X0-2 are respectively shown. Show.

In FIG. 17, assume that a memory cell connected to the Z selection line Z0-0 included in the memory chain MC0-0-0 is selected and read.

While the cell read current flows, the Y selection lines such as Y0-0 and Y0-1 are turned off, and the read bit line RBL and the write plate electrode WR are electrically disconnected. The X selection line X0-0 and the X selection line X0-1 are each turned on, and the selection operation of the memory chain MC0-0-0 is performed. On the other hand, for example, the X selection line X0-2 is turned off.

Note that the cell read current and the reference current flow through the same bit line. The details of the read operation overlapping with the first embodiment will be omitted.

As described above, it is possible to increase the write data rate and the erasing speed by adopting the configuration having the light plate electrode WR.

(Embodiment 3)
<Overview>
In the third embodiment, a semiconductor memory device in which a memory chain is composed of one memory cell will be described. By configuring the memory chain with one memory cell, the read data rate can be increased.

<Configuration of memory array>
FIG. 18 is an explanatory diagram showing an example of a partial circuit configuration of the memory array 202 according to the third embodiment.

As shown in FIG. 18, the memory chain MC included in the memory array 202 has a configuration including one memory cell CELL and an X selection element XMOS. Other configurations are the same as those of the first embodiment shown in FIG.

<Operation of lead circuit>
FIG. 19 is a timing chart showing an operation example of the read circuit provided in the semiconductor memory device having the memory array 202 of FIG. In the third embodiment, the configuration of the read circuit 101 is the same as that of the read circuit 101 in FIG. 1 of the first embodiment.

In FIG. 19, from the top to the bottom, the cell read voltage V _CELL , the reference voltage V _REF , the Z selection line Z 0, the discharge switch DISS, the cell read current selection switch CELLS, the reference current selection switch REFS, the precharge switch PRES, and the sense amplifier activation Signal timings at the switch SA_ENS are shown.

In the case of the memory array 202 shown in FIG. 18, only the Z selection line Z0 exists as the Z selection line. The Z selection line Z0 is turned on when a reference current flows, and the reference current mainly flows through the Z selection transistor ZMOS.

When the cell read current flows, it is turned off, and the cell read current mainly flows through the phase change element PCM. The cell read current and the reference current flow through the same bit line.

Here, we will confirm the characteristics of this configuration again.

・ Multiple memory cells are not connected in series. That is, the semiconductor memory device does not have “a plurality of electrically rewritable memory cells connected in series”. Naturally, since there is no unselected memory cell in the same memory chain as the selected memory cell, it is impossible to “apply a pass voltage that turns on the memory cell regardless of the data”. Furthermore, since there is no non-selected memory cell, the electric resistance of the non-selected memory cell does not exist and it is not necessary to reduce its value.

As described above, the read data rate can be increased.

In the third embodiment, the influence is reduced by the electric resistance of the bit line BL and its variation. Further, the NAND flash memory described in Patent Document 1 is a one-transistor type memory, and the memory cell configuration is different from the 1T-1R type in which one transistor and one resistance element are connected in parallel. For example, in the 1T-1R type, there is no “read voltage at which a memory cell is turned on or off according to the data” described in Patent Document 1 (see abstract).

(Embodiment 4)
<Overview>
In the fourth embodiment, a semiconductor memory device 201 is described in which the value of the reference resistance is changed at the time of reading, at the time of write verify, and at the time of erase verify. As a result, the reliability of the semiconductor memory device can be improved.

<Configuration of lead circuit>
FIG. 20 is an explanatory diagram showing an example of the configuration of the read circuit 101 according to the fourth embodiment.

20 has a configuration in which a switch SW and three reference resistors that are switched by the switch SW are newly provided in the configuration of the read circuit 101 shown in FIG.

The three reference resistors are constituted by a read reference resistor REFR_READ, a write verify reference resistor REFR_WRITEV, and an erase verify reference resistor REFR_ERASEV. The read reference resistor REFR_READ is a first resistor, the erase verify reference resistor REFR_ERASEV is a second resistor, and the write verify reference resistor REFR_WRITEV is a third resistor.

These resistance values are, for example, the read reference resistance REFR_READ is about 1 MΩ, the write verify reference resistance REFR_WRITEV is about 3 MΩ, and the erase verify reference resistance REFR_ERASEV is about 300 kΩ.

That is, the read margin is ensured by setting the resistance value of the read reference resistor REFR_READ between the resistance value of the write verify reference resistor REFR_WRITEV and the erase verify reference resistor REFR_ERASEV.

Note that the resistance value of the read reference resistor REFR_READ is higher than the resistance value of the erase verify reference resistor REFR_ERASEV. Needless to say, the number of reference resistors does not need to be fixed to three types.

For example, the value of the reference resistance can be two types for reading and erasing verification. Since the resistance drift of the phase change element increases with time, a certain degree of reliability can be ensured only by preparing two types for reading and erasing verification.

By reducing the number of reference resistors from three to two, it is possible to reduce the ratio of the reference resistance element to the semiconductor memory device 201, and the semiconductor memory device 201 with a small area and low cost can be realized.

Furthermore, it goes without saying that the number of reference resistors can be four. By changing the value of the reference resistance at the time of “0” 1 ”judgment read,“ 1 ”2” judgment read, “2” 3 ”judgment read, write verify and erase verify A multi-value operation in which more than one bit value is stored in one phase change element can be stably performed.

By changing the reference resistance value between read, write verify, and erase verify, it is possible to provide a large read margin for the resistance value of the phase change element in the write state and the resistance value of the phase change element in the erase state For example, a stable read operation can be performed even when the environmental temperature changes.

(Embodiment 5)
<Overview>
In the fifth embodiment, a read circuit 101 that does not require the reference resistor REFR will be described. As a result, the chip area of the semiconductor memory device is small, and the manufacturing cost is reduced.

<Configuration of lead circuit>
FIG. 21 is an explanatory diagram showing an example of the configuration of the read circuit 101 according to the fifth embodiment.

The read circuit 101 shown in FIG. 21 has a configuration in which the reference resistor REFR is removed from the read circuit 101 of FIG. Other configurations are the same as those in FIG.

The operation of the read circuit 101 not having the reference resistor REFR shown in FIG. 21 will be described.

In this case, the sense amplifier SA compares the cell read voltage V _CELL with the reference voltage V _REF and determines the value recorded in the memory cell CELL using, for example, the following formulas (5) and (6).

V _CELL > reference voltage V _REF × 0.8 → cell is in high resistance state, value is '0' (5)
V _CELL ≤ reference voltage V _REF × 0.8 → cell is in low resistance state, value is '1' (6)
Here, the value of 0.8 times is merely an example, and it goes without saying that the value is actually set appropriately according to the configuration of the memory array. For example, when the size of the memory array is small and the bit line resistance is small, a value smaller than 0.8 is desirable.

Regarding the configuration of the sense amplifier SA, the sense amplifier SA preferably includes a current mirror circuit. By using the current mirror circuit, the values of “0” and “1” can be determined with high accuracy.

The sense amplifier shown in the example with a magnification of 0.8 can be adjusted by changing the driving power by changing the gate width of the transistor used to compare the voltages of the two included in the current mirror circuit.

Instead of changing the circuit configuration of the sense amplifier SA, the precharge voltage is changed by the cell read voltage and the reference voltage. For example, the voltage to be precharged to the cell read voltage is 1 V, and the voltage to be precharged to the reference voltage is 0. Needless to say, it can be set to 8V. Furthermore, it goes without saying that the time for supplying the cell read current and the current for supplying the reference current are changed. For example, the cell read current can be supplied for about 500 ns and the reference current can be supplied for about 400 ns.

As described above, the circuit area of the reference resistor can be reduced by not using the reference resistor. Thereby, the chip area can be reduced and the manufacturing cost of the semiconductor memory device can be reduced.

101 Read Circuit 102 Erase Circuit 201 Semiconductor Memory Device 202 Memory Array 501 Read Circuit 502 Column Decoder 503 Row Decoder 504 Pad Unit 1001 Row System Circuit 1002 Column System Circuit 1003 Control System Circuit 1004 Power Supply Circuit MC Memory Chain XMOS Select Element CELL Memory Cell PCM Phase change element ZMOS Z selection transistor Z0 to Z3 Z selection line Z Z selection line X X selection line BL Bit line PROGS Erase selection switch REFR Reference resistance CELLS Cell read current selection switch REFS Reference current selection switch DISS Discharge switch PRES Precharge switch SA_ENS Sense Amplifier activation switch SA Sense amplifier CCELL Cell read voltage holding capacitor CREF Reference voltage holding capacitor CCEL Cell read voltage holding capacitor SL source electrode CH semiconductor chip MRY memory array WR write plate electrode RBL read bit line YDR Y driver SW switch REFR_READ read reference resistor REFR_WRITEV write verify reference resistor REFR_ERASEV for erase verify reference resistor

Claims

A memory array having a plurality of storage units for storing information;
A read circuit having a first read mode and a second read mode, for reading data stored in the storage unit;
Have
The storage unit includes at least one memory cell,
The memory cell is
A storage element having at least a first storage state and a second storage state due to a difference in electrical resistance;
The first read mode is a mode in which all the storage elements of the storage unit are deselected and a precharge voltage is supplied to the storage unit,
The second read mode is a mode in which the storage element of the storage unit is selected and the precharge voltage is supplied to the storage unit,
The read circuit determines a read data by comparing a reference current flowing through the storage unit in the first read mode with a cell read current flowing through the storage unit in the second read mode. .
The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the read circuit acquires the cell read current and the reference current from the same bit line to which the storage unit selected in the first read mode and the second read mode is connected, respectively. .
The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the read circuit includes a reference resistor that limits a current flowing through the storage unit selected in the first read mode, and sets the reference current by the reference resistor.
The semiconductor memory device according to claim 3.
The reference resistance is
A first resistor having a first resistance value;
A second resistor having a second resistance value;
With
The read circuit obtains the reference current using the first resistor during reading in the first read mode, and determines whether the data has been correctly erased during the erase verify. A semiconductor memory device that obtains the reference current using a resistance of 2.
The semiconductor memory device according to claim 4.
The semiconductor memory device, wherein the first resistor has a higher resistance value than the second resistor.
The semiconductor memory device according to claim 5.
Further, the reference resistor includes a third resistor having a third resistance value,
The semiconductor memory device, wherein the read circuit acquires the reference current by using the third resistor during a write verify that determines whether data has been correctly written.
The semiconductor memory device according to claim 6.
The semiconductor memory device, wherein the third resistance value is lower than the first resistance and higher than the second resistance.
The semiconductor memory device according to claim 1.
The read circuit includes a sense amplifier that differentially amplifies an input signal, and compares the cell read current and the reference current by the sense amplifier.
The semiconductor memory device according to claim 8.
The sense amplifier has a current mirror circuit,
In the semiconductor memory, the driving power of a transistor used in a reference current side circuit to which the reference current is input is different from a driving power of a transistor used in a cell read current side circuit to which the cell read current is input. apparatus.
The semiconductor memory device according to claim 1.
The readout circuit is
A reference voltage holding capacitor for storing a reference voltage generated based on the reference current;
A cell lead voltage holding capacitor for storing a cell lead voltage generated based on the cell lead current;
Have
The semiconductor memory device, wherein the read circuit determines the read data by comparing voltages stored in the reference voltage holding capacitor and the cell read voltage holding capacitor.
The semiconductor memory device according to claim 10.
The read circuit performs a precharge operation of storing the precharge voltage in the reference voltage holding capacitor and the cell read voltage holding capacitor, and then the reference in which the precharge voltage is charged in the first read mode. The remaining voltage after flowing the reference current from the voltage holding capacitor for a certain time is obtained as the reference voltage, and the remaining voltage after flowing the reference current from the cell read voltage holding capacitor charged with the precharge voltage for a certain time Is obtained as the cell read voltage and compared.
The semiconductor memory device according to claim 11.
The semiconductor memory device, wherein the read circuit simultaneously performs a precharge operation on the reference voltage holding capacitor and the cell read voltage holding capacitor.
The semiconductor memory device according to claim 12.
The semiconductor memory device, wherein the precharge voltage stored in the reference voltage holding capacitor is different from the precharge voltage stored in the cell read voltage holding capacitor.
The semiconductor memory device according to claim 11.
The semiconductor memory device, wherein the memory element is a phase change memory.