WO2016045075A1 - 生成随机序列的方法和装置 - Google Patents

生成随机序列的方法和装置 Download PDF

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Publication number
WO2016045075A1
WO2016045075A1 PCT/CN2014/087497 CN2014087497W WO2016045075A1 WO 2016045075 A1 WO2016045075 A1 WO 2016045075A1 CN 2014087497 W CN2014087497 W CN 2014087497W WO 2016045075 A1 WO2016045075 A1 WO 2016045075A1
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sequence
pulse
pulse sequence
period
target
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PCT/CN2014/087497
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English (en)
French (fr)
Inventor
游飞
郝鹏
孔翔鸣
谷卫东
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华为技术有限公司
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Priority to CN201480079692.1A priority Critical patent/CN106462387B/zh
Priority to PCT/CN2014/087497 priority patent/WO2016045075A1/zh
Publication of WO2016045075A1 publication Critical patent/WO2016045075A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators

Definitions

  • the present invention relates to the field of communications, and in particular, to a method and apparatus for generating a random sequence in the field of communications.
  • transceivers have been widely used in various electronic devices.
  • a new type of transceiver that processes multi-band signals at the same time, it is necessary to use a multi-harmonic signal of a complex mode as a local oscillator signal of the mixer to mix with the multi-band input signal.
  • High-speed periodic random sequences have rich high-frequency harmonic components, and at the same time ensure sufficient independence between these harmonic signals, so high-speed periodic random sequences can be used to generate the multi-harmonic signals required by the new transceiver.
  • FPGA Field-Programmable Gate Array
  • Table 1 shows the current price changes of mainstream FPGAs along with the IO port rate. It can be seen that when the rate of random sequences that need to be output is high, the price of the required FPGA is greatly increased, especially after the IO port rate exceeds 6 Gbps. The hardware cost of the FPGA is very high.
  • Embodiments of the present invention provide a method and apparatus for generating a random sequence, which can generate a high speed random sequence using a lower cost.
  • an apparatus for generating a random sequence comprising: a first generating unit, configured to generate a first pulse sequence according to a target rate and a target sequence period, the first pulse sequence listed as a random pulse sequence, and the rate of the first pulse sequence is lower than the target rate, the sequence period of the first pulse sequence is the target sequence period, and the minimum width of the pulse of the first pulse sequence More than a first threshold; a second generating unit, configured to generate a second pulse sequence, the second pulse sequence is a narrow pulse sequence, and a sequence period of the second pulse sequence is the target sequence period, the narrow pulse sequence The width of the pulse is smaller than the first threshold; the superimposing unit is configured to superimpose the first pulse sequence generated by the first generating unit and the second pulse sequence generated by the second generating unit A random sequence such that a pulse of the second pulse sequence is superimposed on a low level of the first pulse sequence.
  • the first generating unit is configured to: generate the first pulse sequence according to the target rate and the target sequence period, so that The minimum width of the pulse of the first pulse sequence is R/f max , and the sequence period is T, wherein f max is the highest frequency corresponding to the target rate, and R is the target rate and the rate of the first pulse sequence The ratio, T is the target sequence period.
  • the second generating unit is specifically configured to: generate the second pulse sequence, so that the second The pulse sequence has a pulse width of 1/f max and a sequence period of T.
  • the second generating unit Specifically, the generating, according to the first pulse sequence generated by the first generating unit, generating the second pulse sequence, so that a rising edge of a pulse of the first pulse sequence generated by the first generating unit is A narrow pulse is formed, and a plurality of narrow pulses constitute the second pulse sequence.
  • the second generating unit is specifically configured to: use the first generated by the first generating unit A pulse sequence, an excitation step recovery diode SRD generates the second pulse sequence.
  • the superimposing unit is specifically used And shifting the first pulse sequence generated by the first generating unit and/or the second pulse sequence generated by the second generating unit, so that the first pulse sequence and the second When the pulse sequence is superimposed, the second pulse sequence is superimposed on a corresponding low level of the first pulse sequence.
  • a method of generating a random sequence comprising: Rate and target sequence periods generate a first pulse sequence, the first pulse sequence is a random pulse sequence, and the rate of the first pulse sequence is lower than the target rate, and the sequence period of the first pulse sequence is a target sequence period, a minimum width of a pulse of the first pulse sequence is greater than a first threshold; a second pulse sequence is generated, the second pulse sequence is a narrow pulse sequence, and a sequence period of the second pulse sequence is a target sequence period, a width of a pulse of the narrow pulse sequence being less than the first threshold; superimposing the first pulse sequence and the second pulse sequence as the random sequence such that a pulse of the second pulse sequence Superimposed on the low level of the first pulse sequence.
  • the generating the first pulse sequence according to the target rate and the target sequence period comprises: generating the according to the target rate and the target sequence period a first pulse sequence such that a minimum width of the pulse of the first pulse sequence is R/f max and a sequence period is T, wherein f max is the highest frequency corresponding to the target rate, and R is the target rate and The ratio of the rates of the first pulse sequence, T is the target sequence period.
  • the generating the second pulse sequence includes: generating a second pulse sequence, such that the second pulse sequence The pulse width is 1/f max and the sequence period is T. .
  • the generating the second pulse a sequence comprising: generating, according to the first pulse sequence, the second pulse sequence such that a narrow pulse is formed at a rising edge of a pulse of the first pulse sequence, and a plurality of narrow pulses constitute the second pulse sequence
  • the generating, according to the first pulse sequence, generating the second pulse sequence includes: The first pulse sequence, the excitation step recovery diode SRD generates the second pulse sequence. .
  • Superimposing a pulse sequence and the second pulse sequence as the random sequence comprises: shifting the first pulse sequence and/or the second pulse sequence such that the first pulse sequence and the first When the two pulse sequences are superimposed, the second pulse sequence is superimposed on a corresponding low level of the first pulse sequence.
  • the method and apparatus for generating a random sequence provided by the embodiments of the present invention can generate randomness and richness by superimposing a low-speed random sequence and a narrow pulse sequence. A random sequence of high frequency components at a lower cost.
  • FIG. 1 is a schematic block diagram of an apparatus for generating a random sequence in accordance with one embodiment of the present invention.
  • FIG. 2 is a schematic diagram of port voltage and current waveforms of an SRD in accordance with one embodiment of the present invention.
  • FIG. 3 is a schematic block diagram of an apparatus for generating a random sequence in accordance with one embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method of generating a random sequence in accordance with one embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a method of generating a random sequence according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a method of generating a random sequence, in accordance with one embodiment of the present invention.
  • FIG. 1 shows a schematic block diagram of an apparatus 100 for generating a random sequence in accordance with an embodiment of the present invention.
  • the apparatus 100 for generating a random sequence includes:
  • the first generating unit 110 is configured to generate a first pulse sequence according to the target rate and the target sequence period, the first pulse sequence is a random pulse sequence, and the rate of the first pulse sequence is lower than the target rate, and the sequence sequence of the first pulse sequence For the target sequence period, the minimum width of the pulse of the first pulse sequence is greater than the first threshold;
  • the second generating unit 120 generates a second pulse sequence, the second pulse sequence is a narrow pulse sequence, the sequence period of the second pulse sequence is a target sequence period, and the pulse width of the narrow pulse sequence is smaller than the first threshold;
  • the superimposing unit 130 is configured to superimpose the first pulse sequence generated by the first generating unit 110 and the second pulse sequence generated by the second generating unit 120 into a random sequence, so that the pulse of the second pulse sequence is superimposed on the low of the first pulse sequence. Level.
  • the apparatus 100 for generating a random sequence replaces the high speed random sequence by superimposing a low speed random sequence, that is, a first pulse sequence, with at least one narrow pulse sequence, that is, a second pulse sequence.
  • the random sequence obtained by the superposition has both good randomness and rich high-frequency components, which can meet the requirements of the new transceiver, and the cost of the device for generating the low-speed random sequence and the narrow pulse sequence is lower than that of directly generating the high-speed random sequence. s installation.
  • the low-speed random sequence may be generated by the first generating unit 110, for example, by an FPGA, or may be generated by other commonly used means, such as by using a logic method such as a shift register, or may be a digital signal processor (Digital Signal Processor) , DSP) generation, this embodiment of the present invention does not limit this.
  • the generated low-speed random sequence is generated according to the rate of the finally required high-speed random sequence, that is, the target rate, and the sequence period of the finally required high-speed random sequence, that is, the target sequence period.
  • the generated first pulse sequence that is, the rate of the low-speed random sequence is lower than the target rate, and the sequence period is the target sequence period.
  • the generated low-speed random sequence corresponds to the finally required high-speed random sequence
  • the sequence period including the low-speed random sequence corresponds to the sequence period of the high-speed random sequence
  • the pulse width of the low-speed random sequence and the pulse of the high-speed random sequence The width corresponds. That is, the minimum width of the pulse of the first pulse sequence is greater than the first threshold, and the first threshold should be greater than or equal to the minimum width of the pulse of the high-speed random sequence to ensure that the rate of the first pulse sequence is decreased relative to the high-speed random sequence. of.
  • the narrow pulse sequence can be generated by the second generation unit 120, for example, by a Step Recovery Diode (SRD).
  • SRD Step Recovery Diode
  • Figure 2 is a schematic diagram of the port voltage and current waveforms of the SRD.
  • SRD is a special varactor.
  • Very narrow pulse voltage, and the position and width of the narrow pulse can be adjusted by changing the parameters of the analog device or by changing the pulse of the excited SRD.
  • the method is simple and convenient to use.
  • the narrow pulse sequence can also be obtained by other methods. For example, a digital logic circuit can be designed to obtain a triggering narrow pulse, which is not limited by the embodiment of the present invention.
  • the sequence period of the generated second pulse sequence, that is, the narrow pulse sequence is also the target sequence period.
  • the width of the pulse of the narrow pulse sequence in embodiments of the present invention is less than the first threshold, for example, the width of the pulse is less than 1 [mu]S or the duty cycle of the pulse is less than 10% or 20%, which may be considered a narrow pulse.
  • the width of the pulse of the narrow pulse sequence is smaller than the first threshold, and it can be ensured that the random sequence obtained by the last superposition has rich high frequency components.
  • the superimposing unit 130 generates the low-speed random sequence and the second generating unit generated by the first generating unit 110
  • the narrow pulse sequence generated by 120 is superimposed such that the pulse of the narrow pulse sequence is superimposed on the low level of the low-speed random sequence, and a superimposed random sequence can be obtained. If necessary, a narrow pulse sequence can be superimposed on the low-speed random sequence. When the high-frequency component of the obtained pulse sequence is still insufficient, a plurality of narrow pulse sequences can be superimposed, which is not limited in the embodiment of the present invention. After the superimposed random sequence is obtained, the superimposed random sequence can be output through the output port as a local oscillator sequence signal.
  • the apparatus for generating a random sequence provided by the embodiment of the present invention can generate a random sequence with good randomness and rich high-frequency components by superimposing a low-speed random sequence, that is, a first pulse sequence and a narrow pulse sequence, that is, a second pulse sequence. And the cost is lower.
  • the first generating unit 110 may be specifically configured to:
  • the first generating unit 110 generates a low-speed random sequence of a rate 1/R of a high-speed random sequence as a basis, and then superimposes the high-frequency component on the low-speed random sequence.
  • the low-speed random sequence provides good randomness for the random sequence generated by the final superposition, and if the low-speed random sequence is generated by using the FPGA, the output rate of the IO port is reduced to 1/1 compared with the direct generation of the high-speed random sequence. R, can greatly reduce the cost of the FPGA.
  • the second generating unit 120 is specifically configured to:
  • a second pulse sequence is generated such that the pulse width of the second pulse sequence is 1/f max and the sequence period is T.
  • the narrow pulse sequence generated by the second generation unit 120 can ensure that the random sequence obtained by the final superposition has sufficient high frequency components. Since the highest frequency of the pulse of the high-speed random sequence as the local oscillation signal is f max and the width of the pulse having the highest frequency is 1/f max , the pulse width of the narrow pulse is 1/f max . In addition, since the generated low-speed random sequence and the narrow pulse sequence need to be superimposed, the relative positions of the high-level and low-level of the generated narrow pulse sequence should be as close as possible to the high-level and low-level positions of the low-speed random sequence. The sequence period should also be consistent to T.
  • the system itself needs a high-speed random sequence with a length of 160 bits as the local oscillator signal, and the sequence period is T, and the length of each bit is T/160. Then, a low-speed random sequence of 20 bits in length can be generated through the FPGA, and the length of each bit is T/20. Then a narrow pulse sequence with a width of T/160 is generated, and the sequence period is also T, so that the pulse of the narrow pulse sequence is superimposed on the low level of the low-speed random sequence, and the random sequence thus obtained is obtained sufficiently high.
  • the frequency component reduces the rate of the output of the IO port to 1/8 of the original when the randomness is guaranteed.
  • the second generating unit 120 is specifically configured to:
  • a simple method of generating a narrow pulse sequence may be to generate a pulse sequence identical to the first pulse sequence generated by the first generation unit 110, and use the pulse sequence to excite the second generation unit 120 to obtain each A narrow pulse sequence in which the relative position of the pulse low level coincides with the relative position of each pulse low level of the low speed random sequence, the generated narrow pulse sequence is more easily superimposed with the low speed random sequence to obtain the required high speed random sequence.
  • the second generating unit 120 may include an SRD.
  • the first pulse sequence generated by the first generating unit 110 activates the step recovery diode SRD to generate a second pulse sequence.
  • the generated first pulse sequence is taken as an input to the SRD to excite the SRD.
  • the SRD generates a narrow pulse at the rising edge of each pulse of the input low-speed random sequence, and the other positions return to a low level. Therefore, the narrow pulse of the narrow pulse sequence generated by the method and the rising edge of each pulse of the low-speed random sequence are generated.
  • the desired random sequence can be obtained.
  • the superposition unit 130 is specifically configured to:
  • the first pulse sequence generated by the first generation unit 110 and/or the second pulse sequence generated by the second generation unit 120 are shifted such that when the first pulse sequence and the second pulse sequence are superimposed, the second pulse sequence is superimposed A pulse sequence corresponds to a low level.
  • the superimposing unit 130 superimposes the low-speed random sequence generated by the first generating unit 110 and the narrow pulse sequence generated by the second generating unit 120 such that the pulse of the narrow pulse sequence is superimposed on the low level of the pulse of the low-speed random sequence.
  • the direct superposition of the low-speed random sequence generated by the first generating unit 110 and the narrow pulse sequence generated by the second generating unit 120 may superimpose the high level of the narrow pulse sequence on the high level of the low-speed random sequence, so that Superimposed random sequence It has a rich effect of high frequency components. Therefore, when superimposing the generated two sequences, it is necessary to shift the low-speed random sequence and/or the narrow pulse sequence as necessary.
  • the method of shifting the pulse sequence may be performed by adding a delay line to the output device of the pulse sequence or by shifting the clocks of the two pulse sequences, which is not limited in this embodiment of the present invention.
  • the apparatus for generating a random sequence provided by the embodiment of the present invention can generate a random sequence simply by superimposing a low-speed random sequence generated by an FPGA, that is, a first pulse sequence and a narrow pulse sequence generated by an SRD, that is, a second pulse sequence.
  • the random sequence has good randomness and rich high frequency components, and the cost is low.
  • the apparatus 200 includes a programmable gate array FPGA 210, a differential amplifier 220, a step recovery diode SRD 230, a voltage comparator 240, a voltage comparator 250, and an output port 260.
  • the FPGA 210 is configured to generate two identical low-speed random sequences, that is, a first pulse sequence and a third pulse sequence, and output the first pulse sequence and the third pulse sequence from the FPGA 210, respectively.
  • the first pulse sequence and the third pulse sequence are amplified by a differential amplifier 220, respectively.
  • the differential signal is converted into a single-ended signal by the voltage comparator 240, and may further include a delay device (not shown, such as a delay line, etc.) to shift the first pulse sequence.
  • the third pulse sequence is amplified and input into the SRD 230 to excite the SRD 230 to generate a narrow pulse sequence corresponding to the first pulse sequence, that is, the second pulse sequence, and the second pulse sequence also passes through the voltage comparator 240.
  • the differential signal is converted to a single-ended signal, which can then be shifted by a delay device (not shown) to facilitate superposition with the first pulse sequence.
  • the shifted first pulse sequence and the second pulse sequence input voltage comparator are superimposed such that the second pulse sequence is superimposed on the low level of the pulse corresponding to the first pulse sequence, and the superimposed pulse sequence is output from the output port For subsequent processing.
  • the delay device may be disposed in both the first pulse sequence and the second pulse sequence, or may be set only in one path, so that the second pulse sequence is superimposed on the low level of the pulse corresponding to the first pulse sequence. Just go up.
  • the first pulse sequence and the third pulse sequence are amplified by a differential amplifier.
  • the pulse sequence may not be amplified, or may be amplified by other devices, which is not used in the embodiment of the present invention. limited.
  • the superimposed pulse sequence output from the output port can also be amplified by a wideband amplifier and input to the local oscillator terminal of the mixer.
  • FIG. 4 shows a schematic flow diagram of a method 300 of generating a random sequence in accordance with an embodiment of the present invention. As shown in FIG. 4, the method 300 of generating a random sequence includes:
  • the first pulse sequence is a random pulse sequence, and the rate of the first pulse sequence is lower than the target rate, and the sequence period of the first pulse sequence is the target sequence period,
  • the minimum width of the pulse of a pulse sequence is greater than the first threshold
  • the second pulse sequence is a narrow pulse sequence
  • the sequence period of the second pulse sequence is a target sequence period
  • the pulse width of the narrow pulse sequence is less than the first threshold
  • embodiments of the present invention replace high speed random sequences by superimposing a low speed random sequence, a first pulse sequence, with at least one narrow pulse sequence, ie, a second pulse sequence.
  • the random sequence obtained by the superposition has both good randomness and rich high-frequency components, which can meet the requirements of the new transceiver, and the cost of the device for generating the low-speed random sequence and the narrow pulse sequence is lower than that of directly generating the high-speed random sequence. s installation.
  • the low-speed random sequence may be generated by using an FPGA, or may be generated by other common means, such as using a logic method such as a shift register, or may be generated by using a DSP, which is not limited by the embodiment of the present invention.
  • the generated low-speed random sequence is generated according to the rate of the finally required high-speed random sequence, that is, the target rate, and the sequence period of the finally required high-speed random sequence, that is, the target sequence period.
  • the generated first pulse sequence that is, the rate of the low-speed random sequence is lower than the target rate, and the sequence period is the target sequence period.
  • the generated low-speed random sequence corresponds to a high-speed random sequence that needs to be generated finally
  • the sequence period including the low-speed random sequence corresponds to the sequence period of the high-speed random sequence
  • the pulse width of the low-speed random sequence and the pulse of the high-speed random sequence The width corresponds. That is, the minimum width of the pulse of the first pulse sequence is greater than the first threshold, and the first threshold should be greater than or equal to the minimum width of the pulse of the high-speed random sequence to ensure that the rate of the first pulse sequence is decreased relative to the high-speed random sequence. of.
  • the narrow pulse sequence can be generated by a Step Recovery Diode (SRD).
  • SRD is a special varactor. During the SRD from forward conduction to reverse conduction (current changes from -I 0 to I 0 and time t a becomes T 1 ), a SRD is generated at both ends.
  • Very narrow pulse voltage, and the position and width of the narrow pulse can be adjusted by changing the parameters of the analog device or by changing the pulse of the excited SRD.
  • the method is simple and convenient to use.
  • the narrow pulse sequence can also be obtained by other methods. For example, a digital logic circuit can be designed to obtain a triggering narrow pulse, which is not limited by the embodiment of the present invention.
  • the sequence sequence of the generated second pulse sequence i.e., the narrow pulse sequence, is also the target sequence period.
  • the width of the pulse of the narrow pulse sequence in embodiments of the present invention is less than the first threshold, for example, the width of the pulse is less than 1 [mu]S or the duty cycle of the pulse is less than 10% or 20%, which may be considered a narrow pulse.
  • the width of the pulse of the narrow pulse sequence is smaller than the first threshold, and it can be ensured that the random sequence obtained by the last superposition has rich high frequency components.
  • the low-speed random sequence and the narrow pulse sequence are superimposed such that the pulse of the narrow pulse sequence is superimposed on the low level of the pulse of the low-speed random sequence, and a high-speed random sequence can be obtained. If necessary, a narrow pulse sequence can be superimposed on the low-speed random sequence. When the high-frequency component of the obtained pulse sequence is still insufficient, a plurality of narrow pulse sequences can be superimposed, which is not limited in the embodiment of the present invention. After the superimposed random sequence is obtained, the superimposed random sequence can be output through the output port as a local oscillator sequence signal.
  • the apparatus for generating a random sequence provided by the embodiment of the present invention can generate a random sequence with good randomness and rich high-frequency components by superimposing a low-speed random sequence, that is, a first pulse sequence and a narrow pulse sequence, that is, a second pulse sequence. And the cost is lower.
  • S310 generates a first pulse sequence according to the target rate and the target sequence period, including:
  • the width (ie, the duration length) of the pulse having the highest frequency is 1/f max .
  • a low-speed random sequence having a rate of 1/R of a high-speed random sequence is generated as a basis, and high-frequency components are superimposed on the low-speed random sequence.
  • the low-speed random sequence provides good randomness for the random sequence generated by the final superposition, and if the low-speed random sequence is generated by using the FPGA, the output rate of the IO port is reduced to 1/1 compared with the direct generation of the high-speed random sequence. R, can greatly reduce the cost of the FPGA.
  • S320 generates a second pulse sequence, including:
  • a second pulse sequence is generated such that the pulse width of the second pulse sequence is 1/f max and the sequence period is T.
  • the narrow pulse sequence can ensure that the random sequence resulting from the final superposition has sufficient high frequency components. Since the highest frequency of the pulse of the high-speed random sequence as the local oscillation signal is f max and the width of the pulse having the highest frequency is 1/f max , the pulse width of the narrow pulse is 1/f max . In addition, since the generated low-speed random sequence and the narrow pulse sequence need to be superimposed, the relative positions of the high-level and low-level of the generated narrow pulse sequence should be as close as possible to the high-level and low-level positions of the low-speed random sequence. The sequence period should also be consistent to T.
  • S320 generates a second pulse sequence, including:
  • the excitation generates a second pulse sequence such that a narrow pulse is formed at a rising edge of the pulse of the first pulse sequence, and a plurality of narrow pulses constitute the second pulse sequence.
  • a simple method of generating a narrow pulse sequence may be to generate a pulse sequence identical to the low-speed random sequence, and use the pulse sequence to excite a device that can generate a narrow pulse sequence, and obtain a relative low level of each pulse.
  • a narrow pulse sequence whose position coincides with the relative position of each pulse low level of the low-speed random sequence, the generated narrow pulse sequence is more easily superimposed with the low-speed random sequence to obtain the required high-speed random sequence.
  • generating a second pulse sequence according to the first pulse sequence comprises:
  • the excitation SRD generates a second pulse sequence based on the first pulse sequence.
  • the first pulse sequence is taken as the input to the SRD to excite the SRD.
  • the SRD generates a narrow pulse at the rising edge of each pulse of the input low-speed random sequence, and the other positions return to a low level. Therefore, the narrow pulse of the narrow pulse sequence generated by the method and the rising edge of each pulse of the low-speed random sequence are generated. To the correspondence, by appropriate processing and superimposing with the first pulse sequence, the desired random sequence can be obtained.
  • S330 superimposes the first pulse sequence and the second pulse sequence into a random sequence, including:
  • the first pulse sequence and/or the second pulse sequence are shifted such that when the first pulse sequence and the second pulse sequence are superimposed, the second pulse sequence is superimposed on a corresponding low level of the first pulse sequence.
  • the generated low-speed random sequence and the narrow pulse sequence are superimposed such that the pulse of the narrow pulse sequence is superimposed on the low level of the pulse of the low-speed random sequence.
  • the direct superposition of the generated low-speed random sequence and the narrow pulse sequence may superimpose the high level of the narrow pulse sequence on the high level of the low-speed random sequence, so that the random sequence obtained by the superposition has rich high-frequency components. effect. Therefore, when superimposing the generated two sequences, it is necessary to shift the low-speed random sequence and/or the narrow pulse sequence as necessary.
  • the means of shifting the pulse sequence can be done by adding a delay to the output device The line, or the clocks of the two pulse sequences are staggered, which is not limited by the embodiment of the present invention.
  • the method for generating a random sequence provided by the embodiment of the present invention can easily generate a high-speed random sequence by superimposing a low-speed random sequence, that is, a first pulse sequence and a narrow pulse sequence, that is, a second pulse sequence, and the generated high-speed random sequence has Good randomness and rich high frequency components, and low cost.
  • a method 400 for generating a random sequence according to an embodiment of the present invention will be described in detail below with reference to a specific example. As shown in FIG. 5, the method 400 includes:
  • S410 Generate, according to the high-speed random sequence generated, a low-speed random sequence corresponding to the high-speed random sequence by the FPGA.
  • the highest frequency of the pulse of the high-speed random sequence is f max
  • the corresponding pulse width is 1/f max
  • the sequence period is T
  • the width of the pulse of the highest frequency of the generated low-speed random sequence R/f max is T
  • the waveform diagram of the generated low-speed random sequence is as shown in FIG. 6A.
  • S420 input a pulse sequence identical to the low-speed random sequence generated in S410 into the SRD to excite the SRD.
  • a narrow pulse sequence is generated by the SRD.
  • the pulse width of the narrow pulse sequence is 1/f max and the sequence period is T.
  • the waveform diagram is as shown in FIG. 6B.
  • the following is an analysis of the low-speed random sequence obtained by the above method and the random sequence obtained by superposition, and the randomness of the high-speed random sequence directly generated by the FPGA.
  • the power density at different frequencies can be characterized by normalized Fourier coefficients of different frequencies.
  • the Toeplitz matrix is constructed by the Fourier coefficient vector, the matrix of the autocorrelation coefficients of the matrix is calculated, and then the randomness is characterized by the magnitude of the elements of the autocorrelation coefficient matrix.
  • the high-speed random sequence directly generated by the FPGA has low correlation and good randomness.
  • the low-frequency random sequence generated by the FPGA has a low amplitude of high-frequency components, a strong correlation of sequences, and poor randomness.
  • the random sequence obtained by superimposing the low-speed random sequence and the narrow pulse sequence has a significantly improved power density of the high-frequency component compared with the original low-speed random sequence, and the randomness also has a much improved low-speed random sequence.
  • the method for generating a random sequence provided by the embodiment of the present invention is generated by using an FPGA.
  • the low-speed random sequence that is, the first pulse sequence and the narrow pulse sequence generated by the SRD, that is, the second pulse sequence are superimposed, can easily generate a random sequence, and the generated random sequence has good randomness and rich high-frequency components, and the cost is low. .
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the execution order of each process should be determined by its function and internal logic, and should not be implemented in the embodiments of the present invention.
  • the process constitutes any limitation.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

本发明公开了一种生成随机序列的方法和装置，该装置包括：第一生成单元，用于根据目标速率和目标序列周期生成第一脉冲序列，第一脉冲序列为随机的脉冲序列，并且第一脉冲序列的速率低于目标速率，序列周期为目标序列周期；第二生成单元，生成第二脉冲序列，第二脉冲序列为窄脉冲序列，第二脉冲序列的序列周期为目标序列周期，窄脉冲序列的脉冲的宽度小于第一阈值；叠加单元，用于将第一生成单元生成的第一脉冲序列和第二生成单元生成的第二脉冲序列叠加为随机序列，使得第二脉冲序列的脉冲叠加在第一脉冲序列的低电平上。本发明实施例提供的生成随机序列的方法和装置，可以生成随机性良好且具有丰富的高频分量的随机序列，并且成本较低。

Description

生成随机序列的方法和装置 技术领域
本发明涉及通信领域，尤其涉及通信领域中的生成随机序列的方法和装置。
背景技术
在通信技术突飞猛进的今天，电子设备的种类和数量也成倍地增长，各种电子设备中大量用到收发信机。在同时处理多带信号的新型收发信机中，需要使用复杂模式的多谐波信号作为混频器的本振信号，与多带输入信号进行混频。高速周期随机序列拥有丰富的高频谐波分量，同时可以保证这些谐波信号之间有足够的独立性，因此可以用高速周期随机序列来产生该新型收发信机所需的多谐波信号。
一般可以用现场可编程门阵列(Field－Programmable Gate Array，FPGA)来产生随机序列，但当所需随机序列的速率很高时，FPGA需要支持高速IO口(如GTH端口和GTX端口)，只能选用高端FPGA，这样就大大提高了收发信机系统的成本。
表1为目前市面上主流FPGA价格随IO端口速率的变化情况说明，可以看到，当需要输出的随机序列的速率较高时，所需FPGA的价格大大提高，特别是IO端口速率超过6Gbps以后，FPGA的硬件成本很高。
表1目前市面主流FPGA IO端口速率与FPGA价格说明
型号 Spartan-6 Artix-7 Kintex-7 Virtex-7
收发速率 3.2Gbps 6.6Gbps 12.5Gbps 28.05Gbps
参考价格 3000 10000 20000 35000
发明内容
本发明实施例提供一种生成随机序列的方法和装置，可以使用较低的成本生成高速随机序列。
第一方面，提供了一种生成随机序列的装置，该装置包括：第一生成单元，用于根据目标速率和目标序列周期生成第一脉冲序列，所述第一脉冲序 列为随机的脉冲序列，并且所述第一脉冲序列的速率低于所述目标速率，所述第一脉冲序列的序列周期为所述目标序列周期，所述第一脉冲序列的脉冲的最小宽度大于第一阈值；第二生成单元，用于生成第二脉冲序列，所述第二脉冲序列为窄脉冲序列，所述第二脉冲序列的序列周期为所述目标序列周期，所述窄脉冲序列的脉冲的宽度小于所述第一阈值；叠加单元，用于将所述第一生成单元生成的所述第一脉冲序列和所述第二生成单元生成的所述第二脉冲序列叠加为所述随机序列，使得所述第二脉冲序列的脉冲叠加在所述第一脉冲序列的低电平上。
结合第一方面，在第一方面的第一种可能的实现方式中，所述第一生成单元具体用于：根据所述目标速率和所述目标序列周期生成所述第一脉冲序列，使得所述第一脉冲序列的脉冲的最小宽度为R/fmax，序列周期为T，其中，fmax为所述目标速率对应的最高频率，R为所述目标速率与所述第一脉冲序列的速率的比值，T为所述目标序列周期。
结合第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述第二生成单元具体用于：生成所述第二脉冲序列，使得所述第二脉冲序列的脉冲宽度为1/fmax，序列周期为T。
结合第一方面和第一方面的第一种至第二种可能的实现方式中的任一种可能的实现方式，在第一方面的第三种可能的实现方式中，所述第二生成单元具体用于：根据所述第一生成单元生成的所述第一脉冲序列，激发生成所述第二脉冲序列，使得所述第一生成单元生成的所述第一脉冲序列的脉冲的上升沿处形成窄脉冲，多个窄脉冲组成所述第二脉冲序列。
结合第一方面的第三种可能的实现方式，在第一方面的第四种可能的实现方式中，所述第二生成单元具体用于：根据所述第一生成单元生成的所述第一脉冲序列，激发阶跃恢复二极管SRD生成所述第二脉冲序列。
结合第一方面和第一方面的第一种至第四种可能的实现方式中的任一种可能的实现方式，在第一方面的第五种可能的实现方式中，所述叠加单元具体用于：将所述第一生成单元生成的所述第一脉冲序列和/或所述第二生成单元生成的所述第二脉冲序列进行移位，使得所述第一脉冲序列和所述第二脉冲序列叠加时，所述第二脉冲序列叠加在所述第一脉冲序列相对应的低电平上。
第二方面，提供了一种生成随机序列的方法，该方法包括：根据目标速 率和目标序列周期生成第一脉冲序列，所述第一脉冲序列为随机的脉冲序列，并且所述第一脉冲序列的速率低于所述目标速率，所述第一脉冲序列的序列周期为所述目标序列周期，所述第一脉冲序列的脉冲的最小宽度大于第一阈值；生成第二脉冲序列，所述第二脉冲序列为窄脉冲序列，所述第二脉冲序列的序列周期为所述目标序列周期，所述窄脉冲序列的脉冲的宽度小于所述第一阈值；将所述第一脉冲序列和所述第二脉冲序列叠加为所述随机序列，使得所述第二脉冲序列的脉冲叠加在所述第一脉冲序列的低电平上。
结合第二方面，在第二方面的第一种可能的实现方式中，所述根据目标速率和目标序列周期生成第一脉冲序列，包括：根据所述目标速率和所述目标序列周期生成所述第一脉冲序列，使得所述第一脉冲序列的脉冲的最小宽度为R/fmax，序列周期为T，其中，fmax为所述目标速率对应的最高频率，R为所述目标速率与所述第一脉冲序列的速率的比值，T为所述目标序列周期。
结合第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述生成第二脉冲序列，包括：生成第二脉冲序列，使得所述第二脉冲序列的脉冲宽度为1/fmax，序列周期为T。。
结合第二方面和第二方面的第一种至第二种可能的实现方式中的任一种可能的实现方式，在第二方面的第三种可能的实现方式中，所述生成第二脉冲序列，包括：根据所述第一脉冲序列，激发生成所述第二脉冲序列，使得所述第一脉冲序列的脉冲的上升沿处形成窄脉冲，多个窄脉冲组成所述第二脉冲序列
结合第二方面的第三种可能的实现方式，在第二方面的第四种可能的实现方式中，所述根据所述第一脉冲序列，激发生成所述第二脉冲序列，包括：根据所述第一脉冲序列，激发阶跃恢复二极管SRD生成所述第二脉冲序列。。
结合第二方面和第二方面的第一种至第四种可能的实现方式中的任一种可能的实现方式，在第二方面的第五种可能的实现方式中，所述将所述第一脉冲序列和所述第二脉冲序列叠加为所述随机序列，包括：将所述第一脉冲序列和/或所述第二脉冲序列进行移位，使得所述第一脉冲序列和所述第二脉冲序列叠加时，所述第二脉冲序列叠加在所述第一脉冲序列相对应的低电平上。
基于上述技术方案，本发明实施例提供的生成随机序列的方法和装置，通过将低速随机序列和窄脉冲序列叠加，可以生成随机性良好且具有丰富的 高频分量的随机序列，并且成本较低。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明一个实施例的生成随机序列的装置的示意性框图。
图2是根据本发明一个实施例的SRD的端口电压和电流波形示意图。
图3是根据本发明一个实施例的生成随机序列的装置的示意性框图。
图4是根据本发明一个实施例的生成随机序列的方法的示意性流程图。
图5是根据本发明一个实施例的生成随机序列的方法的示意性流程图。
图6是根据本发明一个实施例的生成随机序列的方法的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
图1示出了根据本发明实施例的生成随机序列的装置100的示意性框图。如图1所示，该生成随机序列的装置100包括：
第一生成单元110，用于根据目标速率和目标序列周期生成第一脉冲序列，第一脉冲序列为随机的脉冲序列，并且第一脉冲序列的速率低于目标速率，第一脉冲序列的序列周期为目标序列周期，第一脉冲序列的脉冲的最小宽度大于第一阈值；
第二生成单元120，生成第二脉冲序列，第二脉冲序列为窄脉冲序列，第二脉冲序列的序列周期为目标序列周期，窄脉冲序列的脉冲的宽度小于第一阈值；
叠加单元130，用于将第一生成单元110生成的第一脉冲序列和第二生成单元120生成的第二脉冲序列叠加为随机序列，使得第二脉冲序列的脉冲叠加在第一脉冲序列的低电平上。
具体而言，本发明实施例的生成随机序列的装置100通过将一个低速随机序列即第一脉冲序列，和至少一个窄脉冲序列即第二脉冲序列相叠加来替代高速随机序列。使得叠加得到的随机序列既具有良好的随机性，又具有丰富的高频分量，能够符合新型收发信机的需求，并且生成低速随机序列和窄脉冲序列的装置的成本低于直接产生高速随机序列的装置。
其中，低速随机序列可以通过第一生成单元110生成，例如由FPGA生成，也可以通过其它常用的手段生成，如用移位寄存器等逻辑办法来生成，或者可以用数字信号处理器(Digital Signal Processor，DSP)生成，本发明实施例对此不作限定。所生成的低速随机序列是根据最终需要的高速随机序列的速率即目标速率，以及最终需要的高速随机序列的序列周期即目标序列周期生成的。生成的第一脉冲序列即低速随机序列的速率低于目标速率，序列周期为目标序列周期。相应地，所生成的低速随机序列与最终需要的高速随机序列对应，包括低速随机序列的序列周期与高速随机序列的序列周期相对应，并且低速随机序列的脉冲的宽度与高速随机序列的脉冲的宽度相对应。即第一脉冲序列的脉冲的最小宽度大于第一阈值，该第一阈值应是大于或等于高速随机序列的脉冲的最小宽度的，以保证第一脉冲序列相对于高速随机序列，其速率是下降的。
窄脉冲序列可以通过第二生成单元120生成，例如通过阶跃恢复二极管(Step Recovery Diode，SRD)生成。图2为SRD的端口电压和电流波形示意图。SRD是一种特殊的变容二极管，在SRD由正向导通到反向导通(电流由-I0变为I0，时间为ta变为T1)的过程中，SRD两端会产生一个很窄的脉冲电压，而该窄脉冲的位置和宽度可以通过改变模拟器件的参数，或者通过改变激发SRD的脉冲来调节，方法简单，方便使用。窄脉冲序列还可以通过其它方法获得，例如可以设计数字逻辑电路来获得触发窄脉冲，本发明实施例对此不作限定。所生成的第二脉冲序列即窄脉冲序列的序列周期也为目标序列周期。
应理解，本发明实施例中的窄脉冲序列的脉冲的宽度小于第一阈值，例如，脉冲的宽度小于1μS或者脉冲的占空比小于10％或20％，可以认为该脉冲为窄脉冲。窄脉冲序列的脉冲的宽度小于第一阈值，可以保证最后叠加得到的随机序列具有丰富的高频分量。
叠加单元130将第一生成单元110生成的低速随机序列和第二生成单元 120生成的窄脉冲序列叠加，使得窄脉冲序列的脉冲叠加在低速随机序列的低电平上，可以得到叠加的随机序列。根据需要，可以在低速随机序列上叠加一个窄脉冲序列，当获得的脉冲序列的高频分量仍不足时，可以叠加多个窄脉冲序列，本发明实施例对此不作限定。在得到叠加的随机序列后，可以通过输出端口将叠加的随机序列输出，以作为本振序列信号。
因此，本发明实施例提供的生成随机序列的装置，通过将低速随机序列即第一脉冲序列和窄脉冲序列即第二脉冲序列叠加，可以生成随机性良好且具有丰富的高频分量的随机序列，并且成本较低。
可选地，作为一个实施例，第一生成单元110具体可以用于：
根据目标速率和目标序列周期生成第一脉冲序列，使得第一脉冲序列的脉冲的最小宽度为R/fmax，序列周期为T，其中，fmax为目标速率对应的最高频率，R为目标速率与第一脉冲序列的速率的比值，T为目标序列周期。
具体而言，假设用于作为本振信号的高速随机序列的脉冲的最高频率为fmax，则频率最高的脉冲的宽度(即持续时间长度)为1/fmax。作为本振信号的高速随机序列的序列周期为T，序列长度为N＝T fmax，与谐波的基频信号的序列长度相同。在本发明实施例中，由第一生成单元110生成一个速率为高速随机序列的速率1/R的低速随机序列作为基础，再在该低速随机序列上叠加高频分量。低速随机序列的序列周期为T，序列长度为M＝N/R＝T fmax/R，低速随机序列的脉冲的最小宽度为T/M＝R/fmax。该低速随机序列为最终叠加生成的随机序列提供了良好的随机性，并且如果使用FPGA生成该低速随机序列，相较于直接生成高速随机序列而言，IO端口的输出速率降为原来的1/R，可以大大降低FPGA的成本。
可选地，作为一个实施例，第二生成单元120具体用于：
生成第二脉冲序列，使得第二脉冲序列的脉冲宽度为1/fmax，序列周期为T。
具体而言，第二生成单元120生成的窄脉冲序列可以保证最终叠加得到的随机序列具有足够的高频分量。因为作为本振信号的高速随机序列的脉冲的最高频率为fmax，频率最高的脉冲的宽度为1/fmax，所以该窄脉冲的脉冲宽度为1/fmax。此外，因为需将生成的低速随机序列和窄脉冲序列相叠加，因此生成的窄脉冲序列的高电平和低电平的相对位置与低速随机序列的高电平和低电平的相对位置应尽量一致，序列周期也应一致为T。
下面以一个实例来分析本发明实施例的方案。例如，系统本身需要一个长度为160bit的高速随机序列作为本振信号，序列周期为T，每1bit的长度为T/160。则可以先通过FPGA产生一个长度20bit的低速随机序列，每1bit的长度为T/20。然后生成一个宽度为T/160的窄脉冲序列，其序列周期也为T，使得窄脉冲序列的脉冲叠加在低速随机序列的低电平上，由此获得的随机序列就得到了足够多的高频分量，在保证了随机性的情况下降IO口的输出的速率降低为原来的1/8。
可选地，作为一个实施例，第二生成单元120具体用于：
根据第一生成单元110生成的第一脉冲序列，激发生成第二脉冲序列，使得第一生成单元生成的第一脉冲序列的脉冲的上升沿处形成窄脉冲，多个窄脉冲组成第二脉冲序列。
具体而言，生成窄脉冲序列的一个简便的方法可以是，生成一个与第一生成单元110生成的第一脉冲序列完全相同的脉冲序列，利用该脉冲序列激发第二生成单元120，可以获得各脉冲低电平的相对位置与低速随机序列的各脉冲低电平的相对位置一致的窄脉冲序列，生成的该窄脉冲序列更易于与低速随机序列叠加而获得需要的高速随机序列。
优选地，第二生成单元120可以包括一个SRD。第一生成单元110生成的第一脉冲序列，激发阶跃恢复二极管SRD生成第二脉冲序列。将生成的第一脉冲序列作为SRD的输入，以激发SRD。SRD在输入的低速随机序列的各脉冲的上升沿处产生一个窄脉冲，其它位置恢复为低电平，因此，通过该方法生成的窄脉冲序列的窄脉冲与低速随机序列的各脉冲的上升沿向对应，通过适当的处理后与第一脉冲序列相叠加，就可以获得需要的随机序列。
可选地，叠加单元130具体用于：
将第一生成单元110生成的第一脉冲序列和/或第二生成单元120生成的第二脉冲序列进行移位，使得第一脉冲序列和第二脉冲序列叠加时，第二脉冲序列叠加在第一脉冲序列相对应的低电平上。
具体而言，叠加单元130将第一生成单元110生成的低速随机序列和第二生成单元120生成的窄脉冲序列经过叠加，使得窄脉冲序列的脉冲叠加在低速随机序列的脉冲的低电平上。第一生成单元110生成的低速随机序列和第二生成单元120生成的窄脉冲序列直接叠加可能会将窄脉冲序列的高电平叠加在低速随机序列的高电平上，这样就不能起到使得叠加得到的随机序列 具有丰富的高频分量的效果。因此，将生成的两个序列叠加时，必要时需将低速随机序列和/或窄脉冲序列进行移位。对脉冲序列进行移位的手段可以通过在脉冲序列的输出设备上增加延时线，或者将两个脉冲序列的时钟错开，本发明实施例对此不作限定。
因此，本发明实施例提供的生成随机序列的装置，通过将FPGA生成的低速随机序列即第一脉冲序列和SRD生成的窄脉冲序列即第二脉冲序列叠加，可以简便地生成随机序列，所生成的随机序列有良好的随机性和丰富的高频分量，并且成本较低。
以下将具体介绍本发明一个实施例的生成随机序列的装置200。如图3所示，该装置200包括：可编程门阵列FPGA210、差分放大器220、阶跃恢复二极管SRD230、电压比较器240、电压比较器250和输出端口260。其中，FPGA210用于生成两个完全相同的低速随机序列，即第一脉冲序列和第三脉冲序列，并分别将第一脉冲序列和第三脉冲序列从FPGA210输出。第一脉冲序列和第三脉冲序列分别经过差分放大器220进行放大。第一脉冲序列经放大后，经过电压比较器240把差分信号变成单端信号，在其后还可以包括延时器件(未示出，如延时线等)对第一脉冲序列进行移位，以便于与另一路叠加；第三脉冲序列经放大后输入SRD230中，以激发SRD230生成与第一脉冲序列相对应的窄脉冲序列即第二脉冲序列，第二脉冲序列也经过电压比较器240把差分信号变成单端信号，在其后还可以经过延时器件(未示出)进行移位，以便于与第一脉冲序列叠加。经过移位的第一脉冲序列和第二脉冲序列输入电压比较器进行叠加，使得第二脉冲序列叠加在第一脉冲序列相对应的脉冲的低电平上，叠加后的脉冲序列从输出端口输出，以进行后续处理。
应理解，在第一脉冲序列和第二脉冲序列两路中可以都设置延时器件，也可以仅在一路中设置，使得第二脉冲序列叠加在第一脉冲序列相对应的脉冲的低电平上即可。此外，上述例子中对第一脉冲序列和第三脉冲序列通过差分放大器进行了放大，在本发明实施例中可以不对脉冲序列进行放大，也可以通过其它器件进行放大，本发明实施例对此不作限定。从输出端口输出的叠加的脉冲序列还可以经过宽带放大器放大，输入混频器的本振端。
图4示出了根据本发明实施例的生成随机序列的方法300的示意性流程图。如图4所示，该生成随机序列的方法300包括：
S310，根据目标速率和目标序列周期生成第一脉冲序列，第一脉冲序列为随机的脉冲序列，并且第一脉冲序列的速率低于目标速率，第一脉冲序列的序列周期为目标序列周期，第一脉冲序列的脉冲的最小宽度大于第一阈值；
S320，生成第二脉冲序列，第二脉冲序列为窄脉冲序列，第二脉冲序列的序列周期为目标序列周期，窄脉冲序列的脉冲的宽度小于第一阈值；
S330，将第一脉冲序列和第二脉冲序列叠加为随机序列，使得第二脉冲序列的脉冲叠加在第一脉冲序列的低电平上。
具体而言，本发明实施例通过将一个低速随机序列即第一脉冲序列，和至少一个窄脉冲序列即第二脉冲序列相叠加来替代高速随机序列。使得叠加得到的随机序列既具有良好的随机性，又具有丰富的高频分量，能够符合新型收发信机的需求，并且生成低速随机序列和窄脉冲序列的装置的成本低于直接产生高速随机序列的装置。
其中，低速随机序列可以通过FPGA生成，也可以通过其它常用的手段生成，如用移位寄存器等逻辑办法来生成，或者可以用DSP生成，本发明实施例对此不作限定。所生成的低速随机序列是根据最终需要的高速随机序列的速率即目标速率，以及最终需要的高速随机序列的序列周期即目标序列周期生成的。生成的第一脉冲序列即低速随机序列的速率低于目标速率，序列周期为目标序列周期。相应地，所生成的低速随机序列与最终需要生成的高速随机序列对应，包括低速随机序列的序列周期与高速随机序列的序列周期相对应，并且低速随机序列的脉冲的宽度与高速随机序列的脉冲的宽度相对应。即第一脉冲序列的脉冲的最小宽度大于第一阈值，该第一阈值应是大于或等于高速随机序列的脉冲的最小宽度的，以保证第一脉冲序列相对于高速随机序列，其速率是下降的。
窄脉冲序列可以通过阶跃恢复二极管(Step Recovery Diode，SRD)生成。SRD是一种特殊的变容二极管，在SRD由正向导通到反向导通(电流由-I0变为I0，时间为ta变为T1)的过程中，SRD两端会产生一个很窄的脉冲电压，而该窄脉冲的位置和宽度可以通过改变模拟器件的参数，或者通过改变激发SRD的脉冲来调节，方法简单，方便使用。窄脉冲序列还可以通过其它方法获得，例如可以设计数字逻辑电路来获得触发窄脉冲，本发明实施例对此不作限定。所生成的第二脉冲序列即窄脉冲序列的序列周期也为目 标序列周期。
应理解，本发明实施例中的窄脉冲序列的脉冲的宽度小于第一阈值，例如，脉冲的宽度小于1μS或者脉冲的占空比小于10％或20％，可以认为该脉冲为窄脉冲。窄脉冲序列的脉冲的宽度小于第一阈值，可以保证最后叠加得到的随机序列具有丰富的高频分量。
将低速随机序列和窄脉冲序列叠加，使得窄脉冲序列的脉冲叠加在低速随机序列的脉冲的低电平上，可以得到高速随机序列。根据需要，可以在低速随机序列上叠加一个窄脉冲序列，当获得的脉冲序列的高频分量仍不足时，可以叠加多个窄脉冲序列，本发明实施例对此不作限定。在得到叠加的随机序列后，可以通过输出端口将叠加的随机序列输出，以作为本振序列信号。
因此，本发明实施例提供的生成随机序列的装置，通过将低速随机序列即第一脉冲序列和窄脉冲序列即第二脉冲序列叠加，可以生成随机性良好且具有丰富的高频分量的随机序列，并且成本较低。
可选地，作为一个实施例，S310根据目标速率和目标序列周期生成第一脉冲序列，包括：
根据目标速率和目标序列周期生成第一脉冲序列，使得第一脉冲序列的脉冲的最小宽度为R/fmax，序列周期为T，其中，fmax为目标速率对应的最高频率，R为目标速率与第一脉冲序列的速率的比值，T为目标序列周期。
具体而言，假设用于作为本振信号的高速随机序列的脉冲的最高频率为fmax，则频率最高的脉冲的宽度(即持续时间长度)为1/fmax。作为本振信号的高速随机序列的序列周期为T，序列长度为N＝T fmax，与谐波的基频信号的序列长度相同。在本发明实施例中，生成一个速率为高速随机序列的速率1/R的低速随机序列作为基础，再在该低速随机序列上叠加高频分量。低速随机序列的序列周期为T，序列长度为M＝N/R＝T fmax/R，低速随机序列的脉冲的最小宽度为T/M＝R/fmax。该低速随机序列为最终叠加生成的随机序列提供了良好的随机性，并且如果使用FPGA生成该低速随机序列，相较于直接生成高速随机序列而言，IO端口的输出速率降为原来的1/R，可以大大降低FPGA的成本。
可选地，作为一个实施例，S320生成第二脉冲序列，包括：
生成第二脉冲序列，使得第二脉冲序列的脉冲宽度为1/fmax，序列周期 为T。
具体而言，窄脉冲序列可以保证最终叠加得到的随机序列具有足够的高频分量。因为作为本振信号的高速随机序列的脉冲的最高频率为fmax，频率最高的脉冲的宽度为1/fmax，所以该窄脉冲的脉冲宽度为1/fmax。此外，因为需将生成的低速随机序列和窄脉冲序列相叠加，因此生成的窄脉冲序列的高电平和低电平的相对位置与低速随机序列的高电平和低电平的相对位置应尽量一致，序列周期也应一致为T。
可选地，作为一个实施例，S320生成第二脉冲序列，包括：
根据第一脉冲序列，激发生成第二脉冲序列，使得第一脉冲序列的脉冲的上升沿处形成窄脉冲，多个窄脉冲组成所述第二脉冲序列。
具体而言，生成窄脉冲序列的一个简便的方法可以是，生成一个与低速随机序列完全相同的脉冲序列，利用该脉冲序列激发可以产生窄脉冲序列的器件，可以获得各脉冲低电平的相对位置与低速随机序列的各脉冲低电平的相对位置一致的窄脉冲序列，生成的该窄脉冲序列更易于与低速随机序列叠加而获得需要的高速随机序列。
优选地，根据第一脉冲序列，激发生成第二脉冲序列，包括：
根据第一脉冲序列，激发SRD生成第二脉冲序列。将第一脉冲序列作为SRD的输入，以激发SRD。SRD在输入的低速随机序列的各脉冲的上升沿处产生一个窄脉冲，其它位置恢复为低电平，因此，通过该方法生成的窄脉冲序列的窄脉冲与低速随机序列的各脉冲的上升沿向对应，通过适当的处理后与第一脉冲序列相叠加，就可以获得需要的随机序列。
可选地，作为一个实施例，S330将第一脉冲序列和第二脉冲序列叠加为随机序列，包括：
将第一脉冲序列和/或第二脉冲序列进行移位，使得第一脉冲序列和第二脉冲序列叠加时，第二脉冲序列叠加在第一脉冲序列相对应的低电平上。
具体而言，生成的低速随机序列和窄脉冲序列经过叠加，使得窄脉冲序列的脉冲叠加在低速随机序列的脉冲的低电平上。生成的低速随机序列和窄脉冲序列直接叠加可能会将窄脉冲序列的高电平叠加在低速随机序列的高电平上，这样就不能起到使得叠加得到的随机序列具有丰富的高频分量的效果。因此，将生成的两个序列叠加时，必要时需将低速随机序列和/或窄脉冲序列进行移位。对脉冲序列进行移位的手段可以通过在输出设备上增加延时 线，或者将两个脉冲序列的时钟错开，本发明实施例对此不作限定。
因此，本发明实施例提供的生成随机序列的方法，通过将低速随机序列即第一脉冲序列和窄脉冲序列即第二脉冲序列叠加，可以简便的生成高速随机序列，所生成的高速随机序列有良好的随机性和丰富的高频分量，并且成本较低。
以下将结合一个具体的例子对本发明实施例的生成随机序列的方法400，进行详细的说明。如图5所示，该方法400包括：
S410，根据需要生成的高速随机序列，由FPGA生成与该高速随机序列对应的低速随机序列。其中，高速随机序列的脉冲的最高频率为fmax，对应的脉冲宽度为1/fmax，序列周期为T，序列长度为N＝T fmax；生成的低速随机序列的最高频率的脉冲的宽度为R/fmax，序列周期为T，序列长度为M＝N/R＝Tfmax/R，生成的低速随机序列的波形示意图如图6A所示。
S420，将与S410中生成的低速随机序列完全相同的一个脉冲序列输入SRD，以激发SRD。由SRD生成窄脉冲序列，该窄脉冲序列的脉冲宽度为1/fmax，序列周期为T，其波形示意图如图6B所示。
S430，将生成的低速随机序列和/或窄脉冲序列进行移位，以便于将两个脉冲序列相叠加。
S440，将经过S430步骤处理的低速随机序列和窄脉冲序列叠加为随机序列，使得窄脉冲序列的脉冲叠加在低速随机序列的低电平上。叠加后的随机序列的波形示意图如图6C所示。
下面对以上方法所得到的低速随机序列和叠加得到的随机序列、以及由FPGA直接生成的高速随机序列的随机性加以分析。可以通过不同频率的归一化傅里叶系数来表征不同频率上的功率密度。通过傅里叶系数向量构成托普利茨(Toeplitz)矩阵，计算矩阵的自相关系数矩阵，然后通过自相关系数矩阵的元素的幅值来表征随机性。
根据计算结果可以得出由FPGA直接生成的高速随机序列的相关性较低，随机性较好。由FPGA生成的低速随机序列的高频分量幅度很低，序列的相关性也较强，随机性较差。低速随机序列和窄脉冲序列叠加得到的随机序列相比原本的低速随机序列，高频分量的功率密度有了明显提升，而随机性也较低速随机序列改善很多。
因此，本发明实施例提供的生成随机序列的方法，通过将FPGA生成的 低速随机序列即第一脉冲序列和SRD生成的窄脉冲序列即第二脉冲序列叠加，可以简便地生成随机序列，所生成的随机序列有良好的随机性和丰富的高频分量，并且成本较低。
应理解，在本发明各实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (12)

  1. 一种生成随机序列的装置，其特征在于，包括：
    第一生成单元，用于根据目标速率和目标序列周期生成第一脉冲序列，所述第一脉冲序列为随机的脉冲序列，并且所述第一脉冲序列的速率低于所述目标速率，所述第一脉冲序列的序列周期为所述目标序列周期，所述第一脉冲序列的脉冲的最小宽度大于第一阈值；
    第二生成单元，用于生成第二脉冲序列，所述第二脉冲序列为窄脉冲序列，所述第二脉冲序列的序列周期为所述目标序列周期，所述窄脉冲序列的脉冲的宽度小于所述第一阈值；
    叠加单元，用于将所述第一生成单元生成的所述第一脉冲序列和所述第二生成单元生成的所述第二脉冲序列叠加为所述随机序列，使得所述第二脉冲序列的脉冲叠加在所述第一脉冲序列的低电平上。
  2. 根据权利要求1所述的装置，其特征在于，所述第一生成单元具体用于：
    根据所述目标速率和所述目标序列周期生成所述第一脉冲序列，使得所述第一脉冲序列的脉冲的最小宽度为R/fmax，序列周期为T，其中，fmax为所述目标速率对应的最高频率，R为所述目标速率与所述第一脉冲序列的速率的比值，T为所述目标序列周期。
  3. 根据权利要求2所述的装置，其特征在于，所述第二生成单元具体用于：
    生成所述第二脉冲序列，使得所述第二脉冲序列的脉冲宽度为1/fmax，序列周期为T。
  4. 根据权利要求1至3中任一项所述的装置，其特征在于，所述第二生成单元具体用于：
    根据所述第一生成单元生成的所述第一脉冲序列，激发生成所述第二脉冲序列，使得所述第一生成单元生成的所述第一脉冲序列的脉冲的上升沿处形成窄脉冲，多个窄脉冲组成所述第二脉冲序列。
  5. 根据权利要求4所述的装置，其特征在于，所述第二生成单元具体用于：根据所述第一生成单元生成的所述第一脉冲序列，激发阶跃恢复二极管SRD生成所述第二脉冲序列。
  6. 根据权利要求1至5中任一项所述的装置，其特征在于，所述叠加单 元具体用于：
    将所述第一生成单元生成的所述第一脉冲序列和/或所述第二生成单元生成的所述第二脉冲序列进行移位，使得所述第一脉冲序列和所述第二脉冲序列叠加时，所述第二脉冲序列叠加在所述第一脉冲序列相对应的低电平上。
  7. 一种生成随机序列的方法，其特征在于，包括：
    根据目标速率和目标序列周期生成第一脉冲序列，所述第一脉冲序列为随机的脉冲序列，并且所述第一脉冲序列的速率低于所述目标速率，所述第一脉冲序列的序列周期为所述目标序列周期，所述第一脉冲序列的脉冲的最小宽度大于第一阈值；
    生成第二脉冲序列，所述第二脉冲序列为窄脉冲序列，所述第二脉冲序列的序列周期为所述目标序列周期，所述窄脉冲序列的脉冲的宽度小于所述第一阈值；
    将所述第一脉冲序列和所述第二脉冲序列叠加为所述随机序列，使得所述第二脉冲序列的脉冲叠加在所述第一脉冲序列的低电平上。
  8. 根据权利要求7所述的方法，其特征在于，所述根据目标速率和目标序列周期生成第一脉冲序列，包括：
    根据所述目标速率和所述目标序列周期生成所述第一脉冲序列，使得所述第一脉冲序列的脉冲的最小宽度为R/fmax，序列周期为T，其中，fmax为所述目标速率对应的最高频率，R为所述目标速率与所述第一脉冲序列的速率的比值，T为所述目标序列周期。
  9. 根据权利要求8所述的方法，其特征在于，所述生成第二脉冲序列，包括：
    生成第二脉冲序列，使得所述第二脉冲序列的脉冲宽度为1/fmax，序列周期为T。
  10. 根据权利要求7至9中任一项所述的方法，其特征在于，所述生成第二脉冲序列，包括：
    根据所述第一脉冲序列，激发生成所述第二脉冲序列，使得所述第一脉冲序列的脉冲的上升沿处形成窄脉冲，多个窄脉冲组成所述第二脉冲序列。
  11. 根据权利要求10所述的方法，其特征在于，所述根据所述第一脉冲序列，激发生成所述第二脉冲序列，包括：
    根据所述第一脉冲序列，激发阶跃恢复二极管SRD生成所述第二脉冲序列。
  12. 根据权利要求7至11中任一项所述的方法，其特征在于，所述将所述第一脉冲序列和所述第二脉冲序列叠加为所述随机序列，包括：
    将所述第一脉冲序列和/或所述第二脉冲序列进行移位，使得所述第一脉冲序列和所述第二脉冲序列叠加时，所述第二脉冲序列叠加在所述第一脉冲序列相对应的低电平上。
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US20090157780A1 (en) * 2003-09-30 2009-06-18 Kabushiki Kaisha Toshiba Random number generating circuit, semiconductor integrated circuit, ic card and information terminal device
CN102176199A (zh) * 2011-01-28 2011-09-07 中国科学院西安光学精密机械研究所 一种真随机数产生方法及装置
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