WO2016042902A1 - メモリコントローラ、記憶装置、情報処理システムおよび不揮発メモリの制御方法 - Google Patents
メモリコントローラ、記憶装置、情報処理システムおよび不揮発メモリの制御方法 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0076—Write operation performed depending on read result
Definitions
- This technology relates to a memory controller. More specifically, the present invention relates to a memory controller, a storage device, an information processing system, and a nonvolatile memory control method for writing and verifying data in the nonvolatile memory.
- a NAND flash memory which is a nonvolatile memory
- This NAND flash memory stores data by accumulating electric charges in a floating gate disposed in a MOS transistor in a memory cell.
- non-volatile memories that store data by changing the physical properties of the storage elements in the memory cells are attracting attention because of their advantages such as high speed and random access. Examples of such a nonvolatile memory include PCRAM (Phase-Change RAM) and ReRAM (Resistance RAM).
- PCRAM Phase-Change RAM
- ReRAM Resistance RAM
- non-volatile memories using magnetic materials such as MRAM (Magnetoresistive RAM) and STT-MRAM (Spin transfer torque-MRAM) are also applicable.
- PCRAM stores data by changing the electrical resistance of a storage element that is a phase change element arranged in a memory cell.
- the storage element is set to a crystalline state or an amorphous state, and a storage operation is performed using a difference in electric resistance.
- the memory element has a low resistance when in a crystalline state, and the memory element has a high resistance when in an amorphous state.
- an operation for setting the memory element in the low resistance state is expressed as a set operation
- an operation for setting the high resistance state is expressed as a reset operation.
- Data in the PCRAM is written by performing a reset and set operation on the memory cell.
- the storage element In order to change the state of the memory element, it is necessary to apply a voltage (write voltage) to the memory element to flow current and to heat it.
- the conditions of the temperature and heat generation time at that time are changed to change the state of the memory element to a crystalline state or an amorphous state.
- the storage element has a substantially melting temperature and a heating condition for a short time, the storage element is in an amorphous state and a reset operation is performed.
- the crystallization temperature is lower than the melting point and the heating conditions are for a long time, the memory element is crystallized and the set operation is performed.
- ReRAM stores data by changing the electrical resistance of the memory element arranged in the memory cell.
- the memory element of ReRAM has a two-layer structure composed of an insulating layer and a metal ion supply layer.
- a voltage is applied to the memory element, a conductive filament made of metal ions supplied from the metal ion supply layer is formed in the insulating layer. Diffuses into a low resistance state.
- a voltage having a reverse polarity is applied, the metal ions of the conductive filaments that have been diffused return to the metal ion supply layer, so that the memory element enters a high resistance state.
- an operation for setting the memory element in the low resistance state is expressed as a set operation
- an operation for setting the high resistance state is expressed as a reset operation.
- a phenomenon is known in which the state of the storage element is not stable immediately after a reset and set operation, which is a data write operation. This is a phenomenon in which the resistance value of the memory element immediately after data writing becomes a value in the vicinity of the threshold value for determining the low resistance state or the high resistance state, and settles to a normal resistance value as time passes (for example, non-patent Reference 1).
- Non-volatile memory needs to verify whether correct data is written after data is written. Therefore, the data is read after the data is written, and the read data is compared with the data related to the writing. In the above-described PCRAM, this reading is performed by applying a voltage (read voltage) lower than the write voltage to the memory element and measuring the resistance value of the memory element. However, since the memory element is heated at the time of writing and crystallization is performed during the cooling period, the state of the memory element becomes unstable during this period. Therefore, when a read voltage is applied during this period, the state of the memory element changes and the written data may be destroyed.
- a voltage read voltage
- the state of the storage element becomes unstable immediately after data writing. If data is read during this period, the data is not normally read out, and as a result of verification, it is determined that there is a write failure.
- the nonvolatile memory in which data is written by changing the physical properties of the memory element has an unstable period due to the change in physical properties immediately after the writing. Therefore, if the data for verification is read immediately after the data is written, there is a possibility that it is determined that the writing is defective. As a result, there is a problem that the writing reliability is lowered.
- This technology has been created in view of such a situation, and aims to accurately verify write data and improve the write reliability of the nonvolatile memory.
- the present technology has been made in order to solve the above-described problems.
- the first aspect of the present technology is that after writing data in a nonvolatile memory including a memory cell in which a state is unstable after writing data.
- a write controller that performs the writing of the data and the rewriting of the write data based on the result of the verification. This brings about the effect that the verification is performed after determining whether or not the state of the memory cell of the nonvolatile memory is stable.
- the nonvolatile memory may be a nonvolatile memory in which the written data is destroyed when reading is performed immediately after the data is written.
- the nonvolatile memory may be a nonvolatile memory in which the written data is not normally read out immediately after the data is written.
- the verification is performed after determining whether the state of the memory cell of the nonvolatile memory is stable even in the nonvolatile memory in which the written data is not normally read out immediately after the data is written. Bring.
- the determination unit may make the determination based on the elapse of a predetermined stabilization time after the data is written. This brings about the effect that the above determination is made based on the passage of a predetermined stabilization time.
- the nonvolatile memory is accessed in page units by a page address
- the write control unit continuously writes data consisting of a plurality of pages
- the verification unit The verification may be performed for each page in the order of writing, and the determination unit may determine that the state of the memory cell is stable during the verification. This brings about the effect that it is determined that the state of the memory cell is stable after the data composed of a plurality of pages is written.
- the first aspect further includes a rewrite address information holding unit that holds rewrite address information that is information of a page address of the nonvolatile memory that performs the rewrite, and the verification unit includes the plurality of pages.
- the verification is continuously performed after the data is written, and the rewrite address information based on the result of the verification is held in the rewrite address information holding unit, and the write control unit is configured to store the held rewrite
- the rewriting may be performed based on the address information. As a result, rewriting is performed based on the rewriting address information.
- a verification address information holding unit that holds verification address information that is information of a page address of the nonvolatile memory that performs the verification is further provided, and the write control unit includes the writing and the rewriting.
- the writing is performed, the page address information that has been written and rewritten is held as the verification address information in the verification address information holding unit, and the verification unit is based on the held verification address information.
- the above verification may be performed. As a result, the verification is performed based on the verification address information.
- the nonvolatile memory is accessed in page units by a page address
- the write control unit continuously writes data consisting of a plurality of pages
- the verification unit The verification is performed on a page-by-page basis in the order in which writing is performed
- the determination unit determines the number of pages at which the number of pages of the writing data is a writing time corresponding to a predetermined stabilization time after data writing in the nonvolatile memory.
- the number of state-stabilized pages is equal to or greater than the number of state-stabilized pages, it is determined that the state of the memory cell is stable at the time of the verification. It may be determined that the state of the memory cell is stable after the stabilization time elapses.
- the above determination is made based on the number of pages of the write data. If the number of pages of the write data is smaller than the predetermined state stabilization page number, the predetermined stable This makes it possible to perform the above determination based on the elapse of the conversion time.
- a write control unit for writing data in a nonvolatile memory including a memory cell in which a state is unstable after data writing, and a state of the memory cell after writing the data
- a determination unit for determining whether or not the data is stable, verification for comparing the read data read from the memory cell in which the data is written based on the result of the determination, and the write data related to the write; and A verification writing unit that rewrites the write data based on the verification result may be included. This brings about the effect that the verification is performed after determining whether or not the state of the memory cell of the nonvolatile memory is stable.
- a nonvolatile memory including a memory cell having a period of unstable state after data writing, and a state of the memory cell after data writing in the nonvolatile memory are stabilized.
- a determination unit that determines whether or not, a verification unit that compares and verifies the read data read from the memory cell in which the data is written based on the determination result and the write data related to the write,
- the storage device includes a write control unit that writes the data and rewrites the write data based on the verification result. This brings about the effect that the verification is performed after determining whether or not the state of the memory cell of the nonvolatile memory is stable.
- a nonvolatile memory including a memory cell having an unstable period after data is written, a memory controller that controls the nonvolatile memory, and the nonvolatile memory via the memory controller.
- a host computer that accesses the memory, wherein the memory controller determines whether or not the state of the memory cell after data writing in the nonvolatile memory is stable;
- a verification unit that compares and verifies the read data read from the memory cell in which the data is written and the write data related to the write, and rewrites the write data based on the result of the data write and the comparison
- An information processing system including a writing control unit that performs writing. This brings about the effect that the verification is performed after determining whether or not the state of the memory cell of the nonvolatile memory is stable.
- a non-volatile memory including a memory cell in which a state is unstable after data writing
- a write control procedure for rewriting the write data based on the result of the comparison brings about the effect that the verification is performed after determining whether or not the state of the memory cell of the nonvolatile memory is stable.
- FIG. 1 It is a figure which shows an example of the process sequence (memory controller) of the normal write process in 1st Embodiment of this technique. It is a figure showing an example of a processing procedure (memory controller) of stable state judgment processing in a 1st embodiment of this art. It is a figure showing an example of a processing procedure (memory controller) of verification writing processing in a 1st embodiment of this art. It is a figure showing an example of processing procedure (memory) of write-in processing in a 1st embodiment of this art. It is a figure showing an example of a processing procedure (memory) of verification writing processing in a 1st embodiment of this art.
- FIG. 4 It is a figure showing an example of a processing procedure (memory) of verification processing in a 4th embodiment of this art. It is a figure showing an example of a processing procedure (memory) of rewriting processing in a 4th embodiment of this art. It is a figure showing an example of the processing procedure (memory) of the rewriting processing in the 1st modification of a 4th embodiment of this art. It is a figure showing an example of a processing procedure (memory controller) of verification processing in the 2nd modification of a 4th embodiment of this art. It is a figure showing an example of the processing procedure (memory controller) of the rewrite processing in the 2nd modification of a 4th embodiment of this art.
- FIG. 1 is a diagram illustrating a configuration example of an information processing system according to the first embodiment of the present technology.
- the information processing system in FIG. 1 includes a host computer 100, a memory controller 200, a memory 300, and signal lines 109 and 208.
- the memory 300 is an example of a nonvolatile memory described in the claims.
- the host computer 100 inputs and outputs data with the memory 300 via the memory controller 200.
- the host computer 100 includes a processor 110, a DRAM 120, a memory controller interface 130, and a bus device 101.
- the processor 110 controls the overall operation of the host computer 100.
- the DRAM 120 temporarily stores data used by the host computer 100.
- the memory controller interface 130 is an interface for exchanging with the memory controller 200.
- the bus device 101 connects the processor 110, the DRAM 120, and the memory controller interface 130 to each other.
- the host computer 100 inputs and outputs data between the memory controller 200 and the memory 300 by issuing a command to the memory controller 200 via the signal line 109.
- FIG. 2 is a diagram illustrating a configuration example of the memory controller according to the first embodiment of the present technology.
- the memory controller 200 shown in the figure includes a processor 210, a RAM 220, a host interface 230, an ECC processing unit 250, a ROM 260, a memory interface 270, and a bus device 201.
- the processor 210 controls the entire operation of the memory controller 200.
- the processor 210 also interprets commands issued by the host computer 100 and performs processing based thereon.
- the RAM 220 temporarily stores data used by the memory controller 200.
- the host interface 230 is an interface that communicates with the host computer 100.
- the ECC processing unit 250 performs encoding that adds a parity to the data output from the host computer 100 to form an ECC code, and decoding that extracts the original data from the ECC code. During this decoding, data error correction is performed.
- the ROM 260 stores the firmware of the memory controller 200.
- the processor 210 operates according to this firmware.
- the memory interface 270 is an interface that communicates with the memory 300.
- the bus device 201 connects the units in the memory controller 200 described above.
- the memory controller 200 issues a request to the memory 300 via the signal line 208, and performs data input / output, that is, data writing and reading.
- FIG. 3 is a diagram illustrating a configuration example of the memory according to the first embodiment of the present technology.
- the memory 300 in FIG. 1 includes a control unit 310, a working memory 320, a memory controller interface 330, an address decoder 340, a memory cell array 350, a buffer 360, and a bus device 301.
- the control unit 310 controls the entire operation of the memory 300.
- the control unit 310 also interprets a request issued by the memory controller 200 and performs processing based on the interpretation.
- the work memory 320 temporarily stores data used in the memory 300.
- the memory controller interface 330 is an interface for exchanging with the memory controller 200.
- the memory cell array 350 stores data.
- the memory cell array 350 is configured by two-dimensionally arranging memory cells made of a nonvolatile memory. These memory cells are accessed page by page address. This page is 512 bytes in size, for example.
- the address decoder 340 converts a given page address into a page selection signal and outputs it to the memory cell array 350.
- the buffer 360 holds data to be input / output to / from the memory cell array 350.
- the buffer 360 has the same capacity as data of a size corresponding to one page (hereinafter referred to as page data).
- non-volatile memory in the embodiment of the present technology, a non-volatile memory including a memory cell having a period in which the state is unstable after data writing can be used.
- a nonvolatile memory for example, PCRAM and ReRAM are applicable.
- ReRAM will be described as an example.
- the processor 210 instructs the ECC processing unit 250 to encode the read write data. Thereafter, the processor 210 generates a write request and issues it to the memory 300. At that time, the encoded write data is output to the memory 300. Finally, it is verified whether or not the data writing is successful.
- This verification is also performed by the memory controller 200 issuing a verification request to the memory 300. If the writing is unsuccessful as a result of the verification, the request is issued again and rewriting is performed. These request and write data are input to the memory 300 via the memory interface 270 and the memory controller interface 330 and stored in the working memory 320. Thereafter, the control unit 310 interprets the request and performs processing. Note that, in the first embodiment of the present technology, instead of separately issuing a verification request and a write request based on the verification request, a verification write request that integrates them is issued to simplify the processing.
- FIG. 4 is a diagram illustrating a functional configuration example according to the first embodiment of the present technology. This figure assumes a functional configuration for writing data.
- the memory controller 200 includes a write control unit 292, a determination unit 280, and a verification write unit 299. These functions are realized by firmware executed by the processor 210 described in FIG.
- the write control unit 292 is an example of a write control unit described in the claims.
- the determination unit 280 determines whether or not the state of the memory cell after data writing in the nonvolatile memory is stable. As described above, the ReRAM has a period in which the state of the memory cell is unstable immediately after data writing. The determination unit 280 determines whether or not the state of the memory cell becomes stable and data for verification can be read stably.
- the verification writing unit 299 verifies the data writing based on the determination result of the determination unit 280.
- the verification is to check whether or not the data has been normally written. This verification is performed by comparing the read data read from the memory cell in which the data is written after the data is written with the write data related to the write. Further, the verification writing unit 299 further rewrites the write data based on the verification result. That is, the verification writing unit 299 performs verification and rewriting based on the verification result. The verification writing unit 299 performs verification and rewriting by issuing the above-described verification write request to the memory 300.
- the write control unit 292 writes data.
- the write control unit 292 issues the above-described write request to the memory 300.
- the write control unit 292 also outputs write information necessary for the above determination to the determination unit 280. The operation of the write information and determination unit 280 will be described later.
- the memory 300 in the figure includes a control unit 310, a working memory 320, a buffer 360, and a memory cell array 350. These are the same as those described with reference to FIG. Such processing in the memory controller 200 and the memory 300 will be described.
- the write control unit 292 issues a write request to the memory 300.
- This write request includes, for example, an operation code indicating writing, write data, and a write destination page address.
- the control unit 310 interprets this request and stores the write data and the write destination page address included in the request in the work memory 320.
- the control unit 310 transfers the write data to the buffer 360 to hold it.
- the write data held in the buffer 360 is written into the memory cell array 350. Details of the write operation in the memory cell array 350 will be described later.
- the control unit 310 outputs, to the write control unit 292, the number of write pages that is the number of pages that have been written as a write response.
- the write control unit 292 outputs write information based on the write response output from the memory 300 to the determination unit 280. That is, the write control unit 292 outputs the number of write pages as write information every time the write operation is completed.
- the determination unit 280 performs the above-described determination, and outputs the determination result to the verification writing unit 299.
- the verification writing unit 299 performs verification based on the determination result. Specifically, verification is performed by the following procedure. First, the verification writing unit 299 reads the write data of the page to be verified from the DRAM 120 of the host computer 100 and stores it in the RAM 220. This write data is used as comparison data for verification. Next, the verification writing unit 299 generates a verification write request and issues it to the memory 300.
- This verification write request includes, for example, an operation code representing verification write, comparison data, and a verification destination page address.
- This verification destination page address is the page address of the page to be verified, and is the same page address as the write destination page address of the write data described above. In the first embodiment of the present technology, both the write data and the comparison data in the write and verification write requests are configured by page data.
- the control unit 310 interprets the request and stores the comparison data and the verification destination page address included in the request in the work memory 320.
- the control unit 310 reads the memory cell array 350 based on the verification destination page address.
- the read data is held in the buffer 360 as read data.
- the control unit 310 compares the comparison data stored in the work memory 320 with the read data held in the buffer 360. This comparison is performed based on whether or not the two data are completely the same. This comparison may be performed based on whether or not the number of mismatched bits is equal to or less than a predetermined threshold. This is because even if the two data do not completely match, the error is corrected and the desired data can be read out by the ECC processing unit 250 provided in the memory controller 200.
- the control unit 310 rewrites the write data. This rewriting is performed by writing the comparison data stored in the working memory 320 into the memory cell array 350. Thereafter, the control unit 310 outputs the number of pages on which rewriting has been performed to the verification writing unit 299 as a verification write response, and ends the processing.
- the verification writing unit 299 outputs write information based on the verification write response output from the memory 300 to the determination unit 280.
- FIG. 5 is a diagram illustrating a configuration example of the determination unit according to the first embodiment of the present technology.
- the determination unit 280 shown in the figure includes a timer unit 281, a written page number determination unit 282, and a memory cell stable state determination unit 283.
- the timer unit 281 measures the stabilization time after the data is written by the writing control unit 292 and the verification writing unit 299.
- the stabilization time is a time until the state of the memory cell of the nonvolatile memory that has become unstable after data writing is stabilized.
- the timer unit 281 newly starts timing, and outputs this result when the stabilization time has elapsed.
- the written page number determination unit 282 determines whether or not the number of written pages is equal to or greater than the number of state stabilization pages.
- the number of state stabilization pages is the number of pages that becomes a writing time corresponding to the stabilization time after the writing of data in the nonvolatile memory when writing the write data composed of a plurality of pages.
- stabilization time may elapse in the memory cell that was initially written during the writing process. . In such a case, it is possible to determine that the state of the memory cell related to this writing is stable without measuring the stabilization time by the timer unit 281 described above.
- the write page number determination unit 282 may include a counter that counts the number of write pages based on the write information. The written page number determination unit 282 outputs this result when the count value is equal to or greater than the number of state-stabilized pages.
- the memory cell stable state determination unit 283 determines the stable state of the memory cell based on the outputs of the timer unit 281 and the write page number determination unit 282. Specifically, when the stabilization time after the data is written in the timer unit 281 or when writing more than the number of state stabilization pages in the write page number determination unit 282 occurs, the state of the memory cell related to these writes Is considered stable. Thereafter, the determination result is output. As a result, the determination unit 280 makes a determination based on the number of pages of the write data after writing the data composed of a plurality of pages. If the number of pages of the write data is smaller than the number of state stabilization pages, the stabilization time The determination can be made based on the progress of the above.
- FIG. 6 is a diagram illustrating a write operation according to the first embodiment of the present technology.
- a write operation in the memory cell array 350 of the memory 300 will be described with reference to FIG.
- writing is performed by performing a reset operation and a set operation on a memory cell.
- the value “1” corresponds to the case where the storage element of the ReRAM is in the low resistance state
- the value “0” corresponds to the case where it is in the high resistance state.
- the value “0” is written in the memory cell by the reset operation
- the value “1” is written in the memory cell by the set operation.
- the reset operation data is data in which the target bit in the page data, that is, the bit for writing the value “0” is set to the value “1” and the other bits are set to the value “0”.
- the set operation data is data in which the target bit in the page data, that is, the bit for writing the value “1” is the value “1” and the other bits are the value “0”.
- pre-erasing may be performed before the data writing operation.
- pre-erasing is an operation for setting all bits of the target memory cell to a value “1” prior to data writing.
- the ReRAM can write data without pre-erasing.
- the information processing system may have a pre-erase function, and pre-erase may be performed before data writing processing.
- the memory 300 needs to know whether or not the memory cell to be subjected to the writing process has been previously erased. This is because the write operation in the memory 300 differs depending on the presence or absence of prior erasure. For this reason, the memory 300 can use, for example, a method in which a flag is provided in the working memory 320 and whether or not to delete in advance is set in this flag. Next, writing and rewriting operations will be described separately.
- the memory 300 performs a reset operation and a set operation.
- the reset operation data is calculated by the following procedure. First, the data written in the memory cell is read out. Next, a bitwise exclusive OR operation is performed on the read data and write data. Finally, a bitwise AND operation is performed on the result of this exclusive OR operation and the read data. The memory 300 uses the obtained calculation result as reset operation data.
- RData ((W ⁇ R) & R) Equation 2
- R represents the read data (page data).
- ⁇ and & are operators representing an exclusive OR operation for each bit and an AND operation for each bit, respectively.
- (D) In case of rewriting operation (without pre-erasing) In this case, the same operation as (b) can be performed. That is, the memory 300 performs a reset operation and a set operation. The reset operation data and the set operation data are calculated based on Equation 2 and Equation 3, respectively.
- FIG. 7 is a diagram illustrating an example of a processing procedure (memory controller) of the writing process according to the first embodiment of the present technology.
- the rewrite counter and the offset register are used in the write process in the first embodiment of the present technology. These are counters and registers implemented by software in the memory controller 200.
- the rewrite counter holds the number of rewrites performed in the write process.
- the offset register holds an offset value from the start address of the write data in the DRAM 120. This offset value is a value with the number of pages as a unit.
- the memory controller 200 When a write command is issued from the host computer 100, the memory controller 200 starts a write process. First, the memory controller 200 performs normal writing (step S910). In the first embodiment of the present technology, writing of write data including a plurality of pages is performed in the normal writing process. Next, the memory controller 200 performs a stable state determination process (step S920). Next, the memory controller 200 initializes a rewrite counter (step S903) and performs verification writing (step S930). The number of times of rewriting is held in the rewriting counter by this verification writing process.
- step S904: Yes When the value of this rewrite counter is “0” (step S904: Yes), it indicates that rewrite did not occur in the verification write process. That is, it indicates that the writing process has been successful, and the memory controller 200 notifies the host computer 100 that the writing process has been completed normally and ends the writing process.
- step S904: No if the value of the rewrite counter is not “0” (step S904: No), it indicates that rewrite has occurred in the verification write process. That is, it is shown that the verification writing process for the corresponding part is necessary again. In this case, the rewrite process (the process from step S920) is executed in a loop until the value of the rewrite counter becomes “0”.
- step S905 when the upper limit of the number of rewrite processes has been reached (step S905: Yes), the memory controller 200 performs error processing (step S906) without performing the rewrite process. As this error processing, the memory controller 200 notifies the host computer 100 that the data writing has ended abnormally. Thereafter, the memory controller 200 ends the writing process.
- the upper limit of the rewriting process can be set to twice.
- FIG. 8 is a diagram illustrating an example of a processing procedure (memory controller) of normal write processing according to the first embodiment of the present technology.
- This process is a process corresponding to step S910 described in FIG.
- the memory controller 200 performs write setting (step S911). Specifically, based on the write command, the start address of the write data of the DRAM 120 that is the read source of the write data, the number of pages of the write data, and the page address in the memory 300 that is the write destination are set.
- the memory controller 200 initializes the offset register (step S912). Thereafter, the memory controller 200 checks whether or not all data has been written (step S916). Specifically, the memory controller 200 compares the number of pages of write data set in step S911 with the number of pages for which writing has been completed, for example, the value of an offset register.
- step S916: Yes when all the data has been written (step S916: Yes), the normal writing process is finished. On the other hand, if writing of all data has not been completed (step S916: No), the process proceeds to step S913.
- the memory controller 200 acquires write data from the host computer 100 (step S913). Specifically, the host controller 230 instructs the memory controller interface 130 to transfer write data. At this time, the address of the DRAM 120 from which data is read is designated. This address is obtained by adding the product of the offset register value and the page size to the start address of the write data in the DRAM 120.
- the memory controller interface 130 reads page data at a specified address from the DRAM 120 and outputs the page data to the memory controller 200 as write data.
- the memory controller 200 stores the page data in the RAM 220.
- the ECC processing unit 250 encodes the page data.
- the memory controller 200 generates and issues a write request including the encoded page data (step S914).
- a value obtained by adding the value of the offset register to the write address (page address) in the memory 300 included in the write command output from the host computer 100 can be used as the write destination page address of the write request. That is, the page address can be designated by the relative address based on the value of the offset register.
- the memory controller 200 updates the offset register (step S918) and returns to the process of step S916.
- the memory controller 200 outputs write information based on the write response to the determination unit 280 when the process of step S914 is performed. Thereby, it is possible to start the measurement of the stabilization time by the timer unit 281 and the determination regarding the number of state stabilization pages by the write page number determination unit 282.
- FIG. 9 is a diagram illustrating an example of a processing procedure (memory controller) of the stable state determination processing according to the first embodiment of the present technology.
- This process is a process corresponding to step S920 described in FIG.
- the memory controller 200 determines whether or not the number of written pages is equal to or greater than the number of state stabilization pages (step S921). As a result, when the number of written pages is equal to or greater than the number of state stabilization pages (step S921: Yes), the stable state determination process is terminated.
- step S921 determines whether or not the stabilization time has elapsed (step S922) and stabilizes. It waits until time passes (step S922: No). On the other hand, when the stabilization time has elapsed (step S922: Yes), the stable state determination process is terminated.
- the memory controller 200 performs the process of step S921, the memory controller 200 resets the counter of the write page number determination unit 282 so that the number of write pages held therein is zero.
- FIG. 10 is a diagram illustrating an example of a processing procedure (memory controller) of verification writing processing according to the first embodiment of the present technology.
- This process is a process corresponding to step S930 described in FIG.
- the memory controller 200 initializes an offset register (step S932).
- the memory controller 200 checks whether or not all data has been verified (step S936). As a result, when the verification of all the data has been completed (step S936: Yes), the verification writing process is terminated. On the other hand, when the verification of all the data has not been completed (step S936: No), the process proceeds to step S933.
- the memory controller 200 acquires write data from the host computer 100 (step S933). Next, the memory controller 200 generates and issues a verification write request including the write data (step S934). As a response to this request (verification write response), the memory 300 outputs the number of write pages in rewriting. When rewriting is performed by the memory 300 as a result of this request, the memory controller 200 updates the rewriting counter. That is, when the number of pages to be written in the verification write response is not zero (step S935: Yes), the memory controller 200 adds the number of pages to be written in the verification write response to the rewrite counter (step S937). Thereafter, the memory controller 200 proceeds to the process of step S938.
- step S935 when the rewrite is not performed by the memory 300, that is, when the number of pages to be written in the verification write response is zero (step S935: No), the memory controller 200 skips the process of step S937, The process proceeds to S938.
- step S938 the memory controller 200 updates the offset register (step S938), and returns to the process of step S936. Note that the memory controller 200 outputs write information based on the verification write response to the determination unit 280 when performing the process of step S934.
- FIG. 11 is a diagram illustrating an example of a processing procedure (memory) of the writing process according to the first embodiment of the present technology.
- the memory 300 starts a write process. Note that write data associated with the request is stored in the work memory 320.
- the memory 300 checks whether or not pre-erasure has been performed (step S701). If pre-erasure has not been performed (step S701: No), the processing of steps S702 to S706 is executed. On the other hand, when pre-erasing has been performed (step S701: Yes), the memory 300 executes the processes of steps S707 and S708.
- step S702 the processing from step S702 to step S706 will be described.
- This case corresponds to the case of the above-described (b) write operation (no pre-erasure).
- the memory 300 reads page data from the memory cell that is the target of the write operation (step S702). Based on the read page data and the write data stored in the work memory 320, the memory 300 calculates reset operation data (step S703) and performs the reset operation (step S704). Next, the memory 300 calculates set operation data (step S705), performs the set operation (step S706), and proceeds to the processing of step S709.
- step S707 and step S708 will be described. This case corresponds to the above-described (a) write operation (with pre-erase).
- the memory 300 calculates the reset operation data without reading the page data from the memory cell (step S707). Next, the memory 300 performs a reset operation (step S708), and proceeds to the process of step S709. In step S709, the memory 300 outputs the number of written pages to the memory controller 200 as a result of the writing process (step S709), and ends the writing process.
- FIG. 12 is a diagram illustrating an example of a processing procedure (memory) of the verification writing process according to the first embodiment of the present technology.
- the memory 300 starts verification write processing.
- the comparison data accompanying the request is stored in the work memory 320.
- the memory 300 reads data (page data) from the memory cell (step S712).
- the read data is held in the buffer 360.
- the memory 300 compares the data (step S718). Specifically, the memory 300 compares the comparison data stored in the work memory 320 and the data held in the buffer 360.
- step S720 when both do not match (step S711: No), rewriting is performed (step S720). On the other hand, if the two match (step S711: Yes), the process of step S720 is skipped and the process proceeds to step S719. In step S719, the memory 300 outputs the number of written pages to the memory controller 200 as a result of the verification write process (step S719), and ends the verification write process.
- FIG. 13 is a diagram illustrating an example of a processing procedure (memory) of the rewrite processing according to the first embodiment of the present technology.
- This process is a process corresponding to step S720 described in FIG. That is, since the process is called from the verification write process described above, the data read from the memory cell is held in the buffer 360. Rewrite using this data.
- the memory 300 calculates the reset operation data (step S723) and performs the reset operation (step S724). In the first embodiment of the present technology, at the time of rewriting, a reset operation is performed regardless of the presence or absence of prior erasure.
- step S721 the memory 300 checks the presence / absence of pre-erasure (step S721). If the pre-erasure has not been performed (step S721: No), the processing of step S725 and step S726 is executed. This case corresponds to the case of the above-described (d) rewrite operation (without pre-erasing). On the other hand, when pre-erasing has been performed (step S721: Yes), the memory 300 proceeds to the process of step S729. This case corresponds to the case of the above-described (c) rewrite operation (with advance erasure). The process of step S725 and step S726 will be described.
- the memory 300 calculates set operation data (step S725), performs the set operation (step S726), and proceeds to the process of step S729.
- step S729 the memory 300 outputs the number of written pages to the memory controller 200 as a result of the rewrite process (step S729), and ends the rewrite process.
- the number of written pages equal to or greater than the number of state-stabilized pages and the elapse of the stabilization time after writing Whether or not the state of the memory cell is stable is determined based on the above. By determining that the state of the memory cell is stable, reading the data, and performing verification, it is possible to verify the correct write data and improve the write reliability.
- verification data is read from the DRAM 120 of the host computer 100 one page at a time and transferred in step S933 of the verification write process described with reference to FIG.
- a plurality of page data may be transferred together. This is because the data transfer time can be shortened. Therefore, in the first modified example, a plurality of page data is transferred from the DRAM 120 together in the verification write process.
- the transferred multiple pages of data are stored in the RAM 220 of the memory controller 200, read out one page at a time during the verification write request issue process (step S934), and used for verification.
- step S934 of the verification write process described with reference to FIG. 10 the page data is output with the issue of the verification write request.
- a plurality of page data may be output together and transferred to the memory 300. This is because the data transfer time can be shortened as in the first modification. Therefore, in the second modified example, a plurality of page data are collectively output when a verification write request is issued in the verification write process.
- the transferred plurality of page data is stored in the working memory 320 of the memory 300, read out one page at a time in the verification writing process in the memory 300, and used for verification and rewriting.
- the determination unit 280 in FIG. 4 stabilizes the state of the memory cell based on either the number of written pages equal to or greater than the number of state-stabilized pages and the passage of stabilization time after writing. It was judged whether or not. However, the determination may be made based only on the passage of the stabilization time. This is because the configuration of the determination unit 280 can be simplified. Therefore, in the third modification, the write page number determination unit 282 is omitted, and the determination is performed only based on the elapse of the stabilization time by the timer unit 281.
- the determination unit 280 in FIG. 4 stabilizes the state of the memory cell based on either the number of written pages equal to or greater than the number of state-stabilized pages and the passage of stabilization time after writing. It was judged whether or not.
- the determination unit 280 continuously writes data consisting of a plurality of pages in the write control unit 292, and after verification is performed in the verification write unit 299 in the order in which the writing is performed, It may be determined that the state is stable. This is because, when the page data size is large and processing takes time, the passage of a predetermined stabilization time is secured by writing data consisting of a plurality of pages. Therefore, the write page number determination unit 282 makes a determination based on whether or not the write includes a plurality of pages. Thereby, the structure of the determination part 280 can be simplified.
- the writing and rewriting operations will be described separately for each case.
- a ′ In case of write operation (with pre-erasure)
- the memory 300 performs only a reset operation.
- the reset operation data is calculated based on Equation 1. That is, the same operation as (a) described above can be performed.
- B ′ In case of write operation (no pre-erasure)
- the memory 300 performs a reset operation and a set operation.
- the reset operation data and the set operation data are calculated based on Equation 2 and Equation 3, respectively. That is, the same operation as (b) described above can be performed.
- C ′ In case of rewriting operation (with pre-erasing) In this case, the same operation as (b ′) can be performed.
- D ′ In case of rewriting operation (without pre-erasing) In this case, the same operation as (b ′) can be performed.
- FIG. 14 is a diagram illustrating an example of a processing procedure (memory) of the rewrite processing in the modification of the first embodiment of the present technology.
- the reset operation and the set operation are performed regardless of the presence or absence of prior erasure, so that the process is simplified compared to the rewrite process described with reference to FIG.
- the memory 300 calculates reset operation data (step S723) and performs a reset operation (step S724).
- the memory 300 calculates set operation data (step S725) and performs the set operation (step S726).
- the memory 300 outputs the number of written pages to the memory controller 200 as a result of the rewriting process (step S729), and ends the rewriting process.
- the ReRAM is assumed as the nonvolatile memory.
- a PCRAM in which the written data is destroyed when reading is performed immediately after the data is written may be used.
- the PCRAM after writing data composed of a plurality of pages, it is possible to verify the write data accurately by determining whether or not the state of the memory cell is stable and performing the verification. Thereby, the writing reliability can be improved.
- the PCRAM can generate the reset operation data and the set operation data without reading the data in the memory cell when writing data. Therefore, the process is simplified.
- the memory controller 200 calculates reset operation data. This is calculated based on Equation 1.
- the other processing procedures are the same as the processing procedures in FIG.
- the data of the memory cell may be read and the reset operation data and the set operation data may be generated with reference to the data.
- the generation of the reset operation data and the set operation data in this case can be performed in the same manner as the generation of these data in the above-described ReRAM.
- the memory controller 200 includes the write control unit 292, the determination unit 280, and the verification write unit 299.
- the memory 300 may include these. This is because the processing of the memory controller 200 can be simplified. In this case, the memory controller 200 issues only a write request to the memory 300. Then, the memory 300 performs writing, determination, and verification writing based on this request.
- Second Embodiment> In the first embodiment described above, when rewriting is performed, writing is performed without changing the write voltage or the like applied to the memory element. In contrast, in the second embodiment of the present technology, the write condition is changed at the time of rewriting. This improves the writing reliability.
- FIG. 15 is a diagram illustrating a functional configuration example according to the second embodiment of the present technology.
- the memory controller 200 shown in the figure includes a write condition setting unit 294.
- This write condition setting unit sets a write condition for the memory 300.
- the write condition is a condition for writing data to the memory cell.
- the write condition is set by issuing a write condition setting request to the memory 300.
- the memory 300 holds the write condition based on this write condition setting request and applies it at the time of writing.
- Other configurations are the same as those of the memory controller 200 and the memory 300 described with reference to FIG.
- the write conditions in the ReRAM include a write voltage applied to the memory element of the memory cell, its pulse width and pulse number, a current flowing through the memory cell, a read voltage, and a reference voltage at the time of reading.
- the memory controller 200 according to the second embodiment of the present technology sets a predetermined write condition in the memory 300 and performs normal write, and changes the write condition when rewriting. For example, rewriting is performed by changing the writing voltage.
- the diffusion voltage of the metal ions in the insulating layer of the memory element can be increased by increasing the writing voltage.
- the mobility of metal ions in the insulating layer is low, the resistance value of the memory element becomes a value near the threshold value at the time of writing, and even if the memory cell fails to be written, the writing voltage is increased at the time of rewriting.
- the memory element can be brought into a desired high resistance state or low resistance state. Thereby, writing can be made successful and write reliability can be improved. Note that power consumption increases when the write voltage is increased.
- the writing reliability can be improved while suppressing an increase in power consumption of the entire writing process by setting the writing voltage to be high only at the time of rewriting.
- FIG. 16 is a diagram illustrating an example of a processing procedure (memory controller) of a writing process according to the second embodiment of the present technology.
- the memory controller 200 starts a write process.
- the memory controller 200 issues a write condition setting request (step S951).
- a predetermined write condition is set in the memory 300.
- the memory controller 200 interprets the command and performs normal writing (step S960).
- the memory controller 200 performs a stable state determination process (step S970).
- the memory controller 200 changes the write condition (step S957) and issues a write condition setting request based on the changed condition (step S958).
- the memory controller 200 initializes a rewrite counter (step S959) and performs verification writing (step S980). Thereafter, when the value of the rewrite counter is “0” (step S954: Yes), the memory controller 200 notifies the host computer 100 that the write process has been completed normally and ends the write process.
- step S954: No When the value of the rewrite counter is not “0” (step S954: No), until the value of the rewrite counter becomes “0”, the rewrite processing count does not reach the upper limit (step S955: No).
- the rewrite process (process from step S970) is executed in a loop. However, if the number of rewrite processes has reached the upper limit in step S955 (step S955: Yes), the memory controller 200 performs error processing (step S956) without performing the rewrite process. As this error processing, the memory controller 200 notifies the host computer 100 that the data writing has ended abnormally. Thereafter, the memory controller 200 ends the writing process.
- the normal write (step S960) processing is the same as the normal write (step S910) described in FIG.
- the processing of the stable state determination (step S970) is the same as the processing of the stable state determination (step S920) described with reference to FIG.
- the verification write (step S980) processing is the same as the verification write (step S930) described in FIG. Further, the processing in the memory 300 is the same as the processing in the first embodiment of the present technology, and thus the description thereof is omitted.
- the write reliability can be further improved by changing the write condition at the time of rewriting.
- FIG. 17 is a diagram illustrating a functional configuration example according to the third embodiment of the present technology.
- the memory controller 200 shown in the figure includes a verification address information holding unit 295.
- the verification address information holding unit 295 holds verification address information.
- the verification address information is page address information of a page in the memory 300 to be verified.
- the writing control unit 292 causes the verification address information holding unit 295 to hold the page address information that has been written when writing is performed as verification address information.
- the verification writing unit 299 causes the verification address information holding unit 295 to hold the information of the page address that has been rewritten when the rewriting is performed, as verification address information.
- the verification writing unit 299 performs verification based on the verification address information held in the verification address information holding unit 295.
- Other configurations are the same as those of the memory controller 200 and the memory 300 described with reference to FIG.
- FIG. 18 is a diagram illustrating an example of a processing procedure (memory controller) of a writing process according to the third embodiment of the present technology.
- the memory controller 200 starts a write process.
- the memory controller 200 performs normal writing (step S810).
- the memory controller 200 holds verification address information (step S801).
- page addresses of all pages to be written are held in the verification address information holding unit 295 as verification address information.
- the page address designation method in the memory 300 is adopted, as in the first embodiment described above.
- a value obtained by adding the value of the offset register to the write address in the memory 300 included in the write command output from the host computer 100 is used as the write address (page address) in the memory 300. Therefore, the value of the offset register is used as the verification address information held in the verification address holding unit 295.
- the memory controller 200 performs a stable state determination process (step S820).
- the memory controller 200 initializes a rewrite counter (step S809) and performs verification writing (step S830). Thereafter, when the value of the rewrite counter is “0” (step S804: Yes), the memory controller 200 notifies the host computer 100 that the write process has been completed normally, and ends the write process. .
- step S804: No If the value of the rewrite counter is not “0” (step S804: No), the rewrite processing count does not reach the upper limit until the value of the rewrite counter becomes “0” (step S805: No).
- the rewrite process (process from step S820) is executed in a loop. However, if the number of rewrite processes has reached the upper limit in step S805 (step S805: Yes), the memory controller 200 performs error processing (step S806) without performing the rewrite process. As this error processing, the memory controller 200 notifies the host computer 100 that the data writing has ended abnormally. Thereafter, the memory controller 200 ends the writing process.
- FIG. 19 is a diagram illustrating an example of a processing procedure (memory controller) of verification writing processing according to the third embodiment of the present technology.
- This process is a process corresponding to step S830 described in FIG.
- the memory controller 200 checks whether or not all data has been verified (step S836). As a result, when the verification of all data has been completed (step S836: Yes), the verification writing process is terminated. On the other hand, if the verification of all the data has not been completed (step S836: No), the process proceeds to the verification write loop process from step S831.
- the memory controller 200 acquires verification address information (offset register value) from the verification address information holding unit 295 (step S831).
- the memory controller 200 acquires write data from the host computer 100 based on the verification address information (step S833). Further, the memory controller 200 specifies the verification destination page address in the memory 300 based on the verification address information, and generates and issues a verification write request (step S834).
- step S835: No when rewriting is not performed in the memory 300 (step S835: No), the memory controller 200 proceeds to the process of step S836.
- step S835: Yes when rewriting is performed in the memory 300 (step S835: Yes), the memory controller 200 adds the number of response write pages to the rewrite counter (step S837).
- step S837 the memory controller 200 holds the page address of the rewritten page as new verification address information in the verification address information holding unit 295 (step S839). This new verification address information is used for the next verification write process.
- the page address (offset register value) related to the verification address information acquired in step S831 is held in the verification address information holding unit 295 as the page address of the rewritten page. Therefore, the memory controller 200 can perform relative address designation by using the value of the offset register without using the offset register in the verification writing (step S830). Thereafter, the memory controller 200 returns to the process of step S836.
- the memory controller 200 outputs write information based on the write response to the determination unit 280 when performing the process of step S834.
- the verification address information holding unit 295 can have, for example, first and second FIFO (First-In / First-Out) memories.
- the verification address information generated in the normal writing or the immediately preceding verification write loop is held in the first FIFO memory, and is sequentially acquired in step S831.
- the new verification address information generated in step S839 is held in the second FIFO memory.
- the verification address information held in the second FIFO memory is moved to the first FIFO memory, so that the verification address information is processed in step S831 in the next verification write process. It can be.
- the value of the offset register can be used as verification address information.
- step S810 normal writing
- step S910 normal writing
- step S920 stable state determination
- information on a page address that has been rewritten is held as verification address information, and verification is performed based on this information. Can be suppressed. For this reason, the writing process can be speeded up.
- FIG. 20 is a diagram illustrating a functional configuration example according to the fourth embodiment of the present technology.
- the memory controller 200 shown in the figure includes a write control unit 291, a determination unit 280, a verification unit 293, and a rewrite address information holding unit 296.
- the write control unit 291 performs data writing and rewriting of the write data based on the verification result.
- the write control unit 291 issues a write request to the memory 300.
- the memory 300 outputs the number of write pages in writing and rewriting to the memory controller 200 as a write response.
- the write control unit 291 outputs the number of write pages to the determination unit 280 as write information.
- the rewrite address information holding unit 296 holds rewrite address information.
- the rewrite address information is information on the page address of the memory 300 to be rewritten.
- the above-described write control unit 291 performs rewriting based on the rewrite address information held in the rewrite address information holding unit 296.
- the verification unit 293 performs the verification described above.
- the verification unit 293 verifies data writing based on the determination result of the determination unit 280.
- the verification unit 293 performs verification by issuing a verification request to the memory 300.
- the memory 300 performs the verification process described in the first embodiment, and outputs the verification result to the memory controller 200 as a verification response.
- rewrite address information based on the verification result is held in the rewrite address information holding unit 296.
- the verification unit 293 in the fourth embodiment of the present technology performs only verification.
- verification and rewriting are issued as individual requests.
- Other configurations are the same as those of the memory controller 200 and the memory 300 described with reference to FIG.
- the write control unit 291 is an example of a write control unit described in the claims.
- the rewrite address information holding unit 296 is an example of a rewrite address information holding unit described in the claims.
- FIG. 21 is a diagram illustrating an example of a processing procedure (memory controller) of a writing process according to the fourth embodiment of the present technology.
- the memory controller 200 starts a write process. First, the memory controller 200 interprets the command and performs normal writing (step S860). Next, the memory controller 200 performs a stable state determination process (step S870). Next, the memory controller 200 initializes a rewrite counter (step S859), performs verification (step S880), and performs rewrite (step S890). Thereafter, when the value of the rewrite counter is “0” (step S854: Yes), the memory controller 200 notifies the host computer 100 that the write process has been completed normally, and ends the write process.
- step S854: No When the value of the rewrite counter is not “0” (step S854: No), the rewrite processing count does not reach the upper limit until the value of the rewrite counter becomes “0” (step S855: No).
- the rewrite process (process from step S870) is executed in a loop. However, if the number of rewrite processes has reached the upper limit in step S855 (step S855: Yes), the memory controller 200 performs error processing (step S856) without performing the rewrite process. As this error processing, the memory controller 200 notifies the host computer 100 that the data writing has ended abnormally. Thereafter, the memory controller 200 ends the writing process.
- step S860 and stable state determination (step S870) processes are the same as the normal write (step S910) and stable state determination (step S920) described in FIG.
- FIG. 22 is a diagram illustrating an example of a processing procedure (memory controller) of the verification processing according to the fourth embodiment of the present technology.
- This process is a process corresponding to step S880 described in FIG.
- the memory controller 200 initializes the offset register and the rewrite address information holding unit 296 (step S882).
- the memory controller 200 checks whether or not all data has been verified (step S886). As a result, when the verification of all data has been completed (step S886: Yes), the verification process is terminated. On the other hand, if the verification of all the data has not been completed (step S886: No), the process proceeds to step S883.
- the memory controller 200 acquires write data from the host computer 100 (step S883).
- the memory controller 200 generates and issues a verification request using the write data acquired in step S883 as comparison data (step S884).
- the memory controller 200 holds the result of the request returned from the memory 300 in the rewrite address information holding unit 296 together with the page address of the page (step S889).
- the page address of the page whose request result is “mismatch” is recognized as the page address of the page that needs to be rewritten in the subsequent rewriting process.
- the page address of the memory 300 is specified by the relative address based on the value of the offset register. For this reason, the page address of the page that needs to be rewritten is indicated by a relative address using the value of the offset register.
- the memory controller 200 updates the offset register (step S888) and returns to the process of step S886.
- the rewrite address information holding unit 296 can be constituted by, for example, a RAM that holds address information corresponding to the value of the offset register and a verification result at the address.
- FIG. 23 is a diagram illustrating an example of a rewrite process procedure (memory controller) according to the fourth embodiment of the present technology. This process is a process corresponding to step S890 described in FIG.
- the memory controller 200 initializes the offset register (step S892).
- the memory controller 200 checks whether or not all data has been rewritten (step S896). As a result, when rewriting of all data has been completed (step S896: Yes), the rewriting process is terminated.
- step S896 if rewriting of all data has not been completed (step S896: No), the process proceeds to step S891.
- the memory controller 200 acquires the verification result at the address corresponding to the value of the offset register from the rewrite address information holding unit 296 (step S891). If the result is “mismatch” (step S895: No), the memory controller 200 acquires write data from the host computer 100 (step S893). Next, the memory controller 200 generates and issues a rewrite request including the write data acquired in step S893 (step S894). After the rewrite operation in the memory 300 is completed and a write response is output from the memory 300, the memory controller 200 adds the number of response write pages to the rewrite counter (step S897), and proceeds to the process of step S898. .
- step S895 if the result is “match” (step S895: Yes), rewriting is not necessary, and the memory controller 200 skips the processing of step S893, step S894, and step S897, and proceeds to the processing of step S898. To do.
- step S898 the memory controller 200 updates the offset register (step S898), and returns to the process of step S896. Note that the memory controller 200 outputs write information based on the write response to the determination unit 280 when the process of step S894 is performed.
- FIG. 24 is a diagram illustrating an example of a processing procedure (memory) of the verification processing according to the fourth embodiment of the present technology.
- the memory 300 starts verification processing.
- the comparison data accompanying the request is stored in the work memory 320.
- the memory 300 reads data from the memory cell (step S732).
- the read data is held in the buffer 360.
- the memory 300 compares the data (step S738).
- the memory 300 compares the comparison data stored in the work memory 320 and the data held in the buffer 360.
- the result is output to the memory controller 200 (step S739), and the verification process is terminated.
- FIG. 25 is a diagram illustrating an example of a processing procedure (memory) of the rewrite processing according to the fourth embodiment of the present technology.
- the memory 300 starts a rewrite process.
- the memory controller 200 reads data from the memory cell (step S742).
- the buffer 360 does not hold data, so this read process is necessary.
- the memory 300 calculates reset operation data (step S743) and performs a reset operation (step S744).
- step S741 the memory 300 checks whether or not there is prior erasure.
- the case where the pre-erasing is not performed corresponds to the case of the above-described (d) rewriting operation (no pre-erasing).
- the memory 300 calculates set operation data (step S745), performs the set operation (step S746), and proceeds to the process of step S749.
- the case where the pre-erasure is performed corresponds to the case of the above-described (c) rewrite operation (with pre-erasure).
- the memory 300 skips the processes of step S745 and step S746 and proceeds to the process of step S749.
- step S749 as a result of the writing process, the memory 300 outputs the number of pages written to the memory controller 200 (step S749), and ends the rewriting process.
- FIG. 26 is a diagram illustrating an example of a processing procedure (memory) of the rewrite processing in the first modification example of the fourth embodiment of the present technology.
- the memory 300 reads page data from the memory cell (step S692).
- the memory 300 calculates reset operation data (step S693) and performs a reset operation (step S694).
- the memory 300 calculates set operation data (step S695), and performs the set operation (step S696).
- the memory 300 outputs the number of written pages to the memory controller 200 as a result of the rewriting process (step S699), and ends the rewriting process.
- step S889 of the verification process described with reference to FIG. 22 the results of all verification requests are held in the rewrite address information holding unit 296 as rewrite address information.
- the page address of the page in which the verification request result does not match may be held as address information. This is because in the subsequent rewriting process, the page address of the page that needs to be rewritten is specified, and the process is simplified.
- FIG. 27 is a diagram illustrating an example of the processing procedure (memory controller) of the verification processing according to the second modification example of the fourth embodiment of the present technology.
- This process is a process corresponding to step S880 described in FIG.
- step S885 the memory controller 200 checks the result of the request returned from the memory 300. If this result does not match (step S885: No), the memory controller 200 holds the page address of the page related to the verification request in the rewrite address information holding unit 296 (step S889). Thereafter, the process proceeds to step S888.
- step S885: Yes the memory controller 200 skips the process of step S889 and proceeds to the process of step S888.
- step S888 the memory controller 200 updates the offset register (step S888), and returns to the process of step S886.
- the processing procedure is the same as that described in FIG.
- FIG. 28 is a diagram illustrating an example of a processing procedure (memory controller) of a rewrite process according to the second modification example of the fourth embodiment of the present technology.
- This process is a process corresponding to step S890 described in FIG.
- this process is obtained by deleting the processes of Step S892, Step S895, and Step S898 from the process procedure described in FIG.
- the memory controller 200 identifies a page that needs to be rewritten and rewrites it.
- the processing procedure is the same as that described in FIG.
- FIG. 29 is a diagram illustrating a functional configuration example in the third modification example of the fourth embodiment of the present technology.
- the memory controller 200 shown in the figure includes a verification address information holding unit 295. Since the configuration other than this is the same as the functional configuration example described with reference to FIG.
- FIG. 30 is a diagram illustrating an example of a processing procedure (memory controller) of a writing process according to the third modification example of the fourth embodiment of the present technology.
- the process of step S801 is added between step S810 and step S820 with respect to the process procedure described in FIG.
- the processing procedure is the same as that described in FIG.
- FIG. 31 is a diagram illustrating an example of the processing procedure (memory controller) of the verification processing according to the third modification example of the fourth embodiment of the present technology.
- This process is a process corresponding to step S880 described in FIG.
- the memory controller 200 only initializes the rewrite address information holding unit 296.
- the memory controller 200 acquires verification address information from the verification address information holding unit 295 (step S881).
- the memory controller 200 checks the result of the request returned from the memory 300. If this result does not match (step S885: No), the memory controller 200 holds the page address of the page related to the verification request in the rewrite address information holding unit 296 (step S889).
- step S886 the process proceeds to step S886.
- the memory controller 200 skips the process of step S889 and proceeds to the process of step S886.
- step S888 it is possible to specify a page that needs to be verified, perform verification, and hold only the page address of the page for which the verification request result does not match as the verification result in the rewritten address information holding unit 296.
- step S888 since the process of step S888 is unnecessary, it is deleted. Other than this, the processing procedure is the same as that described in FIG.
- FIG. 32 is a diagram illustrating an example of a processing procedure (memory controller) of the rewrite processing in the third modification example of the fourth embodiment of the present technology.
- This process is a process corresponding to step S890 described in FIG. Further, this process is obtained by deleting steps S892, S895, and S898 from the procedure described in FIG. 23, and adding step S899 after step S897.
- the memory controller 200 identifies the page that needs to be rewritten and rewrites it, and causes the verification address information holding unit 295 to hold the page address of the page that has been rewritten.
- the processing procedure is the same as that described in FIG.
- the memory controller 200 includes the write control unit 291, the determination unit 280, the verification unit 293, and the rewrite address information holding unit 296. You may prepare. This is because the processing of the memory controller 200 can be simplified. In this case, the memory controller 200 issues only a write request to the memory 300. Then, the memory 300 performs writing, determination, and verification processing based on this request.
- the information processing system according to the first embodiment described above does not have a data backup function.
- the information processing system according to the fifth embodiment of the present technology includes a data backup function, and backs up data when a power supply abnormality occurs.
- FIG. 33 is a diagram illustrating a configuration example of an information processing system according to the fifth embodiment of the present technology.
- the information processing system shown in the figure is an example of an information processing system having a data backup function.
- the information processing system of FIG. 1 includes a host computer 100, a memory controller 200, a memory 300, signal lines 109 and 208, and a power supply voltage monitoring unit 107.
- the power supply voltage monitoring unit 107 monitors the voltage of the power supplied to the information system.
- the power supply voltage monitoring unit 107 outputs power supply voltage drop information to the memory controller 200 when the power supply voltage drops due to a power failure such as a power failure.
- the information processing system in the figure includes a backup power source such as a battery or a super capacitor (not shown). By supplying power from the backup power supply, the information processing system can operate in a short time even when a power supply abnormality occurs. During this time, the memory controller 200 saves the data held in the host computer to the memory 300.
- a backup power source such as a battery or a super capacitor (not shown).
- the host computer 100 shown in the figure is different from the host computer 100 described in FIG. 1 in that it includes a switching unit 150 instead of the memory controller interface 130.
- the switching unit 150 switches the connection destination of the DRAM 120 to the processor 110 or the memory controller 200.
- the switching unit 150 normally connects the DRAM 120 to the processor 110 via the bus device 101.
- the DRAM 120 stores data necessary for the operation of the processor 110.
- the memory controller 200 that has obtained information on the power supply voltage drop from the power supply voltage monitoring unit 107 outputs a control signal to the switching unit 150.
- the switching unit 150 connects the DRAM 120 to the memory controller 200. Since the configuration of the other information processing system is the same as that of the information processing system described with reference to FIG.
- FIG. 34 is a diagram illustrating a configuration example of the memory controller according to the fifth embodiment of the present technology.
- the memory controller 200 shown in the figure is different from the memory controller 200 described in FIG. 2 in that a DRAM interface 240 is provided instead of the host interface 230 and an input port 290 is provided.
- the DRAM interface 240 is an interface that communicates with the DRAM 120 of the host computer 100.
- the input port 290 is an input port to which the output of the power supply voltage monitoring unit 107 is connected.
- the input port 290 receives information about a power supply voltage drop by the power supply voltage monitoring unit 107.
- the other configuration of the memory controller 200 is the same as that of the memory controller 200 described with reference to FIG.
- the configuration of the memory 300 is the same as that of the memory 300 described with reference to FIG.
- FIG. 35 is a diagram illustrating a functional configuration example according to the fifth embodiment of the present technology. This figure assumes a functional configuration for writing data.
- the memory controller 200 shown in the figure is different from the memory controller 200 described in FIG. 17 in that it includes a DRAM control unit 297 and an address conversion information holding unit 298.
- the DRAM control unit 297 controls the switching unit 150.
- the DRAM control unit 297 also controls the DRAM 120 via the switching unit 150.
- the DRAM control unit 297 outputs a control signal to the switching unit 150 when the power supply is abnormal, and switches the connection destination of the DRAM 120 from the processor 110 to the memory controller 200. Thereafter, the DRAM control unit 297 outputs a control signal to the DRAM 120 via the switching unit 150, thereby accessing the DRAM 120 and outputting the data stored in the DRAM 120.
- the DRAM control unit 297 also generates address conversion information that is address conversion information for the memory address of the DRAM 120. This address conversion information will be described later.
- the write control unit 292 captures data output from the DRAM 120 as write data for the memory 300.
- the address translation information holding unit 298 holds address translation information.
- FIG. 36 is a diagram for explaining data movement in the DRAM.
- the figure shows an example of a DRAM 120 having ten storage areas, with the left side showing the state before data movement and the right side showing the state after data movement, respectively, as viewed in the drawing.
- the DRAM 120a in FIG. 2 is composed of two DRAMs, each DRAM having five storage areas, which are arranged at an upper address and a lower address. These are represented as a first region and a second region, respectively.
- Data # 1 to data # 10 are stored in the order of addresses in the DRAM 120 before data movement. It is assumed that data is written to the memory 300 by the memory controller 200 and the data # 2, data # 5, and data # 9 need to be rewritten as a result of the verification. Before rewriting is performed, the DRAM control unit 297 moves the data to the DRAM corresponding to the first area. Thereafter, the supply of power to the DRAM corresponding to the second region is stopped. As a result, the power consumption of the DRAM 120 can be reduced, and the battery or supercapacitor of the backup power source can be made to have a small capacity. Thereafter, rewriting is performed on the moved data.
- B in the figure represents an example in which the DRAM 120 is divided in the data direction. That is, the upper bit data is assigned to the first area, and the lower bit data is assigned to the second area. As in the above example, it is assumed that data # 2, data # 5, and data # 9 need to be rewritten.
- data # 2B, data # 5B, and data # 9B stored in the second area are moved to the first area. Thereafter, the supply of power to the DRAM corresponding to the second region is stopped.
- data is collected in a part of DRAMs by moving data of the DRAM 120 configured by a plurality of DRAMs. Therefore, it is necessary to determine whether the amount of data to be moved is a data amount that can be aggregated before the data is moved.
- this determination method for example, a method can be adopted in which the capacity of a plurality of DRAMs constituting the DRAM 120 is used as a threshold value and a determination is made based on whether or not the amount of data to be verified next time is equal to or less than this threshold value.
- the verification address information held in the verification address information holding unit 295 can be used. That is, the number of page addresses held in the verification address information multiplied by the page data amount can be used as the data amount to be verified next time.
- the write processing method of the memory controller 200 according to the fifth embodiment of the present technology is not limited to the method including the verification address information holding unit (the method according to the third embodiment of the present technology), but also the above-described method. Other methods can also be used. In other words, a method including the write condition setting unit (the method according to the second embodiment of the present technology) and a method including the rewrite address information holding unit (the method according to the fourth embodiment of the present technology) are used. You can also. Further, the method described in the first embodiment that does not use the verification address information holding unit or the like can be used.
- the address conversion information described above is address conversion information accompanying this data movement, is generated by the DRAM control unit 297, and is held in the address conversion information holding unit 298.
- the DRAM control unit 297 performs access based on the address conversion information held in the address conversion information holding unit 298.
- FIG. 37 is a diagram illustrating an example of a processing procedure (memory controller) of a writing process according to the fifth embodiment of the present technology.
- the memory controller 200 When the power supply voltage drop information is input from the power supply voltage monitoring unit 107, the memory controller 200 outputs a control signal to the switching unit 150. As a result, the switching unit 150 connects the DRAM 120 to the memory controller 200. Thereafter, the memory controller 200 starts a writing process. First, the memory controller 200 performs normal writing on all page data in the DRAM 120 (step S760). Next, the memory controller 200 holds verification address information (step S751).
- the page addresses of all pages to be written are held in the verification address information holding unit 295 as verification address information.
- the memory controller 200 checks whether or not rewriting has already been performed on the memory 300 (step S752). If rewriting has been performed (step S752: Yes), the data is moved. (Step S790).
- step S752 when rewriting is not performed (step S752: No), the process of step S790 is skipped.
- the memory controller 200 performs a stable state determination process (step S770).
- step S759 the memory controller 200 initializes a rewrite counter (step S759), and performs verification writing (step S780). Thereafter, when the value of the rewrite counter is “0” (step S754: Yes), the memory controller 200 ends the write process.
- step S754: No until the value of the rewrite counter becomes “0”, the rewrite processing count does not reach the upper limit (step S755: No).
- the rewrite process (process from step S752) is executed in a loop.
- step S755 the memory controller 200 performs error processing (step S756) without performing the rewrite process.
- error processing for example, the memory controller 200 notifies the host computer 100 that data backup has failed. Thereafter, the writing process is terminated.
- the normal write (step S760) processing is the same as the normal write (step S910) described in FIG.
- the process of the stable state determination (step S770) is the same as the stable state determination (step S920) described with reference to FIG.
- the verification writing (step S780) is the same as the verification writing (step S930) described in FIG.
- FIG. 38 is a diagram illustrating an example of a processing procedure (memory controller) of data movement processing according to the fifth embodiment of the present technology. This process is a process corresponding to step S790 described in FIG.
- the memory controller 200 checks whether or not the data has been moved (step S791). If the data has been moved (step S791: Yes), the subsequent process is skipped and the data movement process is terminated. On the other hand, if it has not been moved (step S791: No), the amount of data to be verified next time is calculated (step S792). If the calculated data amount is not less than or equal to the threshold (step S793: No), the memory controller 200 skips the subsequent processing and ends the data movement processing.
- step S793 if the calculated data amount is equal to or smaller than the threshold (step S793: Yes), the memory controller 200 moves the data in the DRAM 120 (step S794), and turns off the power of the DRAM after the data movement (step S795). Finally, the memory controller 200 generates address conversion information (step S796) and ends the data movement process.
- the memory controller 200 checks whether or not rewriting is performed (step S752), and moves data (step S790). However, it is also possible to configure an information processing system having a data backup function that omits these processes.
- the backup power supply can be reduced in size by moving data within the DRAM 120 and supplying power only to the DRAM in which data is collected. Furthermore, the calculation of the amount of data related to the data movement process can be simplified by using the verification address information when moving the data.
- the embodiment of the present technology it is determined whether or not the state of the memory cell is stable after the data is written, and the data is read after the state of the memory cell is stabilized. By performing the verification, it is possible to verify the correct write data. Thereby, unnecessary rewriting can be suppressed and the writing reliability of the nonvolatile memory can be improved.
- the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it.
- a recording medium for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.
- this technique can also take the following structures.
- a determination unit configured to determine whether or not the state of the memory cell after data writing is stable in a nonvolatile memory including a memory cell in which the state is unstable after data writing;
- a verification unit that compares and verifies the read data read from the memory cell in which the data is written based on the determination result and the write data related to the write;
- a memory controller comprising: a write control unit that performs writing of the data and rewriting of the write data based on a result of the verification.
- the memory controller according to any one of (1) to (3), wherein the determination unit performs the determination based on a lapse of a predetermined stabilization time after the data is written.
- the nonvolatile memory is accessed on a page basis by a page address,
- the write control unit continuously writes data consisting of a plurality of pages,
- the verification unit performs the verification in page units in the order in which the data is written,
- the memory controller according to any one of (1) to (3), wherein the determination unit determines that the state of the memory cell is stable during the verification.
- a rewrite address information holding unit that holds rewrite address information that is information of a page address of the nonvolatile memory that performs the rewrite
- the verification unit continuously performs the verification after writing the data consisting of the plurality of pages, and holds the rewrite address information based on the verification result in the rewrite address information holding unit
- the memory controller according to (5), wherein the write control unit performs the rewrite based on the held rewrite address information.
- a verification address information holding unit that holds verification address information that is information of a page address of the nonvolatile memory that performs the verification;
- the write control unit causes the verification address information holding unit to hold, as the verification address information, information on the page address on which the writing and the rewriting are performed when the writing and the rewriting are performed,
- the memory controller according to (5), wherein the verification unit performs the verification based on the held verification address information.
- the nonvolatile memory is accessed on a page basis by a page address
- the write control unit continuously writes data consisting of a plurality of pages
- the verification unit performs the verification in page units in the order in which the data is written
- the determination unit determines the verification if the number of pages of the write data is equal to or greater than the number of state stabilization pages, which is the number of pages corresponding to a predetermined stabilization time after data is written in the nonvolatile memory.
- the state of the memory cell is determined to be stable, and if the number of pages of the write data is less than the number of state-stabilized pages, the state of the memory cell is awaited after elapse of the predetermined stabilization time
- the memory controller according to any one of (1) to (3), in which it is determined that is stable.
- a write control unit for writing data in a nonvolatile memory including a memory cell in which a period of unstable state exists after data writing;
- a determination unit configured to determine whether or not the state of the memory cell after writing the data is stable; Verification that compares the read data read from the memory cell in which the data is written based on the determination result and the write data related to the write, and rewrites the write data based on the verification result
- a memory controller comprising a writing unit.
- (10) a nonvolatile memory composed of memory cells in which a period of unstable state exists after data writing;
- a determination unit configured to determine whether or not a state of the memory cell after data writing in the nonvolatile memory is stable;
- a verification unit that compares and verifies the read data read from the memory cell in which the data is written based on the determination result and the write data related to the write;
- a storage device comprising: a write control unit that writes the data and rewrites the write data based on the verification result.
- (11) a nonvolatile memory composed of memory cells in which a period of unstable state exists after data is written;
- a memory controller for controlling the nonvolatile memory;
- a host computer that accesses the nonvolatile memory via the memory controller;
- the memory controller is A determination unit configured to determine whether or not a state of the memory cell after data writing in the nonvolatile memory is stable;
- a verification unit that compares and verifies the read data read from the memory cell in which the data is written based on the determination result and the write data related to the write;
- An information processing system comprising: a writing control unit that performs writing of the data and rewriting of the writing data based on a result of the comparison.
- a determination procedure for determining whether or not the state of the memory cell after data writing is stable in a nonvolatile memory including a memory cell in which the state is unstable after data writing;
- a verification procedure for comparing and verifying the read data read from the memory cell in which the data is written based on the result of the determination and the write data related to the write;
- a non-volatile memory control method comprising: a write control procedure for writing the data and rewriting the write data based on the result of the comparison.
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Abstract
Description
1.第1の実施の形態(複数ページの書込みを連続して行う例)
2.第2の実施の形態(書込み条件を変更する例)
3.第3の実施の形態(検証アドレス情報を使用する例)
4.第4の実施の形態(複数ページの書込みおよび検証を連続して行う例)
5.第5の実施の形態(データバックアップ装置に適用した例)
[情報処理システムの構成]
図1は、本技術の第1の実施の形態における情報処理システムの構成例を示す図である。同図の情報処理システムは、ホストコンピュータ100と、メモリコントローラ200と、メモリ300と、信号線109および208とを備える。なお、メモリ300は、特許請求の範囲に記載の不揮発メモリの一例である。
図2は、本技術の第1の実施の形態におけるメモリコントローラの構成例を示す図である。同図のメモリコントローラ200は、プロセッサ210と、RAM220と、ホストインターフェース230と、ECC処理部250と、ROM260と、メモリインターフェース270と、バス装置201とを備える。
図3は、本技術の第1の実施の形態におけるメモリの構成例を示す図である。同図のメモリ300は、制御部310と、作業メモリ320と、メモリコントローラインターフェース330と、アドレスデコーダ340と、メモリセルアレイ350と、バッファ360と、バス装置301とを備える。
本技術の第1の実施の形態における情報処理システムの書込み処理のデータのやり取りについて、ホストコンピュータ100がDRAM120に記憶されているデータをメモリ300に書込む場合を例に挙げて説明する。まず、ホストコンピュータ100が、書込みコマンドを生成し、メモリコントローラ200に対して発行する。このコマンドにはDRAM120における書込みデータの先頭アドレス、書込みデータサイズ(ページ数)およびメモリ300における書込みアドレス(ページアドレス)が含まれている。発行されたコマンドは、メモリコントローラインターフェース130およびホストインターフェース230を介してメモリコントローラ200に入力され、RAM220に記憶される。プロセッサ210は、このコマンドを解釈してデータの書込みを行う。まず、コマンドに基づいてDRAM120から書込みデータを読み出して、RAM220に記憶させる。次に、プロセッサ210は、ECC処理部250に指示を出し、読み出した書込みデータの符号化を行わせる。その後、プロセッサ210は、書込みリクエストを生成してメモリ300に対して発行する。その際に、符号化した書込みデータをメモリ300に対して出力する。最後に、データの書込みが成功したか否かについて検証を行う。
図4は、本技術の第1の実施の形態における機能構成例を示す図である。同図は、データの書込みを行う際の機能構成を想定したものである。メモリコントローラ200は、書込制御部292と、判断部280と、検証書込み部299とを備える。これらの機能は、図2において説明したプロセッサ210が実行するファームウェアにより実現される。なお、書込制御部292は、特許請求の範囲に記載の書込み制御部の一例である。
図5は、本技術の第1の実施の形態における判断部の構成例を示す図である。同図の判断部280は、タイマ部281と、書込みページ数判断部282と、メモリセル安定状態判断部283とを備える。
図6は、本技術の第1の実施の形態における書込み操作を説明する図である。同図を参照して、メモリ300のメモリセルアレイ350における書込み操作について説明する。前述のように、ReRAMでは、メモリセルに対してリセット操作およびセット操作を行うことにより書込が行われる。ここで、ReRAMの記憶素子が低抵抗状態にある場合を値「1」、高抵抗状態にある場合を値「0」に対応させる。これにより、リセット操作によりメモリセルには値「0」が書き込まれ、セット操作によりメモリセルには値「1」が書き込まれることとなる。
事前消去によりメモリセルのデータは全て値「1」となっているため、メモリ300はリセット操作のみを行う。リセット操作用データは、書込みデータに対してビット毎の論理反転演算を行うことにより算出される。この演算を論理式で表すと、次式のようになる。
RData=~W ・・・式1
ただし、RDataはリセット操作用データを表す。Wは書込みデータ(ページデータ)を表す。~はビット毎の論理反転を表す演算子である。同図におけるaに書込みデータ、メモリセルのデータおよびリセット操作用データの関係を表した。
メモリ300は、リセット操作およびセット操作を行う。リセット操作用データは、以下の手順により算出される。まず、メモリセルに書き込まれているデータが読み出される。次に、読み出されたデータと書込みデータとについてビット毎の排他的論理和演算が行われる。最後に、この排他的論理和演算の結果と読み出されたデータとについてビット毎の論理積演算が行われる。メモリ300は、得られた演算結果をリセット操作用データとする。これらの演算を論理式で表すと、次式のようになる。
RData=((W^R)&R) ・・・式2
ただし、Rは読み出したデータ(ページデータ)を表す。また、^および&はそれぞれビット毎の排他的論理和演算およびビット毎の論理積演算を表す演算子である。
SData=((W^R)&W) ・・・式3
ただし、SDataはセット操作用データを表す。同図におけるbに書込みデータ、読み出されたデータ、リセット操作用データおよびセット操作用データの関係を表した。
メモリ300はリセット操作のみを行う。リセット操作用データは、式2に基づいて算出される。
この場合は、(b)と同じ操作にすることができる。すなわち、メモリ300は、リセット操作およびセット操作を行う。リセット操作用データおよびセット操作用データは、それぞれ式2および式3に基づいて算出される。
図7は、本技術の第1の実施の形態における書込み処理の処理手順(メモリコントローラ)の一例を示す図である。なお、本技術の第1の実施の形態における書込み処理では、再書込みカウンタおよびオフセットレジスタを使用する。これらは、メモリコントローラ200においてソフトウェアにより実現されるカウンタおよびレジスタである。再書込みカウンタは、書込み処理における再書込みを行った回数を保持するものである。オフセットレジスタは、DRAM120における書込みデータの先頭アドレスからのオフセット値を保持するものである。なお、このオフセット値は、ページ数を単位とする値である。
図8は、本技術の第1の実施の形態における通常書込み処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図7において説明したステップS910に対応する処理である。まず、メモリコントローラ200は、書込み設定を行う(ステップS911)。具体的には、書込みコマンドに基づいて、書込みデータの読出し元であるDRAM120の書込みデータの先頭アドレス、書込みデータのページ数および書込み先であるメモリ300におけるページアドレスを設定する。次に、メモリコントローラ200は、オフセットレジスタを初期化する(ステップS912)。その後、メモリコントローラ200は、全てのデータの書込みが終了したか否かを調べる(ステップS916)。具体的には、メモリコントローラ200が、ステップS911において設定した書込みデータのページ数と書込みが終了したページ数、例えば、オフセットレジスタの値とを比較することにより行う。
図9は、本技術の第1の実施の形態における安定状態判断処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図7において説明したステップS920に対応する処理である。まず、メモリコントローラ200は、書込みページ数が状態安定化ページ数以上か否かを判断する(ステップS921)。その結果、書込みページ数が状態安定化ページ数以上であった場合には(ステップS921:Yes)、安定状態判断処理を終了する。一方、書込みページ数が状態安定化ページ数未満であった場合には(ステップS921:No)、メモリコントローラ200は、安定化時間が経過しているか否かを判断し(ステップS922)、安定化時間が経過するまで待機する(ステップS922:No)。一方、安定化時間が経過している場合には(ステップS922:Yes)、安定状態判断処理を終了する。なお、メモリコントローラ200は、ステップS921の処理を行った際に、書込みページ数判断部282のカウンタをリセットしてこれに保持された書込みページ数をゼロにする。
図10は、本技術の第1の実施の形態における検証書込み処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図7において説明したステップS930に対応する処理である。まず、メモリコントローラ200は、オフセットレジスタを初期化する(ステップS932)。次に、メモリコントローラ200は、全てのデータの検証が終了したか否かを調べる(ステップS936)。その結果、全てのデータの検証が終了していた場合には(ステップS936:Yes)、検証書込み処理を終了する。一方、全てのデータの検証が終了していない場合には(ステップS936:No)、ステップS933からの処理に移行する。
図11は、本技術の第1の実施の形態における書込み処理の処理手順(メモリ)の一例を示す図である。メモリ300は、メモリコントローラ200から書込みリクエストが発行されると、書込み処理を開始する。なお、リクエストに伴う書込みデータは、作業メモリ320に記憶される。まず、メモリ300は、事前消去の有無を調べ(ステップS701)、事前消去がされていない場合は(ステップS701:No)、ステップS702乃至ステップS706の処理を実行する。一方、事前消去がされている場合は(ステップS701:Yes)、メモリ300は、ステップS707およびステップS708の処理を実行する。
図12は、本技術の第1の実施の形態における検証書込み処理の処理手順(メモリ)の一例を示す図である。メモリ300は、メモリコントローラ200から検証書込みリクエストが発行されると、検証書込み処理を開始する。なお、リクエストに伴う比較データは、作業メモリ320に記憶される。まず、メモリ300は、メモリセルからデータ(ページデータ)の読出しを行う(ステップS712)。読み出されたデータは、バッファ360に保持される。次に、メモリ300は、データの比較を行う(ステップS718)。具体的には、メモリ300は、作業メモリ320に記憶された比較データおよびバッファ360に保持されたデータの比較を行う。
図13は、本技術の第1の実施の形態における再書込み処理の処理手順(メモリ)の一例を示す図である。本処理は、図12において説明したステップS720に対応する処理である。すなわち、上述の検証書込み処理から呼び出される処理であるため、バッファ360にはメモリセルから読み出したデータが保持されている。このデータを使用して再書込みを行う。メモリ300は、リセット操作用データの算出を行い(ステップS723)、リセット操作を行う(ステップS724)。本技術の第1の実施の形態では、再書込みの際、事前消去の有無にかかわらずリセット操作を行う。
上述の第1の実施の形態では、図10において説明した検証書込み処理のステップS933において、検証のためのデータを1ページずつホストコンピュータ100のDRAM120から読み出して転送していた。しかし、複数のページデータをまとめて転送してもよい。データ転送時間を短縮することができるためである。そこで、第1の変形例では、検証書込み処理において、DRAM120から複数のページデータをまとめて転送する。これにより、転送された複数ページのデータはメモリコントローラ200のRAM220に記憶され、検証書込みリクエスト発行処理(ステップS934)の際に、1ページずつ読み出されて、検証に使用される。
上述の第1の実施の形態では、図10において説明した検証書込み処理のステップS934において、検証書込みリクエストの発行に伴ってページデータを出力していた。しかし、複数のページデータをまとめて出力し、メモリ300に転送してもよい。第1の変形例と同様、データ転送時間を短縮することができるためである。そこで、第2の変形例では、検証書込み処理において、検証書込みリクエスト発行の際に、複数のページデータをまとめて出力する。これにより、転送された複数のページデータはメモリ300の作業メモリ320に記憶され、メモリ300における検証書込み処理の際に、1ページずつ読み出されて、検証および再書込みに使用される。
上述の第1の実施の形態では、図4における判断部280は、状態安定化ページ数以上の書込みページ数および書込み後の安定化時間の経過の何れかに基づいてメモリセルの状態が安定しているか否かの判断を行っていた。しかし、安定化時間の経過のみに基づいて判断を行ってもよい。判断部280の構成を簡素化することができるためである。そこで、第3の変形例では、書込みページ数判断部282を省略し、タイマ部281による安定化時間の経過のみに基づいて判断を行う。
上述の第1の実施の形態では、図4における判断部280は、状態安定化ページ数以上の書込みページ数および書込み後の安定化時間の経過の何れかに基づいてメモリセルの状態が安定しているか否かの判断を行っていた。しかし、判断部280は、書込制御部292における複数ページからなるデータの書込みが連続して行われ、この書込みが行われた順に検証書込み部299において検証が行われた後には、メモリセルの状態が安定していると判断してもよい。ページデータサイズが大きく処理に時間がかかる場合等には、複数ページからなるデータの書込みにより、所定の安定化時間の経過が担保されるためである。そこで、書込みページ数判断部282は、複数ページからなる書込みであるか否かに基づいて判断を行う。これにより、判断部280の構成を簡素化することができる。
上述の第1の実施の形態では、事前消去されている場合の再書込み処理においてリセット操作のみを行っていたが、事前消去されている場合であってもリセット操作およびセット操作により再書込みを行ってもよい。リセット操作によりライトディスターブ現象が発生した場合であっても、セット操作を行うことによりメモリセルに書込まれたデータの反転を防ぐことができる。なお、ライトディスターブ現象とは、メモリセルに書込みを行った際に、近隣のメモリセルに記憶されたデータが書き換えられる現象である。そこで、事前消去されている場合であってもリセット操作およびセット操作により再書込みを行う。これにより、データの書込みの信頼性を向上させることができる。
(a')書込み操作(事前消去あり)の場合
メモリ300はリセット操作のみを行う。リセット操作用データは、式1に基づいて算出される。すなわち、前述した(a)と同じ操作にすることができる。
(b')書込み操作(事前消去なし)の場合
メモリ300は、リセット操作およびセット操作を行う。リセット操作用データおよびセット操作用データは、それぞれ式2および式3に基づいて算出される。すなわち、前述した(b)と同じ操作にすることができる。
(c')再書込み操作(事前消去あり)の場合
この場合は、(b')と同じ操作にすることができる。
(d')再書込み操作(事前消去なし)の場合
この場合も、(b')と同じ操作にすることができる。
図14は、本技術の第1の実施の形態の変形例における再書込み処理の処理手順(メモリ)の一例を示す図である。第5の変形例では、事前消去の有無にかかわらずリセット操作およびセット操作を行うため、図13において説明した再書込み処理と比較して処理が簡素化される。まず、メモリ300は、リセット操作用データを算出し(ステップS723)、リセット操作を行う(ステップS724)。次に、メモリ300は、セット操作用データを算出し(ステップS725)、セット操作を行う(ステップS726)。次に、メモリ300は、再書込み処理の結果として、書込みを行ったページ数をメモリコントローラ200に対して出力し(ステップS729)、再書込み処理を終了する。
上述の第1の実施の形態では、不揮発性メモリとして、ReRAMを想定していたが、データの書込みの直後に読出しを行うと書き込まれたデータが破壊されるPCRAMであってもよい。PCRAMにおいても、複数ページからなるデータの書込みを行った後に、メモリセルの状態が安定しているか否かの判断を行って、検証を行うことにより、正確な書込みデータの検証が可能になる。これにより、書込み信頼性を向上させることができる。
PCRAMは、データの書込みの際に、メモリセルのデータを読み出すことなくリセット操作用データおよびセット操作用データを生成することができる。そのため、処理が簡素化される。なお、本技術の第1の実施の形態の第6の変形例では、事前消去は行われないものと想定する。これにより、書込み処理および再書込み処理は同一の処理となり、図14において説明した処理と同様の処理手順となる。ステップS723において、メモリコントローラ200は、リセット操作用データを算出する。これは、式1に基づいて算出される。ステップS725において、メモリコントローラ200は、セット操作用データを算出する。これは、次式に基づいて算出される。
SData=W
これ以外の処理手順は、図14における処理手順と同様であるため説明を省略する。なお、PCRAMにおいても、ReRAMと同様に、メモリセルのデータの読み出しを行い、これを参照してリセット操作用データおよびセット操作用データを生成してもよい。この場合のリセット操作用データおよびセット操作用データの生成は、前述したReRAMにおけるこれらのデータの生成と同様にすることができる。
上述の第1の実施の形態では、メモリコントローラ200が、書込み制御部292と、判断部280と、検証書込み部299とを備えていたが、メモリ300がこれらを備えてもよい。メモリコントローラ200の処理を簡素化できるからである。この場合、メモリコントローラ200は、メモリ300に対して、書込みリクエストのみを発行する。そして、メモリ300が、このリクエストに基づいて書込み、判断および検証書込みの処理を行う。
上述の第1の実施の形態では、再書込みを行う際、記憶素子に印加する書込み電圧等を変更せずに書込みを行っていた。これに対し本技術の第2の実施の形態では、再書込みの際に、書込み条件を変更する。これにより、書込みの信頼性を向上させる。
図15は、本技術の第2の実施の形態における機能構成例を示す図である。同図のメモリコントローラ200は、書込み条件設定部294を備える。この書込み条件設定部はメモリ300に対して書込み条件を設定するものである。ここで、書込み条件とは、メモリセルにデータを書き込む際の条件である。書込み条件の設定は、メモリ300に対して書込み条件設定リクエストを発行することにより行われる。メモリ300は、この書込み条件設定リクエストに基づく書込み条件を保持し、書込みの際に適用する。これ以外の構成は、図4において説明したメモリコントローラ200およびメモリ300と同様であるため、説明を省略する。
ReRAMにおける書込み条件としては、メモリセルの記憶素子に印加する書込み電圧とそのパルス幅およびパルス数、メモリセルに流す電流ならびに読出し電圧および読出しの際の参照電圧が挙げられる。本技術の第2の実施の形態のメモリコントローラ200は、既定の書込み条件をメモリ300に設定して通常書込みを行い、再書込みの際には書込み条件を変更する。例えば、書込み電圧を変更して再書込みを行う。
図16は、本技術の第2の実施の形態における書込み処理の処理手順(メモリコントローラ)の一例を示す図である。ホストコンピュータ100から書込みコマンドが発行されると、メモリコントローラ200は、書込み処理を開始する。まず、メモリコントローラ200は、書込み条件設定リクエストの発行を行う(ステップS951)。これにより、既定の書込み条件がメモリ300に設定される。次に、メモリコントローラ200は、コマンドを解釈して通常書込みを行う(ステップS960)。次に、メモリコントローラ200は、安定状態判断処理を行う(ステップS970)。その後、メモリコントローラ200は、後続する検証書込み処理に先立ち、書込み条件を変更し(ステップS957)、変更した条件に基づく書込み条件設定リクエストを発行する(ステップS958)。次に、メモリコントローラ200は、再書込みカウンタを初期化し(ステップS959)、検証書込みを行う(ステップS980)。その後、再書込みカウンタの値が「0」の場合は(ステップS954:Yes)、メモリコントローラ200は、ホストコンピュータ100に対して書込み処理が正常に終了したことを通知し、書込み処理を終了する。
上述の第1の実施の形態では、再書込みの際、書込み処理の対象となった全てのメモリセルに対して検証を行うため、長い処理時間を要していた。これに対し、本技術の第3の実施の形態では、検証が必要なページのページアドレスを保持して検証を行い、不必要な検証を抑制することにより、書込み処理を高速化する。
図17は、本技術の第3の実施の形態における機能構成例を示す図である。同図のメモリコントローラ200は、検証アドレス情報保持部295を備える。この検証アドレス情報保持部295は、検証アドレス情報を保持するものである。ここで、検証アドレス情報とは、検証を行うメモリ300におけるページのページアドレスの情報である。書込制御部292は、書込みを行った際に書込みを行ったページアドレスの情報を検証アドレス情報として検証アドレス情報保持部295に保持させる。同様に、検証書込み部299は、再書込みを行った際に再書込みを行ったページアドレスの情報を検証アドレス情報として検証アドレス情報保持部295に保持させる。また、検証書込み部299は、検証アドレス情報保持部295に保持された検証アドレス情報に基づいて検証を行う。これ以外の構成は、図4において説明したメモリコントローラ200およびメモリ300と同様であるため、説明を省略する。
図18は、本技術の第3の実施の形態における書込み処理の処理手順(メモリコントローラ)の一例を示す図である。ホストコンピュータ100から書込みコマンドが発行されると、メモリコントローラ200は、書込み処理を開始する。まず、メモリコントローラ200は、通常書込みを行う(ステップS810)。次に、メモリコントローラ200は、検証アドレス情報の保持を行う(ステップS801)。この場合、書込み対象となった全てのページのページアドレスが検証アドレス情報として、検証アドレス情報保持部295に保持される。なお、第3の実施の形態においても、前述した第1の実施の形態と同様の、メモリ300におけるページアドレスの指定方式を採用している。すなわち、ホストコンピュータ100が出力した書込みコマンドに含まれるメモリ300における書込みアドレスにオフセットレジスタの値を加算した値をメモリ300における書込みアドレス(ページアドレス)としている。このため、検証アドレス保持部295に保持される検証アドレス情報として、オフセットレジスタの値が使用される。
図19は、本技術の第3の実施の形態における検証書込み処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図18において説明したステップS830に対応する処理である。まず、メモリコントローラ200は、全てのデータの検証が終了したか否かを調べる(ステップS836)。その結果、全てのデータの検証が終了していた場合には(ステップS836:Yes)、検証書込み処理を終了する。一方、全てのデータの検証が終了していない場合には(ステップS836:No)、ステップS831からの検証書込みループの処理に移行する。メモリコントローラ200は、検証アドレス情報保持部295から検証アドレス情報(オフセットレジスタの値)を取得する(ステップS831)。次に、メモリコントローラ200は、この検証アドレス情報に基づいてホストコンピュータ100から書込みデータを取得する(ステップS833)。また、メモリコントローラ200は、検証アドレス情報に基づいてメモリ300における検証先ページアドレスを特定し、検証書込みリクエストを生成して発行する(ステップS834)。
上述の第1の実施の形態では、通常書込みは連続して行うものの、検証と再書込みとは交互に行うため、リクエストの生成が煩雑となる問題があった。このため、検証リクエストと書込みリクエストを統合した検証書込みリクエストを使用していた。しかし、その一方で、メモリ300におけるリクエストの処理が複雑なものになっていた。これに対し、本技術の第4の実施の形態では、検証および再書込みも連続して行う。これにより、リクエストの生成を容易なものにする。
図20は、本技術の第4の実施の形態における機能構成例を示す図である。同図のメモリコントローラ200は、書込制御部291と、判断部280と、検証部293と、再書込アドレス情報保持部296とを備える。
図21は、本技術の第4の実施の形態における書込み処理の処理手順(メモリコントローラ)の一例を示す図である。ホストコンピュータ100から書込みコマンドが発行されると、メモリコントローラ200は、書込み処理を開始する。まず、メモリコントローラ200は、コマンドを解釈して通常書込みを行う(ステップS860)。次に、メモリコントローラ200は、安定状態判断処理を行う(ステップS870)。次に、メモリコントローラ200は、再書込みカウンタを初期化し(ステップS859)、検証を行い(ステップS880)、再書込みを行う(ステップS890)。その後、再書込みカウンタの値が「0」の場合は(ステップS854:Yes)、メモリコントローラ200は、ホストコンピュータ100に対して書込み処理が正常に終了したことを通知し、書込み処理を終了する。
図22は、本技術の第4の実施の形態における検証処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図21において説明したステップS880に対応する処理である。まず、メモリコントローラ200は、オフセットレジスタおよび再書込アドレス情報保持部296を初期化する(ステップS882)。次に、メモリコントローラ200は、全てのデータの検証が終了したか否かを調べる(ステップS886)。その結果、全てのデータの検証が終了していた場合には(ステップS886:Yes)、検証処理を終了する。一方、全てのデータの検証が終了していない場合には(ステップS886:No)、ステップS883からの処理に移行する。メモリコントローラ200は、ホストコンピュータ100から書込みデータを取得する(ステップS883)。次に、メモリコントローラ200は、ステップS883において取得した書込みデータを比較データとして検証リクエストを生成し、発行する(ステップS884)。
図23は、本技術の第4の実施の形態における再書込み処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図21において説明したステップS890に対応する処理である。まず、メモリコントローラ200は、オフセットレジスタを初期化する(ステップS892)。次に、メモリコントローラ200は、全てのデータの再書込みが終了したか否かを調べる(ステップS896)。その結果、全てのデータの再書込みが終了していた場合には(ステップS896:Yes)、再書込み処理を終了する。
図24は、本技術の第4の実施の形態における検証処理の処理手順(メモリ)の一例を示す図である。メモリ300は、メモリコントローラ200から検証のリクエストが発行されると、検証処理を開始する。なお、リクエストに伴う比較データは、作業メモリ320に記憶される。まず、メモリ300は、メモリセルからデータの読出しを行う(ステップS732)。読み出されたデータは、バッファ360に保持される。次に、メモリ300は、データの比較を行う(ステップS738)。具体的には、メモリ300は、作業メモリ320に記憶された比較データおよびバッファ360に保持されたデータの比較を行う。その結果をメモリコントローラ200に対して出力し(ステップS739)、検証処理を終了する。
図25は、本技術の第4の実施の形態における再書込み処理の処理手順(メモリ)の一例を示す図である。メモリ300は、メモリコントローラ200から再書込みのリクエストが発行されると、再書込み処理を開始する。まず、メモリコントローラ200は、メモリセルからデータの読出しを行う(ステップS742)。図13において説明した再書込み処理とは異なり、バッファ360には、データが保持されていないため、この読出し処理が必要となる。次に、メモリ300は、リセット操作用データの算出を行い(ステップS743)、リセット操作を行う(ステップS744)。
上述の第4の実施の形態では、事前消去がある場合の再書込み処理においてリセット操作のみを行っていたが、事前消去がある場合であってもリセット操作およびセット操作により再書込みを行ってもよい。前述の第1の実施の形態の第5の変形例と同様に、ライトディスターブ現象が発生した場合であっても、メモリセルに書込まれたデータの反転を防いで、データの書込みの信頼性を向上させることができるためである。書込みおよび再書込みの操作は、前述の第1の実施の形態の第5の変形例において説明した(a')~(d')と同様であるため説明を省略する。
図26は、本技術の第4の実施の形態の第1の変形例における再書込み処理の処理手順(メモリ)の一例を示す図である。まず、メモリ300は、メモリセルからページデータの読出しを行う(ステップS692)。次に、メモリ300は、リセット操作用データを算出し(ステップS693)、リセット操作を行う(ステップS694)。次に、メモリ300は、セット操作用データを算出し(ステップS695)、セット操作を行う(ステップS696)。次に、メモリ300は、再書込み処理の結果として、書込みを行ったページ数をメモリコントローラ200に対して出力し(ステップS699)、再書込み処理を終了する。
上述の第4の実施の形態では、図22において説明した検証処理のステップS889において、全ての検証リクエストの結果を再書込みアドレス情報として再書込アドレス情報保持部296に保持させていた。しかし、検証リクエストの結果が不一致となったページのページアドレスをアドレス情報として保持させてもよい。後続の再書込み処理において、再書込みが必要なページのページアドレスが特定されて、処理が簡略化されるためである。
図27は、本技術の第4の実施の形態の第2の変形例における検証処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図21において説明したステップS880に対応する処理である。ステップS885において、メモリコントローラ200は、メモリ300から返されたリクエストの結果を調べる。この結果が一致でなかった場合(ステップS885:No)、メモリコントローラ200は、検証リクエストに係るページのページアドレスを再書込アドレス情報保持部296に保持させる(ステップS889)。その後、ステップS888の処理に移行する。一方、メモリ300から返されたリクエストの結果が一致であった場合(ステップS885:Yes)、メモリコントローラ200は、ステップS889の処理をスキップしてステップS888の処理に移行する。これにより、検証リクエストの結果が不一致となったページのページアドレスのみを検証結果として再書込みアドレス情報に保持させることができる。ステップS888において、メモリコントローラ200は、オフセットレジスタを更新し(ステップS888)、ステップS886の処理に戻る。これ以外は、図22において説明した処理手順と同様であるため説明を省略する。
図28は、本技術の第4の実施の形態の第2の変形例における再書込み処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図21において説明したステップS890に対応する処理である。また、本処理は、図23において説明した処理手順のうちステップS892、ステップS895およびステップS898の処理を削除したものである。これにより、メモリコントローラ200は、再書込みが必要なページを特定して再書込みを行う。これ以外は、図21において説明した処理手順と同様であるため、説明を省略する。
上述の第4の実施の形態では、図22において説明した検証処理において、書込み処理の対象となる全てのページについて検証を行っていた。しかし、第3の実施の形態において説明した検証アドレス情報保持部295を使用して、検証が必要なページのみ検証を行ってもよい。検証の処理が簡略化されるためである。
図29は、本技術の第4の実施の形態の第3の変形例における機能構成例を示す図である。同図のメモリコントローラ200は、検証アドレス情報保持部295を備える。これ以外の構成は図20において説明した機能構成例と同様であるため説明を省略する。
図30は、本技術の第4の実施の形態の第3の変形例における書込み処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図21において説明した処理手順に対して、ステップS801の処理をステップS810とステップS820との間に追加したものである。これ以外は図21において説明した処理手順と同様であるため説明を省略する。
図31は、本技術の第4の実施の形態の第3の変形例における検証処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図21において説明したステップS880に対応する処理である。ステップS882において、メモリコントローラ200は、再書込アドレス情報保持部296の初期化のみを行う。ステップS881において、メモリコントローラ200は、検証アドレス情報保持部295から検証アドレス情報を取得する(ステップS881)。ステップS885において、メモリコントローラ200は、メモリ300から返されたリクエストの結果を調べる。この結果が一致でなかった場合(ステップS885:No)、メモリコントローラ200は、検証リクエストに係るページのページアドレスを再書込アドレス情報保持部296に保持させる(ステップS889)。その後、ステップS886の処理に移行する。一方、メモリ300から返されたリクエストの結果が一致であった場合(ステップS885:Yes)、メモリコントローラ200は、ステップS889の処理をスキップしてステップS886の処理に移行する。これにより、検証が必要なページを特定して検証を行い、検証リクエストの結果が不一致となったページのページアドレスのみを検証結果として再書込アドレス情報保持部296に保持させることができる。なお、ステップS888の処理は不要であるため、削除している。これ以外は、図22において説明した処理手順と同様であるため説明を省略する。
図32は、本技術の第4の実施の形態の第3の変形例における再書込み処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図21において説明したステップS890に対応する処理である。また、本処理は、図23において説明した処理手順のうちステップS892、ステップS895およびステップS898の処理を削除し、ステップS897の後にステップS899の処理を追加したものである。これにより、メモリコントローラ200は、再書込みが必要なページを特定して再書込みを行うとともに、再書込みを行ったページのページアドレスを検証アドレス情報保持部295に保持させる。これ以外は、図21において説明した処理手順と同様であるため、説明を省略する。
上述の第4の実施の形態では、メモリコントローラ200が、書込み制御部291と、判断部280と、検証部293と、再書込みアドレス情報保持部296とを備えていたが、メモリ300がこれらを備えてもよい。メモリコントローラ200の処理を簡素化できるからである。この場合、メモリコントローラ200は、メモリ300に対して、書込みリクエストのみを発行する。そして、メモリ300が、このリクエストに基づいて書込み、判断および検証の処理を行う。
上述の第1の実施の形態の情報処理システムは、データバックアップ機能を備えていなかった。これに対し、本技術の第5の実施の形態の情報処理システムでは、データバックアップ機能を備え、電源異常が生じた際に、データのバックアップを行う。
図33は、本技術の第5の実施の形態における情報処理システムの構成例を示す図である。同図の情報処理システムは、データバックアップ機能を備えた情報処理システムの例である。同図の情報処理システムは、ホストコンピュータ100と、メモリコントローラ200と、メモリ300と、信号線109および208と、電源電圧監視部107とを備える。電源電圧監視部107は、情報システムに供給される電源の電圧を監視するものである。この電源電圧監視部107は、停電等の電源異常により電源の電圧が低下した場合に、メモリコントローラ200に対して電源電圧低下の情報を出力する。なお、同図の情報処理システムは、電池またはスーパーキャパシタ等のバックアップ用電源を備えている(不図示)。このバックアップ用電源から給電することにより、電源異常となった場合であっても、情報処理システムは、短時間ながら動作可能である。この間に、メモリコントローラ200は、ホストコンピュータに保持されているデータをメモリ300に退避させる。
図34は、本技術の第5の実施の形態におけるメモリコントローラの構成例を示す図である。同図のメモリコントローラ200は、ホストインターフェース230の代わりにDRAMインターフェース240を備え、また、入力ポート290を備える点で図2において説明したメモリコントローラ200と異なる。DRAMインターフェース240は、ホストコンピュータ100のDRAM120とのやり取りを行うインターフェースである。入力ポート290は、電源電圧監視部107の出力が接続される入力ポートである。この入力ポート290には、電源電圧監視部107による電源電圧低下の情報が入力される。これ以外のメモリコントローラ200の構成は、図2において説明したメモリコントローラ200と同様であるため説明を省略する。また、メモリ300の構成も、図3において説明したメモリ300と同様であるため説明を省略する。
図35は、本技術の第5の実施の形態における機能構成例を示す図である。同図は、データの書込みを行う際の機能構成を想定したものである。同図のメモリコントローラ200は、DRAM制御部297およびアドレス変換情報保持部298を備える点で図17において説明したメモリコントローラ200と異なる。
電源電圧監視部107から電源電圧低下の情報が入力されると、DRAM制御部297は、DRAM120にアクセスしてDRAM120に記憶されている全データを出力させる。書込制御部292は、リクエストを生成してこのデータを書込みデータとしてメモリ300に出力する。その後、書込みデータは、メモリ300のメモリセルアレイ350に記憶される。そのため、メモリ300の記憶容量は、DRAM120の記憶容量以上にする必要がある。データの書込み後に、検証書込み部299による検証およびこの結果に基づく再書込みが行われる。この際、再書込みが必要なDRAM120のデータに対してDRAM120内においてデータの移動を行う。
図36は、DRAMにおけるデータの移動を説明する図である。同図は、10個の記憶領域を有するDRAM120の例であり、紙面に向かって左側がデータ移動前の状態を右側がデータ移動後の状態をそれぞれ表している。同図におけるaのDRAM120は、2個のDRAMにより構成され、それぞれのDRAMは5個の記憶領域を有し、上位アドレスおよび下位アドレスに配置されている。これらはそれぞれ第1の領域および第2の領域として表されている。
図37は、本技術の第5の実施の形態における書込み処理の処理手順(メモリコントローラ)の一例を示す図である。電源電圧監視部107から電源電圧低下の情報が入力されると、メモリコントローラ200は、制御信号を切替部150に出力する。これにより、切替部150は、DRAM120をメモリコントローラ200に接続する。その後、メモリコントローラ200は、書込み処理を開始する。まず、メモリコントローラ200は、DRAM120の全ページデータに対して通常書込みを行う(ステップS760)。次に、メモリコントローラ200は、検証アドレス情報の保持を行う(ステップS751)。本技術の第5の実施の形態では、書込み対象となった全てのページのページアドレスが検証アドレス情報として、検証アドレス情報保持部295に保持される。次に、メモリコントローラ200は、既にメモリ300に対する再書込みが行われているか否かを調べ(ステップS752)、再書込みが行われていた場合には(ステップS752:Yes)、データの移動を行う(ステップS790)。
図38は、本技術の第5の実施の形態におけるデータ移動処理の処理手順(メモリコントローラ)の一例を示す図である。本処理は、図37において説明したステップS790に対応する処理である。まず、メモリコントローラ200は、データが移動済みであるか否かを調べ(ステップS791)、移動済みである場合は(ステップS791:Yes)、以降の処理をスキップしてデータ移動処理を終了する。一方、移動済みでない場合は(ステップS791:No)、次回の検証を行うデータ量の算出を行う(ステップS792)。この算出したデータ量が閾値以下でない場合(ステップS793:No)、メモリコントローラ200は、以降の処理をスキップしてデータ移動処理を終了する。
(1)データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証部と、
前記データの書込みと前記検証の結果に基づく前記書込みデータの再書込みとを行う書込み制御部と
を具備するメモリコントローラ。
(2)前記不揮発メモリは、前記データの書込みの直後に読出しを行うと前記書き込まれたデータが破壊される前記(1)に記載のメモリコントローラ。
(3)前記不揮発メモリは、前記データの書込みの直後には書込まれたデータが正常に読み出されない前記(1)に記載のメモリコントローラ。
(4)前記判断部は、前記データの書込み後の所定の安定化時間の経過に基づいて前記判断を行う前記(1)から(3)のいずれかに記載のメモリコントローラ。
(5)前記不揮発メモリは、ページアドレスによりページ単位でアクセスされ、
前記書込み制御部は、複数ページからなるデータの書込みを連続して行い、
前記検証部は、前記データの書込みが行われた順にページ単位で前記検証を行い、
前記判断部は、前記検証の際には前記メモリセルの状態が安定していると判断する
前記(1)から(3)のいずれかに記載のメモリコントローラ。
(6)前記再書込みを行う前記不揮発メモリのページアドレスの情報である再書込みアドレス情報を保持する再書込みアドレス情報保持部をさらに具備し、
前記検証部は、前記複数ページからなるデータの書込み後に前記検証を連続して行って当該検証の結果に基づく前記再書込みアドレス情報を前記再書込みアドレス情報保持部に保持させ、
前記書込み制御部は、前記保持された前記再書込みアドレス情報に基づいて前記再書込みを行う
前記(5)に記載のメモリコントローラ。
(7)前記検証を行う前記不揮発メモリのページアドレスの情報である検証アドレス情報を保持する検証アドレス情報保持部をさらに具備し、
前記書込み制御部は、前記書込みおよび前記再書込みを行った際に前記書込みおよび前記再書込みを行ったページアドレスの情報を前記検証アドレス情報として前記検証アドレス情報保持部に保持させ、
前記検証部は、前記保持された前記検証アドレス情報に基づいて前記検証を行う
前記(5)に記載のメモリコントローラ。
(8)前記不揮発メモリは、ページアドレスによりページ単位でアクセスされ、
前記書込み制御部は、複数ページからなるデータの書込みを連続して行い、
前記検証部は、前記データの書込みが行われた順にページ単位で前記検証を行い、
前記判断部は、前記書込みデータのページ数が前記不揮発メモリにおけるデータの書込み後の所定の安定化時間に相当する書込み時間となるページ数である状態安定化ページ数以上の場合には前記検証の際に前記メモリセルの状態が安定していると判断し、前記書込みデータのページ数が前記状態安定化ページ数未満の場合には前記所定の安定化時間の経過を待って前記メモリセルの状態が安定していると判断する
前記(1)から(3)のいずれかに記載のメモリコントローラ。
(9)データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリにおいてデータの書込みを行う書込み制御部と、
前記データの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較する検証と前記検証の結果に基づく前記書込みデータの再書込みとを行う検証書込み部と
を具備するメモリコントローラ。
(10)データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリと、
前記不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証部と、
前記データの書込みと前記検証の結果に基づく前記書込みデータの再書込みとを行う書込み制御部と
を具備する記憶装置。
(11)データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリと、
前記不揮発メモリを制御するメモリコントローラと、
前記メモリコントローラを介して前記不揮発メモリにアクセスするホストコンピュータと
を具備し、
前記メモリコントローラは、
前記不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証部と、
前記データの書込みと前記比較の結果に基づく前記書込みデータの再書込みとを行う書込み制御部とを備える
情報処理システム。
(12)データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断手順と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証手順と、
前記データの書込みと前記比較の結果に基づく前記書込みデータの再書込みとを行う書込み制御手順と
を具備する不揮発メモリの制御方法。
101、201、301 バス装置
107 電源電圧監視部
109、208 信号線
110 プロセッサ
120 DRAM
130、330 メモリコントローラインターフェース
150 切替部
200 メモリコントローラ
210 プロセッサ
220 RAM
230 ホストインターフェース
240 DRAMインターフェース
250 ECC処理部
260 ROM
270 メモリインターフェース
280 判断部
281 タイマ部
282 書込みページ数判断部
283 メモリセル安定状態判断部
290 入力ポート
291、292 書込制御部
293 検証部
294 書込み条件設定部
295 検証アドレス情報保持部
296 再書込アドレス情報保持部
297 DRAM制御部
298 アドレス変換情報保持部
299 検証書込み部
300 メモリ
310 制御部
320 作業メモリ
340 アドレスデコーダ
350 メモリセルアレイ
360 バッファ
Claims (12)
- データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証部と、
前記データの書込みと前記検証の結果に基づく前記書込みデータの再書込みとを行う書込み制御部と
を具備するメモリコントローラ。 - 前記不揮発メモリは、前記データの書込みの直後に読出しを行うと前記書き込まれたデータが破壊される請求項1記載のメモリコントローラ。
- 前記不揮発メモリは、前記データの書込みの直後には書込まれたデータが正常に読み出されない請求項1記載のメモリコントローラ。
- 前記判断部は、前記データの書込み後の所定の安定化時間の経過に基づいて前記判断を行う請求項1記載のメモリコントローラ。
- 前記不揮発メモリは、ページアドレスによりページ単位でアクセスされ、
前記書込み制御部は、複数ページからなるデータの書込みを連続して行い、
前記検証部は、前記データの書込みが行われた順にページ単位で前記検証を行い、
前記判断部は、前記検証の際には前記メモリセルの状態が安定していると判断する
請求項1記載のメモリコントローラ。 - 前記再書込みを行う前記不揮発メモリのページアドレスの情報である再書込みアドレス情報を保持する再書込みアドレス情報保持部をさらに具備し、
前記検証部は、前記複数ページからなるデータの書込み後に前記検証を連続して行って当該検証の結果に基づく前記再書込みアドレス情報を前記再書込みアドレス情報保持部に保持させ、
前記書込み制御部は、前記保持された前記再書込みアドレス情報に基づいて前記再書込みを行う
請求項5記載のメモリコントローラ。 - 前記検証を行う前記不揮発メモリのページアドレスの情報である検証アドレス情報を保持する検証アドレス情報保持部をさらに具備し、
前記書込み制御部は、前記書込みおよび前記再書込みを行った際に前記書込みおよび前記再書込みを行ったページアドレスの情報を前記検証アドレス情報として前記検証アドレス情報保持部に保持させ、
前記検証部は、前記保持された前記検証アドレス情報に基づいて前記検証を行う
請求項5記載のメモリコントローラ。 - 前記不揮発メモリは、ページアドレスによりページ単位でアクセスされ、
前記書込み制御部は、複数ページからなるデータの書込みを連続して行い、
前記検証部は、前記データの書込みが行われた順にページ単位で前記検証を行い、
前記判断部は、前記書込みデータのページ数が前記不揮発メモリにおけるデータの書込み後の所定の安定化時間に相当する書込み時間となるページ数である状態安定化ページ数以上の場合には前記検証の際に前記メモリセルの状態が安定していると判断し、前記書込みデータのページ数が前記状態安定化ページ数未満の場合には前記所定の安定化時間の経過を待って前記メモリセルの状態が安定していると判断する
請求項1記載のメモリコントローラ。 - データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリにおいてデータの書込みを行う書込み制御部と、
前記データの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較する検証と前記検証の結果に基づく前記書込みデータの再書込みとを行う検証書込み部と
を具備するメモリコントローラ。 - データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリと、
前記不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証部と、
前記データの書込みと前記検証の結果に基づく前記書込みデータの再書込みとを行う書込み制御部と
を具備する記憶装置。 - データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリと、
前記不揮発メモリを制御するメモリコントローラと、
前記メモリコントローラを介して前記不揮発メモリにアクセスするホストコンピュータと
を具備し、
前記メモリコントローラは、
前記不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断部と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証部と、
前記データの書込みと前記比較の結果に基づく前記書込みデータの再書込みとを行う書込み制御部とを備える
情報処理システム。 - データの書込み後に状態が不安定な期間が存在するメモリセルからなる不揮発メモリにおいてデータの書込み後の前記メモリセルの状態が安定しているか否かの判断を行う判断手順と、
前記判断の結果に基づいて前記データが書き込まれた前記メモリセルから読み出した読出しデータと前記書込みに係る書込みデータとを比較して検証する検証手順と、
前記データの書込みと前記比較の結果に基づく前記書込みデータの再書込みとを行う書込み制御手順と
を具備する不揮発メモリの制御方法。
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JP2014041573A (ja) * | 2012-08-24 | 2014-03-06 | Sony Corp | 記憶制御装置、記憶装置、情報処理システムおよび記憶制御方法 |
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JP2011060388A (ja) * | 2009-09-11 | 2011-03-24 | Toshiba Corp | 不揮発性メモリ装置 |
JP2011181134A (ja) * | 2010-02-26 | 2011-09-15 | Elpida Memory Inc | 不揮発性半導体装置の制御方法 |
JP2014041573A (ja) * | 2012-08-24 | 2014-03-06 | Sony Corp | 記憶制御装置、記憶装置、情報処理システムおよび記憶制御方法 |
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JP6481691B2 (ja) | 2019-03-13 |
JPWO2016042902A1 (ja) | 2017-06-29 |
US20170277442A1 (en) | 2017-09-28 |
US10310742B2 (en) | 2019-06-04 |
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