WO2016035479A1

WO2016035479A1 - Field effect transistor

Info

Publication number: WO2016035479A1
Application number: PCT/JP2015/071377
Authority: WO
Inventors: 哲三永久; 勝久保
Original assignee: シャープ株式会社
Priority date: 2014-09-04
Filing date: 2015-07-28
Publication date: 2016-03-10
Also published as: JP2017199700A

Abstract

This field effect transistor comprises, on a nitride semiconductor layer, a source electrode (4), a drain electrode (5), a gate electrode (6), a first insulating film (7) and a second insulating film (9). The first insulating film (7) is formed to an edge (8) of the contact surface of the drain electrode (5) and the nitride semiconductor layer. The drain electrode (5) has a field plate part (10) which protrudes toward the gate electrode (6) in the form of an eave, and which is in contact with the upper surface of the second insulating film (9). This field effect transistor is provided with: a single layer film region (11) which is provided below the field plate part (10) in the vicinity of the edge (8) of the contact surface of the drain electrode (5) and the nitride semiconductor layer, and wherein only the first insulating film (7) is formed; and a multilayer film region (12) which is provided below the field plate part (10) on a side of the single layer film region (11), said side being opposite to the side of the edge (8) of the contact surface, and wherein the first insulating film (7) and the second insulating film (9) are formed and laminated.

Description

Field effect transistor

The present invention relates to a nitride semiconductor field effect transistor.

Conventionally, as a nitride semiconductor HFET (Heterojunction Field Effect Transistor), there is a semiconductor device disclosed in Japanese Patent Laid-Open No. 2006-278812 (Patent Document 1). In this semiconductor device, silicon is present on the surface of the GaN-based semiconductor layer formed on the substrate from silicon nitride having a higher stoichiometric composition ratio (for example, a silicon / nitrogen composition ratio of 1.85 to 1.9). An insulating film is formed, and a gate electrode, a source electrode, and a drain electrode are formed on the GaN-based semiconductor layer.

Thus, the collapse phenomenon is suppressed by reducing the oxide of the group III element in the surface layer of the GaN-based semiconductor layer, which is considered to cause the collapse phenomenon that the drain current decreases when a high drain voltage is applied. ing.

As a nitride semiconductor HFET, there is a field effect transistor disclosed in Japanese Unexamined Patent Application Publication No. 2004-200248 (Patent Document 2). In this field effect transistor, a GaN channel layer and an AlGaN electron supply layer are formed on a substrate, and a source electrode and a drain electrode in ohmic contact are formed on the electron supply layer. A gate electrode having a field plate portion protruding in the shape of an eave on the drain side and having a Schottky contact is provided between the source electrode and the drain electrode. A laminated film composed of a SiN film and a SiO ₂ film is formed under the field plate portion, and the surface of the AlGaN electron supply layer is covered with the SiN film.

Thus, the trade-off relationship between the amount of collapse and the gate breakdown voltage is improved by the synergistic effect of the gate electrode structure including the field plate and the layer structure below the field plate.

JP 2006-278812 A JP 2004-200248 A

However, the conventional nitride semiconductor HFET has a problem that either of Patent Document 1 and Patent Document 2 is insufficiently improved with respect to collapse in the case of high voltage during switching operation. .

Therefore, an object of the present invention is to provide a field effect transistor that can improve collapse even in the case of a high voltage during switching operation.

In order to solve the above problems, the field effect transistor of the present invention is
A nitride semiconductor layer including a heterojunction;
A source electrode and a drain electrode disposed on the nitride semiconductor layer at a distance from each other;
A gate electrode disposed between the source electrode and the drain electrode on the nitride semiconductor layer;
A first insulating film formed between the gate electrode and the drain electrode immediately above the nitride semiconductor layer and having at least silicon and nitrogen as constituent elements;
A second insulating film formed on the first insulating film,
The first insulating film is formed up to an edge of a contact surface between the drain electrode and the nitride semiconductor layer,
The drain electrode has a field plate portion protruding in an eave shape toward the gate electrode side and in contact with the upper surface of the second insulating film,
A single-layer film region provided below the field plate in the vicinity of the edge of the contact surface between the drain electrode and the nitride semiconductor layer, and in which only the first insulating film is formed;
A multi-layer film region provided under the field plate portion on the opposite side of the contact surface of the single-layer film region and formed by laminating the first insulating film and the second insulating film; It is characterized by having.

In the field effect transistor of one embodiment,
A third insulating film having a dielectric constant smaller than that of the first insulating film is further laminated on the second insulating film,
The field plate portion is in contact with the upper surface of the third insulating film.

In the field effect transistor of one embodiment,
The second insulating film or the third insulating film covers an insulating film having a dielectric constant larger than that of the insulating film under the field plate portion in the vicinity of the drain electrode.

In the field effect transistor of one embodiment,
The dielectric constant of the second insulating film is smaller than the dielectric constant of the first insulating film.

In the field effect transistor of one embodiment,
The first insulating film, the second insulating film, and the third insulating film below the field plate portion have a smaller dielectric constant as the upper insulating film.

As is clear from the above, the field effect transistor of the present invention is
The first insulating film and the second insulating film are stacked in this order between the gate electrode and the drain electrode immediately above the nitride semiconductor layer and below the field plate portion. ing. Thus, by increasing the total thickness of the insulating film under the field plate portion, the electric field on the surface of the nitride semiconductor layer can be relaxed.

At this time, since the first insulating film includes silicon and nitrogen as constituent elements, it is possible to perform interface control that makes it difficult for negative charges to be accumulated on the surface of the nitride semiconductor layer, and the drain electrode and the nitride semiconductor can be controlled. Formed to the edge of the contact surface with the layer.

Furthermore, by providing a single-layer film region and a multi-layer film region as an insulating film covering the nitride semiconductor layer, the field plate portion of the drain electrode can be formed stepwise. Therefore, the electric field strength in the vicinity of the drain electrode can be further relaxed, and the occurrence of disconnection of the drain electrode can be suppressed.

Therefore, according to the present invention, the collapse in the case of a high voltage during the switching operation can be remarkably improved.

It is sectional drawing in the nitride semiconductor HFET as a field effect transistor of this invention. It is an enlarged view of the drain electrode vicinity in FIG. It is a figure which shows the relationship between the total film thickness of a 1st, 2nd insulating film required for collapse improvement, and the film thickness of a barrier layer. It is a diagram showing the relationship between the thickness of the total thickness and the barrier layer of the second insulating film using SiO ₂ required for the collapse improvement. FIG. 5 is a diagram in which the sum of the first and second insulating films is taken on the vertical axis in the case of FIG. 4. FIG. 3 is an enlarged cross-sectional view of the vicinity of a drain electrode in a nitride semiconductor HFET different from FIG. FIG. 7 is an enlarged cross-sectional view of the vicinity of a drain electrode in a nitride semiconductor HFET different from FIGS. 2 and 6.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

First Embodiment FIG. 1 is a cross-sectional view of a nitride semiconductor HFET which is an example of a field effect transistor according to the present embodiment. FIG. 2 is an enlarged view of the vicinity of the drain electrode in FIG.

As shown in FIG. 1, in the HFET according to the present embodiment, a channel layer 2 made of GaN and a barrier layer made of Al _x Ga _1-x N (0 <x <1) are formed on a substrate 1 made of Si. 3 are stacked in this order. In the present embodiment, the Al crystal ratio x in the Al _x Ga _1-x N barrier layer 3 is set to x = 0.17 as an example. Further, in the present embodiment, the GaN channel layer 2 and the Al _x Ga _1-x N barrier layer 3 constitute the nitride semiconductor layer, and the thickness of the Al _x Ga _1-x N barrier layer 3 is 30 nm. Yes.

A source electrode 4 and a drain electrode 5 are formed on the Al _x Ga _1-x N barrier layer 3 with a predetermined interval therebetween. Here, in the present embodiment, the source electrode 4 and the drain electrode 5 are formed using Ti / Al in which Ti and Al are stacked in this order. In that case, recesses are formed in the barrier layer 3 and the channel layer 2 at the positions where the source electrode 4 and the drain electrode 5 are formed, and an electrode material is deposited and annealed, so that the

electrodes

4, 5 and the channel layer 2 are formed. An ohmic contact is formed with 2DEG (two dimensional electron gas) formed on the surface layer.

A gate electrode 6 is formed between the source electrode 4 and the drain electrode 5 on the Al _x Ga _1-x N barrier layer 3. In the present embodiment, the gate electrode 6 is formed using WN / W in which WN and W are stacked in this order.

And between the source electrode 4 to the gate electrode 6 on the barrier layer 3, the the period from the gate electrode 6 on the barrier layer 3 to the drain electrode 5, the first insulating film 7 made of SiN _y is formed Yes. In particular, the first insulating film 7 is formed to extend to the edge 8 of the contact surface between the drain electrode 5 and the nitride semiconductor layer (hereinafter simply referred to as the contact surface edge 8). In the vicinity of, the nitride semiconductor layer is completely covered with the first insulating film 7. In the present embodiment, as an example, the thickness of the first insulating film 7 is 30 nm.

The function of the first insulating film 7 is to control the interface of the surface of the nitride semiconductor layer. In order to suppress the collapse, it is necessary to form the film while keeping the growth rate at 800 Å / min or less.

Here, the “interface control” is control that makes it difficult for negative charges to be accumulated at the interface between the nitride semiconductor layer and the first insulating film 7 in order to suppress the collapse. It is to appropriately treat dangling bonds generated on the surface, reduce generation of interface states, reduce the depth of interface states, and the like. If negative charges are accumulated at the interface between the nitride semiconductor layer and the first insulating film 7, the polarization of the barrier layer 3 is weakened. As a result, the carrier concentration in 2DEG is reduced and collapsed. A phenomenon will occur.

On the first insulating film 7, the second insulating film 9 made of SiN _z is formed. In the present embodiment, as an example, the thickness of the second insulating film 9 is 230 nm.

The drain electrode 5 has a field plate portion 10 that protrudes toward the gate electrode 6 and is in contact with the upper surface of the second insulating film 9. With this field plate structure, the electric field strength at the lower portion of the field plate portion 10, particularly in the vicinity of the contact surface edge 8 can be reduced. Here, the length of the field plate portion 10 is a distance from the contact surface edge 8 to the tip of the field plate portion 10 and is 2 μm.

Further, as shown in FIG. 2, in the present embodiment, the insulation covering the nitride semiconductor layer is provided in the vicinity of the edge (contact surface edge) 8 of the contact surface between the drain electrode 5 and the nitride semiconductor layer. As a film, a single layer film region 11 where only the first insulating film 7 is formed is provided. The first insulating film 7 and the second insulating film 9 are laminated and formed below the field plate portion 10 on the opposite side of the contact surface edge 8 from the single layer film region 11. A layer film region 12 is provided.

Here, in the single-layer film region 11, the thickness of the first insulating film 7 is set to 25 nm. Further, in the multilayer film region 12, the film thickness of the first insulating film 7 is 30 nm, and the film thickness of the second insulating film 9 is 230 nm. The film thickness of the first insulating film 7 is different between the single-layer film region 11 and the multilayer film region 12 because of process processing, and even if the film thicknesses of both regions are different as in this embodiment. It may be the same or the same.

Here, the gist of the present invention will be described.

The inventors have revealed for the first time that a phenomenon completely different from the collapse phenomenon known so far has occurred under the condition of high voltage during switching operation, which is a problem of the present invention. Here, the high voltage is a drain voltage of 400 V or higher, and the switching is a frequency of 10 kHz or higher. In this embodiment, the experiment is performed with a drain voltage of 600 V and a frequency of 100 kHz.

The above-mentioned different phenomenon is a mechanism in which a large current flows in the vicinity of the drain electrode 5 at a high electric field momentarily at the time of the switching, and an electron trap or a semiconductor is deteriorated by the energy, thereby causing a collapse phenomenon. The inventors thought that.

Therefore, in the present invention, by adopting a field plate structure for the drain electrode 5, an electric field in the vicinity of the contact surface edge 8 is particularly relaxed. Furthermore, by controlling the interface of the nitride semiconductor layer, the first insulating film 7 for suppressing the collapse is formed on the nitride semiconductor layer without being interrupted to the contact surface edge 8. Yes.

By adopting a field plate structure for the drain electrode 5, the electric field in the vicinity of the drain electrode 5 is relaxed, but that alone is not sufficient for the collapse in the case of a high voltage during switching operation. It has been revealed for the first time by the present inventors. The reason is that when switching is performed at a high voltage, an electric field is induced in the nitride semiconductor layer corresponding to the lower side of the tip of the field plate portion 10 in the drain electrode 5 and collapse occurs in that region.

Also, the field plate portion 10 of the drain electrode 5 can be formed stepwise by providing the single layer film region 11 and the multilayer film region 12 as an insulating film covering the nitride semiconductor layer. Therefore, the electric field strength in the vicinity of the drain electrode 5 can be relaxed, and the occurrence of disconnection of the drain electrode 5 can be suppressed. In order to reduce the electric field strength in the vicinity of the drain electrode 5, the thickness of the first insulating film 7 in the single layer film region 11 is desirably 60 nm or less.

Here, in consideration of the electric field applied to the insulating film in the single-layer film region 11, the problem that the dielectric breakdown occurs when an insulating film having a low dielectric constant is used as the insulating film in the single-layer film region 11. Etc. found. Therefore, in the present invention, the SiNy film having a high dielectric constant and capable of interface control in the nitride semiconductor layer is used as the first insulating film 7 in the single-layer film region 11 to solve the above problem. succeeded in.

In addition, the inventors of the present invention have formed the insulating films (the first insulating film 7 and the second insulating film 9) formed below the field plate portion 10 protruding from the drain electrode 5, particularly in the multilayer film region 12. It has been determined that it is necessary to increase the total film thickness to some extent.

However, in that case, the first insulating film 7 inevitably has a low deposition rate because it is necessary to control the interface of the surface of the nitride semiconductor layer, and only the first insulating film 7 is used during the switching operation. It is difficult to obtain a film thickness that can suppress collapse in the case of high voltage. Therefore, in this embodiment, the insulating film located above the nitride semiconductor layer and below the field plate portion 10 of the drain electrode 5 is formed at least twice.

FIG. 3 shows the total film thickness of the first insulating film (SiN _y ) 7 and the second insulating film (SiN _z ) 9 necessary for improving the collapse in the case of a high voltage during the switching operation, and Al _x Ga ₁₋ The relationship with the film thickness of _xN barrier layer 3 is shown. Here, each film thickness indicates the film thickness in the multilayer film region. The reason for this is that, as described above, the collapse is caused by the induction of an electric field in the nitride semiconductor layer corresponding to the lower side of the tip of the field plate portion 10 in the drain electrode 5. This is because the thickness of the region is important.

As can be seen from FIG. 3, the required total film thickness of the insulating layer with respect to the film thickness of 20 nm of the barrier layer 3 is 264 nm, and the required total film thickness of the insulating layer with respect to the film thickness of 30 nm of the barrier layer 3 is 255 nm. The required total film thickness of the insulating layer with respect to the film thickness of the barrier layer 3 is 40 nm. As described above, the total film thickness of the insulating layer necessary for improving the collapse in the case of a high voltage during the switching operation is slightly dependent on the film thickness of the barrier layer 3. Therefore, as described above, the total film thickness of the insulating film formed under the field plate portion 10 needs to be “somewhat” thicker than the film thickness obtained from FIG. 3, specifically, the total film thickness of 270 nm or more. Film thickness is required.

In the present embodiment, SiN _y is used as the first insulating film 7 and SiN _z is used as the second insulating film 9, but the second insulating film 9 has the same film quality as the first insulating film 7. It doesn't matter if it is present or not. That is, the second insulating film 9, to may be a SiN _z to be z = y, to may be a SiN _z as the z ≠ y, since it may be an insulating film other than SiN _z is there.

In particular, by using a film having a dielectric constant lower than that of the first insulating film 7 as the second insulating film 9, an electric field applied to the surface of the nitride semiconductor layer under the condition of a high voltage during switching operation. The strength can be reduced as compared with the case where a film having the same dielectric constant as that of the first insulating film 7 is used. Accordingly, the lower the dielectric constant of the film used for the second insulating film 9, the smaller the required film thickness for the second insulating film 9, thereby suppressing the occurrence of disconnection of the drain electrode 5. it can.

4, the thickness of the second insulating film 9 need to improve the collapse in the case of the high voltage during the switching operation in the case of using the SiO ₂ lower dielectric constant than SiN _z as the second insulating film 9 The relationship with the film thickness of the Al _x Ga _1-x N barrier layer 3 is shown. For comparison with FIG. 3, FIG. 5 shows a graph in which the vertical axis represents the sum of the first insulating film (SiN _z ) 7 and the second insulating film (SiO ₂ ) 9 in the case of FIG.

As can be seen from FIG. 4, the required thickness of the second insulating film 9 varies depending on the thickness of the first insulating film 7. However, as can be seen from FIG. 5, the film thickness of the first insulating film 7 does not depend on the required total film thickness of the first insulating film 7 and the second insulating film 9, and the total film thickness is 200 nm or more. Is sufficient.

Further, as apparent from comparison between FIG. 5 and FIG. 3, the second insulating film 9 has a lower dielectric constant (SiO ₂ ) than the first insulating film 7 (SiN _y : relative dielectric constant = about 8). : Relative dielectric constant = about 3.9), the required total film thickness of the first insulating film 7 and the second insulating film 9 can be significantly reduced. As a result, the occurrence of disconnection of the drain electrode 5 can be suppressed.

4 and 5, SiO ₂ is used as an example of a film having a dielectric constant lower than that of the first insulating film 7 with respect to the second insulating film 9, but in order to significantly reduce the required total film thickness. As long as the insulating film has a lower dielectric constant than the first insulating film 7, other films can be used. Examples of other films include SiN _z (z> y), which has a higher N composition than the first insulating film 7. In particular, stoichiometric SiN _z (z = 4/3), SiN _z (z> 4/3) having a higher N composition than that, SiON, and SiOC.

The relative dielectric constant of SiN _y used for the first insulating film 7 is preferably in the range of 7.5 to 9.5. Since it is necessary to control the interface of the surface of the nitride semiconductor layer, the first insulating film 7 is desirably a film having a higher Si composition than the stoichiometry, that is, y <4/3. In that case, if there is too much Si composition, a leak will occur. Therefore, it is desirable that the relative dielectric constant is within the above range. In addition, the first insulating film 7 only needs to contain silicon and nitrogen within a range in which the interface of the nitride semiconductor layer surface can be controlled as a constituent element, and may be, for example, a SiON film.

In addition, the dimensions and film thicknesses of the respective parts in the present embodiment are merely examples, and if they have the structure of the present invention, they are within the scope of the present invention.

For example, the thickness of the Al _x Ga _1-x N barrier layer 3 is generally 20 nm to 40 nm, but is not particularly limited. In order to obtain a desirable sheet carrier concentration, a desirable threshold voltage, etc., it may be set freely.

Further, Al _x Ga _1-x N having a mixed crystal ratio x = 0.17% is used for the barrier layer 3. However, if the 2DEG induces crystallinity to operate as a transistor, the mixed crystal is used. The ratio x is not particularly limited. The reason is that since the dielectric constant does not greatly change depending on the mixed crystal ratio x, the effect of the present invention can be obtained regardless of the mixed crystal ratio x.

The film thickness of the first insulating film 7 is preferably several nm to 200 nm. This is because if the film thickness of the first insulating film 7 is too thin, it is difficult to control the interface of the nitride semiconductor layer, but it is difficult to form a film thickness of 200 nm or more at a low deposition rate. However, it is not the same thing that can be formed by improving process technology.

The film thickness of the second insulating film 9 is preferably 100 nm to several μm although it depends on the film thickness of the first insulating film 7. In order to suppress the electric field on the surface of the nitride semiconductor layer, it is desirable that the total film thickness of the first insulating film 7 and the second insulating film 9 is 200 nm or more, so that the total film thickness is half (100 nm) or more. This is because if the film thickness is too thick (several μm or more), stress is applied and the wafer warps.

Further, with respect to the length of the field plate portion 10 of the drain electrode 5, the length from the contact surface edge 8 to the tip of the field plate portion 10 is preferably 0.3 μm or more. This is because the electric field at the edge 8 of the contact surface with the nitride semiconductor layer is not relaxed without a certain length. Although the upper limit of the length of the field plate portion 10 is not particularly limited, it naturally depends on the distance from the gate electrode 6 and the source electrode 4, and the gate electrode 6 or the source electrode 4 also adopts a field plate structure. It depends on whether you are doing it. In principle, it is desirable that the length be such that dielectric breakdown does not occur between the drain electrode 5 and the gate electrode 6 or the source electrode 4.

Second Embodiment FIG. 6 is a cross-sectional view in the HFET of the nitride semiconductor layer in the second embodiment, and is an enlarged view near the drain electrode.

In this embodiment, the same parts as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted, and the features of the present embodiment are described. Do.

As shown in FIG. 6, in the present embodiment, as in the case of the first embodiment, the vicinity of the edge (contact surface edge) 8 of the contact surface between the drain electrode 5 and the nitride semiconductor layer. A single layer film region 11 is provided, and a multi layer film region 12 is provided below the field plate portion 10 on the opposite side of the contact surface edge 8 from the single layer film region 11. However, in the present embodiment, the multilayer film region 12 includes a two-layer film region 12 a in which the first insulating film 7 and the second insulating film 9 are stacked, and a third insulating film on the second insulating film 9. It is composed of a three-layer film region 12b on which a film 13 is laminated.

In the present embodiment, SiN _y (y <4/3, relative dielectric constant = about 8) having a higher Si composition than the stoichiometry is used as the first insulating film 7. As the second insulating film 9, SiN _z (z≈4 / 3, relative dielectric constant = about 7.5) having an Si composition substantially equal to the stoichiometry is used. Further, SiO ₂ (relative permittivity = about 3.9) is used as the third insulating film 13.

Here, in the single-layer film region 11, the thickness of the first insulating film 7 is set to 25 nm. Further, in the multilayer film region 12, the thickness of the first insulating film 7 is 30 nm, the thickness of the second insulating film 9 is 100 nm, and the thickness of the third insulating film 13 is 200 nm. As in the case of the second embodiment, the film thickness of the first insulating film 7 differs between the single-layer film region 11 and the multilayer film region 12 because of process processing. As in the form, the thicknesses of both regions may be different or the same.

As in this embodiment, the field plate portion 10 of the drain electrode 5 is formed in three stages by forming a three-layer structure as an insulating film that covers the nitride semiconductor layer and is located under the field plate portion 10 of the drain electrode 5. Can be formed. Therefore, the occurrence of disconnection of the drain electrode 5 can be further suppressed. Furthermore, the total film thickness of the insulating film can be increased, the electric field strength on the surface of the nitride semiconductor layer can be further relaxed, and the collapse in the case of a high voltage during the switching operation can be improved.

Here, the relative dielectric constant of the first insulating film 7 is about 8, the relative dielectric constant of the second insulating film 9 is about 7.5, and the relative dielectric constant of the third insulating film 13 is about 3.9. It is. As described above, it is desirable that the upper film constituting the insulating film has a lower dielectric constant. The reason is that by lowering the dielectric constant of the upper film, the electric field concentration can be kept away from the surface of the nitride semiconductor layer, so that the influence of collapse on the 2DEG can be reduced.

As in the case of the first embodiment, SiN _z (z≈4 / 3, relative dielectric constant = about 7.5) is used as the second insulating film 9 in which the Si composition is substantially equal to the stoichiometry. Although SiO ₂ (relative dielectric constant = approximately 3.9) was used as the third insulating film 13, the second insulating film 9 and the third insulating film 13 have a dielectric constant higher than that of the first insulating film 7. In other examples, SiN _z (z> y) having a higher N composition than the first insulating film 7, especially stoichiometric SiN _z (z = 4/3) and N composition often SiN _{z (z>} 4/3) and the, SiON, SiOC, and the like. As described above, it is desirable to lower the dielectric constant of the upper film.

In the present embodiment, the insulating film located under the field plate portion 10 of the drain electrode 5 has a three-layer structure, but it may be further multilayered. In that case, the occurrence of disconnection of the drain electrode 5 can be further suppressed, and the total film thickness of the insulating film can be increased to further relax the electric field on the surface of the nitride semiconductor layer, thereby increasing the level during switching operation. It is possible to improve the collapse in the case of voltage.

Furthermore, even when the insulating film located under the field plate portion 10 has a multilayer structure of four or more layers, it is desirable that the upper film has a lower dielectric constant for the reasons described above.

In the present embodiment, as shown in FIG. 7, the thickness of the second insulating film 9 is constant in the multilayer film region 12, but the thickness may vary depending on the location. . In particular, there may be a step in the process process between the region where the third insulating film 13 is formed on the upper surface and the region where the drain electrode 5 is formed on the upper surface. However, in the present invention, the step may be generated. Absent. This is the same when the number of insulating films in the multilayer film region 12 is further increased.

For the same reason as in the first embodiment, the relative dielectric constant of SiN _y used for the first insulating film 7 is preferably in the range of 7.5 to 9.5. Further, the first insulating film 7 only needs to contain silicon and nitrogen as constituent elements within a range in which the interface control of the nitride semiconductor layer surface can be performed, and may be, for example, a SiON film.

Further, the dimensions and film thicknesses of the respective parts in the present embodiment are merely examples, and it is within the scope of the present invention if it has the structure of the present invention.

For example, the thickness of the Al _x Ga _1-x N barrier layer 3 is generally 20 nm to 40 nm, but is not particularly limited. In order to obtain a desired sheet carrier concentration, a desired threshold voltage, etc., it may be set freely.

The film thickness of each layer in the case of the second insulating film 9, the third insulating film 13, and four or more layers is not limited. However, the total thickness of all the insulating films formed above the first insulating film 7 is desirably 100 nm to several μm. In order to suppress the electric field on the surface of the nitride semiconductor layer, it is desirable that the total film thickness of the insulating film be 200 nm or more, so that it is desirably half or more (100 nm) of the total film thickness, and the film thickness is too thick ( This is because there is a problem that the wafer is warped due to the stress of several μm or more.

Further, with respect to the length of the field plate portion 10 of the drain electrode 5, the length from the contact surface edge 8 to the tip of the field plate portion 10 is preferably 0.3 μm or more. This is because the electric field at the contact surface edge 8 is not relaxed without a certain length. Although the upper limit of the length of the field plate portion 10 is not particularly limited, it naturally depends on the distance from the gate electrode 6 and the source electrode 4, and the gate electrode 6 or the source electrode 4 also adopts a field plate structure. It depends on whether you are doing it. In principle, it is desirable that the length be such that dielectric breakdown does not occur between the drain electrode 5 and the gate electrode 6 or the source electrode 4.

Third Embodiment FIG. 7 is a cross-sectional view in the HFET of the nitride semiconductor layer in the third embodiment, and is an enlarged view near the drain electrode.

In this embodiment, the same parts as those in the first and second embodiments are given the same numbers as in the first and second embodiments, and the description thereof is omitted. The features of the form will be described.

As shown in FIG. 7, in the present embodiment, as in the case of the second embodiment, a single layer film region 11 is provided in the vicinity of the contact surface edge 8, and the single layer film region is provided. A multilayer film region 12 is provided below the field plate portion 10 on the opposite side of the contact surface edge 8 from 11. However, the multilayer film region 12 in the present embodiment includes a two-layer film region 12 a in which the first insulating film 7 and the third insulating film 13 are stacked, and a second insulating film on the first insulating film 7. 9 and the third insulating film 13 are constituted by a three-layer film region 12b laminated in this order. That is, the second insulating film 9 is not formed in the two-layer film region 12a, and the third insulating film 13 in the three-layer film region 12b extends into the two-layer film region 12a, and the second insulating film 9 The structure covers the end face and reaches the upper surface of the first insulating film 7.

In the present embodiment, SiN _y (y <4/3, relative dielectric constant = about 8) having a higher Si composition than the stoichiometry is used as the first insulating film 7. As the second insulating film 9, SiN _z (z≈4 / 3, relative dielectric constant = about 7.5) having an Si composition substantially equal to the stoichiometry is used. Further, SiO ₂ (relative permittivity = about 3.9) is used as the third insulating film 13. Therefore, the third insulating film 13 having a dielectric constant lower than that of the second insulating film 9 covers the surface and end face of the second insulating film 9 in the vicinity of the drain electrode 5.

Here, in the single-layer film region 11, the thickness of the first insulating film 7 is set to 25 nm. Further, in the multilayer film region 12, the thickness of the first insulating film 7 is 30 nm, the thickness of the second insulating film 9 is 100 nm, and the thickness of the third insulating film 13 is 200 nm. As in the second and third embodiments, the thickness of the first insulating film 7 differs between the single-layer film region 11 and the multi-layer film region 12 because of process processing. As in the embodiment, the thicknesses of both regions may be different or the same.

As in this embodiment, in the multilayer film region 12 that covers the nitride semiconductor layer and is located under the field plate portion 10, an insulating film having a lower dielectric constant is covered with an insulating film having a lower dielectric constant than the insulating film. This makes it possible to relax the electric field on the surface of the nitride semiconductor layer over a wide range. Therefore, it is possible to further improve the collapse in the case of a high voltage during the switching operation.

The first insulating film 7 needs to be installed on the nitride semiconductor layer in order to control the interface of the nitride semiconductor layer. Therefore, the insulating film except the first insulating film 7 in the single layer film region 11 is covered with the insulating film having a low dielectric constant.

Further, when the insulating film has a multilayer structure of four or more layers, it is desirable to cover with an insulating film having the lowest dielectric constant among the insulating films. In combination with the above, in the case of a multilayer structure, an insulating film having the lowest dielectric constant is disposed in the uppermost layer in the multilayer film region 12, and an insulating film other than the first insulating film 7 is formed by the insulating film. It is more desirable to cover completely. By doing so, the other insulating film is covered with the insulating film having the lowest dielectric constant, so that the electric field on the surface of the nitride semiconductor layer can be relaxed over a wide range.

In addition, when the insulating film has a multilayer structure of four or more layers, it is desirable that the insulating film having the lowest dielectric constant is thicker than the other insulating films. By doing so, it is possible to alleviate the electric field applied to the surface of the nitride semiconductor layer by the action of the insulating film having the lowest dielectric constant, and to improve the collapse in the case of a high voltage during the switching operation.

In each of the above embodiments, a Si substrate is used as the substrate 1 of the HFET. However, the substrate is not limited to the Si substrate, and a sapphire substrate, an SiC substrate, or a GaN substrate may be used.

Further, GaN is used as the channel layer 2 of the HFET, and Al _x Ga _1-x N is used as the barrier layer 3. However, it is not limited to the above configuration, and the channel layer 2 and the barrier layer 3 are represented by Al _x In _w Ga _1-xw N (x ≧ 0, w ≧ 0, 0 ≦ x + w <1). A nitride semiconductor layer may be used. That is, the nitride semiconductor layer composed of the channel layer 2 and the barrier layer 3 may be configured to contain AlGaN, GaN, InGaN, or the like.

In each of the above embodiments, a normally-on type HFET has been described. The same effect can be obtained even with a normally-off type HFET.

In each of the above embodiments, the nitride semiconductor layer is configured by directly forming the barrier layer 3 on the channel layer 2. In the present invention, the substrate 1, the nitride semiconductor layer, A buffer layer may be appropriately formed between and between the layers constituting the nitride semiconductor layer.

Further, an AlN layer having a thickness of about 1 nm may be formed between the channel layer 2 and the barrier layer 3 in order to improve mobility.

Further, GaN may be formed on the barrier layer 3 as a cap layer.

In each of the above embodiments, a recess is formed in the barrier layer 3 and the channel layer 2 where the source electrode 4 and the drain electrode 5 are formed, and an electrode material is deposited and annealed. , 5 and the 2DEG are formed as ohmic contacts. However, the formation method of the ohmic contact is not limited to this, and any formation method may be used as long as an ohmic contact can be formed between the

electrodes

4 and 5 and the 2DEG. For example, an undoped AlGaN layer for contact is formed on the channel layer 2 with a thickness of, for example, 15 nm, and an electrode material is directly deposited on the undoped AlGaN layer without forming a recess to form the source electrode 4 and the drain electrode 5. The ohmic contact may be formed by forming and annealing.

In each of the above embodiments, the gate electrode 6 is formed using WN / W in which WN and W are stacked in this order. However, the present invention is not limited to this, and any material may be used as long as it functions as a gate of a transistor. For example, TiN, Pt / Au, or Ni / Au can be used. Further, as the gate electrode material, a material that forms a Schottky junction when bonded to the nitride semiconductor layer may be used.

In each of the above embodiments, the source electrode 4 and the drain electrode 5 are formed using Ti / Al in which Ti and Al are laminated in this order. However, the present invention is not limited to this, and any material may be used as long as it has electrical conductivity and can make ohmic contact with the 2DEG. For example, Ti / Al / TiN may be formed using Ti / Al / TiN laminated in this order. Further, AlSi, AlCu, and Au may be used instead of the above-described Al, or may be laminated on Al.

Although specific embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention.

Hereinafter, when this invention is summarized, the field effect transistor of this invention is:
A nitride semiconductor layer including a heterojunction;
A source electrode 4 and a drain electrode 5 which are spaced apart from each other on the nitride semiconductor layer;
A gate electrode 6 disposed between the source electrode 4 and the drain electrode 5 on the nitride semiconductor layer;
A first insulating film 7 formed between the gate electrode 6 and the drain electrode 5 immediately above the nitride semiconductor layer, and having at least silicon and nitrogen as constituent elements;
A second insulating film 9 formed by laminating on the first insulating film 7,
The first insulating film 7 is formed up to the edge 8 of the contact surface between the drain electrode 5 and the nitride semiconductor layer,
The drain electrode 5 has a field plate portion 10 that protrudes toward the gate electrode 6 side and is in contact with the upper surface of the second insulating film 9.
A single-layer film region 11 provided under the field plate portion 10 in the vicinity of the edge 8 of the contact surface between the drain electrode 5 and the nitride semiconductor layer, and in which only the first insulating film 7 is formed;
The single-layer film region 11 is provided below the field plate portion 10 on the side opposite to the edge 8 side of the contact surface, and is formed by laminating the first insulating film 7 and the second insulating film 9. The multilayer film region 12 is provided.

According to the above configuration, the first insulating film 7 and the second insulating film are between the gate electrode 6 and the drain electrode 5 immediately above the nitride semiconductor layer and below the field plate portion 10. 9 are laminated in this order. Thus, by increasing the total film thickness of the insulating film under the field plate portion 10, the electric field on the surface of the nitride semiconductor layer can be relaxed.

At that time, since the first insulating film 7 includes silicon and nitrogen as constituent elements, the interface control of the surface of the nitride semiconductor layer can be performed, and the contact surface between the drain electrode 5 and the nitride semiconductor layer can be controlled. Are formed up to the edge 8.

By providing the single-layer film region 11 and the multilayer film region 12 as an insulating film covering the nitride semiconductor layer under the field plate portion 10, the field plate portion 10 can be formed stepwise. it can. Therefore, the electric field strength in the vicinity of the drain electrode 5 can be further relaxed, and the occurrence of disconnection of the drain electrode 5 can be suppressed.

In the field effect transistor of one embodiment,
The dielectric constant of the second insulating film 9 is smaller than the dielectric constant of the first insulating film 7.

According to this embodiment, the electric field concentration is kept away from the surface of the nitride semiconductor layer by reducing the dielectric constant of the second insulating film 9 located on the surface side of the insulating film below the field plate portion 10. be able to. Therefore, the electric field strength applied to the surface of the nitride semiconductor layer in the case of a high voltage during the switching operation can be further reduced, and the influence of the collapse on the 2DEG can be reduced.

Further, by using a film having a dielectric constant lower than that of the first insulating film 7 as the second insulating film 9, the required total film thickness of the first insulating film 7 and the second insulating film 9 is remarkably increased. Can be small. As a result, the occurrence of disconnection of the drain electrode 5 can be suppressed.

In the field effect transistor of one embodiment,
The relative dielectric constant of the first insulating film 7 is in the range of 7.5 to 9.5.

Since the first insulating film 7 needs to control the interface of the surface of the nitride semiconductor layer, a film having a higher silicon composition than the stoichiometry is desirable. In that case, if the silicon composition is too large, leakage occurs.

According to this embodiment, the relative dielectric constant of the first insulating film 7 is in the range of 7.5 or more and 9.5 or less. Therefore, the first insulating film 7 can perform interface control of the surface of the nitride semiconductor layer without causing leakage.

In the field effect transistor of one embodiment,
On the second insulating film 9, a third insulating film 13 having a dielectric constant smaller than that of the first insulating film 7 is further laminated.
The field plate portion 10 is in contact with the upper surface of the third insulating film 13.

According to this embodiment, the field plate portion 10 of the drain electrode 5 is formed by forming a multi-layer structure of three or more layers as an insulating film that covers the nitride semiconductor layer and is located under the field plate portion 10. Can be made into three or more stages. Therefore, the occurrence of disconnection of the drain electrode 5 can be further suppressed. Furthermore, the total film thickness of the insulating film can be increased, and the electric field strength on the surface of the nitride semiconductor layer can be further relaxed to improve the collapse in the case of a high voltage during switching operation. .

In the field effect transistor of one embodiment,
The second insulating film 9 or the third insulating film 13 covers an insulating film having a dielectric constant larger than that of the insulating film under the field plate portion 10 in the vicinity of the drain electrode 5.

According to this embodiment, the second insulating film 9 or the third insulating film 13 covers an insulating film having a dielectric constant larger than that of the insulating film. Therefore, it is possible to relax the electric field on the surface of the nitride semiconductor layer over a wide range. As a result, the collapse in the case of a high voltage during the switching operation can be further improved.

In the field effect transistor of one embodiment,
The first insulating film 7, the second insulating film 9, and the third insulating film 13 below the field plate portion 10 have a lower dielectric constant as the upper insulating film.

According to this embodiment, by lowering the dielectric constant of the upper insulating film, the electric field concentration can be kept away from the surface of the nitride semiconductor layer. Therefore, it is possible to further reduce the electric field strength applied to the surface of the nitride semiconductor layer in the case of a high voltage during the switching operation, and the influence of collapse on the 2DEG can be reduced.

In the field effect transistor of one embodiment,
The insulating film covering the insulating film 9 having a high dielectric constant under the field plate portion 10 in the vicinity of the drain electrode 5 has the lowest dielectric constant under the field plate portion 10 in the vicinity of the drain electrode 5. It is an insulating film.

According to this embodiment, since the other insulating film is covered with the insulating film having the lowest dielectric constant, the electric field on the surface of the nitride semiconductor layer can be relaxed over a wide range.

In the field effect transistor of one embodiment,
The total thickness of the insulating film formed under the field plate portion 10 is 200 nm or more.

According to this embodiment, the total film thickness of the insulating film under the field plate portion 10 is 200 nm or more. Therefore, the electric field on the surface of the nitride semiconductor layer in the vicinity of the drain electrode 5 is sufficiently relaxed, and the total film thickness is necessary for improving the collapse in the case of a high voltage during the switching operation.

1 ... Si substrate 2 ... GaN channel layer _{_{3 ... Al x Ga 1-x}} N (0 <x <1) barrier layer 4 ... source electrode 5 ... drain electrode 6 ... gate electrode 7 ... first insulating film 8 ... contact surface edge DESCRIPTION OF SYMBOLS 9 ... 2nd insulating film 10 ... Field plate part 11 ... Single layer film area | region 12 ... Multi-layer film area | region 12a ... 2 layer film area | region 12b ... 3 layer film area | region 13 ... 3rd insulating film

Claims

A nitride semiconductor layer including a heterojunction;
A source electrode (4) and a drain electrode (5) spaced apart from each other on the nitride semiconductor layer;
A gate electrode (6) disposed between the source electrode (4) and the drain electrode (5) on the nitride semiconductor layer;
A first insulating film (7) formed between the gate electrode (6) and the drain electrode (5) immediately above the nitride semiconductor layer, and comprising at least silicon and nitrogen as constituent elements;
A second insulating film (9) formed on the first insulating film (7),
The first insulating film (7) is formed up to the edge (8) of the contact surface between the drain electrode (5) and the nitride semiconductor layer,
The drain electrode (5) has a field plate portion (10) protruding in an eave-like shape toward the gate electrode (6) and in contact with the upper surface of the second insulating film (9). ,
Provided under the field plate portion (10) in the vicinity of the edge (8) of the contact surface between the drain electrode (5) and the nitride semiconductor layer, and only the first insulating film (7) is formed. A single layer film region (11),
The first insulating film (7) and the second insulating film are provided below the field plate portion (10) on the side opposite to the edge (8) side of the contact surface of the single layer film region (11). And a multilayer film region (12) formed by laminating (9).
The field effect transistor according to claim 1.
A third insulating film (13) having a dielectric constant smaller than that of the first insulating film (7) is further laminated on the second insulating film (9).
The field plate transistor (10) is in contact with the upper surface of the third insulating film (13).
The field effect transistor according to claim 2.
The second insulating film (9) or the third insulating film (13) has an insulating film having a dielectric constant larger than that of the insulating film under the field plate portion (10) in the vicinity of the drain electrode (5). A field effect transistor characterized by covering.
The field effect transistor according to any one of claims 1 to 3,
The field effect transistor according to claim 1, wherein a dielectric constant of the second insulating film (9) is smaller than a dielectric constant of the first insulating film (7).
The field effect transistor according to claim 2 or 3,
The first insulating film (7), the second insulating film (9), and the third insulating film (13) under the field plate portion (10) have a lower dielectric constant as the upper insulating film. A field effect transistor.