WO2016033755A1

WO2016033755A1 - Task handling apparatus and method, and electronic device

Info

Publication number: WO2016033755A1
Application number: PCT/CN2014/085834
Authority: WO
Inventors: 徐胜新; 崔爱国; 祝建华
Original assignee: 华为技术有限公司
Priority date: 2014-09-03
Filing date: 2014-09-03
Publication date: 2016-03-10
Also published as: CN105579963A; CN105579963B

Abstract

A task handling apparatus and method, and an electronic device. The method comprises: running at least one thread in a user layer (701); running an operating system in the thread, the operating system being used for handling a task (702); and in a task execution process, performing interrupt handling and/or task scheduling by means of the operating system in the thread (703). The problem of influence on the timeliness of a task handling process due to a larger delay for a single-time interrupt handling process and a task scheduling process caused by the fact that the interrupt handling process and the task scheduling process are implemented by repeated switching to a Linux kernel layer is solved. Effects of directly completing the interrupt handling and/or the task scheduling in the user layer without handling by the repeated switching to the kernel layer, shortening consumed time for the interrupt handling and/or the task scheduling and improving the timeliness of task handling are achieved.

Description

Task processing device, electronic device and method

Technical field

The present invention relates to the field of operating systems, and in particular, to a task processing apparatus, an electronic device, and a method.

Background technique

In the field of telecommunications, the Linux operating system is increasingly being used to implement processing of high real-time services.

Please refer to FIG. 1, which shows a schematic diagram of an architecture using a Linux operating system to process high real-time services. The architecture includes a hardware layer 120, a Linux kernel layer 140, and a user layer 160. User layer 160 can run at least one thread 162, each thread 162 for processing tasks. The task scheduling process and interrupt response process for each thread 162 is primarily implemented by the Linux kernel layer 140.

In the process of implementing the present invention, the inventors have found that the prior art has at least the following problems: since the task scheduling process and the interrupt response process are mainly implemented by the Linux kernel layer 140, multiple switching is required in a single task scheduling process or an interrupt response process. Processing in the Linux kernel layer 140 may result in a large delay in a single task scheduling process or an interrupt response process, which affects the real-time nature of the task processing process.

Summary of the invention

In order to solve the task scheduling process and the interrupt response process, it is necessary to switch to the Linux kernel layer for processing, resulting in a large delay of the single task scheduling process or the interrupt response process, which affects the real-time problem of the task processing process. Embodiments of the present invention provide a task processing apparatus, method, and electronic device. The technical solution is as follows:

According to a first aspect of the present invention, a task processing apparatus is provided, the apparatus comprising:

a first running module, configured to run at least one thread at a user layer;

a second running module, configured to run an operating system in the thread, where the operating system is used to process a task;

a task processing module, configured to perform an interrupt response and/or task scheduling by the operating system in the thread during processing of the task.

In a first possible implementation manner of the first aspect, the task processing module includes:

a request receiving unit, configured to receive an interrupt request of an interrupt source through a kernel layer;

a requesting transmission unit, configured to transmit, by the kernel layer, the interrupt request to an operating system of a corresponding thread in the user layer;

And a request response unit, configured to perform an interrupt response to the interrupt request by an interrupt processing program of an operating system of a corresponding thread in the user layer.

With reference to the first possible implementation manner of the first aspect, in the second possible implementation, the request transmission unit includes:

a first saving subunit, configured to save an operating site of the interrupted thread in a core stack of the kernel layer, where the running site includes a first user state instruction location;

a transfer subunit, configured to transfer the first user state instruction location from a first storage location in the core stack to a second storage location in a shared storage area, and store the interrupt request to the a third storage location in the shared storage area, where the shared storage area is a storage area accessible by both the kernel layer and the user layer;

An interrupt storage subunit, configured to store, in a first storage location in the core stack, a start instruction location of an interrupt handler in the operating system of the interrupted thread;

The subunit is exited for exiting the kernel layer response to the interrupt request.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation, the request response unit includes:

a first recovery subunit, configured to: when recovering the interrupted thread, read a start instruction position of an interrupt handler of the operating system from a first storage location of the core stack;

a second saving subunit, configured to save an operation site of the interrupted task in a user stack of the thread, where the running site includes a second user state instruction location;

a stack switching subunit, configured to switch from the user stack to an interrupt stack;

An interrupt response subunit, configured to read the interrupt request from the shared memory area, and perform an interrupt response based on the interrupt stack;

And a second recovery subunit, configured to resume the interrupted task or another task that needs to be scheduled after the end of the interrupt response.

In conjunction with the third possible implementation of the first aspect, in a fourth possible implementation, the request response unit further includes:

a replacement subunit, configured to replace the second user state instruction location saved in the user stack The first user state instruction location saved in the second storage location of the shared storage area;

The second recovery subunit is configured to recover the interrupted task by using the running site saved in the user stack.

Combining the first aspect or the first possible implementation of the first aspect or the second possible implementation of the first aspect or the third possible implementation of the first aspect or the fourth possible implementation of the first aspect In an embodiment, in a fifth possible implementation, the task processing module includes:

a task switching unit, configured to save, by the operating system, an operation site of the interrupted first task when switching from the first task to the second task, where the operation site of the first task includes register information, and a third a user state instruction location and a lock interruption information of the first task;

a first acquiring unit, configured to acquire, by using the operating system, an operating site of the second task, where the operating site of the second task includes register information, a fourth user state command location, and a lock interruption information of the second task ;

The first recovery unit recovers the second task and processes according to the operating site of the second task by the operating system.

Combining the first aspect or the first possible implementation of the first aspect or the second possible implementation of the first aspect or the third possible implementation of the first aspect or the fourth possible implementation of the first aspect In an embodiment, in a sixth possible implementation, the task processing module includes:

a task detecting unit, configured to detect, by the operating system, whether there is a third task that needs to be preferentially scheduled when an interrupt response ends;

a second obtaining unit, configured to acquire, by the operating system, an operation site of the third task when the third task exists, where the running site of the third task includes a register information, a fifth user state instruction location, and The lock interruption information of the third task;

And a second recovery unit, configured to recover the third task and process according to the operating site of the third task by using the operating system.

According to a second aspect of the present invention, an electronic device is provided, the electronic device comprising: a processor and a memory;

The memory is configured to store one or more instructions for implementing a task processing method;

The method order includes:

Running at least one thread at the user level;

Running an operating system in the thread, the operating system for processing a task;

Interrupting response and/or task scheduling by the operating system in the thread during processing of the task;

The processor is operative to execute the instructions.

In a first possible implementation of the second aspect, instructions for performing the following operations are also stored:

Receiving an interrupt request of an interrupt source through a kernel layer;

Transmitting the interrupt request to an operating system of a corresponding thread in the user layer by the kernel layer;

Interrupting the interrupt request by an interrupt processing program of an operating system of a corresponding thread in the user layer;

The processor is operative to execute the instructions.

In conjunction with the first possible implementation of the second aspect, in a second possible implementation, instructions for performing the following operations are also stored:

Saving an operation site of the interrupted thread in a core stack of the kernel layer, the operation site including a first user state instruction location;

Transferring the first user state instruction location from a first storage location in the core stack to a second storage location in a shared storage area for storage, and storing the interrupt request in the shared storage area Three storage locations;

Storing a start instruction location of an interrupt handler in the operating system of the interrupted thread in a first storage location in the core stack;

Exiting the kernel layer's response to the interrupt request;

The processor is operative to execute the instructions.

In conjunction with the second possible implementation of the second aspect, in a third possible implementation, the memory further stores instructions for performing the following operations:

Reading the initial instruction location of the interrupt handler of the operating system from the first storage location of the core stack when the interrupted thread is restored;

A user site of the thread saves an operation site of the interrupted task, the operation site including a second user state instruction location;

Switching from the user stack to an interrupt stack;

Reading the interrupt request from the shared memory area and performing an interrupt based on the interrupt stack should;

After the interrupt response ends, recovering the interrupted task or another task requiring priority scheduling;

The processor is operative to execute the instructions.

In conjunction with the third possible implementation of the second aspect, in a fourth possible implementation, an instruction for performing the following operations is also stored:

Replacing the second user state instruction location saved in the user stack with the first user state instruction location saved in the second storage location of the shared storage area;

Recovering the interrupted task by the running site saved in the user stack;

The processor is operative to execute the instructions.

Combining the second aspect or the first possible implementation of the second aspect or the second possible implementation of the second aspect or the third possible implementation of the second aspect or the fourth possible implementation of the second aspect Embodiments, in a fifth possible implementation, an instruction for performing the following operations is also stored:

When the first task is switched to the second task, the operating site of the interrupted first task is saved by the operating system, and the running site of the first task includes register information, a third user state command location, and a location The lock interrupt information of the first task;

Obtaining, by the operating system, an operation site of the second task, where the operation site of the second task includes register information, a fourth user state instruction location, and lock interruption information of the second task;

Recovering and processing the second task according to the operating site of the second task by the operating system;

The processor is also operative to execute the instructions.

Combining the second aspect or the first possible implementation of the second aspect or the second possible implementation of the second aspect or the third possible implementation of the second aspect or the fourth possible implementation of the second aspect Embodiments, in a sixth possible implementation, an instruction for performing the following operations is also stored:

At the end of an interrupt response, the operating system detects whether there is a third task requiring priority scheduling;

When the third task exists, the operating site of the third task is acquired by the operating system, and the running site of the third task includes register information, a fifth user state command location, and a lock of the third task. Interrupt information;

Recovering and processing the third task according to the operating site of the third task by the operating system;

The processor is also operative to execute the instructions.

According to a third aspect of the embodiments of the present invention, a task processing method is provided, the method comprising:

Running at least one thread at the user level;

In the process of processing the task, an interrupt response and/or task scheduling is performed by the operating system in the thread.

In a first possible implementation manner of the third aspect, in the process of processing the task, performing an interrupt response by using the operating system in the thread, including:

Receiving an interrupt request of an interrupt source through a kernel layer;

The interrupt request is interrupted by an interrupt handler of an operating system of a corresponding thread in the user layer.

In conjunction with the first possible implementation of the third aspect, in a second possible implementation, the transmitting, by the kernel layer, the interrupt request to the corresponding one of the user layers Operating system, including:

Transferring the first user state instruction location from a first storage location in the core stack to a second storage location in a shared storage area for storage, and storing the interrupt request in the shared storage area a storage location, where the shared storage area is a storage area accessible by both the kernel layer and the user layer;

Exiting the kernel layer's response to the interrupt request.

With the second possible implementation of the third aspect, in a third possible implementation, the interrupt request is interrupted by an interrupt processing program in the operating system, including:

Switching from the user stack to an interrupt stack;

Reading the interrupt request from the shared storage area, and performing an interrupt response based on the interrupt stack;

After the interrupt response ends, the interrupted task or another task requiring prioritization is resumed.

In conjunction with the third possible implementation of the third aspect, in a fourth possible implementation, before the switching from the user stack to the interrupt stack, the method further includes:

Recovering the interrupted task after the interrupt response ends, including:

The interrupted task is resumed by the running site saved in the user stack.

Combining the third aspect or the first possible implementation of the third aspect or the second possible implementation of the third aspect or the third possible implementation of the third aspect or the fourth possible aspect of the third aspect Embodiments, in a fifth possible implementation manner, in the process of performing the task, performing task scheduling by using the operating system in the thread, including:

And recovering, by the operating system, the second task according to the running site of the second task and processing.

With reference to the third aspect or the first possible implementation of the third aspect or the second possible implementation of the third aspect or the third possible implementation or the fourth possible implementation of the third aspect, In a sixth possible implementation manner, in the process of performing the task, performing task scheduling by using the operating system in the thread, including:

Obtaining, by the operating system, the running of the third task when the third task exists Field, the operation site of the third task includes register information, a fifth user state instruction location, and lock interruption information of the third task;

And recovering, by the operating system, the third task according to an operation site of the third task and processing.

The beneficial effects of the technical solutions provided by the embodiments of the present invention are:

By running the operating system in the thread of the user layer for interrupt response and/or task scheduling; solving the interrupt response process and the task scheduling process need to switch to the Linux kernel layer for processing, resulting in a single interrupt response process and The delay of the task scheduling process is large, which affects the real-time behavior of the task processing. It achieves the interrupt response and/or task scheduling directly in the user layer. It does not need to switch to the kernel layer for processing, reducing the interrupt response and / Or the time-consuming task scheduling improves the real-time performance of the task processing, and also reduces the load of the kernel layer.

DRAWINGS

In order to more clearly illustrate the prior art or the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only the present invention. For some embodiments, other drawings may be obtained from those of ordinary skill in the art without departing from the drawings.

FIG. 1 is a schematic diagram of an architecture using a Linux operating system to process high real-time services;

2 is a block diagram showing the structure of a task processing apparatus according to an embodiment of the present invention;

FIG. 3 is a block diagram showing the structure of a task processing apparatus according to another embodiment of the present invention; FIG.

FIG. 3B is a block diagram showing the structure of the request transmission unit provided in FIG. 3A; FIG.

FIG. 3C is a structural block diagram of the request response unit provided in FIG. 3A; FIG.

4 is a block diagram showing the structure of a task processing apparatus according to still another embodiment of the present invention;

FIG. 5 is a block diagram showing the structure of an electronic device according to an embodiment of the present invention; FIG.

FIG. 5B is a structural block diagram of an electronic device according to another embodiment of the present invention; FIG.

6A and FIG. 6B are schematic diagrams showing the structure of an electronic device according to the task processing method provided by the embodiment of the present invention;

7 is a flowchart of a method for processing a task according to an embodiment of the present invention;

FIG. 8 is a flowchart of a method for processing a task according to another embodiment of the present invention; FIG.

9 is a flow chart showing the sub-steps of the task processing method provided in the embodiment shown in FIG. 8;

10 is a flow chart of sub-steps of the task processing method provided in the embodiment shown in FIG.

11 is a flowchart of a method for processing a task according to still another embodiment of the present invention;

Figure 12 is a flow chart showing the sub-steps of the task processing method provided in the embodiment shown in Figure 11;

FIG. 13 is a flow chart showing the sub-steps of the task processing method provided in the embodiment shown in FIG.

detailed description

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

Firstly, some nouns related to the embodiments of the present invention are introduced:

Hardware layer: The hardware layer is the hardware foundation in the electronic device. It usually includes a processor (Central: Central Processing Unit, CPU) and memory. The processor can be a single core processor or a multi-core processor. The electronic device may be an electronic device that has certain requirements for real-time processing of tasks, such as a base station device, a transmission device, and an industrial robot. In the Global System for Mobile Communication (GSM) system, the base station equipment can be a base transceiver station (English: Base Transmitter Station, abbreviation: BTS); in the third generation (English: 3rd- Generation, abbreviation: 3G) In mobile communication technology, the base station equipment can be Node B (English: Node Base station, abbreviation: Node B); in the fourth generation (English: the 4Generation, abbreviation: 4G) mobile communication technology, the base station The device may be an evolved Node B (English: Evolved Node Base station, abbreviation: eNB).

Kernel and User Layers: The kernel layer is the operating system kernel, virtual storage space, and the layer that drives the application to run; the user layer is the layer in which normal applications run.

Interrupt: Interrupt refers to any unusual or unexpected urgent need to be processed in the system during the execution of the computer, so that the processor temporarily interrupts the currently executing program and then goes to execute the corresponding event handler. After the processing is completed, Returns the process of continuing execution or scheduling a new process execution. The event that caused the interrupt to occur is called the interrupt source. The request interrupt processing signal sent by the interrupt source to the processor is called an interrupt request. The process by which a processor processes an interrupt request is called an interrupt response.

Core stack: The stack used by the operating system kernel.

User stack: Each thread has a user stack used by itself, which can be a real-time thread or a normal thread.

Please refer to FIG. 2, which is a structural block diagram of a task processing apparatus according to an embodiment of the present invention. The task processing device can be implemented as an electronic device by software, hardware, or a combination of both All or part. The task processing device includes a first running module 220, a second running module 240, and a task processing module 260.

The first running module 220 is configured to run at least one thread at the user layer.

The second running module 240 is configured to run an operating system in the thread, where the operating system is used to process the task. There can be one operating system running in each thread, which is used to process tasks. The operating system needs to have the ability to independently perform interrupt response and/or task scheduling. Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads. The type of the above operating system is not particularly limited in the embodiment of the present invention.

Tasks are generic tasks that the operating system can handle. When the electronic device is a base station device, the task may be a task of issuing a scheduling instruction, a task of allocating a channel resource, a task of processing an access request, and the like.

The task processing module 260 is configured to perform an interrupt response and/or task scheduling by an operating system in the thread during the processing of the task.

In summary, the task processing apparatus provided in this embodiment performs interrupt response and/or task scheduling through an operating system in a thread; and solves the interrupt response process and the task scheduling process, which requires multiple switching to the Linux kernel layer for processing. The delay of the single interrupt response process and the task scheduling process is large, which affects the real-time behavior of the task processing; the interrupt response and/or task scheduling are directly completed in the user layer, and it is not necessary to switch to the kernel layer multiple times. Processing, reducing the time consuming of interrupt response and/or task scheduling, improves the real-time effect of task processing.

At the same time, since the interrupt response and/or task scheduling in the background technology are performed by the kernel layer, the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.

Please refer to FIG. 3A, which is a structural block diagram of a task processing apparatus according to another embodiment of the present invention. The task processing device can be implemented as all or part of an electronic device by software, hardware, or a combination of both. The task processing apparatus includes a first execution module 220 for running at least one thread at the user layer.

The second running module 240 is configured to run an operating system in a thread running by the first running module 220, where the operating system is used to process a task.

The task processing module 260 is configured to perform an interrupt response by the operating system running in the thread by the second running module 240 during the processing of the task.

In this embodiment, the task processing module 260 includes:

The request receiving unit 261 is configured to receive an interrupt request of the interrupt source through the kernel layer.

The request transmission unit 262 is configured to transmit, by the kernel layer, the interrupt request received by the request receiving unit 261 to the operating system of the corresponding thread in the user layer run by the second running module 240.

The request response unit 263 is configured to perform an interrupt response to the interrupt request received by the request transmission unit 262 by an interrupt processing program of an operating system of a corresponding thread in the user layer.

As shown in FIG. 3B, the request transmission unit 262 may include:

The first save subunit 262a is configured to save an operation site of the interrupted thread in a core stack of the kernel layer, where the run site includes a first user state instruction location.

The transfer subunit 262b is configured to transfer the first user state instruction location saved by the first save subunit 262a from the first storage location in the core stack to the second storage location in the shared storage area for storage, and the request receiving unit The received interrupt request is stored in a third storage location in the shared storage area, and the shared storage area is a storage area accessible by both the kernel layer and the user layer.

The interrupt storage sub-unit 262c is configured to transfer the first user state instruction position from the first storage location in the core stack to the second storage location in the shared storage area after the transfer sub-unit 262b is stored, in the core stack The starting instruction location of the interrupt handler in the operating system that stores the interrupted thread in a storage location.

The exit sub-unit 262d is configured to exit the kernel layer response to the interrupt request after the interrupt storage sub-unit 262c stores the start instruction position in the first storage location in the core stack.

As shown in FIG. 3C, the request response unit 263 may include:

The first recovery subunit 263a is configured to: after the exit subunit 262d exits the kernel layer response to the interrupt request, read the interrupt handler of the operating system from the first storage location of the core stack when restoring the interrupted thread Start command position.

The second save subunit 263b, the user stack of the thread for recovery at the first recovery subunit 263a saves the run site of the interrupted task, the run site including the second user state command location.

The stack switching sub-unit 263c is configured to switch from the user stack used by the second saving sub-unit 263b to the interrupt stack.

The interrupt response sub-unit 263d is configured to read an interrupt request from the shared memory area and perform an interrupt response based on the interrupt stack to which the stack switching sub-unit 263c is switched.

The second recovery sub-unit 263e is configured to resume the interrupted task or another task requiring priority scheduling after the interrupt response sub-unit 263d interrupts the response.

The request response unit 263 may further include:

a replacement subunit 263f, configured to replace the second user state instruction location saved in the user stack by the second save subunit 263b with the first user state instruction location saved in the second storage location of the shared storage area;

The second recovery subunit 263e is configured to recover the interrupted task by using the running scene saved in the user stack, the running scene is saved by the second saving subunit 263b, and the second user state instruction is replaced by the replacing subunit 263f. The position is replaced with the first user mode command position.

In summary, the task processing apparatus provided in this embodiment performs interrupt processing by using an operating system in a thread by running an operating system in a thread; and the interrupt processing process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation. The delay of the interrupt processing process is large, which affects the real-time problem of the task processing process; the interrupt processing is completed directly in the user layer, and it is not necessary to switch to the kernel layer for processing, reducing the time-consuming processing of the interrupt processing and improving The real-time nature of the task processing.

At the same time, since the interrupt response in the background art is performed by the kernel layer, the load of the kernel layer is high, and the task processing apparatus provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.

The task processing apparatus provided by the embodiment further stores the interrupt request in the shared storage area through the kernel layer, and after the thread of the user layer is restored, acquires the interrupt request from the shared storage area, so that the kernel layer can report the interrupt request to the thread. The interrupt request is processed by the operating system in the thread.

The task processing apparatus provided in this embodiment further replaces the first user state instruction position in the core stack with the start instruction position of the interrupt processing program of the operating system, so that the thread of the user layer is restored, and the entry is not interrupted. The first user state instruction position continues to run, but forcibly jumps to the interrupt handler in the operating system, and enters the interrupt response process without delay, realizing the effect of fast reporting and response of the interrupt request.

The task processing apparatus provided in this embodiment also independently completes the interrupt response by the interrupt processing program of the operating system, and does not need to switch to the kernel layer for processing in the process, and the time required to complete the complete interrupt response process is very small. Effect.

Please refer to FIG. 4, which is a structural block diagram of a task processing apparatus according to another embodiment of the present invention. The task processing device can be implemented as all or part of an electronic device by software, hardware, or a combination of both. The task processing device can include:

a second running module 240, configured to run an operating system in a thread running by the first running module 220, This operating system is used to process tasks.

The task processing module 260 is configured to perform task scheduling by the operating system running in the thread by the second running module 240 during the processing of the task.

In this embodiment, the task processing module 260 may include:

The task switching unit 264 is configured to: when the first task is switched to the second task, the operating system running by the second running module 240 saves the running site of the interrupted first task, where the running site of the first task includes register information, The third user mode instruction location and the lock interruption information of the first task.

The first obtaining unit 265 is configured to obtain, after the task switching unit 264 saves the running site of the interrupted first task, the operating site of the second task by using the operating system, where the running site of the second task includes the register information and the fourth user state. The command position and the lock interrupt information of the second task.

The first recovery unit 266 restores the second task and processes it according to the operating site of the second task saved by the first obtaining unit 265 by the operating system.

In this embodiment, the task processing module 260 may further include:

The task detecting unit 267 is configured to detect, by the operating system running by the second running module 240, whether there is a third task that needs to be preferentially scheduled when the interrupt response ends.

The second obtaining unit 268 is configured to acquire, by the operating system, the running site of the third task when the task detecting unit 267 detects that the third task exists, where the running site of the third task includes the register information, the fifth user state command position, and the Three task lock interrupt information.

The second recovery unit 269 is configured to recover and process the third task according to the operating site of the third task acquired by the second obtaining unit 268 by the operating system.

In summary, the task processing apparatus provided in this embodiment performs task scheduling by running an operating system in a thread through an operating system in a thread; and solves the problem that the task scheduling process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation. The delay of the task scheduling process is large, which affects the real-time problem of the task processing process. It achieves the task scheduling directly in the user layer, does not need to switch to the kernel layer multiple times, reduces the time-consuming task scheduling, and improves the task. The effect of real-time processing.

At the same time, since the task scheduling in the background technology is performed by the kernel layer, the load of the kernel layer is high, and the task processing apparatus provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.

Please refer to FIG. 5A, which is a structural block diagram of an electronic device according to an embodiment of the present invention. The electronic device 500 includes a processor 520 and a memory 540. The processor 520 and the memory 540 can be connected by a communication bus. The memory 540 can be an instruction memory, a memory, a register, and the like.

The memory 540 is configured to store one or more instructions for implementing a task processing method, the instructions including:

Running at least one thread at the user level;

Running an operating system in a thread that is used to process tasks;

Interrupt response and/or task scheduling is performed by the operating system in the thread during the processing of the task.

The processor 520 is configured to execute the above instructions.

Among them, each thread can run an operating system, which is used to process tasks. The operating system needs to have the ability to independently perform interrupt response and/or task scheduling. Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads. The type of the above operating system is not particularly limited in the embodiment of the present invention.

In summary, the electronic device provided in this embodiment performs interrupt response and/or task scheduling through an operating system in a thread; the interrupt response process and the task scheduling process need to be switched to the Linux kernel layer for processing, resulting in processing. The delay of the single interrupt response process and the task scheduling process is large, which affects the real-time performance of the task processing process; the interrupt response and/or task scheduling are directly completed in the user layer, and it is not necessary to switch to the kernel layer multiple times. Processing, reducing the time consuming of interrupt response and/or task scheduling, improves the real-time effect of task processing.

In an alternative embodiment provided based on the embodiment illustrated in Figure 5A, the memory 540 also stores instructions for performing the following operations:

The interrupt request of the interrupt source is received through the kernel layer.

The interrupt request is transmitted through the kernel layer to the operating system of the corresponding thread in the user layer.

The interrupt request is interrupted by an interrupt handler of an operating system of a corresponding thread in the user layer;

The processor 520 is also operative to execute the above instructions. The processor 520 typically receives an interrupt request for the interrupt source via an interrupt line on the bus 560.

Optionally, the memory 540 also stores instructions for performing the following operations:

The running site of the interrupted thread is saved in the core stack of the kernel layer, which includes the first user state instruction location.

The first user state instruction location is transferred from the first storage location in the core stack to the second storage location in the shared storage area for storage, and the interrupt request is stored to a third storage location in the shared storage area.

Storing a start instruction location of an interrupt handler in an operating system of the interrupted thread in a first storage location in the core stack;

Exit the kernel layer's response to the interrupt request;

The processor 520 is also operative to execute the above instructions. The core stack and the shared storage area may be a logical location in physical memory. This physical memory can belong to the memory 540.

Reading the initial instruction location of the interrupt handler of the operating system from the first storage location of the core stack when restoring the interrupted thread;

The user stack of the thread saves the running site of the interrupted task, the running site including the second user state command location;

Switch from the user stack to the interrupt stack;

Reading an interrupt request from the shared memory and performing an interrupt response based on the interrupt stack;

After the interrupt response ends, the interrupted task or another task that needs to be scheduled is resumed;

The processor 520 is also operative to execute the above instructions. The interrupt stack and the user stack corresponding to each thread may be a logical location in physical memory. This physical memory can belong to the memory 540.

Resume the interrupted task through the running site saved in the user stack;

The processor 520 is also operative to execute the above instructions.

In summary, the electronic device provided by the embodiment further stores the interrupt request in the shared storage area through the kernel layer, and after the thread of the user layer recovers, acquires the interrupt request from the shared storage area, so that the kernel layer can request the interrupt. Reported to the thread, the interrupt request is processed by the operating system in the thread.

The electronic device provided by the embodiment further replaces the first user state instruction position in the core stack with the start instruction position of the interrupt handler of the operating system, so that the thread of the user layer is restored, and the entry is not interrupted. The first user mode instruction position continues to run, but the forced jump to the operating system The interrupt handler in the program directly enters the interrupt response process without delay, and achieves the effect of fast reporting and response of the interrupt request.

The electronic device provided in this embodiment also independently completes the interrupt response by the interrupt processing program of the operating system, and does not need to switch to the kernel layer for processing in the process, and the time required to complete the complete interrupt response process is very small. effect.

In an alternative embodiment provided based on the embodiment shown in Figure 5A:

The memory 540 also stores instructions for performing the following operations:

When the first task is switched to the second task, the operating site of the interrupted first task is saved by the operating system, and the running site of the first task includes the register information, the third user state instruction position, and the lock interruption information of the first task. .

Obtaining, by the operating system, a running site of the second task, where the running site of the second task includes register information, a fourth user state command location, and a lock interruption information of the second task;

Recovering the second task and processing by the operating system according to the operation site of the second task;

The processor 520 is also operative to execute the above instructions.

At the end of an interrupt response, the operating system detects whether there is a third task requiring priority scheduling.

When there is a third task, the operating site of the third task is acquired by the operating system, and the running site of the third task includes the register information, the fifth user state instruction location, and the lock interruption information of the third task.

The third task is resumed and processed by the operating system according to the operation site of the third task;

The processor 520 is also operative to execute the above instructions.

In summary, the electronic device provided in this embodiment performs task scheduling through an operating system in a thread by running an operating system in a thread. The task scheduling process needs to be switched to the Linux kernel layer multiple times, resulting in a single task. The delay of the scheduling process is large, which affects the real-time problem of the task processing process. It achieves the task scheduling directly in the user layer, does not need to switch to the kernel layer multiple times, reduces the time-consuming task scheduling, and improves the task processing. The effect of real time.

In addition, referring to FIG. 5B, the electronic device 500 may further include a communication bus 530 and transmitting power. Path 552 and receiving circuit 554 and the like. The processor 520 controls the operation of the electronic device 500. The processor 520 may also be referred to as a central processing unit (English: Central Processing Unit, abbreviated CPU). Memory 540 can include read only memory and random access memory and provides instructions and data to processor 520. A portion of the memory 540 may also include a non-volatile random access memory (Non-Volatile Random Access Memory, abbreviated as NVRAM). In a particular application, transmit circuitry 552 and receive circuitry 554 can be coupled to transceiver 550. The various components of electronic device 500 are coupled together via communication bus 530, which may include, in addition to the data bus, a power bus, a control bus, interrupt lines, and other status signal buses. However, for clarity of description, various buses are labeled as communication bus 530 in the figure.

The following are embodiments of the method of the present invention, each of which corresponds to the above apparatus embodiment.

Please refer to FIG. 6A, which is a schematic structural diagram of an electronic device involved in a task processing method according to an embodiment of the present invention. The electronic device includes a hardware layer 620, a kernel layer 640, and a user layer 660.

The hardware layer 620 includes a processor, which may have a processor core 622, ie, the processor is a single core processor.

The kernel layer 640 includes an operating system kernel 642 and a driver application (not shown), which may be a Linux kernel.

The user layer 660 can run a thread (English: thread) 662, and each thread 662 runs an operating system (English: operation system, abbreviation: os), which can be a real-time thread and/or a user thread. The operating system can monopolize the processor core 622 to form an Asymmetric Multi-Processing (abbreviation: AMP) structure.

Please refer to FIG. 6B, which is a schematic structural diagram of still another electronic device involved in the task processing method provided by the embodiment of the present invention. The electronic device includes a hardware layer 620, a kernel layer 640, and a user layer 660.

The hardware layer 620 includes a processor, which may include two or more processor cores 622 (illustrated by two processor cores in the figure), that is, a multi-core processor.

User layer 660 can run with threads 662, each of which runs an operating system for processing tasks. The thread 662 can be a real-time thread and/or a user thread. Each operating system can monopolize a processor core 622 to form a Symmetric Multi-Processing (SMP) structure.

Please refer to FIG. 7, which is a flowchart of a method for processing a task according to an embodiment of the present invention. This embodiment is exemplified by applying the task processing method to the electronic device shown in FIG. 6A or FIG. 6B. The method includes:

Step 701, running at least one thread in the user layer;

Step 702, running an operating system in a thread, the operating system can be used to process a task;

There can be one operating system running in each thread, which is used to process tasks.

The operating system needs to have the ability to independently perform interrupt response and/or task scheduling. Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads. The type of the above operating system is not particularly limited in the embodiment of the present invention.

The task is generally referred to as a task that the operating system can process. When the electronic device is a base station device, the task may be a task of issuing a scheduling instruction, a task of allocating a channel resource, a task of processing an access request, and the like.

In step 703, during the execution of the task, the interrupt response and/or task scheduling is performed by the operating system in the thread.

In summary, the task processing method provided in this embodiment performs interrupt response and/or task scheduling through an operating system in a thread; and the interrupt response process and the task scheduling process need to be switched to the Linux kernel layer for processing. The delay of the single interrupt response process and the task scheduling process is large, which affects the real-time behavior of the task processing; the interrupt response and/or task scheduling are directly completed in the user layer, and it is not necessary to switch to the kernel layer multiple times. Processing, reducing the time consuming of interrupt response and/or task scheduling, improves the real-time effect of task processing.

The following is an explanation of the interrupt response process and the task scheduling process in two embodiments.

Please refer to FIG. 8 , which illustrates a method flow of a task processing method according to another embodiment of the present invention. Cheng Tu. This embodiment is exemplified by applying the task processing method to the electronic device shown in FIG. 6A or FIG. 6B. The method includes:

Step 801, running at least one thread in the user layer;

The electronic device runs at least one thread in the user layer, which may be a real-time thread for processing a real-time task, or a normal thread for processing a normal task.

Step 802, running an operating system in a thread;

The electronic device runs the operating system in a thread. An operating system can be run separately in each thread. The electronic device processes the task through the operating system.

Step 803, receiving an interrupt request of an interrupt source through a kernel layer;

The electronic device receives an interrupt request of the interrupt source through the kernel layer, and the interrupt source may be an external hardware device, and the external hardware device may be a hardware device such as a mouse, a keyboard, a network card, or a graphics card.

Optionally, an interrupt fast processing program can be implemented in the kernel layer, the interrupt fast processing program is configured to receive an interrupt request in the kernel layer, and report the interrupt request to an operating system in the corresponding thread, so that the operating system in the thread Respond to the interrupt request.

The electronic device receives an interrupt request of the interrupt source through the interrupt fast processing program.

After the interrupt fast processing program receives the interrupt request, the electronic device enters the lock interrupt state by interrupting the fast processing program.

The lock interrupt status is used to prevent the processor from receiving another interrupt request during the processing of an interrupt request, thereby causing the interrupt request processing to be interrupted. The implementation of the lock interrupt status can be either a hardware lock interrupt or a software lock interrupt.

When the hardware lock is interrupted, the kernel layer will no longer receive other interrupt requests during the processing of this interrupt request.

When the software lock is interrupted, the kernel layer still receives other interrupt requests during the processing of the interrupt request, but does not interrupt the processing of the interrupt request, but stores the subsequently received interrupt request in the kernel layer. In the interrupt request queue, after the processing of the interrupt request is completed, other interrupt requests are sequentially processed from the interrupt request queue.

Step 804, the interrupt request is transmitted to the operating system of the corresponding thread in the user layer through the kernel layer;

Unlike the background art, the electronic device does not respond to the interrupt request in the kernel layer, but responds by transmitting the interrupt request to the operating system of the corresponding thread in the user layer through the kernel layer. The thread corresponding to the interrupt request is usually the thread that was interrupted by the interrupt request. That is, step 804 can include the following sub-steps, as shown in FIG.

804a. The electronic device saves an operation site of the interrupted thread in a core stack of the kernel layer, where the operation site includes a first user state instruction location;

Since the processor can only process one program fragment per unit time, for example, the processor is currently processing one thread, it cannot process other threads or program fragments belonging to the kernel layer. When the processor receives an interrupt request in the kernel layer, the interrupt request interrupts the currently running thread of the processor, and the processor will respond to the interrupt request. In order for the interrupted thread to resume operation at a later time, the electronic device saves the running site of the interrupted thread in the kernel stack of the kernel layer by interrupting the fast processing program, and the running site includes various register values of the thread when interrupted. The first user mode instruction location. The first user state instruction location is also referred to as a first user state PC (English: program counter, Chinese: program counter) pointer, and the first user state PC pointer refers to the next instruction that the interrupted thread originally planned to run before the interruption. s position. When the thread is restored, the processor can resume the operation of the thread by running a program instruction corresponding to the location of the first user state instruction.

The core stack is the stack in the kernel layer. The electronic device saves the running site of the thread in the core stack by interrupting the fast processing program. The first user state instruction location is stored in a first storage location of the core stack.

804b. The electronic device moves the first user state instruction location from the first storage location in the core stack to the second storage location in the shared storage area for storage, and stores the interrupt request in a third storage location in the shared storage area. The shared storage area is a storage area accessible by both the kernel layer and the user layer;

The electronic device can move the first user state instruction location from the first storage location in the core stack to the second storage location in the shared storage area by an interrupt fast handler in the kernel layer.

804c. The electronic device stores a starting instruction position of an interrupt processing program of the operating system in a first storage location in the core stack.

The operating system in the thread provided by the embodiment of the present invention has the function of independently completing the interrupt response. Optionally, an interrupt handler can be implemented in the operating system of the thread, the interrupt handler being responsive to an interrupt request reported by the kernel layer to an operating system in the thread.

The electronic device stores the starting instruction position of the operating system interrupt processing program in the first storage location in the core stack through the interrupt fast processing program in the kernel layer, the operating system is the interrupted thread The operating system in .

That is, when the interrupted thread is resumed, the processor will read the interrupt handler of the operating system in the thread instead of the program instruction corresponding to the first user state instruction position.

804d, the electronic device exits the processing of the interrupt request through the kernel layer.

At this point, the interrupt request is stored in the shared memory area waiting for the operating system in the thread in the user layer to process.

It should be noted that steps 804a to 804d are all implemented by the electronic device through the kernel layer.

In step 805, the interrupt request is interrupted by an interrupt handler in the operating system.

Step 805 includes the following sub-steps, as shown in FIG. 10:

805a, the electronic device reads the starting instruction position of the operating system interrupt processing program from the first storage location of the core stack when restoring the interrupted thread;

The first user state instruction location stored by the first storage location in the core stack is replaced with the starting instruction location of the operating system's interrupt handler. When the electronic device restores the interrupted thread according to the running scene saved in the core stack, the program instruction read by the processor according to the first storage location in the core stack is a program instruction corresponding to the interrupt processing program of the operating system in the thread. . Thereafter, the operating system in the thread interrupts the interrupt request through the interrupt handler.

805b, the electronic device saves an operation site of the interrupted task in a thread user stack, and the operation site includes a second user state instruction location;

Because the operating system in the thread is a separate operating system, and the operating system in the thread is used to process the task. When there is an interrupt request to be processed, the interrupt request interrupts the running task in the operating system, and the electronic device first saves the running site of the interrupted task in the user stack of the thread through the interrupt handler, and the running site includes the task. The various register values and the second user mode command position when interrupted. The second user state instruction location is also referred to as a second user state PC pointer, and the second user state PC pointer is the pointer location corresponding to the next instruction that the interrupted task was scheduled to run before the interruption.

Since the processor directly reads the interrupt handler to run when the thread resumes in step 805a, the second user state instruction location is typically the same as the first user state instruction location in step 804a. For example, if the thread in step 804a is interrupted when it is going to run to the A position in the program code corresponding to a certain task, then the program instruction position of the task to be interrupted in the thread in step 805b should also be the A position, and No change.

Each thread has its own user stack, and the electronic device runs the task through an interrupt handler. The scene is saved in the user stack. The second user mode instruction location is saved in a fourth storage location in the user stack.

Step 805c: The electronic device replaces the second user state instruction location saved in the user stack with the first user state instruction location saved in the second storage location of the shared storage area;

Since the second user state instruction position stored in step 805b may save an error, the second user state instruction position of the saved error may be different from the first user state instruction position, in order to ensure the correctness of the task when the operation is resumed, The electronic device replaces the second user state instruction position saved in the user stack in step 805b with the first user state instruction position saved in the second storage location of the shared storage area by the interrupt processing program, that is, the step 804b is replaced. The first user mode instruction location is transferred to the shared memory area.

Step 805d, the electronic device switches from the user stack to the interrupt stack;

The interrupt stack is used to store data during the interrupt response process.

Step 805e: The electronic device reads the interrupt request from the shared storage area, and performs an interrupt response based on the interrupt stack.

The electronic device reads the interrupt request from the shared memory by the interrupt handler, and the interrupt request may specifically be an interrupt number, and then the interrupt handler interrupts the interrupt request based on the interrupt stack.

Step 805f: After the interrupt response ends, the electronic device resumes the interrupted task or another task that needs to be scheduled preferentially;

After the interrupt response ends, if there are no other tasks that need to be scheduled preferentially, the electronic device restores the interrupted task according to the running scene saved in the user stack through the interrupt handler.

If there are other tasks that need to be scheduled in priority, the electronic device resumes another task that needs to be scheduled according to the running site saved in the user stack through the interrupt handler.

The electronic device may also change the lock interrupt status in the kernel layer to the unlock interrupt status through the interrupt handler when the interrupted task or the task requiring priority scheduling is resumed. When in the unlocked interrupt state, the electronic device can continue to receive the interrupt request.

It should be noted that in step 804d, the electronic device needs to remain in the lock interrupt state. Due to the difference between the hardware lock interrupt and the software lock interrupt, if the hardware lock is interrupted, as long as the electronic device continues to maintain the lock interrupt state, if If the software lock is interrupted, the electronic device needs to exit the interrupt request processing at the kernel layer and restore the interrupted thread. Check whether the state of the software lock interrupt is the lock interrupt status. If not, the software lock interrupt status needs to be updated. Interrupt state and keep.

Another point that needs additional explanation is that since the state of the software lock interrupt is the lock interrupt state, The kernel layer in the child device still receives interrupt requests from the interrupt source and saves these interrupt requests in the kernel layer's interrupt request queue. Therefore, after step 805f, if the electronic device changes the state of the software lock interrupt from the lock interrupt state to the unlock interrupt state, it is also necessary to detect whether there is another interrupt request in the interrupt request queue, and if there are other interrupt requests, the electronic device re-executes The interrupt response process shown in step 804 and step 805 in the above embodiment.

In summary, the task processing method provided in this embodiment performs interrupt processing by running an operating system in a thread through an operating system in a thread; and solves the problem that the interrupt processing process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation. The delay of the interrupt processing process is large, which affects the real-time problem of the task processing process; the interrupt processing is completed directly in the user layer, and it is not necessary to switch to the kernel layer for processing, reducing the time-consuming processing of the interrupt processing and improving The real-time nature of the task processing.

At the same time, since the interrupt response in the background technology is performed by the kernel layer, the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.

The task processing method provided by the embodiment further stores the interrupt request in the shared storage area through the kernel layer, and after the thread of the user layer is restored, acquires the interrupt request from the shared storage area, so that the kernel layer can report the interrupt request to the thread. The interrupt request is processed by the operating system in the thread.

The task processing method provided in this embodiment further replaces the first user state instruction position in the core stack with the start instruction position of the operating system interrupt processing program, so that the user layer thread is restored, and the entry is not interrupted. The first user state instruction position continues to run, but forcibly jumps to the interrupt handler in the operating system, and enters the interrupt response process without delay, realizing the effect of fast reporting and response of the interrupt request.

The task processing method provided in this embodiment also completes the interrupt response independently by the interrupt processing program of the operating system, and does not need to switch to the kernel layer for processing in the process, and the time required to complete the complete interrupt response process is very small. Effect.

Please refer to FIG. 11 , which is a flowchart of a method for processing a task according to still another embodiment of the present invention. This embodiment is exemplified by applying the task processing method to the electronic device shown in FIG. 6A or FIG. 6B. The method includes:

Step 1101, running at least one thread in the user layer;

The electronic device runs at least one thread in the user layer. This thread can be a real-time thread for processing real-time tasks or a normal thread for handling common tasks.

Step 1102: Run an operating system in a thread, where the operating system is used to process a task;

Step 1103: During the processing of the task, the task scheduling is performed by the operating system in the thread.

Different from the background art, the electronic device does not perform task scheduling on the tasks in the thread through the kernel layer, but performs task scheduling on the tasks in the thread by the operating system in the thread. The interrupt response logic of the kernel layer is not needed, and it is not affected by the task scheduling of the kernel layer, and the task scheduling is completed independently. The scheduling policy at the time of scheduling can adopt an existing task scheduling policy.

Common task schedules include the following two types:

The first one takes the example of switching from the first task to the second task. This step includes the following sub-steps, as shown in FIG. 12:

1103A, when switching from the first task to the second task, the electronic device saves the running scene of the interrupted first task by using an operating system in the thread, where the running field of the first task includes the register information, the third user state instruction position, and Lock interrupt information for the first task;

The operating system in the thread provided by this embodiment has the function of independently completing task scheduling. A task scheduler can be implemented in the thread's operating system, and the task scheduler is used to perform task scheduling for each task processed in the operating system.

Alternatively, switching from the first task to the second task may be triggered by an interrupt request or may be actively triggered by a task scheduler in the operating system.

For example, if the second task needs to be delayed by n milliseconds, the second task will enable one timer after the suspension, and the timer generates an interrupt request after the delay of n milliseconds, and the interrupt request is used to request that the interrupt is being processed. The first task is run, and the first task that is running is switched to the second task to resume the running of the second task.

For another example, the task scheduler may switch the running first task to the second task when the priority of the second task reaches a preset condition.

At this time, the electronic device saves the running site of the interrupted first task by using a task scheduler in the operating system, where the running site of the first task includes the register information, the third user state command position, and the first The lock of the task is interrupted.

The lock interrupt information means that because task A may be interrupted by task B, task B may be interrupted by task C, and interrupt nesting is formed at this time. Lock interrupt information refers to the level of an interrupt request in interrupt nesting. .

1103B, the electronic device acquires a running site of the second task by using an operating system in the thread, where the running site of the second task includes the register information, the fourth user state command position, and the lock interruption information of the second task;

The electronic device can acquire the running site of the second task through the task scheduler in the operating system.

1103C: The electronic device restores the second task and processes according to the operating site of the second task by using an operating system in the thread.

The electronic device can restore the second task according to the register information in the running field and the fourth user state command position by the task scheduler in the operating system.

When the second task is resumed, the electronic device switches the unlocking interrupt state according to the lock interrupt information of the second task by the task scheduler, and then processes the second task.

Secondly, after an interrupt processing, the electronic device is scheduled to a third task that needs priority scheduling, and the third task may be a new task. This step includes the following sub-steps, as shown in Figure 13:

1103a, at the end of an interrupt processing, the electronic device detects, by the operating system in the thread, whether there is a third task that needs to be scheduled preferentially;

The electronic device detects whether there is a third task requiring priority scheduling through a task scheduler in the operating system.

For example, if the network card device receives a new data packet, an interrupt request is also generated at this time, and the interrupt request is used to request processing of the data packet, and the interrupt request is generated to be processed for processing the data packet. The third task.

1103b, if there is a third task, the electronic device acquires a running site of the third task by using an operating system in the thread, where the running site of the third task includes the register information, the fifth user state command location, and the lock interruption information of the third task;

The electronic device acquires the running site of the third task through the task scheduler in the operating system.

1103c. The electronic device restores the third task and processes according to the operating site of the third task by using an operating system in the thread.

The electronic device can resume the third task according to the register information according to the operation site and the fifth user state command position.

When the third task is resumed, the electronic device switches the lock interruption state in the kernel layer to the unlock interruption state according to the lock interruption information of the third task by the task scheduler, and then processes the third task.

In summary, the task processing method provided in this embodiment performs task scheduling by running an operating system in a thread through an operating system in a thread; and the task scheduling process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation. The delay of the task scheduling process is large, which affects the real-time problem of the task processing process. It achieves the task scheduling directly in the user layer, does not need to switch to the kernel layer multiple times, reduces the time-consuming task scheduling, and improves the task. The effect of real-time processing.

At the same time, since the task scheduling in the background technology is performed by the kernel layer, the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.

It can be understood that the task processing apparatus provided in any of the embodiments of FIG. 2 or FIG. 4 or the electronic apparatus provided in the embodiment of FIG. 5A or FIG. 5B can perform the task processing method provided in any of the embodiments of FIG. 7 to FIG. The specific functions and working procedures of the various units or modules of the device embodiments may be referred to the related parts of the method embodiments, and the descriptions of the various embodiments provided by the present invention may also be referred to each other.

A person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium. The storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalents, improvements, etc., which are within the spirit and scope of the present invention, should be included in the protection of the present invention. Within the scope.

Claims

A task processing device, characterized in that the device comprises:

a first running module, configured to run at least one thread at a user layer;

a second running module, configured to run an operating system in the thread, where the operating system is used to process a task;

a task processing module, configured to perform an interrupt response and/or task scheduling by the operating system in the thread during processing of the task.
The device according to claim 1, wherein the task processing module comprises:

a request receiving unit, configured to receive an interrupt request of an interrupt source through a kernel layer;

a requesting transmission unit, configured to transmit, by the kernel layer, the interrupt request to an operating system of a corresponding thread in the user layer;

And a request response unit, configured to perform an interrupt response to the interrupt request by an interrupt processing program of an operating system of a corresponding thread in the user layer.
The device according to claim 2, wherein the request transmission unit comprises:

a first saving subunit, configured to save an operating site of the interrupted thread in a core stack of the kernel layer, where the running site includes a first user state instruction location;

a transfer subunit, configured to transfer the first user state instruction location from a first storage location in the core stack to a second storage location in a shared storage area, and store the interrupt request to the a third storage location in the shared storage area, where the shared storage area is a storage area accessible by both the kernel layer and the user layer;

An interrupt storage subunit, configured to store, in a first storage location in the core stack, a start instruction location of an interrupt handler in the operating system of the interrupted thread;

The subunit is exited for exiting the kernel layer response to the interrupt request.
The device according to claim 3, wherein the request response unit comprises:

a first recovery subunit, configured to: when recovering the interrupted thread, read a start instruction position of an interrupt handler of the operating system from a first storage location of the core stack;

a second saving subunit, configured to save a running site of the interrupted task in a user stack of the thread, The operation site includes a second user state instruction location;

a stack switching subunit, configured to switch from the user stack to an interrupt stack;

An interrupt response subunit, configured to read the interrupt request from the shared memory area, and perform an interrupt response based on the interrupt stack;

And a second recovery subunit, configured to resume the interrupted task or another task that needs to be scheduled after the end of the interrupt response.
The device according to claim 4, wherein the request response unit further comprises:

a replacement subunit, configured to replace the second user state instruction location saved in the user stack with the first user state instruction location saved in a second storage location of the shared storage area;

The second recovery subunit is configured to recover the interrupted task by using the running site saved in the user stack.
The device according to any one of claims 1 to 5, wherein the task processing module comprises:

a task switching unit, configured to save, by the operating system, an operation site of the interrupted first task when switching from the first task to the second task, where the operation site of the first task includes register information, and a third a user state instruction location and a lock interruption information of the first task;

a first acquiring unit, configured to acquire, by using the operating system, an operating site of the second task, where the operating site of the second task includes register information, a fourth user state command location, and a lock interruption information of the second task ;

The first recovery unit recovers the second task and processes according to the operating site of the second task by the operating system.
The device according to any one of claims 1 to 5, wherein the task processing module comprises:

a task detecting unit, configured to detect, by the operating system, whether there is a third task that needs to be preferentially scheduled when an interrupt response ends;

a second obtaining unit, configured to acquire, by the operating system, an operation site of the third task when the third task exists, where the running site of the third task includes a register information, a fifth user state instruction location, and The lock interruption information of the third task;

And a second recovery unit, configured to recover the third task and process according to the operating site of the third task by using the operating system.
An electronic device, comprising: a processor and a memory;

The memory is configured to store one or more instructions for implementing a task processing method;

The method includes:

Running at least one thread at the user level;

Running an operating system in the thread, the operating system for processing a task;

Interrupting response and/or task scheduling by the operating system in the thread during processing of the task;

The processor is operative to execute the instructions.
The electronic device of claim 8, wherein the memory further stores instructions for performing the following operations:

Receiving an interrupt request of an interrupt source through a kernel layer;

Transmitting the interrupt request to an operating system of a corresponding thread in the user layer by the kernel layer;

Interrupting the interrupt request by an interrupt processing program of an operating system of a corresponding thread in the user layer;

The processor is also operative to execute the instructions.
The electronic device of claim 9, wherein the memory further stores instructions for performing the following operations:

Saving an operation site of the interrupted thread in a core stack of the kernel layer, the operation site including a first user state instruction location;

Transferring the first user state instruction location from a first storage location in the core stack to a second storage location in a shared storage area for storage, and storing the interrupt request in the shared storage area Three storage locations;

Storing a start instruction location of an interrupt handler in the operating system of the interrupted thread in a first storage location in the core stack;

Exiting the kernel layer's response to the interrupt request;

The processor is also operative to execute the instructions.
The electronic device of claim 10, wherein the memory further stores instructions for performing the following operations:

Reading the initial instruction location of the interrupt handler of the operating system from the first storage location of the core stack when the interrupted thread is restored;

A user site of the thread saves an operation site of the interrupted task, the operation site including a second user state instruction location;

Switching from the user stack to an interrupt stack;

Reading the interrupt request from the shared storage area, and performing an interrupt response based on the interrupt stack;

After the interrupt response ends, recovering the interrupted task or another task requiring priority scheduling;

The processor is also operative to execute the instructions.
The electronic device according to claim 11, characterized by further storing instructions for performing the following operations:

Replacing the second user state instruction location saved in the user stack with the first user state instruction location saved in the second storage location of the shared storage area;

Recovering the interrupted task by the running site saved in the user stack;

The processor is also operative to execute the instructions.
The electronic device according to any one of claims 8 to 12, characterized by further storing instructions for performing the following operations:

When the first task is switched to the second task, the operating site of the interrupted first task is saved by the operating system, and the running site of the first task includes register information, a third user state command location, and a location The lock interrupt information of the first task;

Obtaining, by the operating system, an operation site of the second task, where the operation site of the second task includes register information, a fourth user state instruction location, and lock interruption information of the second task;

Recovering and processing the second task according to the operating site of the second task by the operating system;

The processor is also operative to execute the instructions.
The electronic device according to any one of claims 8 to 12, characterized by further storing instructions for performing the following operations:

At the end of an interrupt response, the operating system detects whether there is a third task requiring priority scheduling;

When the third task exists, the operating site of the third task is acquired by the operating system, and the running site of the third task includes register information, a fifth user state command location, and a lock of the third task. Interrupt information;

Recovering and processing the third task according to the operating site of the third task by the operating system;

The processor is also operative to execute the instructions.
A task processing method, characterized in that the method comprises:

Running at least one thread at the user level;

Running an operating system in the thread, the operating system for processing a task;

In the process of processing the task, an interrupt response and/or task scheduling is performed by the operating system in the thread.
The method according to claim 15, wherein in the process of processing the task, the interrupt response is performed by the operating system in the thread, including:

Receiving an interrupt request of an interrupt source through a kernel layer;

Transmitting the interrupt request to an operating system of a corresponding thread in the user layer by the kernel layer;

The interrupt request is interrupted by an interrupt handler of an operating system of a corresponding thread in the user layer.
The method according to claim 16, wherein the transmitting, by the kernel layer, the interrupt request to the operating system of the corresponding one of the user layers comprises:

Saving an operation site of the interrupted thread in a core stack of the kernel layer, the operation site including a first user state instruction location;

Transferring the first user state instruction location from a first storage location in the core stack to a second storage location in a shared storage area for storage, and storing the interrupt request in the shared storage area a storage location, where the shared storage area is a storage area accessible by both the kernel layer and the user layer;

Storing a start instruction location of an interrupt handler in the operating system of the interrupted thread in a first storage location in the core stack;

Exiting the kernel layer's response to the interrupt request.
The method of claim 17, wherein the interrupting the interrupt request by the interrupt handler in the operating system comprises:

Reading the initial instruction location of the interrupt handler of the operating system from the first storage location of the core stack when the interrupted thread is restored;

A user site of the thread saves an operation site of the interrupted task, the operation site including a second user state instruction location;

Switching from the user stack to an interrupt stack;

Reading the interrupt request from the shared storage area, and performing an interrupt response based on the interrupt stack;

After the interrupt response ends, the interrupted task or another task requiring prioritization is resumed.
The method according to claim 18, wherein before the switching from the user stack to the interrupt stack, the method further comprises:

Replacing the second user state instruction location saved in the user stack with the first user state instruction location saved in the second storage location of the shared storage area;

Recovering the interrupted task after the interrupt response ends, including:

The interrupted task is resumed by the running site saved in the user stack.
The method according to any one of claims 15 to 19, wherein in the performing the task, the task scheduling is performed by the operating system in the thread, including:

When the first task is switched to the second task, the operating site of the interrupted first task is saved by the operating system, and the running site of the first task includes register information, a third user state command location, and a location The lock interrupt information of the first task;

Obtaining, by the operating system, an operation site of the second task, where the operation site of the second task includes register information, a fourth user state instruction location, and lock interruption information of the second task;

And recovering, by the operating system, the second task according to the running site of the second task and processing.
The method according to any one of claims 15 to 19, wherein in the performing the task, the task scheduling is performed by the operating system in the thread, including:

At the end of an interrupt response, the operating system detects whether there is a third task requiring priority scheduling;

When the third task exists, the operating site of the third task is acquired by the operating system, and the running site of the third task includes register information, a fifth user state command location, and a lock of the third task. Interrupt information;

And recovering, by the operating system, the third task according to an operation site of the third task and processing.