WO2016033755A1 - Procédé et appareil de gestion de tâche et dispositif électronique - Google Patents

Procédé et appareil de gestion de tâche et dispositif électronique Download PDF

Info

Publication number
WO2016033755A1
WO2016033755A1 PCT/CN2014/085834 CN2014085834W WO2016033755A1 WO 2016033755 A1 WO2016033755 A1 WO 2016033755A1 CN 2014085834 W CN2014085834 W CN 2014085834W WO 2016033755 A1 WO2016033755 A1 WO 2016033755A1
Authority
WO
WIPO (PCT)
Prior art keywords
task
interrupt
operating system
thread
user
Prior art date
Application number
PCT/CN2014/085834
Other languages
English (en)
Chinese (zh)
Inventor
徐胜新
崔爱国
祝建华
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2014/085834 priority Critical patent/WO2016033755A1/fr
Priority to CN201480034730.1A priority patent/CN105579963B/zh
Publication of WO2016033755A1 publication Critical patent/WO2016033755A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt

Definitions

  • the present invention relates to the field of operating systems, and in particular, to a task processing apparatus, an electronic device, and a method.
  • the Linux operating system is increasingly being used to implement processing of high real-time services.
  • FIG. 1 shows a schematic diagram of an architecture using a Linux operating system to process high real-time services.
  • the architecture includes a hardware layer 120, a Linux kernel layer 140, and a user layer 160.
  • User layer 160 can run at least one thread 162, each thread 162 for processing tasks.
  • the task scheduling process and interrupt response process for each thread 162 is primarily implemented by the Linux kernel layer 140.
  • the inventors have found that the prior art has at least the following problems: since the task scheduling process and the interrupt response process are mainly implemented by the Linux kernel layer 140, multiple switching is required in a single task scheduling process or an interrupt response process. Processing in the Linux kernel layer 140 may result in a large delay in a single task scheduling process or an interrupt response process, which affects the real-time nature of the task processing process.
  • Embodiments of the present invention provide a task processing apparatus, method, and electronic device. The technical solution is as follows:
  • a task processing apparatus comprising:
  • a first running module configured to run at least one thread at a user layer
  • a second running module configured to run an operating system in the thread, where the operating system is used to process a task
  • a task processing module configured to perform an interrupt response and/or task scheduling by the operating system in the thread during processing of the task.
  • the task processing module includes:
  • a request receiving unit configured to receive an interrupt request of an interrupt source through a kernel layer
  • a requesting transmission unit configured to transmit, by the kernel layer, the interrupt request to an operating system of a corresponding thread in the user layer;
  • a request response unit configured to perform an interrupt response to the interrupt request by an interrupt processing program of an operating system of a corresponding thread in the user layer.
  • the request transmission unit includes:
  • a first saving subunit configured to save an operating site of the interrupted thread in a core stack of the kernel layer, where the running site includes a first user state instruction location;
  • a transfer subunit configured to transfer the first user state instruction location from a first storage location in the core stack to a second storage location in a shared storage area, and store the interrupt request to the a third storage location in the shared storage area, where the shared storage area is a storage area accessible by both the kernel layer and the user layer;
  • An interrupt storage subunit configured to store, in a first storage location in the core stack, a start instruction location of an interrupt handler in the operating system of the interrupted thread;
  • the subunit is exited for exiting the kernel layer response to the interrupt request.
  • the request response unit includes:
  • a first recovery subunit configured to: when recovering the interrupted thread, read a start instruction position of an interrupt handler of the operating system from a first storage location of the core stack;
  • a second saving subunit configured to save an operation site of the interrupted task in a user stack of the thread, where the running site includes a second user state instruction location;
  • a stack switching subunit configured to switch from the user stack to an interrupt stack
  • An interrupt response subunit configured to read the interrupt request from the shared memory area, and perform an interrupt response based on the interrupt stack
  • a second recovery subunit configured to resume the interrupted task or another task that needs to be scheduled after the end of the interrupt response.
  • the request response unit further includes:
  • a replacement subunit configured to replace the second user state instruction location saved in the user stack The first user state instruction location saved in the second storage location of the shared storage area
  • the second recovery subunit is configured to recover the interrupted task by using the running site saved in the user stack.
  • the task processing module includes:
  • a task switching unit configured to save, by the operating system, an operation site of the interrupted first task when switching from the first task to the second task, where the operation site of the first task includes register information, and a third a user state instruction location and a lock interruption information of the first task;
  • a first acquiring unit configured to acquire, by using the operating system, an operating site of the second task, where the operating site of the second task includes register information, a fourth user state command location, and a lock interruption information of the second task ;
  • the first recovery unit recovers the second task and processes according to the operating site of the second task by the operating system.
  • the task processing module includes:
  • a task detecting unit configured to detect, by the operating system, whether there is a third task that needs to be preferentially scheduled when an interrupt response ends;
  • a second obtaining unit configured to acquire, by the operating system, an operation site of the third task when the third task exists, where the running site of the third task includes a register information, a fifth user state instruction location, and The lock interruption information of the third task;
  • a second recovery unit configured to recover the third task and process according to the operating site of the third task by using the operating system.
  • an electronic device comprising: a processor and a memory;
  • the memory is configured to store one or more instructions for implementing a task processing method
  • the method order includes:
  • the processor is operative to execute the instructions.
  • instructions for performing the following operations are also stored:
  • the processor is operative to execute the instructions.
  • instructions for performing the following operations are also stored:
  • the processor is operative to execute the instructions.
  • the memory further stores instructions for performing the following operations:
  • a user site of the thread saves an operation site of the interrupted task, the operation site including a second user state instruction location;
  • the processor is operative to execute the instructions.
  • an instruction for performing the following operations is also stored:
  • the processor is operative to execute the instructions.
  • an instruction for performing the following operations is also stored:
  • the operating site of the interrupted first task is saved by the operating system, and the running site of the first task includes register information, a third user state command location, and a location The lock interrupt information of the first task;
  • the processor is also operative to execute the instructions.
  • an instruction for performing the following operations is also stored:
  • the operating system detects whether there is a third task requiring priority scheduling
  • the operating site of the third task is acquired by the operating system, and the running site of the third task includes register information, a fifth user state command location, and a lock of the third task.
  • Interrupt information
  • the processor is also operative to execute the instructions.
  • a task processing method comprising:
  • an interrupt response and/or task scheduling is performed by the operating system in the thread.
  • performing an interrupt response by using the operating system in the thread including:
  • the interrupt request is interrupted by an interrupt handler of an operating system of a corresponding thread in the user layer.
  • the transmitting, by the kernel layer, the interrupt request to the corresponding one of the user layers Operating system including:
  • the interrupt request is interrupted by an interrupt processing program in the operating system, including:
  • a user site of the thread saves an operation site of the interrupted task, the operation site including a second user state instruction location;
  • the method before the switching from the user stack to the interrupt stack, the method further includes:
  • Recovering the interrupted task after the interrupt response ends including:
  • the interrupted task is resumed by the running site saved in the user stack.
  • the operating site of the interrupted first task is saved by the operating system, and the running site of the first task includes register information, a third user state command location, and a location The lock interrupt information of the first task;
  • performing task scheduling by using the operating system in the thread including:
  • the operating system detects whether there is a third task requiring priority scheduling
  • the operation site of the third task includes register information, a fifth user state instruction location, and lock interruption information of the third task;
  • FIG. 1 is a schematic diagram of an architecture using a Linux operating system to process high real-time services
  • FIG. 2 is a block diagram showing the structure of a task processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a block diagram showing the structure of a task processing apparatus according to another embodiment of the present invention.
  • FIG. 3B is a block diagram showing the structure of the request transmission unit provided in FIG. 3A;
  • FIG. 3C is a structural block diagram of the request response unit provided in FIG. 3A; FIG.
  • FIG. 4 is a block diagram showing the structure of a task processing apparatus according to still another embodiment of the present invention.
  • FIG. 5 is a block diagram showing the structure of an electronic device according to an embodiment of the present invention.
  • FIG. 5B is a structural block diagram of an electronic device according to another embodiment of the present invention.
  • FIG. 6A and FIG. 6B are schematic diagrams showing the structure of an electronic device according to the task processing method provided by the embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for processing a task according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of a method for processing a task according to another embodiment of the present invention.
  • FIG. 9 is a flow chart showing the sub-steps of the task processing method provided in the embodiment shown in FIG. 8;
  • FIG. 10 is a flow chart of sub-steps of the task processing method provided in the embodiment shown in FIG.
  • FIG. 11 is a flowchart of a method for processing a task according to still another embodiment of the present invention.
  • Figure 12 is a flow chart showing the sub-steps of the task processing method provided in the embodiment shown in Figure 11;
  • FIG. 13 is a flow chart showing the sub-steps of the task processing method provided in the embodiment shown in FIG.
  • the hardware layer is the hardware foundation in the electronic device. It usually includes a processor (Central: Central Processing Unit, CPU) and memory.
  • the processor can be a single core processor or a multi-core processor.
  • the electronic device may be an electronic device that has certain requirements for real-time processing of tasks, such as a base station device, a transmission device, and an industrial robot.
  • the base station equipment can be a base transceiver station (English: Base Transmitter Station, abbreviation: BTS); in the third generation (English: 3rd- Generation, abbreviation: 3G) In mobile communication technology, the base station equipment can be Node B (English: Node Base station, abbreviation: Node B); in the fourth generation (English: the 4Generation, abbreviation: 4G) mobile communication technology, the base station The device may be an evolved Node B (English: Evolved Node Base station, abbreviation: eNB).
  • Kernel and User Layers The kernel layer is the operating system kernel, virtual storage space, and the layer that drives the application to run; the user layer is the layer in which normal applications run.
  • Interrupt refers to any unusual or unexpected urgent need to be processed in the system during the execution of the computer, so that the processor temporarily interrupts the currently executing program and then goes to execute the corresponding event handler. After the processing is completed, Returns the process of continuing execution or scheduling a new process execution.
  • the event that caused the interrupt to occur is called the interrupt source.
  • the request interrupt processing signal sent by the interrupt source to the processor is called an interrupt request.
  • the process by which a processor processes an interrupt request is called an interrupt response.
  • Core stack The stack used by the operating system kernel.
  • Each thread has a user stack used by itself, which can be a real-time thread or a normal thread.
  • FIG. 2 is a structural block diagram of a task processing apparatus according to an embodiment of the present invention.
  • the task processing device can be implemented as an electronic device by software, hardware, or a combination of both All or part.
  • the task processing device includes a first running module 220, a second running module 240, and a task processing module 260.
  • the first running module 220 is configured to run at least one thread at the user layer.
  • the second running module 240 is configured to run an operating system in the thread, where the operating system is used to process the task.
  • the operating system needs to have the ability to independently perform interrupt response and/or task scheduling. Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads.
  • the type of the above operating system is not particularly limited in the embodiment of the present invention.
  • Tasks are generic tasks that the operating system can handle.
  • the task may be a task of issuing a scheduling instruction, a task of allocating a channel resource, a task of processing an access request, and the like.
  • the task processing module 260 is configured to perform an interrupt response and/or task scheduling by an operating system in the thread during the processing of the task.
  • the task processing apparatus performs interrupt response and/or task scheduling through an operating system in a thread; and solves the interrupt response process and the task scheduling process, which requires multiple switching to the Linux kernel layer for processing.
  • the delay of the single interrupt response process and the task scheduling process is large, which affects the real-time behavior of the task processing; the interrupt response and/or task scheduling are directly completed in the user layer, and it is not necessary to switch to the kernel layer multiple times. Processing, reducing the time consuming of interrupt response and/or task scheduling, improves the real-time effect of task processing.
  • the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • FIG. 3A is a structural block diagram of a task processing apparatus according to another embodiment of the present invention.
  • the task processing device can be implemented as all or part of an electronic device by software, hardware, or a combination of both.
  • the task processing apparatus includes a first execution module 220 for running at least one thread at the user layer.
  • the first running module 220 is configured to run at least one thread at the user layer.
  • the second running module 240 is configured to run an operating system in a thread running by the first running module 220, where the operating system is used to process a task.
  • the task processing module 260 is configured to perform an interrupt response by the operating system running in the thread by the second running module 240 during the processing of the task.
  • the task processing module 260 includes:
  • the request receiving unit 261 is configured to receive an interrupt request of the interrupt source through the kernel layer.
  • the request transmission unit 262 is configured to transmit, by the kernel layer, the interrupt request received by the request receiving unit 261 to the operating system of the corresponding thread in the user layer run by the second running module 240.
  • the request response unit 263 is configured to perform an interrupt response to the interrupt request received by the request transmission unit 262 by an interrupt processing program of an operating system of a corresponding thread in the user layer.
  • the request transmission unit 262 may include:
  • the first save subunit 262a is configured to save an operation site of the interrupted thread in a core stack of the kernel layer, where the run site includes a first user state instruction location.
  • the transfer subunit 262b is configured to transfer the first user state instruction location saved by the first save subunit 262a from the first storage location in the core stack to the second storage location in the shared storage area for storage, and the request receiving unit
  • the received interrupt request is stored in a third storage location in the shared storage area, and the shared storage area is a storage area accessible by both the kernel layer and the user layer.
  • the interrupt storage sub-unit 262c is configured to transfer the first user state instruction position from the first storage location in the core stack to the second storage location in the shared storage area after the transfer sub-unit 262b is stored, in the core stack
  • the starting instruction location of the interrupt handler in the operating system that stores the interrupted thread in a storage location.
  • the exit sub-unit 262d is configured to exit the kernel layer response to the interrupt request after the interrupt storage sub-unit 262c stores the start instruction position in the first storage location in the core stack.
  • the request response unit 263 may include:
  • the first recovery subunit 263a is configured to: after the exit subunit 262d exits the kernel layer response to the interrupt request, read the interrupt handler of the operating system from the first storage location of the core stack when restoring the interrupted thread Start command position.
  • the second save subunit 263b the user stack of the thread for recovery at the first recovery subunit 263a saves the run site of the interrupted task, the run site including the second user state command location.
  • the stack switching sub-unit 263c is configured to switch from the user stack used by the second saving sub-unit 263b to the interrupt stack.
  • the interrupt response sub-unit 263d is configured to read an interrupt request from the shared memory area and perform an interrupt response based on the interrupt stack to which the stack switching sub-unit 263c is switched.
  • the second recovery sub-unit 263e is configured to resume the interrupted task or another task requiring priority scheduling after the interrupt response sub-unit 263d interrupts the response.
  • the request response unit 263 may further include:
  • a replacement subunit 263f configured to replace the second user state instruction location saved in the user stack by the second save subunit 263b with the first user state instruction location saved in the second storage location of the shared storage area;
  • the second recovery subunit 263e is configured to recover the interrupted task by using the running scene saved in the user stack, the running scene is saved by the second saving subunit 263b, and the second user state instruction is replaced by the replacing subunit 263f.
  • the position is replaced with the first user mode command position.
  • the task processing apparatus performs interrupt processing by using an operating system in a thread by running an operating system in a thread; and the interrupt processing process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation.
  • the delay of the interrupt processing process is large, which affects the real-time problem of the task processing process; the interrupt processing is completed directly in the user layer, and it is not necessary to switch to the kernel layer for processing, reducing the time-consuming processing of the interrupt processing and improving The real-time nature of the task processing.
  • the task processing apparatus provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • the task processing apparatus provided by the embodiment further stores the interrupt request in the shared storage area through the kernel layer, and after the thread of the user layer is restored, acquires the interrupt request from the shared storage area, so that the kernel layer can report the interrupt request to the thread.
  • the interrupt request is processed by the operating system in the thread.
  • the task processing apparatus provided in this embodiment further replaces the first user state instruction position in the core stack with the start instruction position of the interrupt processing program of the operating system, so that the thread of the user layer is restored, and the entry is not interrupted.
  • the first user state instruction position continues to run, but forcibly jumps to the interrupt handler in the operating system, and enters the interrupt response process without delay, realizing the effect of fast reporting and response of the interrupt request.
  • the task processing apparatus provided in this embodiment also independently completes the interrupt response by the interrupt processing program of the operating system, and does not need to switch to the kernel layer for processing in the process, and the time required to complete the complete interrupt response process is very small. Effect.
  • FIG. 4 is a structural block diagram of a task processing apparatus according to another embodiment of the present invention.
  • the task processing device can be implemented as all or part of an electronic device by software, hardware, or a combination of both.
  • the task processing device can include:
  • the first running module 220 is configured to run at least one thread at the user layer.
  • a second running module 240 configured to run an operating system in a thread running by the first running module 220, This operating system is used to process tasks.
  • the task processing module 260 is configured to perform task scheduling by the operating system running in the thread by the second running module 240 during the processing of the task.
  • the task processing module 260 may include:
  • the task switching unit 264 is configured to: when the first task is switched to the second task, the operating system running by the second running module 240 saves the running site of the interrupted first task, where the running site of the first task includes register information, The third user mode instruction location and the lock interruption information of the first task.
  • the first obtaining unit 265 is configured to obtain, after the task switching unit 264 saves the running site of the interrupted first task, the operating site of the second task by using the operating system, where the running site of the second task includes the register information and the fourth user state. The command position and the lock interrupt information of the second task.
  • the first recovery unit 266 restores the second task and processes it according to the operating site of the second task saved by the first obtaining unit 265 by the operating system.
  • the task processing module 260 may further include:
  • the task detecting unit 267 is configured to detect, by the operating system running by the second running module 240, whether there is a third task that needs to be preferentially scheduled when the interrupt response ends.
  • the second obtaining unit 268 is configured to acquire, by the operating system, the running site of the third task when the task detecting unit 267 detects that the third task exists, where the running site of the third task includes the register information, the fifth user state command position, and the Three task lock interrupt information.
  • the second recovery unit 269 is configured to recover and process the third task according to the operating site of the third task acquired by the second obtaining unit 268 by the operating system.
  • the task processing apparatus performs task scheduling by running an operating system in a thread through an operating system in a thread; and solves the problem that the task scheduling process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation.
  • the delay of the task scheduling process is large, which affects the real-time problem of the task processing process. It achieves the task scheduling directly in the user layer, does not need to switch to the kernel layer multiple times, reduces the time-consuming task scheduling, and improves the task. The effect of real-time processing.
  • the task scheduling in the background technology is performed by the kernel layer, the load of the kernel layer is high, and the task processing apparatus provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • FIG. 5A is a structural block diagram of an electronic device according to an embodiment of the present invention.
  • the electronic device 500 includes a processor 520 and a memory 540.
  • the processor 520 and the memory 540 can be connected by a communication bus.
  • the memory 540 can be an instruction memory, a memory, a register, and the like.
  • the memory 540 is configured to store one or more instructions for implementing a task processing method, the instructions including:
  • Interrupt response and/or task scheduling is performed by the operating system in the thread during the processing of the task.
  • the processor 520 is configured to execute the above instructions.
  • each thread can run an operating system, which is used to process tasks.
  • the operating system needs to have the ability to independently perform interrupt response and/or task scheduling.
  • Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads.
  • the type of the above operating system is not particularly limited in the embodiment of the present invention.
  • Tasks are generic tasks that the operating system can handle.
  • the task may be a task of issuing a scheduling instruction, a task of allocating a channel resource, a task of processing an access request, and the like.
  • the electronic device performs interrupt response and/or task scheduling through an operating system in a thread; the interrupt response process and the task scheduling process need to be switched to the Linux kernel layer for processing, resulting in processing.
  • the delay of the single interrupt response process and the task scheduling process is large, which affects the real-time performance of the task processing process; the interrupt response and/or task scheduling are directly completed in the user layer, and it is not necessary to switch to the kernel layer multiple times. Processing, reducing the time consuming of interrupt response and/or task scheduling, improves the real-time effect of task processing.
  • the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • the memory 540 also stores instructions for performing the following operations:
  • the interrupt request of the interrupt source is received through the kernel layer.
  • the interrupt request is transmitted through the kernel layer to the operating system of the corresponding thread in the user layer.
  • the interrupt request is interrupted by an interrupt handler of an operating system of a corresponding thread in the user layer;
  • the processor 520 is also operative to execute the above instructions.
  • the processor 520 typically receives an interrupt request for the interrupt source via an interrupt line on the bus 560.
  • the memory 540 also stores instructions for performing the following operations:
  • the running site of the interrupted thread is saved in the core stack of the kernel layer, which includes the first user state instruction location.
  • the first user state instruction location is transferred from the first storage location in the core stack to the second storage location in the shared storage area for storage, and the interrupt request is stored to a third storage location in the shared storage area.
  • the processor 520 is also operative to execute the above instructions.
  • the core stack and the shared storage area may be a logical location in physical memory. This physical memory can belong to the memory 540.
  • the memory 540 also stores instructions for performing the following operations:
  • the user stack of the thread saves the running site of the interrupted task, the running site including the second user state command location;
  • the processor 520 is also operative to execute the above instructions.
  • the interrupt stack and the user stack corresponding to each thread may be a logical location in physical memory. This physical memory can belong to the memory 540.
  • the memory 540 also stores instructions for performing the following operations:
  • the processor 520 is also operative to execute the above instructions.
  • the electronic device provided by the embodiment further stores the interrupt request in the shared storage area through the kernel layer, and after the thread of the user layer recovers, acquires the interrupt request from the shared storage area, so that the kernel layer can request the interrupt. Reported to the thread, the interrupt request is processed by the operating system in the thread.
  • the electronic device provided by the embodiment further replaces the first user state instruction position in the core stack with the start instruction position of the interrupt handler of the operating system, so that the thread of the user layer is restored, and the entry is not interrupted.
  • the first user mode instruction position continues to run, but the forced jump to the operating system
  • the interrupt handler in the program directly enters the interrupt response process without delay, and achieves the effect of fast reporting and response of the interrupt request.
  • the electronic device provided in this embodiment also independently completes the interrupt response by the interrupt processing program of the operating system, and does not need to switch to the kernel layer for processing in the process, and the time required to complete the complete interrupt response process is very small. effect.
  • the memory 540 also stores instructions for performing the following operations:
  • the operating site of the interrupted first task is saved by the operating system, and the running site of the first task includes the register information, the third user state instruction position, and the lock interruption information of the first task. .
  • the processor 520 is also operative to execute the above instructions.
  • the memory 540 also stores instructions for performing the following operations:
  • the operating system detects whether there is a third task requiring priority scheduling.
  • the operating site of the third task is acquired by the operating system, and the running site of the third task includes the register information, the fifth user state instruction location, and the lock interruption information of the third task.
  • the third task is resumed and processed by the operating system according to the operation site of the third task;
  • the processor 520 is also operative to execute the above instructions.
  • the electronic device performs task scheduling through an operating system in a thread by running an operating system in a thread.
  • the task scheduling process needs to be switched to the Linux kernel layer multiple times, resulting in a single task.
  • the delay of the scheduling process is large, which affects the real-time problem of the task processing process. It achieves the task scheduling directly in the user layer, does not need to switch to the kernel layer multiple times, reduces the time-consuming task scheduling, and improves the task processing. The effect of real time.
  • the task scheduling in the background technology is performed by the kernel layer, the load of the kernel layer is high, and the task processing apparatus provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • the electronic device 500 may further include a communication bus 530 and transmitting power. Path 552 and receiving circuit 554 and the like.
  • the processor 520 controls the operation of the electronic device 500.
  • the processor 520 may also be referred to as a central processing unit (English: Central Processing Unit, abbreviated CPU).
  • Memory 540 can include read only memory and random access memory and provides instructions and data to processor 520.
  • a portion of the memory 540 may also include a non-volatile random access memory (Non-Volatile Random Access Memory, abbreviated as NVRAM).
  • transmit circuitry 552 and receive circuitry 554 can be coupled to transceiver 550.
  • communication bus 530 which may include, in addition to the data bus, a power bus, a control bus, interrupt lines, and other status signal buses. However, for clarity of description, various buses are labeled as communication bus 530 in the figure.
  • FIG. 6A is a schematic structural diagram of an electronic device involved in a task processing method according to an embodiment of the present invention.
  • the electronic device includes a hardware layer 620, a kernel layer 640, and a user layer 660.
  • the hardware layer 620 includes a processor, which may have a processor core 622, ie, the processor is a single core processor.
  • the kernel layer 640 includes an operating system kernel 642 and a driver application (not shown), which may be a Linux kernel.
  • the user layer 660 can run a thread (English: thread) 662, and each thread 662 runs an operating system (English: operation system, abbreviation: os), which can be a real-time thread and/or a user thread.
  • the operating system can monopolize the processor core 622 to form an Asymmetric Multi-Processing (abbreviation: AMP) structure.
  • FIG. 6B is a schematic structural diagram of still another electronic device involved in the task processing method provided by the embodiment of the present invention.
  • the electronic device includes a hardware layer 620, a kernel layer 640, and a user layer 660.
  • the hardware layer 620 includes a processor, which may include two or more processor cores 622 (illustrated by two processor cores in the figure), that is, a multi-core processor.
  • the kernel layer 640 includes an operating system kernel 642 and a driver application (not shown), which may be a Linux kernel.
  • User layer 660 can run with threads 662, each of which runs an operating system for processing tasks.
  • the thread 662 can be a real-time thread and/or a user thread.
  • Each operating system can monopolize a processor core 622 to form a Symmetric Multi-Processing (SMP) structure.
  • SMP Symmetric Multi-Processing
  • FIG. 7 is a flowchart of a method for processing a task according to an embodiment of the present invention. This embodiment is exemplified by applying the task processing method to the electronic device shown in FIG. 6A or FIG. 6B.
  • the method includes:
  • Step 701 running at least one thread in the user layer
  • Step 702 running an operating system in a thread, the operating system can be used to process a task
  • the operating system needs to have the ability to independently perform interrupt response and/or task scheduling. Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads.
  • the type of the above operating system is not particularly limited in the embodiment of the present invention.
  • the task is generally referred to as a task that the operating system can process.
  • the task may be a task of issuing a scheduling instruction, a task of allocating a channel resource, a task of processing an access request, and the like.
  • step 703 during the execution of the task, the interrupt response and/or task scheduling is performed by the operating system in the thread.
  • the task processing method performs interrupt response and/or task scheduling through an operating system in a thread; and the interrupt response process and the task scheduling process need to be switched to the Linux kernel layer for processing.
  • the delay of the single interrupt response process and the task scheduling process is large, which affects the real-time behavior of the task processing; the interrupt response and/or task scheduling are directly completed in the user layer, and it is not necessary to switch to the kernel layer multiple times. Processing, reducing the time consuming of interrupt response and/or task scheduling, improves the real-time effect of task processing.
  • the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • FIG. 8 illustrates a method flow of a task processing method according to another embodiment of the present invention. Cheng Tu. This embodiment is exemplified by applying the task processing method to the electronic device shown in FIG. 6A or FIG. 6B.
  • the method includes:
  • Step 801 running at least one thread in the user layer
  • the electronic device runs at least one thread in the user layer, which may be a real-time thread for processing a real-time task, or a normal thread for processing a normal task.
  • Step 802 running an operating system in a thread
  • the electronic device runs the operating system in a thread.
  • An operating system can be run separately in each thread.
  • the electronic device processes the task through the operating system.
  • the operating system needs to have the ability to independently perform interrupt response and/or task scheduling. Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads.
  • the type of the above operating system is not particularly limited in the embodiment of the present invention.
  • the task is generally referred to as a task that the operating system can process.
  • the task may be a task of issuing a scheduling instruction, a task of allocating a channel resource, a task of processing an access request, and the like.
  • Step 803 receiving an interrupt request of an interrupt source through a kernel layer
  • the electronic device receives an interrupt request of the interrupt source through the kernel layer, and the interrupt source may be an external hardware device, and the external hardware device may be a hardware device such as a mouse, a keyboard, a network card, or a graphics card.
  • the interrupt source may be an external hardware device
  • the external hardware device may be a hardware device such as a mouse, a keyboard, a network card, or a graphics card.
  • an interrupt fast processing program can be implemented in the kernel layer, the interrupt fast processing program is configured to receive an interrupt request in the kernel layer, and report the interrupt request to an operating system in the corresponding thread, so that the operating system in the thread Respond to the interrupt request.
  • the electronic device receives an interrupt request of the interrupt source through the interrupt fast processing program.
  • the electronic device After the interrupt fast processing program receives the interrupt request, the electronic device enters the lock interrupt state by interrupting the fast processing program.
  • the lock interrupt status is used to prevent the processor from receiving another interrupt request during the processing of an interrupt request, thereby causing the interrupt request processing to be interrupted.
  • the implementation of the lock interrupt status can be either a hardware lock interrupt or a software lock interrupt.
  • the kernel layer When the hardware lock is interrupted, the kernel layer will no longer receive other interrupt requests during the processing of this interrupt request.
  • the kernel layer still receives other interrupt requests during the processing of the interrupt request, but does not interrupt the processing of the interrupt request, but stores the subsequently received interrupt request in the kernel layer.
  • the interrupt request queue After the processing of the interrupt request is completed, other interrupt requests are sequentially processed from the interrupt request queue.
  • Step 804 the interrupt request is transmitted to the operating system of the corresponding thread in the user layer through the kernel layer;
  • step 804 can include the following sub-steps, as shown in FIG.
  • the electronic device saves an operation site of the interrupted thread in a core stack of the kernel layer, where the operation site includes a first user state instruction location;
  • the processor can only process one program fragment per unit time, for example, the processor is currently processing one thread, it cannot process other threads or program fragments belonging to the kernel layer.
  • the interrupt request interrupts the currently running thread of the processor, and the processor will respond to the interrupt request.
  • the electronic device saves the running site of the interrupted thread in the kernel stack of the kernel layer by interrupting the fast processing program, and the running site includes various register values of the thread when interrupted. The first user mode instruction location.
  • the first user state instruction location is also referred to as a first user state PC (English: program counter, Chinese: program counter) pointer, and the first user state PC pointer refers to the next instruction that the interrupted thread originally planned to run before the interruption. s position.
  • the processor can resume the operation of the thread by running a program instruction corresponding to the location of the first user state instruction.
  • the core stack is the stack in the kernel layer.
  • the electronic device saves the running site of the thread in the core stack by interrupting the fast processing program.
  • the first user state instruction location is stored in a first storage location of the core stack.
  • the electronic device moves the first user state instruction location from the first storage location in the core stack to the second storage location in the shared storage area for storage, and stores the interrupt request in a third storage location in the shared storage area.
  • the shared storage area is a storage area accessible by both the kernel layer and the user layer;
  • the electronic device can move the first user state instruction location from the first storage location in the core stack to the second storage location in the shared storage area by an interrupt fast handler in the kernel layer.
  • the electronic device stores a starting instruction position of an interrupt processing program of the operating system in a first storage location in the core stack.
  • the operating system in the thread provided by the embodiment of the present invention has the function of independently completing the interrupt response.
  • an interrupt handler can be implemented in the operating system of the thread, the interrupt handler being responsive to an interrupt request reported by the kernel layer to an operating system in the thread.
  • the electronic device stores the starting instruction position of the operating system interrupt processing program in the first storage location in the core stack through the interrupt fast processing program in the kernel layer, the operating system is the interrupted thread The operating system in .
  • the processor will read the interrupt handler of the operating system in the thread instead of the program instruction corresponding to the first user state instruction position.
  • the electronic device exits the processing of the interrupt request through the kernel layer.
  • the interrupt request is stored in the shared memory area waiting for the operating system in the thread in the user layer to process.
  • steps 804a to 804d are all implemented by the electronic device through the kernel layer.
  • step 805 the interrupt request is interrupted by an interrupt handler in the operating system.
  • Step 805 includes the following sub-steps, as shown in FIG. 10:
  • the electronic device reads the starting instruction position of the operating system interrupt processing program from the first storage location of the core stack when restoring the interrupted thread;
  • the first user state instruction location stored by the first storage location in the core stack is replaced with the starting instruction location of the operating system's interrupt handler.
  • the program instruction read by the processor according to the first storage location in the core stack is a program instruction corresponding to the interrupt processing program of the operating system in the thread. . Thereafter, the operating system in the thread interrupts the interrupt request through the interrupt handler.
  • the electronic device saves an operation site of the interrupted task in a thread user stack, and the operation site includes a second user state instruction location;
  • the operating system in the thread is a separate operating system, and the operating system in the thread is used to process the task.
  • the interrupt request interrupts the running task in the operating system, and the electronic device first saves the running site of the interrupted task in the user stack of the thread through the interrupt handler, and the running site includes the task.
  • the second user state instruction location is also referred to as a second user state PC pointer, and the second user state PC pointer is the pointer location corresponding to the next instruction that the interrupted task was scheduled to run before the interruption.
  • the second user state instruction location is typically the same as the first user state instruction location in step 804a. For example, if the thread in step 804a is interrupted when it is going to run to the A position in the program code corresponding to a certain task, then the program instruction position of the task to be interrupted in the thread in step 805b should also be the A position, and No change.
  • Each thread has its own user stack, and the electronic device runs the task through an interrupt handler.
  • the scene is saved in the user stack.
  • the second user mode instruction location is saved in a fourth storage location in the user stack.
  • Step 805c The electronic device replaces the second user state instruction location saved in the user stack with the first user state instruction location saved in the second storage location of the shared storage area;
  • the second user state instruction position stored in step 805b may save an error
  • the second user state instruction position of the saved error may be different from the first user state instruction position, in order to ensure the correctness of the task when the operation is resumed
  • the electronic device replaces the second user state instruction position saved in the user stack in step 805b with the first user state instruction position saved in the second storage location of the shared storage area by the interrupt processing program, that is, the step 804b is replaced.
  • the first user mode instruction location is transferred to the shared memory area.
  • Step 805d the electronic device switches from the user stack to the interrupt stack
  • the interrupt stack is used to store data during the interrupt response process.
  • Step 805e The electronic device reads the interrupt request from the shared storage area, and performs an interrupt response based on the interrupt stack.
  • the electronic device reads the interrupt request from the shared memory by the interrupt handler, and the interrupt request may specifically be an interrupt number, and then the interrupt handler interrupts the interrupt request based on the interrupt stack.
  • Step 805f After the interrupt response ends, the electronic device resumes the interrupted task or another task that needs to be scheduled preferentially;
  • the electronic device restores the interrupted task according to the running scene saved in the user stack through the interrupt handler.
  • the electronic device resumes another task that needs to be scheduled according to the running site saved in the user stack through the interrupt handler.
  • the electronic device may also change the lock interrupt status in the kernel layer to the unlock interrupt status through the interrupt handler when the interrupted task or the task requiring priority scheduling is resumed. When in the unlocked interrupt state, the electronic device can continue to receive the interrupt request.
  • step 804d the electronic device needs to remain in the lock interrupt state. Due to the difference between the hardware lock interrupt and the software lock interrupt, if the hardware lock is interrupted, as long as the electronic device continues to maintain the lock interrupt state, if If the software lock is interrupted, the electronic device needs to exit the interrupt request processing at the kernel layer and restore the interrupted thread. Check whether the state of the software lock interrupt is the lock interrupt status. If not, the software lock interrupt status needs to be updated. Interrupt state and keep.
  • step 805f if the electronic device changes the state of the software lock interrupt from the lock interrupt state to the unlock interrupt state, it is also necessary to detect whether there is another interrupt request in the interrupt request queue, and if there are other interrupt requests, the electronic device re-executes The interrupt response process shown in step 804 and step 805 in the above embodiment.
  • the task processing method performs interrupt processing by running an operating system in a thread through an operating system in a thread; and solves the problem that the interrupt processing process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation.
  • the delay of the interrupt processing process is large, which affects the real-time problem of the task processing process; the interrupt processing is completed directly in the user layer, and it is not necessary to switch to the kernel layer for processing, reducing the time-consuming processing of the interrupt processing and improving The real-time nature of the task processing.
  • the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • the task processing method provided by the embodiment further stores the interrupt request in the shared storage area through the kernel layer, and after the thread of the user layer is restored, acquires the interrupt request from the shared storage area, so that the kernel layer can report the interrupt request to the thread.
  • the interrupt request is processed by the operating system in the thread.
  • the task processing method provided in this embodiment further replaces the first user state instruction position in the core stack with the start instruction position of the operating system interrupt processing program, so that the user layer thread is restored, and the entry is not interrupted.
  • the first user state instruction position continues to run, but forcibly jumps to the interrupt handler in the operating system, and enters the interrupt response process without delay, realizing the effect of fast reporting and response of the interrupt request.
  • the task processing method provided in this embodiment also completes the interrupt response independently by the interrupt processing program of the operating system, and does not need to switch to the kernel layer for processing in the process, and the time required to complete the complete interrupt response process is very small. Effect.
  • FIG. 11 is a flowchart of a method for processing a task according to still another embodiment of the present invention. This embodiment is exemplified by applying the task processing method to the electronic device shown in FIG. 6A or FIG. 6B.
  • the method includes:
  • Step 1101 running at least one thread in the user layer
  • the electronic device runs at least one thread in the user layer.
  • This thread can be a real-time thread for processing real-time tasks or a normal thread for handling common tasks.
  • Step 1102 Run an operating system in a thread, where the operating system is used to process a task;
  • the electronic device runs the operating system in a thread.
  • An operating system can be run separately in each thread.
  • the electronic device processes the task through the operating system.
  • the operating system needs to have the ability to independently perform interrupt response and/or task scheduling. Different types of threads can run the same type of operating system, and different types of operating systems can be run in different threads.
  • the type of the above operating system is not particularly limited in the embodiment of the present invention.
  • the task is generally referred to as a task that the operating system can process.
  • the task may be a task of issuing a scheduling instruction, a task of allocating a channel resource, a task of processing an access request, and the like.
  • Step 1103 During the processing of the task, the task scheduling is performed by the operating system in the thread.
  • the electronic device does not perform task scheduling on the tasks in the thread through the kernel layer, but performs task scheduling on the tasks in the thread by the operating system in the thread.
  • the interrupt response logic of the kernel layer is not needed, and it is not affected by the task scheduling of the kernel layer, and the task scheduling is completed independently.
  • the scheduling policy at the time of scheduling can adopt an existing task scheduling policy.
  • the first one takes the example of switching from the first task to the second task.
  • This step includes the following sub-steps, as shown in FIG. 12:
  • the electronic device when switching from the first task to the second task, saves the running scene of the interrupted first task by using an operating system in the thread, where the running field of the first task includes the register information, the third user state instruction position, and Lock interrupt information for the first task;
  • the operating system in the thread provided by this embodiment has the function of independently completing task scheduling.
  • a task scheduler can be implemented in the thread's operating system, and the task scheduler is used to perform task scheduling for each task processed in the operating system.
  • switching from the first task to the second task may be triggered by an interrupt request or may be actively triggered by a task scheduler in the operating system.
  • the second task will enable one timer after the suspension, and the timer generates an interrupt request after the delay of n milliseconds, and the interrupt request is used to request that the interrupt is being processed.
  • the first task is run, and the first task that is running is switched to the second task to resume the running of the second task.
  • the task scheduler may switch the running first task to the second task when the priority of the second task reaches a preset condition.
  • the electronic device saves the running site of the interrupted first task by using a task scheduler in the operating system, where the running site of the first task includes the register information, the third user state command position, and the first The lock of the task is interrupted.
  • the lock interrupt information means that because task A may be interrupted by task B, task B may be interrupted by task C, and interrupt nesting is formed at this time.
  • Lock interrupt information refers to the level of an interrupt request in interrupt nesting. .
  • the electronic device acquires a running site of the second task by using an operating system in the thread, where the running site of the second task includes the register information, the fourth user state command position, and the lock interruption information of the second task;
  • the electronic device can acquire the running site of the second task through the task scheduler in the operating system.
  • the electronic device restores the second task and processes according to the operating site of the second task by using an operating system in the thread.
  • the electronic device can restore the second task according to the register information in the running field and the fourth user state command position by the task scheduler in the operating system.
  • the electronic device switches the unlocking interrupt state according to the lock interrupt information of the second task by the task scheduler, and then processes the second task.
  • the electronic device is scheduled to a third task that needs priority scheduling, and the third task may be a new task.
  • This step includes the following sub-steps, as shown in Figure 13:
  • the electronic device detects, by the operating system in the thread, whether there is a third task that needs to be scheduled preferentially;
  • the electronic device detects whether there is a third task requiring priority scheduling through a task scheduler in the operating system.
  • an interrupt request is also generated at this time, and the interrupt request is used to request processing of the data packet, and the interrupt request is generated to be processed for processing the data packet.
  • the electronic device acquires a running site of the third task by using an operating system in the thread, where the running site of the third task includes the register information, the fifth user state command location, and the lock interruption information of the third task;
  • the electronic device acquires the running site of the third task through the task scheduler in the operating system.
  • the electronic device restores the third task and processes according to the operating site of the third task by using an operating system in the thread.
  • the electronic device can resume the third task according to the register information according to the operation site and the fifth user state command position.
  • the electronic device switches the lock interruption state in the kernel layer to the unlock interruption state according to the lock interruption information of the third task by the task scheduler, and then processes the third task.
  • the task processing method performs task scheduling by running an operating system in a thread through an operating system in a thread; and the task scheduling process needs to be switched to the Linux kernel layer multiple times, resulting in a single operation.
  • the delay of the task scheduling process is large, which affects the real-time problem of the task processing process. It achieves the task scheduling directly in the user layer, does not need to switch to the kernel layer multiple times, reduces the time-consuming task scheduling, and improves the task. The effect of real-time processing.
  • the load of the kernel layer is high, and the task processing method provided in this embodiment can also achieve the effect of reducing the load of the kernel layer.
  • the task processing apparatus provided in any of the embodiments of FIG. 2 or FIG. 4 or the electronic apparatus provided in the embodiment of FIG. 5A or FIG. 5B can perform the task processing method provided in any of the embodiments of FIG. 7 to FIG.
  • the specific functions and working procedures of the various units or modules of the device embodiments may be referred to the related parts of the method embodiments, and the descriptions of the various embodiments provided by the present invention may also be referred to each other.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

La présente invention concerne un procédé et un appareil de gestion de tâche et un dispositif électronique. Le procédé comprend les étapes consistant à : exécuter au moins un fil d'exécution dans une couche utilisateur (701); exécuter un système d'exploitation dans le fil d'exécution, le système d'exploitation étant utilisé afin de gérer une tâche (702); et, dans un processus d'exécution de tâche, effectuer une gestion d'interruption et/ou un ordonnancement de tâche au moyen du système d'exploitation dans le fil d'exécution (703). Le problème d'influence sur la rapidité d'un processus de gestion de tâche en raison d'un retard plus important pour un processus de gestion d'interruption à temps unique et un processus d'ordonnancement de tâche, provoqué par le fait que le processus de gestion d'interruption et le processus d'ordonnancement de tâche sont mis en œuvre par commutation répétée vers une couche de noyau Linux, est résolu. Les effets d'achèvement direct de la gestion d'interruption et/ou de l'ordonnancement de tâche dans la couche utilisateur, sans gestion par la commutation répétée vers la couche de noyau, de raccourcissement du temps consommé pour la gestion d'interruption et/ou l'ordonnancement de tâche et d'amélioration de la rapidité de gestion de tâche, sont obtenus.
PCT/CN2014/085834 2014-09-03 2014-09-03 Procédé et appareil de gestion de tâche et dispositif électronique WO2016033755A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2014/085834 WO2016033755A1 (fr) 2014-09-03 2014-09-03 Procédé et appareil de gestion de tâche et dispositif électronique
CN201480034730.1A CN105579963B (zh) 2014-09-03 2014-09-03 任务处理装置、电子设备及方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2014/085834 WO2016033755A1 (fr) 2014-09-03 2014-09-03 Procédé et appareil de gestion de tâche et dispositif électronique

Publications (1)

Publication Number Publication Date
WO2016033755A1 true WO2016033755A1 (fr) 2016-03-10

Family

ID=55439004

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/085834 WO2016033755A1 (fr) 2014-09-03 2014-09-03 Procédé et appareil de gestion de tâche et dispositif électronique

Country Status (2)

Country Link
CN (1) CN105579963B (fr)
WO (1) WO2016033755A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113141385A (zh) * 2020-01-19 2021-07-20 大唐移动通信设备有限公司 数据接收处理方法、装置、电子设备及存储介质
CN113296900A (zh) * 2020-02-21 2021-08-24 大唐移动通信设备有限公司 一种任务切换方法及装置
CN114564289A (zh) * 2022-02-18 2022-05-31 苏州浪潮智能科技有限公司 任务切换方法、装置及电子设备
CN116521340A (zh) * 2023-04-27 2023-08-01 福州慧林网络科技有限公司 一种基于大带宽网络的低延时并行数据处理系统及方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115774574B (zh) * 2021-09-06 2024-06-04 华为技术有限公司 一种操作系统内核切换方法和装置
CN118689599A (zh) * 2023-03-21 2024-09-24 华为技术有限公司 中断处理的方法、装置和电子设备
CN116737366B (zh) * 2023-05-15 2024-05-10 广州汽车集团股份有限公司 共享栈的处理方法、装置、电子设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101267361A (zh) * 2008-05-09 2008-09-17 武汉飞思科技有限公司 一种基于零拷贝技术的高速网络数据包捕获方法
CN102625064A (zh) * 2012-03-28 2012-08-01 深圳市茁壮网络股份有限公司 一种接收并识别红外遥控信号的方法和装置
CN103440169A (zh) * 2013-08-21 2013-12-11 华为技术有限公司 一种进程中断处理的方法及装置
US20140115591A1 (en) * 2012-10-18 2014-04-24 Oracle International Corporation Apparatus, system and method for providing fairness in task servicing

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7870553B2 (en) * 2003-08-28 2011-01-11 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
CN1825286A (zh) * 2006-03-31 2006-08-30 浙江大学 嵌入式sram操作系统线程实现和线程状态转换的方法
CN103870326B (zh) * 2012-12-11 2018-07-13 厦门雅迅网络股份有限公司 一种将中断处理程序底半部搬移到应用层的方法及应用

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101267361A (zh) * 2008-05-09 2008-09-17 武汉飞思科技有限公司 一种基于零拷贝技术的高速网络数据包捕获方法
CN102625064A (zh) * 2012-03-28 2012-08-01 深圳市茁壮网络股份有限公司 一种接收并识别红外遥控信号的方法和装置
US20140115591A1 (en) * 2012-10-18 2014-04-24 Oracle International Corporation Apparatus, system and method for providing fairness in task servicing
CN103440169A (zh) * 2013-08-21 2013-12-11 华为技术有限公司 一种进程中断处理的方法及装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113141385A (zh) * 2020-01-19 2021-07-20 大唐移动通信设备有限公司 数据接收处理方法、装置、电子设备及存储介质
CN113141385B (zh) * 2020-01-19 2022-11-15 大唐移动通信设备有限公司 数据接收处理方法、装置、电子设备及存储介质
CN113296900A (zh) * 2020-02-21 2021-08-24 大唐移动通信设备有限公司 一种任务切换方法及装置
CN114564289A (zh) * 2022-02-18 2022-05-31 苏州浪潮智能科技有限公司 任务切换方法、装置及电子设备
CN114564289B (zh) * 2022-02-18 2024-06-07 苏州浪潮智能科技有限公司 任务切换方法、装置及电子设备
CN116521340A (zh) * 2023-04-27 2023-08-01 福州慧林网络科技有限公司 一种基于大带宽网络的低延时并行数据处理系统及方法
CN116521340B (zh) * 2023-04-27 2023-10-10 福州慧林网络科技有限公司 一种基于大带宽网络的低延时并行数据处理系统及方法

Also Published As

Publication number Publication date
CN105579963B (zh) 2019-10-01
CN105579963A (zh) 2016-05-11

Similar Documents

Publication Publication Date Title
WO2016033755A1 (fr) Procédé et appareil de gestion de tâche et dispositif électronique
US10884786B2 (en) Switch device, switching method, and computer program product
CN108647104B (zh) 请求处理方法、服务器及计算机可读存储介质
CN106844017B (zh) 用于网站服务器处理事件的方法和设备
US20090271796A1 (en) Information processing system and task execution control method
JP4529767B2 (ja) クラスタ構成コンピュータシステム及びその系リセット方法
JP5167844B2 (ja) プロセッサ、電子機器、割込み制御方法及び割込み制御プログラム
WO2009133669A1 (fr) Dispositif de commande d'ordinateur virtuel, procédé de commande d'ordinateur virtuel et programme de commande d'ordinateur virtuel
US9632842B2 (en) Exclusive access control method prohibiting attempt to access a shared resource based on average number of attempts and predetermined threshold
US10459773B2 (en) PLD management method and PLD management system
JP2007219757A (ja) 仮想計算機システムを機能させるためのプログラム
US9389923B2 (en) Information processing device and method for controlling information processing device
US20160034332A1 (en) Information processing system and method
US9652299B2 (en) Controlling the state of a process between a running and a stopped state by comparing identification information sent prior to execution
KR102053849B1 (ko) 항공기 시스템 및 그것의 제어 방법
WO2011116672A1 (fr) Procédé et appareil de correction de segment de code partagé
JP7012915B2 (ja) コントローラ
JP2006085428A (ja) 並列処理システム、インタコネクションネットワーク、ノード及びネットワーク制御プログラム
US20090113212A1 (en) Multiprocessor electronic circuit including a plurality of processors and electronic data processing system
JP2010134698A (ja) 情報処理システム
WO2021002054A1 (fr) Système informatique et procédé d'exécution de programme
WO2012101759A1 (fr) Procédé de fonctionnement de processeurs et système à processeurs
KR20130104958A (ko) 다중 운영체제들을 실행하는 장치 및 방법
JP7164175B2 (ja) 分散ファイル装置、フェイルオーバ方法、プログラム及び記録媒体
US10261817B2 (en) System on a chip and method for a controller supported virtual machine monitor

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201480034730.1

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14901012

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14901012

Country of ref document: EP

Kind code of ref document: A1