WO2016027829A1 - 連想記憶装置、インデックス生成器、及び登録情報更新方法 - Google Patents
連想記憶装置、インデックス生成器、及び登録情報更新方法 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
Definitions
- the present invention relates to an associative memory device, an index generator, and a registration information update method, and more particularly to a technique for speeding up the update of registration information registered in an index generator provided in the associative memory device.
- CAM Content Addressable Memory
- CAM is used in a wide range of fields such as pattern matching, Internet routers, processor caches, TLBs (Translation Lookaside Buffers), data compression, database accelerators, neural networks, and memory patches.
- TLB Translation Lookaside Buffers
- CAMs are classified into two types according to their functions: binary CAM (Binary CAM: hereinafter referred to as “BCAM”) and ternary CAM (Ternary CAM: hereinafter referred to as “TCAM”).
- BCAM binary CAM
- TCAM ternary CAM
- 0 and 1 are stored in each cell.
- TCAM 0, 1, and * are stored in each cell.
- “*” represents don't care and matches both 0 and 1.
- CAM functions can be realized by software, but those realized by software are significantly slower. For this reason, CAM is often realized using dedicated hardware.
- the conventional CAM is faster than a RAM because it can be searched in parallel, but the device configuration is complicated. Therefore, the price per bit (bit cost) of the CAM is about 10 to 30 times as high as that of the RAM. In addition, power consumption per bit is much larger than RAM (see Non-Patent Document 3). This is because all CAM cells are accessed simultaneously. Therefore, the power consumption per bit is about 50 times that of a normal RAM. Therefore, according to the conventional CAM, it is difficult to increase the storage capacity from the viewpoint of bit cost and power consumption.
- the present invention has been made in view of the above circumstances, and an associative storage device, an index generator, and a registration information update method capable of updating registration information at high speed while enabling a large storage capacity
- the purpose is to provide.
- An associative storage device generates a feature amount of an input vector using a plurality of hash functions, and searches for registration information related to the registration vector based on the feature amount to obtain an index corresponding to the input vector.
- Each of the plurality of index generation units generates a first signal indicating whether or not an index generated based on the feature amount exists as the registration information, supplies the first signal to the control unit, and the feature amount
- a reproduction vector of the input vector is generated using an index generated based on the reproduction vector, and the reproduction vector is input to the input vector.
- Supplied to the control unit generates a second signal indicating whether to match the vector has the structure of the associative memory.
- An index generator includes a hash circuit that calculates and outputs a feature quantity of an input vector from an input vector, and a main storage unit that stores an index corresponding to the registration vector as registration information regarding the registration vector
- a temporary index generation circuit that reads and outputs a temporary index corresponding to the feature amount from the main storage unit, and corresponds to the feature amount based on the temporary index output from the temporary index generation circuit
- a collision signal generation circuit that generates and outputs a first signal indicating whether or not the provisional index exists as the registration information, and a sub-storage unit that stores the registration vector as registration information related to the registration vector.
- a reproduction vector generation circuit for outputting the output vector, a comparison circuit for comparing the reproduction vector and the input vector, and outputting a second signal indicating whether or not the reproduction vector and the input vector match; And an output circuit that outputs the temporary index as a unique index corresponding to the input vector when two signals indicate a match between the reproduction vector and the input vector.
- An information update method is an information update method for updating registration information registered in the associative memory device, and the associative memory device includes a search mode and an update mode as operation modes,
- the control unit provided in the associative storage device has a configuration of an information update method for performing control for updating the registration information in the update mode.
- registration information can be updated at a high speed while enabling a large storage capacity.
- index generation function index generator, input vector
- f (X) is referred to as an index generation function with a weight k.
- the index generation function generates a unique index from 1 to k for k different binary vectors. In the present specification, the value of k is assumed to be sufficiently smaller than the total number of combinations 2 n of the input vector (k ⁇ 2 n).
- an index generator the circuit that performs the above-described index generation function operation is called an index generator.
- a vector input to the index generator is referred to as an input vector.
- An index generation function whose input vector is an n-dimensional vector is called an n-input index generation function.
- a circuit for performing an n-input index generation function is called an n-input index generator.
- the hash function is a mapping from the set S to a set of integers ⁇ 0, 1,..., M ⁇ 1 ⁇ .
- m is a natural number that does not exceed the elements of the set S.
- FIG. 1 is a block diagram showing a configuration example of an associative memory device 100 according to the first embodiment of the present invention.
- the associative memory device 100 generates and outputs a unique index A corresponding to an n-bit (n is a natural number) input vector X (x1, x2,..., Xn) to be searched.
- 110-N an output unit 120, and a control unit 130 (N is a natural number of 2 or more).
- N is a natural number of 2 or more.
- any one of the N index generators 110-1, 110-2, 110-3,..., 110-N is designated as “index generator 110-i” (i is (Natural number from 1 to N).
- each of the index generation units 110-1, 110-2, 110-3,..., 110-N can be handled as a single unit as an index generator, an index generation device, or the like.
- the N index generators 110-1, 110-2, 110-3,..., 110-N generate a feature quantity of the input vector X, and a unique index A1 corresponding to the input vector X is generated from the feature quantity. , A2,..., AN are generated and output, respectively. That is, each of the N index generators 110-1, 110-2, 110-3,..., 110-N generates a feature quantity of the input vector X using a hash function, and based on this feature quantity
- the unique indexes A1, A2, A3,..., AN corresponding to the input vector X are generated by searching registration information related to the registered vectors registered in each index generating unit.
- a linear function that can be realized by a circuit composed of only an exclusive OR gate circuit is used as a hash function.
- the N hash functions respectively used by the N index generators 110-1, 110-2, 110-3,..., 110-N are mutually identical functions as long as the above [Definition 3] is followed. Or different functions from each other. That is, each of the N index generators 110-1, 110-2, 110-3,..., 110-N may use the same hash function as the hash function used in the other index generators, A hash function different from hash functions used in other index generation units may be used.
- each of the index generation units 110-1, 110-2, 110-3,..., 110-N indicates whether or not an index generated based on the feature amount exists as the registration information.
- 1 signal hereinafter referred to as a “collision signal”) CD1, CD2, CD3,..., CDN, and a reproduction vector of the input vector X using an index generated based on the above-described feature amount
- Second signals hereinafter referred to as “match signals” MT1, MT2,..., MTN indicating whether or not the reproduction vector matches the input vector X are generated.
- the “reproduction vector” refers to a vector that reproduces the original input vector X based on an index obtained from the feature quantity of the input vector X.
- the collision signal CD CD1, CD2, CD3,..., CDN
- the coincidence signal MT MT1, MT2,..., MTN
- the output unit 120 combines the outputs (indexes A1, A2, A3,..., AN) of the N index generation units 110-1, 110-2, 110-3,. Is configured to output a unique index A corresponding to.
- the control unit 130 is for controlling the update of the registration information registered in each of the N index generation units 110-1, 110-2, 110-3,..., 110-N.
- a write enable signal WE for controlling the write operation of the registration vector as the registration information from the control unit 130 to the index generation units 110-1, 110-2, 110-3,.
- An index IDX and a selection signal SEL for designating one of the index generation units 110-1, 110-2, 110-3,. Note that the control unit 130 changes the operation mode to the update mode when the command signal UPD is supplied.
- control unit 130 performs an operation of adding new registration information when the command signal UPD and the index IDX are supplied. In addition, the control unit 130 performs an operation of deleting the existing registration information when only the command signal UPD is supplied. In addition, the control unit 130 outputs a signal BSY (busy) indicating that it is operating, for example, during an operation such as an update mode. In addition, for example, when the operation of adding new registration information fails, the control unit 130 outputs a signal FAL (fail) indicating failure.
- N 3
- the associative memory device 100 shown in FIG. 1 is assumed to include three index generation units 110-1, 110-2, and 110-3. Therefore, i indicates an arbitrary natural number of 1, 2, and 3, and the index generation unit 110-i represents one of the index generation units 110-1, 110-2, and 110-3.
- the present invention is not limited to this example, and the number N of index generation units can be arbitrarily set.
- n 6
- 6-bit input vectors X (x1, x2, x3, x4, x5, x6) are input to the index generators 110-1, 110-2, 110-3, respectively.
- FIG. 2 is a block diagram showing a configuration example of the index generation unit 110-i provided in the associative storage device 100 according to the first embodiment of the present invention.
- the index generation unit 110-i includes a hash circuit 111, a temporary index generation circuit 112, a reproduction vector generation circuit 113, a comparison circuit 114, an output circuit 115, and a collision signal generation circuit 116.
- the hash circuit 111 is for generating a p-bit vector Y1 (p is a natural number smaller than n) representing the feature quantity of the input vector X from the n-bit input vector X using a hash function. It is.
- a hash function may give the same value for different inputs, which is referred to as hash collision.
- the hash collision is avoided by using another index generation unit. Details thereof will be described later.
- the temporary index generation circuit 112 generates a q-bit temporary index A ′ corresponding to the p-bit vector Y1 representing the feature quantity of the input vector X.
- q “log 2 (k i +1)”
- k i represents the number of registered vectors realized by the index generation unit 110-i
- log 2 (k i +1)” is rounded up.
- the temporary index generation circuit 112 includes a main storage unit in which registered vector indexes are stored as registration information, and reads and outputs a temporary index A ′ corresponding to the feature quantity of the input vector X from the main storage unit. .
- the main storage unit is composed of a general-purpose semiconductor memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) to which a bit string indicating the feature amount is input as an address signal.
- a general-purpose semiconductor memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) to which a bit string indicating the feature amount is input as an address signal.
- the main memory section need not be a general-purpose memory as long as it is a memory that employs a method of selecting a part of the memory cells in the memory cell array in a single access like a general-purpose memory such as a DRAM.
- a dedicated memory may be used.
- the reproduction vector generation circuit 113 is for reproducing the input vector X corresponding to the temporary index A ′, and has a secondary storage unit in which registration vectors are stored as registration information.
- the reproduction vector generation circuit 113 reads a registration vector corresponding to the temporary index A ′ from the sub storage unit and outputs it as an (np) -bit reproduction vector X2 ′.
- the (np) -bit reproduction vector X2 ′ is an element obtained by reproducing X2 of the input vector X (X1, X2).
- X1 indicates the bits x1, x2, and x3 of the input vector X
- X2 indicates the bits x4, x5, and x6 of the input vector X.
- the sub-storage unit is composed of a general-purpose semiconductor memory such as a DRAM or SRAM (Static Random Access Memory) to which a bit string indicating the temporary index A ′ is input as an address signal.
- the sub storage unit may be a memory designed for exclusive use.
- the reproduction vector generation circuit 113 outputs an n-bit reproduction vector X ′ corresponding to all bits of the input vector X.
- the comparison circuit 114 is for verifying whether or not the reproduction vector X2 'and X2 (x4, x5, x6) of the input vector X match. Verifying whether the reproduction vector X2 'matches the X2 of the input vector X means verifying whether the temporary index A' is a unique index corresponding to the input vector X.
- the comparison circuit 114 compares the reproduction vector X2 ′ with X2 of the input vector X, and based on the result of this comparison, generates a match signal MTi indicating whether or not the reproduction vector X ′ and X2 of the input vector X match. Output.
- the output circuit 115 is for outputting a unique index Ai corresponding to the input vector X or a predetermined invalid value based on the coincidence signal MTi. That is, the output circuit 115 outputs the temporary index A ′ as a unique index Ai when the match signal MTi indicates a match between the reproduction vector X2 ′ and the input vector X2, and the match signal MTi is output as the reproduction vector X2 ′. And a predetermined invalid value are output when the input vector X is inconsistent with X2. In this embodiment, when the values of all bits of the index Ai are “0”, the index Ai indicates a predetermined invalid value.
- the present invention is not limited to this example, and the definition of the invalid value is arbitrary. For example, an index Ai in which all the bit values are “1” may be set as an invalid value.
- the collision signal generation circuit 116 is for generating and outputting the collision signal CDi based on the temporary index A ′ output from the temporary index generation circuit 112 in the update mode.
- the collision signal CDi is generated based on the temporary index A ′ output from the temporary index generation circuit 112. Output.
- the collision signal CDi is a signal indicating the presence or absence of hash collision in the update mode, and when the temporary index A ′ output from the temporary index generation circuit 112 with respect to the input vector X to be updated is not an invalid value, That is, this signal is a value “1” when a hash collision occurs. Note that the value of the collision signal CDi when a hash collision occurs can be arbitrarily set.
- FIG. 3A to 3C are circuit diagrams showing configuration examples of the hash circuit 111 included in the index generation unit 110-i included in the associative storage device 100 according to the first embodiment of the present invention.
- the hash circuit 111 uses 3 bits of X1 (x1, x2, x3) out of 6 bits (x1, x2, x3, x4, x5, x6) of the input vector X as a feature of the input vector X.
- the hash circuit 111 shown in FIG. 3A is composed of three exclusive OR gate circuits.
- Each bit of X1 (x1, x2, x3) is supplied to the first input part of these three exclusive OR gate circuits, and the value '0' is supplied in common to the second input part.
- the hash circuit 111 in FIG. 3A outputs X1 (x1, x2, x3) of the input vector X as a 3-bit vector Y1 (y1, y2, y3).
- the hash circuit 111 uses the 3 bits of X2 (x4, x5, x6) among the 6 bits (x1, x2, x3, x4, x5, x6) of the input vector X as the characteristics of the input vector X.
- the hash circuit 111 shown in FIG. 3B is composed of three exclusive OR gate circuits.
- Each bit of X2 (x4, x5, x6) is supplied to the first input part of these three exclusive OR gate circuits, and the value '0' is supplied in common to the second input part.
- the hash circuit 111 calculates the exclusive OR of the bits x1 and x6 among the 6 bits (x1, x2, x3, x4, x5, x6) of the input vector X, and the calculation result is calculated.
- the exclusive OR gate circuit 111-31 calculates the exclusive OR of the bits x1 and x6, and the operation result is the value of the bit y1 of the vector Y1. Further, the bit x2 and the bit x5 of the input vector X are supplied to the input part of the exclusive OR gate circuit 111-32.
- the exclusive OR gate circuit 111-32 calculates the exclusive OR of the bits x2 and x5, and the operation result is the value of the bit y2 of the vector Y1.
- the bit x3 and the bit x4 of the input vector X are supplied to the input part of the exclusive OR gate circuit 111-33.
- the hash function realized by the hash circuits 111 of the index generation units 110-1, 110-2, and 110-3 can significantly identify a registered vector with a bit number p smaller than the bit number n of the input vector X. It is set according to the contents of the registered vector so that the quantity can be obtained. Details thereof will be described later.
- the temporary index generation circuit 112 includes a general-purpose semiconductor memory such as a DRAM, and the general-purpose semiconductor memory forms the main storage unit of the temporary index generation circuit 112.
- a memory of an arbitrary system such as a ferroelectric memory or a magnetic memory can be used as a memory forming the main storage unit of the temporary index generation circuit 112. it can.
- Information relating to the index of the registration vector is stored as registration information in the memory forming the main storage unit of the temporary index generation circuit 112.
- Each bit of the p-bit vector Y1 output from the hash circuit 111 is supplied as an address signal to the address input terminal of the general-purpose memory forming the main storage unit of the temporary index generation circuit 112.
- the memory cell of the general-purpose memory forming the main storage unit specified by the combination of the values of the bits of the vector Y1 indicates an index corresponding to the feature amount as registration information regarding the index of the registration vector. Data is stored. Therefore, by accessing the general-purpose memory forming the main storage unit based on the vector Y1, the q-bit index corresponding to the feature quantity of the input vector X is read from the main storage unit as the temporary index A ′. It is.
- the reproduction vector generation circuit 113 is configured by a general-purpose semiconductor memory such as a DRAM, and this general-purpose semiconductor memory forms the above-described sub storage unit of the reproduction vector generation circuit 113.
- a memory of an arbitrary system such as a ferroelectric memory or a magnetic memory can be used as a memory forming the sub storage unit of the reproduction vector generation circuit 113. it can.
- the bit value of the registration vector is stored as registration information.
- Each bit of the temporary index A ′ of q bits output from the temporary index generation circuit 112 is supplied as an address signal to the address input terminal of the general-purpose memory forming the sub storage unit of the reproduction vector generation circuit 113.
- the memory cell of the general-purpose memory that forms the above-described sub storage unit specified by the combination of the values of each bit of the temporary index A ′ corresponds to the temporary index A ′ as registration information regarding the registration vector.
- a value of (n ⁇ p) bits that are a part of bits of the registration vector is stored.
- all the bits (that is, n bits) of the registration vector are stored as registration information in the memory forming the sub storage unit.
- the temporary index A ' corresponds to the input vector X. Therefore, by accessing a general-purpose memory that forms the secondary storage unit of the reproduction vector generation circuit 113 based on the temporary index A ′, a part of the registration vector corresponding to X2 of the input vector X is accessed from the secondary storage unit. A bit is read as a reproduction vector X2 ′.
- main storage unit of the temporary index generation circuit 112 and the sub storage unit of the reproduction vector generation circuit 113 may be integrated into one semiconductor memory such as a DRAM. Thereby, the number of components can be reduced and the memory access time can be reduced.
- FIG. 4A is a diagram illustrating a configuration example of the comparison circuit 114 of the index generation unit 110-i provided in the associative storage device 100 according to the first embodiment of the present invention.
- the comparison circuit 114 includes negative exclusive OR gate circuits 1144, 1145 and 1146 which are coincidence gates.
- the input part of the negative exclusive OR gate circuit 1144 is supplied with the bit x4 of X2 of the input vector X and the bit x4 ′ of the reproduction vector X2 ′.
- the input unit of the negative exclusive OR gate circuit 1145 is supplied with the bit x5 of the X2 of the input vector X and the bit x5 ′ of the reproduction vector X2 ′. Furthermore, the input part of the negative exclusive OR gate circuit 1146 is supplied with the bit x6 of X2 of the input vector X and the bit x6 'of the reproduction vector X2 ′.
- the output sections of the negative exclusive OR gate circuits 1144, 1145 and 1146 are connected to the input section of the AND gate circuit 1147, and the output signal of the AND gate circuit 1147 is set as the coincidence signal MTi.
- FIG. 4B is a diagram illustrating a configuration example of the output circuit 115 of the index generation unit 110-i included in the associative storage device 100 according to the first embodiment of the present invention.
- the temporary index A ′ is represented by 4 bits (a1 ′, a2 ′, a3 ′, a4 ′).
- the present invention is not limited to this example, and the number of bits of the temporary index A ′ can be set to an arbitrary value.
- the output circuit 115 includes four AND gate circuits 1151, 1152, 1153, and 1154 corresponding to the number of bits (4 bits) of the temporary index A ′. Bits a1 ', a2', a3 ', and a4' of the temporary index A 'are supplied to the first input portions of the AND gate circuits 1151, 1152, 1153, and 1154, respectively.
- the coincidence signal MTi is commonly supplied to the second input sections of the AND gate circuits 1151, 1152, 1153, and 1154.
- the AND gate circuits 1151, 1152, 1153, and 1154 when the value of the coincidence signal MTi is “1” (high level), the AND gate circuits 1151, 1152, 1153, and 1154 have the bit a1 ′ of the temporary index A ′. , A2 ′, a3 ′, and a4 ′ are output as they are as the values of the bits a1i, a2i, a3i, and a4i of the unique index Ai.
- the AND gate circuits 1151, 1152, 1153, and 1154 When the value of the coincidence signal MTi is “0” (low level), the AND gate circuits 1151, 1152, 1153, and 1154 have the bits a1 ′, a2 ′, a3 ′, and a4 ′ of the temporary index A ′.
- a signal of value '0' (low level) is output, and the values of the bits a1i, a2i, a3i, a4i of the unique index Ai are all '0'. This is a signal indicating an invalid value.
- the collision signal generation circuit 116 includes a 4-input OR gate circuit 1161 corresponding to the number of bits (4 bits) of the temporary index A ′.
- the OR gate circuit 1161 calculates the logical sum of the bits a1 ′, a2 ′, a3 ′, and a4 ′ of the temporary index A ′ and outputs the calculation result as a collision signal CDi.
- the collision signal generation circuit 116 sets the value “1” as the collision signal CDi when any of the bits a1 ′, a2 ′, a3 ′, and a4 ′ of the temporary index A ′ includes the value “1”.
- a high level logic signal is output.
- the value “1” of the collision signal CDi indicates that a hash collision has occurred in the update mode.
- the collision signal The generation circuit 116 outputs a low-level logic signal indicating the value “0” as the collision signal CDi.
- the value “0” of the collision signal CDi indicates that no hash collision has occurred in the update mode.
- FIG. 5 is a diagram illustrating a circuit configuration example of the output unit 120 provided in the associative memory device 100 according to the first embodiment of the present invention.
- the output unit 120 includes three OR gate circuits 1201, 1202, and 1203 corresponding to the number of index generation units 110-1, 110-2, and 110-3.
- the OR gate circuit 1201 In the input part of the OR gate circuit 1201, the bit a1 of the index A1 output from the index generator 110-1, the bit a1 of the index A2 output from the index generator 110-2, and the index generator 110- The bit a1 of the index A3 output from 3 is supplied.
- the OR gate circuit 1201 calculates the logical sum of the bits a1 input from the index generators 110-1, 110-2, and 110-3, and outputs the calculation result as the value of the bit a1 of the index A. .
- the input part of the OR gate circuit 1202 includes the bit a2 of the index A1 output from the index generation part 110-1, the bit a2 of the index A2 output from the index generation part 110-2, and the index generation part.
- the bit a2 of the index A3 output from 110-3 is supplied.
- the OR gate circuit 1202 calculates the logical sum of the bits a2 input from the index generation units 110-1, 110-2, and 110-3, and outputs the calculation result as the value of the bit a2 of the index A. .
- the input part of the OR gate circuit 1203 includes the bit a3 of the index A1 output from the index generation part 110-1, the bit a3 of the index A2 output from the index generation part 110-2, and the index generation part.
- the bit a3 of the index A3 output from 110-3 is supplied.
- the OR gate circuit 1203 calculates the logical sum of the bits a3 input from the index generation units 110-1, 110-2, and 110-3, and outputs the calculation result as the value of the bit a3 of the index A. .
- the output unit 120 By performing the above logical operation, the output unit 120 generates the index A by combining the corresponding bits of the indexes A1, A2, and A3 output from the index generation units 110-1, 110-2, and 110-3. And output.
- the output unit 120 In the process of the logical operation, at most one index generation unit generates a valid value and the other index generation units generate invalid values from the circuit configuration method. Therefore, according to the above configuration, only valid values are output from the output unit 120 as the index A.
- a temporary index A having all bits “1” is defined as an invalid value
- the output unit 120 performs a logical product for performing a logical product operation instead of the logical sum gate circuits 1201, 1202, and 1203.
- a gate circuit may be provided.
- FIG. 6 is a diagram illustrating an example of registration information registered in the associative storage device 100 according to the first embodiment of the present invention.
- an index representing the index A specific to the value of the input vector X is associated as the value of IDX.
- the hash function realized by the hash circuits 111 of the index generation units 110-1, 110-2, and 110-3 described above is registered in the registration information by a p-bit vector Y1 that is smaller than the bit number n of the input vector X. It is set according to the contents of the registered vector so that the feature quantity for significantly identifying the registered vector can be expressed.
- the values of the bit x1 of the registered vector respectively associated with the values “1” and “2” of the index IDX are “0”. . Therefore, it is impossible to identify the registration vectors associated with the index IDX values “1” and “2” based only on the bit x1.
- the value of the bit x2 of the registered vector associated with the values “1” and “2” of the index IDX are both “1”. Therefore, even if attention is paid to the two bits x1 and x2, the registered vectors associated with the values “1” and “2” of the index IDX cannot be identified.
- bit x3 the value of bit x3 of the registration vector associated with index IDX value “1” is “1”, and the registration associated with index IDX value “2”.
- the value of bit x3 of the vector is “0”. Therefore, if attention is paid to the bit x3, it is possible to identify the registered vectors respectively associated with the values “1” and “2” of the index IDX. That is, the feature quantity of the registered vector corresponding to the values “1” and “2” of the index IDX can be expressed using the bits x1, x2, and x3 of X1.
- the registration information that defines the correspondence between the registration vector identifiable using X1 and the index IDX is the three index generation units 110-1, 110. -2 and 110-3, the first index generator 110-1 implements this.
- FIG. 7 is a diagram for explaining registration information realized by the first index generation unit 110-1 included in the associative storage device 100 according to the first embodiment of the present invention.
- the registration information realized by the index generation unit 110-1 includes eight values “4”, “5”, “2” of the index IDX among the registration information shown in FIG. , “1”, “11”, “10”, “15”, “3” and 8 bits (x1, x2, x3, x4, x5, x6) of the registered vectors corresponding to the values of the index IDX ) Is determined so as to define the correspondence with the value of.
- X1 x1, x2, x3 is supplied to the temporary index generation circuit 112 as a vector Y1 (y1, y2, y3).
- each value of the index IDX associated with the bits x1, x2, and x3 of the registration vector is the main storage unit of the temporary index generation circuit 112 of the index generation unit 110-1. Is stored as a temporary index A ′.
- the temporary index A ′ representing the index IDX is stored in the memory cell specified by the bits x1, x2, and x3 of the registration vector corresponding to the index IDX.
- the registration vector and the index IDX are associated with each other and stored as registration information in the main storage unit of the temporary index generation circuit 112.
- each value of the bits x 1, x 2, x 3, x 4, x 5, x 6 of the registration vector is stored in the sub-storage unit of the reproduction vector generation circuit 113. That is, the index IDX is supplied from the temporary index generation circuit 112 to the reproduction vector generation circuit 113 as a q-bit temporary index A ′, and the registration vector is stored in the memory cell of the secondary storage unit specified by the temporary index A ′.
- the values of bits x1, x2, x3, x4, x5, and x6 are stored.
- the value of each bit of the registration vector is stored in the sub-storage unit of the reproduction vector generation circuit 113 as registration information associated with the temporary index A ′.
- the index generation unit 110-1 When the input vector X is supplied in the search mode, the index generation unit 110-1 described above stores the values of the bits x4, x5, and x6 out of all the bits of the input vector X as the secondary storage of the reproduction vector generation circuit 113.
- the value of the match signal MT1 of the comparison circuit 114 When the value matches the value stored in the memory constituting the unit, the value of the match signal MT1 of the comparison circuit 114 is “1”, and the value of the index IDX is output as the index A1.
- the values of the bits x4, x5, and x6 of the input vector X do not match the values stored in the memory constituting the sub storage unit, the value of the match signal MT1 of the comparison circuit 114 becomes “0”, and the index An invalid value is output as index A1 representing the value of IDX. In this case, all bits of the index A1 output from the index generation unit 110-1 are “0”.
- the second index generation unit 110-2 pays attention to the bits x4, x5 and x6 of the registration vector of the registration information, and among the registration information shown in FIG. Registration information that defines the correspondence between the values “7”, “13”, “12”, “6”, “8” and the registration vectors corresponding to these index IDX values is realized.
- the index IDX of the registration information realized by the index generation unit 110-2 is determined using the bits x4, x5, and x6 of X2 of the registration vector.
- FIG. 8 is a diagram for explaining registration information realized by the second index generation unit 110-2 provided in the associative storage device 100 according to the first embodiment of the present invention.
- registration information related to five values “7”, “13”, “12”, “6”, and “8” of the index IDX is realized.
- the remaining two values “9” and “14” of the index IDX cannot be realized by the index generation unit 110-2.
- the value of the coincidence signal MT2 of the comparison circuit 114 is “1”.
- the exclusive of the bits x1, x2, x3 and the bits x4, x5, x6 of the registration vector of the registration information is performed. Registration of the remaining index IDX values “9” and “14” in each memory cell of the main storage unit and the sub storage unit specified by the values of bits y1, y2, and y3 obtained as the logical OR operation result Information is stored.
- the index generator 110-3 uses bits y1, y2, and y3 obtained as an exclusive OR operation result of the bits x1, x2, and x3 of the registration vector of the registration information and the bits x4, x5, and x6.
- the index IDX of the registration information realized in is determined.
- FIG. 9 is a diagram for explaining registration information realized by the third index generation unit 110-3 included in the associative storage device 100 according to the first embodiment of the present invention.
- registration information related to the five values “9” and “14” of the index IDX is realized.
- information relating to the values “9” and “14” of the index IDX is stored in the memory cell of the main storage unit of the temporary index generation circuit 112 specified by the values of the bits y1, y2, and y3.
- the control unit 130 deletes an index corresponding to the existing registration vector, and then adds an index of a new registration vector as registration information. As a result, the registration information is updated.
- An operation for updating the registration information in the update mode is controlled by the control unit 130.
- control unit 130 determines whether there is the specified index generation unit 110-i (step S104). When there is the specified index generation unit 110-i (step S104: YES), the control unit 130 advances the process to step S105. In addition, the control unit 130 ends the process when there is no identified index generation unit 110-i (step S104: NO).
- the main storage unit and the sub storage unit of the unit are set to the write mode, and the registration information stored in these storage units is deleted. Specifically, the value of the temporary index stored in the main storage unit of the index generation unit 110-i in which the registration index to be deleted is stored is rewritten from the valid value to the invalid value.
- the memory constituting the main storage unit of the index generation unit 110-1 The contents of the index IDX at the address (0, 1, 1) are rewritten to (0, 0, 0). As a result, the registration information related to the registration vector supplied from the system to the control unit 130 is deleted.
- the control unit 130 when deleting an index corresponding to an existing registration vector registered as registration information, has a plurality of index generation units 110-1, 110-2, 110. ⁇ 3, an index generation unit that supplies a match signal MTi indicating that the reproduction vector X2 ′ generated using the index of the registered vector to be deleted matches X2 of the input vector X is selected.
- the control unit 130 deletes the index of the existing registration vector from the registration information of the selected index generation unit.
- the control by the control unit 130 includes the following first to third stages.
- First stage In the update mode, an existing registration vector to be deleted is supplied as an input vector X to a plurality of index generation units 110-1, 110-2, 110-3.
- the control unit 130 In any one of the plurality of index generation units 110-1, 110-2, 110-3, when a unique index corresponding to an existing registration vector exists as registration information, the control unit 130 The index value of the existing registered vector existing as is changed from the valid value to the invalid value.
- the control unit 130 when deleting the existing registration information, specifies the index generation unit storing the existing registration vector to be deleted from the value of the match signal MTi, and the control unit 130 determines each index. Since the registration information is deleted by directly accessing the main storage unit and the sub storage unit of the generation unit, the registration information can be deleted at high speed. Therefore, it is possible to perform an update operation accompanied by deletion of existing registration information at high speed.
- FIG. 14 is a flowchart illustrating an example of a method for adding new information according to the first embodiment of the present invention.
- a command signal UPD indicating activation of the update mode is supplied from the system that manages the associative memory device 100 to the control unit 130 of the associative memory device 100.
- the index IDX of the registration vector to be added is supplied from the system.
- the control unit 130 supplies the additional registration vector as an input vector to the plurality of index generation units 110-i. (Step S201). That is, the registration vector to be added is supplied as an input vector X to the three index generation units 110-1, 110-2, and 110-3.
- the control unit 130 refers to the collision signal CDi and identifies the index generation unit 110-i that does not have a registered vector that collides with a vector to be additionally registered (step S203). That is, the control unit 130 detects the collision signals CD1, CD2,... Supplied from the index generation units 110-1, 110-2, and 110-3, respectively. With reference to the value of CD3, an index generation unit capable of registering a registration vector to be added is specified. Here, if there is a registration vector that collides with the registration vector to be added, a hash collision occurs, and the collision signal CDi indicates the value “1”. An index generation unit to which a registration vector can be added can be specified from the value of the collision signal CDi.
- control unit 130 determines whether there is the specified index generation unit 110-i (step S204). When there is the specified index generation unit 110-i (step S204: YES), the control unit 130 advances the process to step S205. In addition, when there is no identified index generation unit 110-i (step S204: NO), the control unit 130 advances the process to step S206.
- the main storage unit and the sub storage unit are set to the write mode, and new registration information is added to these storage units. Specifically, the effective value of the temporary index is written in the main storage unit of the index generation unit where there is no registration vector that collides with the registration vector to be added.
- the address (y1, y2, y3) of the memory constituting the main storage unit of the index generation unit 110-3 (1 , 1, 0), the effective value of the index is written.
- the registration information regarding the registration vector supplied from the system to the control unit 130 is added to the associative memory device 100.
- step S206 the control unit 130 outputs a signal FAL indicating that addition cannot be performed. That is, the control unit 130 adds new registration information when all of the three index generation units 110-1, 110-2, and 110-3 have a registration vector that collides with the registration vector to be added. Do not do. In this case, the control unit 130 outputs a signal FAL indicating that addition cannot be performed.
- the control unit 130 when adding an index of a new registration vector as registration information, of the plurality of index generation units 110-1, 110-2, 110-3, An index generation unit that supplies a collision signal CDi indicating that a new registration vector is not stored as registration information is selected.
- the control unit 130 adds the index of the new registration vector to be added as the registration information of the selected index generation unit.
- any of the plurality of index generation units 110-1, 110-2, and 110-3 when a temporary index corresponding to a new registration vector to be added is stored as registration information, the control unit 130 In another index generation unit in which a temporary index corresponding to the new registration vector does not exist, an effective value is set as the index value corresponding to the new registration vector.
- the control by the control unit 130 includes the following first to third stages.
- First stage A new registration vector to be added is supplied as an input vector X to a plurality of index generators 110-1, 110-2, 110-3.
- Second stage For each of the plurality of index generators 110-1, 110-2, and 110-3, a temporary index corresponding to a new registration vector to be added is registered by the controller 130 based on the collision signal CDi. It is determined whether or not it exists as information.
- Third stage If any temporary index corresponding to the new registration vector does not exist as registration information in any of the plurality of index generators 110-1, 110-2, 110-3, the new registration vector Set a valid value as the index value.
- the control unit 130 when adding new registration information, the control unit 130 identifies an index generation unit that does not collide with the registration vector to be added from the value of the match signal MTi, and the control unit 130 detects the main index of each index generation unit. Since the registration information is added by directly accessing the storage unit and the sub storage unit, the registration information can be added at high speed. Therefore, it is possible to perform an update operation accompanied by addition of new registration information at high speed.
- the plurality of index generation units 110-1, 110-2, and 110-3 extract the feature quantity of the input vector using a plurality of hash functions, and this feature quantity. Since the temporary index A ′ is generated based on the above, even if a hash collision caused by the hash function occurs, the associative storage device stores the registration information using a general-purpose semiconductor memory while avoiding the hash collision. 100 can be realized.
- the hash circuit 111 provided in each of the plurality of index generation units 110-1, 110-2, 110-3,..., 110-N generates a p-bit vector Y1 smaller than the bit number n of the input vector X. Since it is generated, the address space of the memory that constitutes the main storage unit of the temporary index generation circuit 112 to which the vector Y1 is input as an address can be reduced. Therefore, it is possible to reduce the storage capacity of the semiconductor memory that constitutes the main storage unit.
- the hash circuit 111 extracts the feature quantity of the input vector X using a linear function as a hash function
- the sub-storage unit of the reproduction vector generation circuit 113 stores the registration vector as the bit value of the registration vector. It is sufficient to store a value of a part of (n ⁇ p) bits. Therefore, it is possible to effectively reduce the storage capacity of the semiconductor memory constituting the sub storage unit of the reproduction vector generation circuit 113. Therefore, according to the first embodiment, it is possible to increase the storage capacity of the associative storage device 100 while suppressing an increase in bit cost and power consumption.
- the collision signal CDi and the coincidence signal MTi are generated in each of the plurality of index generation units 110-1, 110-2, and 110-3, and these signals are supplied to the control unit 130.
- the control unit 130 refers to the collision signal CDi and the coincidence signal MTi, and thereby an index generation unit in which registration information to be deleted exists, and an index generation unit to which registration information can be added.
- the registration information can be updated by directly accessing. Therefore, it is possible to speed up the update of registered information.
- FIG. 10 is a block diagram showing a configuration example of an associative memory device 200 according to the second embodiment of the present invention.
- the associative memory device 200 further includes an output coupling unit 220.
- the output combining unit 220 combines the index A output from the output unit 120 provided in the associative memory device 100 according to the first embodiment and the index B output from the associative memory 110-C to form one index C. As the output.
- the output combining unit 220 outputs either one of the index A output from the output unit 120 and the index B output from the associative memory 110-C.
- the output coupling unit 220 includes, for example, an OR gate circuit, like the output unit 120 shown in FIG. Others are the same as in the first embodiment.
- FIG. 11 is a block diagram showing an example of a basic configuration of a conventional CAM 1000 used as the associative memory 110-C provided in the associative memory device 200 according to the second embodiment of the present invention (see Patent Document 1).
- the CAM 1000 includes a comparison register 1001, a search bit line driver 1002, m words W 1 to W m , m match sense circuits MSC 1 to MSC m , m match flag registers MFR 1 to MFR m , and priority
- An encoder (priority encoding circuit) PE is provided.
- the comparison register 1001 is a register that stores n-bit search data.
- the search bit line driver 1002 drives each bit of the comparison register 1001 onto the search bit line.
- Each word W 1 to W m includes an n-bit CAM cell.
- the coincidence comparison circuit 1005 includes three nMOS transistors (hereinafter referred to as “nMOS”) 1006, 1007, and 1008.
- the nMOSs 1006 and 1007 are connected in series between the search bit line SLN and the search bit line SL.
- the gates of the nMOSs 1006 and 1007 are connected to the data D and the inverted data DN of the memory cell 1004, respectively.
- the nMOS 1008 is connected between the match line ML and the ground.
- the gate of the nMOS 1008 is connected to a node 1009 between the nMOSs 1006 and 1007.
- data (registration vector) to be searched is entered in each word W 1 to W m of the CAM 1000.
- data writing to the memory cell 1004 and data reading from the memory cell 1004 are performed in the same manner as in a normal SRAM.
- each word W 1 to W m a match search between data stored in advance in each CAM cell and search data driven on the search bit line is executed simultaneously (in parallel), and the result is the match line ML 1. Is output on ML m .
- These search results are input to coincidence sense circuits MSC 1 to MSC m , respectively.
- Each coincidence sense circuit MSC 1 to MSC m amplifies each search result and outputs it as a coincidence sense output to coincidence sense output lines MT 1 to MT m .
- Each match sense output is stored in match flag registers MFR 1 to MFR m and is output as match flag output to match flag output lines MF 1 to MF m . In the match flag, “1” represents “match” and “0” represents “no match”.
- Each match flag output is input to the priority encoder PE.
- the priority encoder PE selects and outputs the address of the highest priority word (highest priority match address: HMA) from the detected words in accordance with the predetermined prioritization. Priority of each word, the word W 1 is the highest, sequentially priority toward the W m shall be low.
- the conventional CAM 1000 used as the associative memory 110-C provided in the associative memory device 200 according to the second embodiment has been described above.
- the associative memory 110-C is provided together with the plurality of index generation units 110-1, 110-2, 110-3,. , 110-3,..., 110-N, even if hash collision cannot be avoided, the associative memory 110-C can realize registration of an arbitrary registration vector. Can be completely eliminated. Since most of the registered vectors can be realized by the plurality of index generation units 110-1, 110-2, 110-3,..., 110-N, the storage capacity of the associative memory 110-C may be small. For this reason, the power consumption of the associative memory 110-C can be suppressed. Therefore, according to the second embodiment, as in the first embodiment, the storage capacity of the associative storage device 200 can be increased while suppressing an increase in bit cost and power consumption, and a hash function can be realized. It is possible to completely avoid the hash collision caused by.
- the update procedure in the experiment is as follows.
- (Procedure 1) k registration vectors are generated and stored in the plurality of index generation units 110-i and the CAM of the associative storage device 100 according to the present invention.
- (Procedure 2) One registration vector is extracted at random from a plurality of registration vectors, and the registration vector is deleted from the associative memory device 100.
- (Procedure 3) A new registration vector is generated and stored in the associative memory device 100.
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Abstract
Description
従って、上記従来のCAMによれば、ビットコスト及び消費電力の観点から記憶容量の大規模化は困難である。
〔定義1〕(登録ベクトル)
相異なるk個(kは自然数)のnビット(nは自然数)のベクトルの集合を考える。このベクトルの集合を登録ベクトル集合(set of registered vectors)といい、登録ベクトル集合に属する各ベクトルを登録ベクトルという。
登録ベクトル集合の各要素と一致する入力に対して1からkまでの固有インデックスに単射し、それ以外の入力に対して0となる関数をインデックス生成関数という。
即ち、関数f(X):Bn→{0,1,…,k}(B={0,1},k∈自然数)において、k個の異なる登録ベクトルai∈Bn(i=1,2,…,k)に対してf(ai)=i(i=1,2,…,k)が成立し、それ以外の(2n-k)個の入力ベクトルaiに対しては、f(ai)=0が成立するとき、f(X)を重みkのインデックス生成関数という。インデックス生成関数は、k個の異なる2値ベクトルに対して、1からkまでの固有インデックスを生成する。なお、本明細書においては、kの値は入力ベクトルの組み合わせ総数2nに比べて十分に小さい(k<<2n)と仮定する。
ハッシュ関数とは、集合Sから整数の集合{0,1,…,m-1}への写像である。ここで、mは、集合Sの要素を超えない自然数である。
(第1実施形態)
1.構成の説明
図1は、本発明の第1実施形態による連想記憶装置100の構成例を示すブロック図である。連想記憶装置100は、検索対象のnビット(nは自然数)の入力ベクトルX(x1,x2,…,xn)に対応した固有のインデックスAを生成して出力するためのものであり、N個(Nは2以上の自然数)のインデックス生成部110-1,110-2,110-3,…,110-N、出力部120、制御部130を備えている。以下では必要に応じて、N個のインデックス生成部110-1,110-2,110-3,…,110-Nのうちの任意の一つを「インデックス生成部110-i」(iは、1からNまでの自然数)と表す。また、インデックス生成部110-1,110-2,110-3,…,110-Nのそれぞれは、インデックス生成器、インデックス生成装置等として単体で取り扱うことができる。
なお、N個のインデックス生成部110-1,110-2,110-3,…,110-Nでそれぞれ用いられるN個のハッシュ関数は、上述の〔定義3〕に従う限り、相互に同一の関数であってもよく、相互に異なる関数であってもよい。即ち、N個のインデックス生成部110-1,110-2,110-3,…,110-Nのそれぞれは、他のインデックス生成部で用いられるハッシュ関数と同一のハッシュ関数を用いてもよく、他のインデックス生成部で用いられるハッシュ関数とは異なるハッシュ関数を用いてもよい。
制御部130は、N個のインデックス生成部110-1,110-2,110-3,…,110-Nのそれぞれに登録された上記の登録情報の更新を制御するためのものである。制御部130からインデックス生成部110-1,110-2,110-3,…,110-Nに対し、登録情報である登録ベクトルの書き込み動作を制御するためのライトイネーブル信号WEと、登録ベクトルのインデックスIDXと、登録情報を書き込むべきインデックス生成部110-1,110-2,110-3,…,110-Nの何れか指定するための選択信号SELが供給される。
なお、制御部130は、指令信号UPDが供給された場合に、動作モードを更新モードに変更する。また、制御部130は、指令信号UPDとインデックスIDXとが供給された場合に、新規な登録情報を追加する動作を行う。また、制御部130は、指令信号UPDのみが供給された場合に、既存の登録情報を削除する動作を行う。
また、制御部130は、例えば、更新モードなどの動作中に、動作中であることを示す信号BSY(ビジー)を出力する。また、制御部130は、例えば、新規な登録情報を追加する動作が失敗した場合に、失敗したことを示す信号FAL(フェイル)を出力する。
図2は、本発明の第1実施形態による連想記憶装置100に備えられたインデックス生成部110-iの構成例を示すブロック図である。インデックス生成部110-iは、ハッシュ回路111、仮インデックス生成回路112、再生ベクトル生成回路113、比較回路114、出力回路115、衝突信号生成回路116を備えている。このうち、ハッシュ回路111は、ハッシュ関数を用いて、nビットの入力ベクトルXから、入力ベクトルXの特徴量を表すpビット(pはnよりも小さい自然数)のベクトルY1を生成するためのものである。ここでは、p=3とする。ハッシュ関数は、異なる入力に対して同じ値を与える場合があり、それをハッシュ衝突(collision)と称す。本実施形態による連想記憶装置100では、或るハッシュ関数でハッシュ衝突が発生した場合、別のインデックス生成部を用いることによりハッシュ衝突を回避する。その詳細については後述する。
なお、上記のハッシュ関数として非線形関数を用いた場合、再生ベクトル生成回路113は、入力ベクトルXの全ビットに対応したnビットの再生ベクトルX’を出力する。
このように、3個のハッシュ回路111(i=1),111(i=2),111(i=3)は、それぞれ異なるハッシュ関数を実現している。
仮インデックス生成回路112は、前述のように、DRAM等の汎用の半導体メモリから構成され、この汎用の半導体メモリは仮インデックス生成回路112の上記の主記憶部を形成する。データの書き込みと読み出しの両方が可能であることを限度に、仮インデックス生成回路112の主記憶部を形成するメモリとして、強誘電体メモリや磁性体メモリ等、任意の方式のメモリを用いることができる。仮インデックス生成回路112の主記憶部を形成するメモリには、登録ベクトルのインデックスに関する情報が登録情報として格納されている。仮インデックス生成回路112の主記憶部を形成する汎用メモリのアドレス入力端子には、ハッシュ回路111から出力されるpビットのベクトルY1の各ビットがアドレス信号として供給される。
再生ベクトル生成回路113は、上述の仮インデックス生成回路112と同様に、DRAM等の汎用の半導体メモリから構成され、この汎用の半導体メモリは再生ベクトル生成回路113の上記の副記憶部を形成する。データの書き込みと読み出しの両方が可能であることを限度に、再生ベクトル生成回路113の副記憶部を形成するメモリとして、強誘電体メモリや磁性体メモリ等、任意の方式のメモリを用いることができる。再生ベクトル生成回路113の副記憶部を形成するメモリには、登録ベクトルのビットの値が登録情報として格納されている。再生ベクトル生成回路113の副記憶部を形成する汎用メモリのアドレス入力端子には、仮インデックス生成回路112から出力されたqビットの仮のインデックスA’の各ビットがアドレス信号として供給される。
図4Aは、本発明の第1実施形態による連想記憶装置100に備えられたインデックス生成部110-iの比較回路114の構成例を示す図である。比較回路114は、一致ゲートである否定的排他的論理和ゲート回路1144,1145,1146から構成されている。否定的排他的論理和ゲート回路1144の入力部には、入力ベクトルXのX2のビットx4と再生ベクトルX2’のビットx4’が供給される。また、否定的排他的論理和ゲート回路1145の入力部には、入力ベクトルXのX2のビットx5と再生ベクトルX2’のビットx5’が供給される。更に、否定的排他的論理和ゲート回路1146の入力部には、入力ベクトルXのX2のビットx6と再生ベクトルX2’のビットx6’が供給される。否定的排他的論理和ゲート回路1144,1145,1146の各出力部は論理積ゲート回路1147の入力部に接続され、論理積ゲート回路1147の出力信号は一致信号MTiとされる。
図4Bは、本発明の第1実施形態による連想記憶装置100に備えられたインデックス生成部110-iの出力回路115の構成例を示す図である。この例では、k=15を考慮して、仮のインデックスA’が4ビット(a1’,a2’,a3’,a4’)で表される場合を想定している。ただし、この例に限定されず、仮のインデックスA’のビット数は任意の値に設定し得る。
図4Cは、本発明の第1実施形態による連想記憶装置100に備えられたインデックス生成部110-iの衝突信号生成回路116の構成例を示す図である。この例でも、k=15を考慮して、仮のインデックスA’が4ビット(a1’,a2’,a3’,a4’)で表される場合を想定している。
以上で、図1に示す連想記憶装置100に備えられたインデックス生成部110-iの構成を説明した。
図5は、本発明の第1実施形態による連想記憶装置100に備えられた出力部120の回路構成例を示す図である。
出力部120は、インデックス生成部110-1,110-2,110-3の個数に対応した3個の論理和ゲート回路1201,1202,1203から構成されている。論理和ゲート回路1201の入力部には、インデックス生成部110-1から出力されたインデックスA1のビットa1と、インデックス生成部110-2から出力されたインデックスA2のビットa1と、インデックス生成部110-3から出力されたインデックスA3のビットa1とが供給される。論理和ゲート回路1201は、インデックス生成部110-1,110-2,110-3からそれぞれ入力されたビットa1の論理和を演算し、その演算結果を、インデックスAのビットa1の値として出力する。
なお、全てのビットが‘1’からなる仮のインデックスA’を無効値として定義した場合、出力部120は、論理和ゲート回路1201,1202,1203に代えて、論理積演算を実施する論理積ゲート回路を備えればよい。
図6は、本発明の第1実施形態による連想記憶装置100に登録される登録情報の一例を示す図である。図6の登録情報は、n=6、k=15、X1=(x1、x2、x3)、X2=(x4,x5,x6)としたときに、入力ベクトルX(x1,x2,x3,x4,x5,x6)の各値と、入力ベクトルXの固有のインデックスAを表すインデックスIDXの値との対応関係を規定している。例えば、入力ベクトルX(x1,x2,x3,x4,x5,x6)の値(0,1,1,0,0,0)に対し、この入力ベクトルXの値に固有のインデックスAを表すインデックスIDXの値として値「1」が対応付けられている。
ただし、この例では、ビットx2、x3のみからインデックスIDXの値「1」及び「2」に対応する登録ベクトルを識別することが可能であり、この場合の登録ベクトルの特徴量としてビットx2,x3の値を用いることもできる。このようにして、X1によって識別可能な登録ベクトルに対応したインデックスIDXの集合が得られる。
図7に示すように、インデックス生成部110-1で実現される登録情報は、上述の図6に示す登録情報のうち、インデックスIDXの8個の値「4」、「5」、「2」、「1」、「11」、「10」、「15」、「3」と、これらのインデックスIDXの値に対応した8個の登録ベクトルのビット(x1,x2,x3,x4,x5,x6)の値との対応関係を規定するように決定される。
この場合、登録ベクトルのX2のビットx4,x5,x6を用いて、インデックス生成部110-2で実現する登録情報のインデックスIDXが決定される。
なお、図8に示す例では、入力ベクトルXの全ビットのうち、ビットx1,x2,x3の値が再生ベクトル生成回路113の副記憶部を構成するメモリに貯えられた値と一致する場合、比較回路114の一致信号MT2の値が‘1’となる。
この例では、上述の図6に示す登録情報のうち、インデックスIDXの5個の値「9」、「14」に関する登録情報が実現されている。この場合、登録情報のうち、インデックスIDXの値「9」、「14」に関する情報は、ビットy1,y2,y3の値によって指定される仮インデックス生成回路112の主記憶部のメモリセルに格納される。また、インデックスIDXの値「9」、「14」に対応した登録ベクトルのビット(y1,y2,y3,x4,x5,x6)の各値は、インデックスIDXの値「9」、「14」を表す仮のインデックスA’によって指定される再生ベクトル生成回路113の副記憶部のメモリセルに格納される。
なお、図9に示す例では、入力ベクトルXの全ビットのうち、ビットx4,x5,x6の値が再生ベクトル生成回路113の副記憶部を構成するメモリに貯えられた値と一致する場合、比較回路114の一致信号MT3の値が‘1’となる。
次に、第1実施形態による連想記憶装置100の通常の検索モードでの動作を説明する。通常の検索モードでの動作時には、入力ベクトルXに応答して、3個のインデックス生成部110-1,110-2,110-3のうち、一つのインデックス生成部110-iが有効値を示すインデックスAiを出力する。他の二つのインデックス生成部110-iは無効値を出力する。出力部120は、3個のインデックス生成部110-1,110-2,110-3からそれぞれ出力されたインデックスA1,A2,A3を結合してインデックスAを生成して出力する。このインデックスAは、3個のインデックス生成部110-1,110-2,110-3から出力されたインデックスA1,A2,A3のうち、有効値を示すインデックスAiと同値になる。入力ベクトルXがインデックス生成部110-1,110-2,110-3に設定された登録ベクトルのいずれとも一致しない場合は、すべてのインデックス生成部110-1,110-2,110-3が無効値を生成する。
更新モードでの動作として、既存の登録情報を削除する動作と、新規な登録情報を追加する動作がある。更新モードにおいて、制御部130は、登録情報として登録された既存の登録ベクトルが存在する場合、その既存の登録ベクトルに対応するインデックスを削除した後、登録情報として新規な登録ベクトルのインデックスを追加することにより、登録情報を更新する。更新モードにおいて登録情報を更新するための動作は制御部130により制御される。
ここでは、図13を参照して、上述した制御部130による既存の登録情報を削除する動作の一例について説明する。
図13は、本発明の第1実施形態による登録情報の削除方法の一例を示すフローチャートである。
既存の登録情報を削除する場合、連想記憶装置100を管理するシステム(図示なし)から、連想記憶装置100の制御部130に、更新モードの起動を示す指令信号UPDが供給される。そして、図13に示すように、指令信号UPDが制御部130に供給されると、制御部130は、削除すべき登録ベクトルを入力ベクトルとして、複数のインデックス生成部110-iに供給する(ステップS101)。すなわち、3個のインデックス生成部110-1,110-2,110-3には、削除すべき登録ベクトルが入力ベクトルXとして共通に供給される。
ここで、削除すべき登録ベクトルが存在すると、衝突が発生するので、衝突信号CDiおよび一致信号MTiが値‘1’を示す。この一致信号MTiから削除すべき登録ベクトルに対応するインデックス生成部を特定することができる。
第1段階:更新モードにおいて、削除すべき既存の登録ベクトルを入力ベクトルXとして複数のインデックス生成部110-1,110-2,110-3に供給する。
第2段階:複数のインデックス生成部110-1,110-2,110-3のそれぞれについて、制御部130は、一致信号MTiに基づき、削除すべき既存の登録ベクトルに対応した固有のインデックスが登録情報として存在するか否かを判定する。
第3段階:複数のインデックス生成部110-1,110-2,110-3の何れかにおいて、既存の登録ベクトルに対応した固有のインデックスが登録情報として存在する場合、制御部130は、登録情報として存在する既存の登録ベクトルのインデックスの値を有効値から無効値に変更する。
ここでは、図14を参照して、上述した制御部130による新規な登録情報を追加する動作の一例について説明する。
図14は、本発明の第1実施形態による新規情報の追加方法の一例を示すフローチャートである。
新規な登録ベクトルを追加する場合、連想記憶装置100を管理するシステムから、連想記憶装置100の制御部130に、更新モードの起動を示す指令信号UPDが供給される。また、同システムから、追加すべき登録ベクトルのインデックスIDXが供給される。そして、図14に示すように、指令信号UPDとインデックスIDXとが制御部130に供給されると、制御部130は、追加登録ベクトルを入力ベクトルとして、複数のインデックス生成部110-iに供給する(ステップS201)。すなわち、3個のインデックス生成部110-1,110-2,110-3には、追加すべき登録ベクトルが入力ベクトルXとして供給される。
第1段階:追加すべき新規な登録ベクトルを入力ベクトルXとして複数のインデックス生成部110-1,110-2,110-3に供給する。
第2段階:複数のインデックス生成部110-1,110-2,110-3のそれぞれについて、制御部130により、衝突信号CDiに基づき、追加すべき新規な登録ベクトルに対応した仮のインデックスが登録情報として存在するか否かを判定する。
第3段階:複数のインデックス生成部110-1,110-2,110-3の何れかにおいて、新規な登録ベクトルに対応した仮のインデックスが登録情報として存在しない場合、新規な登録ベクトルに対応したインデックスの値として有効値を設定する。
従って、第1実施形態によれば、ビットコストと消費電力の上昇を抑制しつつ、連想記憶装置100の記憶容量を大規模化することが可能となる。
次に、本発明の第2実施形態を説明する。
図10は、本発明の第2実施形態による連想記憶装置200の構成例を示すブロック図である。
図11は、本発明の第2実施形態による連想記憶装置200に備えられた連想メモリ110-Cとして用いられる従来型のCAM1000の基本構成の一例を表すブロック図である(特許文献1参照)。CAM1000は、比較レジスタ1001、検索ビット線ドライバ1002、m個のワードW1~Wm、m個の一致センス回路MSC1~MSCm、m個の一致フラグレジスタMFR1~MFRm、及びプライオリティ・エンコーダ(優先度付符号化回路)PEを備えている。
この状態で、一致線MLが‘H’(=‘1’)状態にプリチャージされる。尚、一致線MLは‘H’が「一致」を表す。
従って、1ワードを構成するmビットのCAMセル1003のすべてにおいて一致が検出された場合に限り、一致線MLは‘H’(「一致」)の状態に保持される。一方、1ビットでもCAMセル1003で不一致が検出されると、一致線MLは‘L’(「不一致」)の状態となる。
以上で、第2実施形態による連想記憶装置200に備えられた連想メモリ110-Cとして用いられる従来型のCAM1000を説明した。
(手順1)k個の登録ベクトルを生成し、本発明による連想記憶装置100の複数のインデックス生成部110-iとCAMに格納する。
(手順2)複数の登録ベクトルの中からランダムに1つの登録ベクトルを取り出して、その登録ベクトルを連想記憶装置100から削除する。
(手順3)新規な登録ベクトルを生成し、連想記憶装置100に格納する。
上記の実験により、上述の実施形態による連想記憶装置の有効性を確認することができた。
110-1,110-2,110-3,110-i,110-N…インデックス生成部
110-C…連想メモリ
111…ハッシュ回路
112…仮インデックス生成回路
113…再生ベクトル生成回路
114…比較回路
115…出力回路
116…衝突信号生成回路
120…出力部
130…制御部
1000…CAM
1003…CAMセル
Claims (15)
- 複数のハッシュ関数を用いて入力ベクトルの特徴量を生成し、前記特徴量に基づき登録ベクトルに関する登録情報を検索することにより前記入力ベクトルに対応したインデックスを生成する複数のインデックス生成部と、
前記複数のインデックス生成部の各出力を結合して前記入力ベクトルに対応したインデックスを出力する出力部と、
前記登録情報の更新を制御する制御部と、
を備え、
前記複数のインデックス生成部のそれぞれは、
前記特徴量に基づき生成されたインデックスが前記登録情報として存在するか否かを示す第1信号を生成して前記制御部に供給すると共に、前記特徴量に基づき生成されたインデックスを用いて前記入力ベクトルの再生ベクトルを生成し、前記再生ベクトルが前記入力ベクトルと一致するか否かを示す第2信号を生成して前記制御部に供給する、連想記憶装置。 - 前記複数のインデックス生成部のそれぞれは、
前記入力ベクトルから前記入力ベクトルの特徴量を算出するためのハッシュ回路と、
前記登録ベクトルのインデックスが前記登録情報として格納された主記憶部を有し、前記主記憶部から前記特徴量に対応した仮のインデックスを読み出して出力する仮インデックス生成回路と、
前記仮インデックス生成回路から出力された仮のインデックスに基づいて前記第1信号を生成して出力する衝突信号生成回路と、
前記登録ベクトルが前記登録情報として格納された副記憶部を有し、前記副記憶部から前記仮のインデックスに対応したベクトルを読み出して前記再生ベクトルとして出力する再生ベクトル生成回路と、
前記再生ベクトルと前記入力ベクトルとを比較し、前記再生ベクトルと前記入力ベクトルとが一致するか否かを示す前記第2信号を出力する比較回路と、
前記第2信号が前記再生ベクトルと前記入力ベクトルとの一致を示す場合、前記仮のインデックスを前記入力ベクトルに対応した固有のインデックスとして出力し、前記第2信号が前記再生ベクトルと前記入力ベクトルとの不一致を示す場合、無効値を出力する出力回路と、
を備えた請求項1に記載の連想記憶装置。 - 前記主記憶部と前記副記憶部が、1つのメモリに統合された、請求項2に記載の連想記憶装置。
- 前記主記憶部は、前記特徴量を示すビット列がアドレス信号として入力されるメモリから構成された、請求項2または3に記載の連想記憶装置。
- 前記副記憶部は、前記仮のインデックスを示すビット列がアドレス信号として入力されるメモリから構成された、請求項2から4の何れか1項に記載の連想記憶装置。
- 前記複数のインデックス生成部のうちの一部のインデックス生成部に代えて、または、前記複数のインデックス生成部に加えて、CAMセルを有する連想メモリを備えた、請求項1から5の何れか1項に記載の連想記憶装置。
- 前記制御部は、
前記登録情報として登録ベクトルとそのインデックスとを追加する場合、追加すべき登録ベクトルが前記登録情報として存在しない旨を示す前記第1信号を供給するインデックス生成部を選択し、選択した当該インデックス生成部の登録情報として、前記追加すべき登録ベクトルに対応するインデックスを追加する、請求項1から6の何れか1項に記載の連想記憶装置。 - 前記制御部は、
前記登録情報として登録された登録ベクトルのインデックスを削除する場合、前記複数のインデックス生成部のうち、削除すべき登録ベクトルのインデックスを用いて生成された再生ベクトルが前記入力ベクトルと一致する旨を示す前記第2信号を供給するインデックス生成部を選択し、選択した当該インデックス生成部の登録情報から、前記登録ベクトルに対応するインデックスを削除する、請求項1から7の何れか1項に記載の連想記憶装置。 - 入力ベクトルから前記入力ベクトルの特徴量を算出して出力するハッシュ回路と、
登録ベクトルに関する登録情報として前記登録ベクトルに対応するインデックスが格納された主記憶部を有し、前記主記憶部から前記特徴量に対応した仮のインデックスを読み出して出力する仮インデックス生成回路と、
前記仮インデックス生成回路から出力された仮のインデックスに基づいて、前記特徴量に対応した仮のインデックスが前記登録情報として存在するか否かを示す第1信号を生成して出力する信号生成回路と、
前記登録ベクトルに関する登録情報として前記登録ベクトルが格納された副記憶部を有し、前記副記憶部から前記仮のインデックスに対応したベクトルを読み出して再生ベクトルとして出力する再生ベクトル生成回路と、
前記再生ベクトルと前記入力ベクトルとを比較し、前記再生ベクトルと前記入力ベクトルとが一致するか否かを示す第2信号を出力する比較回路と、
前記第2信号が前記再生ベクトルと前記入力ベクトルとの一致を示す場合、前記仮のインデックスを前記入力ベクトルに対応した固有のインデックスとして出力する出力回路と、
を備えたインデックス生成器。 - 請求項1から8の何れか1項に記載の連想記憶装置の登録情報を更新する情報更新方法であって、
前記連想記憶装置は、動作モードとして、検索モードと更新モードとを備え、
前記連想記憶装置に備えられた制御部は、前記更新モードにおいて前記登録情報を更新するための制御を実施する、情報更新方法。 - 前記検索モードにおいて、前記複数のインデックス生成部と前記出力部とが連想メモリとして機能する、請求項10に記載の情報更新方法。
- 前記更新モードにおいて、前記制御部は、前記登録情報として登録された登録ベクトルに対応するインデックスを削除した後、前記登録情報として追加すべき登録ベクトルに対応するインデックスを追加することにより、前記登録情報を更新する、請求項10または11に記載の情報更新方法。
- 前記更新モードにおいて、
削除すべき登録ベクトルを前記入力ベクトルとして前記連想記憶装置に備えられた複数のインデックス生成部に供給する第1段階と、
前記複数のインデックス生成部のそれぞれについて、前記制御部により、前記第2信号に基づき、前記削除すべき登録ベクトルに対応した固有のインデックスが前記登録情報として存在するか否かを判定する第2段階と、
前記複数のインデックス生成部の何れかにおいて、前記削除すべき登録ベクトルに対応した固有のインデックスが前記登録情報として存在する場合、前記制御部により、前記登録情報として存在する前記削除すべき登録ベクトルに対応するインデックスの値を有効値から無効値に変更する第3段階と、
を含む請求項12に記載の情報更新方法。 - 前記更新モードにおいて、
追加すべき登録ベクトルを前記入力ベクトルとして前記複数のインデックス生成部に供給する第1段階と、
前記複数のインデックス生成部のそれぞれについて、前記制御部により、前記第1信号に基づき、前記追加すべき登録ベクトルに対応した仮のインデックスが前記登録情報として存在するか否かを判定する第2段階と、
前記複数のインデックス生成部の何れかにおいて、前記追加すべき登録ベクトルに対応した仮のインデックスが前記登録情報として存在しない場合、前記追加すべき登録ベクトルに対応したインデックスの値として有効値を設定する第3段階と、
を含む請求項12または13に記載の情報更新方法。 - 前記複数のインデックス生成部の何れかにおいて、前記追加すべき登録ベクトルに対応した仮のインデックスが前記登録情報として存在する場合、前記制御部により、前記追加すべき登録ベクトルに対応した仮のインデックスが存在しない他のインデックス生成部において、前記追加すべき登録ベクトルに対応したインデックスの値として有効値を設定する、請求項14に記載の情報更新方法。
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US11397561B2 (en) * | 2019-09-05 | 2022-07-26 | SK Hynix Inc. | Nonvolatile memory device performing a multiplicaiton and accumulation operation |
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