WO2016016776A1 - Semiconductor device and method for evaluating semiconductor device - Google Patents

Abstract

Provided is a transistor having a low sub-threshold swing value. Also provided is a transistor with a low defect level density of the semiconductor. Also provided is a transistor having excellent electrical characteristics. Also provided is a transistor with stable electrical characteristics. Also provided is a transistor having high frequency characteristics. Also provided is a transistor having minimal current when turned off. Also provided is a semiconductor device having said transistor. This semiconductor device comprises an insulating body, a semiconductor, and a conductive body. The semiconductor has an area in which the semiconductor and the conductive body overlap with one another, with the insulating body interposed therebetween. In this area, there is an area in which of the carrier lifetime due to the microwave photoconductive attenuation of the semiconductor, the component that is rapidly attenuated is from 30nsec to 200nsec. The microwave photoconductive attenuation uses excitation light having a wavelength of less than 337nm.

Description

Semiconductor device and method for evaluating semiconductor device

The present invention relates to, for example, a semiconductor, a transistor, and a semiconductor device. Alternatively, the present invention relates to a semiconductor, a transistor, and a semiconductor device evaluation method. Alternatively, the present invention relates to a method for manufacturing a semiconductor, a transistor, and a semiconductor device. Alternatively, the present invention relates to, for example, a semiconductor, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, and an electronic device. Alternatively, the present invention relates to a method for manufacturing a semiconductor, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device. Alternatively, the present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

A technique for forming a transistor using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is widely applied to semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor applicable to a transistor.

As silicon used for a semiconductor of a transistor, amorphous silicon and polycrystalline silicon are selectively used depending on the application. For example, when applied to a transistor included in a large display device, it is preferable to use amorphous silicon in which a technique for forming a film over a large-area substrate is established. On the other hand, when applied to a transistor included in a high-function display device in which a driver circuit and a pixel circuit are formed over the same substrate, it is preferable to use polycrystalline silicon that can manufacture a transistor with high field-effect mobility. It is. A method of forming polycrystalline silicon by performing heat treatment at high temperature or laser light treatment on amorphous silicon is known.

Thereafter, a transistor including an oxide semiconductor is disclosed (see Patent Document 1). An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a semiconductor of a transistor included in a large display device. In addition, since a transistor including an oxide semiconductor has high field effect mobility, a highly functional display device in which a driver circuit and a pixel circuit are formed over the same substrate can be realized. Further, since it is possible to improve and use a part of the production facility for transistors using amorphous silicon, there is an advantage that capital investment can be suppressed.

In addition, as a method for non-contact evaluation of various characteristics of an oxide semiconductor, a method of irradiating an oxide semiconductor with excitation light and microwave and measuring a reflected wave of the microwave that changes due to excitation light irradiation is disclosed. (See Patent Document 2 and Patent Document 3.) Patent Document 2 shows that an amorphous oxide semiconductor has a penetration length (also referred to as an intrusion length or an intrusion length) of excitation light having a wavelength of 349 nm of about 10 nm.

Non-Patent Document 1 discloses the relationship between the spin density and conductivity of an In—Ga—Zn oxide, which is a typical oxide semiconductor, by electron spin resonance (ESR: Electron Spin Resonance). In addition, as a carrier generation source of the In—Ga—Zn oxide, oxygen vacancies and defect levels due to hydrogen are shown.

11-505377 JP 2012-33857 A JP 2014-19911 A

Another object is to provide a non-contact evaluation method for various characteristics of a semiconductor. Another object is to provide a method for evaluating various characteristics of a wide-gap semiconductor without contact. Another object is to provide a method for evaluating characteristics of an oxide semiconductor in a non-contact manner.

Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a transistor with a low density of defect states in a semiconductor. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor having high frequency characteristics. Another object is to provide a transistor with a low off-state current. Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a new module. Another object is to provide a novel electronic device.

Another object is to provide a method for evaluating the defect state density of a semiconductor in a transistor.

Another object is to manufacture a transistor with high yield. Another object is to manufacture a transistor with high productivity. Another object is to manufacture a transistor at low cost. Another object is to manufacture a semiconductor device including the transistor with high yield. Another object is to manufacture a semiconductor device including the transistor with high productivity. Another object is to inexpensively manufacture a semiconductor device including the transistor.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

(1)
One embodiment of the present invention includes an insulator, a semiconductor, and a conductor. The semiconductor includes a region where the semiconductor and the conductor overlap with each other with the insulator interposed therebetween. This is a semiconductor device having a region in which the component that rapidly decays out of the lifetime of the carrier by the wave photoconductive decay method is 30 nsec or more.

(2)
Alternatively, according to one embodiment of the present invention, in (1), the microwave photoconductive decay method is a semiconductor device using excitation light having a wavelength of less than 337 nm.

(3)
Alternatively, according to one embodiment of the present invention, in (1) or (2), the semiconductor includes an oxide having one or more selected from indium, zinc, and an element M (the element M is aluminum, gallium, yttrium, or tin). It is a semiconductor device having.

A method for evaluating various characteristics of a semiconductor in a non-contact manner can be provided. Alternatively, it is possible to provide a method for evaluating various characteristics of a wide gap semiconductor without contact. Alternatively, a method for evaluating various characteristics of an oxide semiconductor in a non-contact manner can be provided.

A transistor with a small subthreshold swing value can be provided. Alternatively, a transistor with a low density of defect states in a semiconductor can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor with stable electric characteristics can be provided. Alternatively, a transistor having high frequency characteristics can be provided. Alternatively, a transistor with low off-state current can be provided. Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a new module can be provided. Alternatively, a novel electronic device can be provided.

Alternatively, a method for evaluating the defect state density of a semiconductor in a transistor can be provided.

Alternatively, a transistor can be manufactured with high yield. Alternatively, a transistor can be manufactured with high productivity. Alternatively, a transistor can be manufactured at low cost. Alternatively, a semiconductor device including the transistor can be manufactured with high yield. Alternatively, a semiconductor device including the transistor can be manufactured with high productivity. Alternatively, a semiconductor device including the transistor can be manufactured at low cost.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

The schematic diagram of the apparatus which performs evaluation by the microwave photoconductive decay method which concerns on 1 aspect of this invention. The schematic diagram of the apparatus which performs evaluation by the microwave photoconductive decay method which concerns on 1 aspect of this invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a perspective view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. 4A and 4B are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an electronic device according to one embodiment of the present invention. The figure which shows the spin density evaluated by electron spin resonance. The figure which shows the peak value of the reflectance of the microwave evaluated by the microwave photoconductive decay method. The figure which shows the relationship between a spin density and the peak value of the reflectance of a microwave.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach a code in particular.

Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

Note that in this specification, the expression “film” and the expression “layer” can be interchanged with each other.

In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

Note that even when “semiconductor” is described, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% is an impurity. By including impurities, for example, DOS (Density of State) may be formed in a semiconductor, carrier mobility may be reduced, and crystallinity may be reduced. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Note that in this specification, when it is described that A has a region having a concentration B, for example, when the concentration in the entire depth direction in a region with A is B, the concentration in the depth direction in a region with A When the average value of B is B, when the median value of the concentration in the depth direction in the region of A is B, when the maximum value of the concentration in the depth direction of the region of A is B, there is A When the minimum value of the density in the depth direction in the region is B, and when the convergence value of the density in the depth direction in the region of A is B, the concentration in the region where a probable value of A itself is obtained in the measurement. Including the case of B.

Further, in this specification, when A is described as having a region having a size B, a length B, a thickness B, a width B, or a distance B, for example, the entire size and length in a region with A When the thickness, width, or distance is B, the average value of the size, length, thickness, width, or distance in a region of A is B, and the size, length in the region of A is When the median value of thickness, thickness, width, or distance is B, when the maximum value of size, length, thickness, width, or distance in a region of A is B, in the region of A Measured when the minimum value of size, length, thickness, width, or distance is B, and when the converged value of size, length, thickness, width, or distance in a region of A is B The size, length, thickness, width, or distance in a region where a probable value of A above is obtained is B Case, and the like.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other in a top view of a transistor is referred to as an “enclosed channel width ( SCW: Surrounded Channel Width). In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

Note that in this specification, when A is described as having a shape protruding from B, in a top view or a cross-sectional view, it indicates that at least one end of A has a shape that is outside of at least one end of B. There is a case. Therefore, when it is described that A has a shape protruding from B, for example, in a top view, it can be read that one end of A has a shape outside of one end of B.

In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

<Microwave photoconductive decay method>
The microwave photoconductive decay method will be described below with reference to the drawings.

FIG. 1 is a schematic view showing an example of an apparatus for performing a microwave photoconductive decay method. The apparatus shown in FIG. 1 is suitable for evaluating a thin film of a wide gap semiconductor. In particular, it is suitable for evaluation of a wide gap semiconductor of 1 nm to 1 μm, 2 nm to 500 nm, 3 nm to 200 nm, or 5 nm to 100 nm, which is used for a semiconductor of a transistor.

The apparatus shown in FIG. 1 includes a pulse laser oscillator 301, a microwave oscillator 302, a directional coupler 303, a waveguide 305, a mixer 306, a signal processing device 307, and a sample stage 311. In FIG. 1, the waveguide 305 has a shape in which a corner portion has a curvature, but is not limited thereto. A sample 320 can be placed on the sample stage 311. The sample 320 includes, for example, a substrate 320b and a semiconductor 320a on the substrate 320b.

A conductor is disposed on the upper surface of the sample stage 311. As conductors, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, iron, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin A conductor containing one or more of tantalum and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or compound such as stainless steel, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, titanium and nitrogen Alternatively, a conductor containing any of the above may be used.

Note that the spacer 310 may be disposed between the sample 320 and the sample stage 311. The spacer 310 includes a single layer of an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Or may be used in a stacked manner. For example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.

The thickness of the spacer 310 may be selected so that, for example, the distance between the upper surface of the semiconductor 320a and the upper surface of the sample stage 311 is about 1/4 of the wavelength of the microwaves in the substrate 320b and the spacer 310. Note that by arranging the spacer 310, evaluation may be possible even when the sample 320 is arranged upside down. By arranging the sample 320 upside down, for example, information including much influence of the interface between the substrate 320b and the semiconductor 320a may be obtained.

Below, the evaluation method by the microwave photoconductive decay method of the semiconductor 320a is shown.

First, microwaves are radiated from the microwave oscillator 302. The emitted microwave is particularly called a traveling wave (also called an incident wave). A traveling wave is divided into a waveguide 305 and a phase shifter 315 through the directional coupler 303. The traveling wave that has passed through the waveguide 305 enters the sample 320. At this time, the microwave (particularly referred to as a reflected wave) reflected by the semiconductor 320 a of the sample 320 passes through the waveguide 305 again. The reflected wave is mixed with the traveling wave separated by the mixer 306 via the phase shifter 315. The mixed signal is detected by the signal processing device 307.

At this time, the intensity of the signal detected by the signal processing device 307 varies depending on the reflectance of the microwave in the semiconductor 320a. For example, the higher the carrier density of the semiconductor 320a, the higher the microwave reflectance.

The semiconductor 320a generates holes and electrons by absorbing excitation light. That is, by irradiating the semiconductor 320a with excitation light, the carrier density of the semiconductor 320a is increased. Excitation light may be applied to the semiconductor 320a through the mirror 313 and the lens 314.

Since the reflectance of the microwave has a positive correlation with the carrier density, the reflectance of the microwave in the semiconductor 320a is increased by irradiating the semiconductor 320a with excitation light. When excitation light is continuously applied to the semiconductor 320a for a certain period of time, the reflectance of the microwave takes a constant value due to a balance between generation of carriers by the excitation light and disappearance of carriers due to recombination or the like. Since this value is the highest value of the reflectance of the microwave, it can be called the peak value of the reflectance. The peak value of the reflectance may vary depending on the defect level density of the semiconductor 320a. Specifically, when the density of shallow defect states in the semiconductor 320a is high, the peak value of the reflectance is low. Further, when the density of shallow defect states of the semiconductor 320a is low, the peak value of the reflectance is high. This is presumably because the defect level promotes the disappearance of carriers.

As the excitation light, for example, laser light emitted from the pulse laser oscillator 301 can be used. The laser light preferably has a wavelength of energy sufficiently higher than the energy gap of the semiconductor 320a. In particular, laser light having an entry length of less than 250 nm, less than 100 nm, less than 70 nm, or less than 50 nm may be used. For example, laser light having a wavelength of less than 337 nm, less than 315 nm, less than 300 nm, or less than 270 nm may be used. In order to suppress an increase in the cost of the optical system, the wavelength of the laser light is preferably set to 200 nm or more. However, laser light having a wavelength of less than 200 nm may be used. Note that the wavelength of a four times higher long wave of a laser (also referred to as a YLF laser) using yttrium lithium fluoride to which neodymium is added as a laser medium is 266 nm. The light penetration length is a depth at which the light intensity is attenuated to 1 / e, and can be expressed by the following equation.

Here, d indicates an approach length [nm], λ indicates a wavelength [nm], and k indicates an attenuation coefficient.

For example, if laser light having a wavelength sufficiently higher than the energy gap of the semiconductor 320a is not used, the output of the laser light must be increased to some extent in order to increase detection sensitivity. Therefore, the semiconductor 320a may be altered. By using laser light having a wavelength sufficiently higher than the energy gap of the semiconductor 320a, the carrier density of the semiconductor 320a can be sufficiently increased even when the output of the laser light is reduced. Therefore, the alteration of the semiconductor 320a as described above can be suppressed.

In addition, by using laser light with a short entry length into the semiconductor 320a, it is possible to suppress the information on the base such as the substrate 320b from being reflected in the measurement result. In addition, due to the interference effect, it is possible to suppress the occurrence of unevenness in the measurement result according to the thickness of the semiconductor 320a.

Next, when the irradiation of the excitation light to the semiconductor 320a is stopped, the generation of carriers is stopped, and the carrier density of the semiconductor 320a is reduced. That is, the reflectance of the microwave is lowered. Note that since the reflectance of the microwave has a positive correlation with the carrier density, the lifetime of the carrier in the semiconductor 320a can also be measured. The lifetime of the carrier can be divided into a component (also referred to as τ1) that attenuates rapidly and a component (also referred to as τ2) that attenuates slowly from the peak value of the reflectance of the microwave. The method for deriving τ1 and τ2 by the microwave photoconductive decay method is described in S.A. Yasuno, et al. : Journal of Applied Physics 2012 vol. The description of 112,053715 is referred to.

As described above, the semiconductor 320a can be evaluated by the microwave photoconductive decay method. In addition, by moving the sample stage 311 in the X direction and the Y direction, it is possible to evaluate a plurality of places in the plane of the substrate 320b.

As shown in FIG. 2, a device having two waveguides of the waveguide 305a and the waveguide 305b and the magic T304 may be used. Note that the waveguide 305a and the waveguide 305b are preferably symmetric. Alternatively, the microwave path lengths of the waveguide 305a and the waveguide 305b may be the same. In FIG. 2, the waveguide 305a and the waveguide 305b have shapes in which the corners have a curvature, but are not limited thereto.

Also in the case of FIG. 2, first, microwaves are radiated from the microwave oscillator 302. A traveling wave is split into a magic T 304 and a phase shifter 315 via the directional coupler 303. In the magic T304, the traveling wave is divided into the waveguide 305a and the waveguide 305b. The traveling wave that has passed through the waveguide 305a enters the sample 320 together with the excitation light. Further, the traveling wave that has passed through the waveguide 305b is incident on the sample 320 as it is. At this time, the microwave reflected by the semiconductor 320a of the sample 320 returns again to the magic T304 through the waveguides 305a and 305b. The reflected waves that have passed through the waveguides 305a and 305b merge again at the magic T304, and the magic T304 outputs their sum signal. Then, in the mixer 306, the traveling wave separated through the phase shifter 315 is mixed. The mixed signal is detected by the signal processing device 307.

At this time, the reflected wave passing through the waveguide 305b includes the same amount of noise caused by the microwave oscillator 302, disturbance due to mechanical vibration, and the like as the reflected wave passing through the waveguide 305a. Therefore, the influence of noise or the like can be reduced by taking the sum signal. Therefore, the apparatus shown in FIG. 2 can detect the change in the reflectance of the microwave due to the excitation light with higher sensitivity.

<Wide gap semiconductor>
A wide gap semiconductor is a semiconductor having a larger energy gap than silicon or the like. Specifically, it refers to a semiconductor having an energy gap of 2 eV or more and 5 eV or less, 2.2 eV or more and 4.6 eV or less, particularly 2.5 eV or more and 4.0 eV or less.

Since the wide gap semiconductor has a large energy gap, the penetration length of a laser beam having a wavelength of 349 nm or the like that has been used in silicon or the like in the microwave photoconductive decay method becomes deep. Therefore, the above-described problems may occur. In particular, in a wide gap semiconductor with a low density of defect states, the laser beam penetration length may be deeper than previously thought.

For example, a typical wide gap semiconductor includes an oxide semiconductor. The structure of the oxide semiconductor will be described below.

An oxide semiconductor is classified into a non-single-crystal oxide semiconductor and a single-crystal oxide semiconductor. Alternatively, an oxide semiconductor is classified into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor.

Note that examples of the non-single-crystal oxide semiconductor include a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. As a crystalline oxide semiconductor, a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or the like can be given.

First, the CAAC-OS will be described.

The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts.

A plurality of crystal parts can be confirmed by observing a bright field image of CAAC-OS and a combined analysis image of diffraction patterns (also referred to as a high-resolution TEM image) with a transmission electron microscope (TEM: Transmission Electron Microscope). it can. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

When a high-resolution TEM image of a cross section of the CAAC-OS is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in a layered manner in the crystal part. Each layer of metal atoms has a shape reflecting a surface on which a CAAC-OS film is formed (also referred to as a formation surface) or unevenness on an upper surface, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS.

On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When structural analysis is performed on the CAAC-OS using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS having an InGaZnO ₄ crystal by an out-of-plane method, the diffraction angle A peak may appear in the vicinity of (2θ) of 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed.

Note that in the analysis of the CAAC-OS including an InGaZnO ₄ crystal by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. The CAAC-OS preferably has a peak at 2θ of around 31 ° and a peak at 2θ of around 36 °.

The CAAC-OS is an oxide semiconductor with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc. have large atomic radii (or molecular radii). If they are contained inside an oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed and the crystallinity is lowered. It becomes a factor to make. Note that the impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source.

A CAAC-OS is an oxide semiconductor with a low density of defect states. For example, oxygen vacancies in an oxide semiconductor can serve as a carrier trap or a carrier generation source by capturing hydrogen. Therefore, the laser light penetration length may be deeper than that of the amorphous OS.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier traps. Therefore, a transistor including the oxide semiconductor is a highly reliable transistor with little variation in electrical characteristics. Note that the charge trapped in the carrier trap of the oxide semiconductor takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

In addition, a transistor using a CAAC-OS has little change in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, a microcrystalline oxide semiconductor will be described.

A microcrystalline oxide semiconductor has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor including a nanocrystal (nc: nanocrystal) that is 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor). In addition, for example, the nc-OS may not clearly confirm the crystal grain boundary in a high-resolution TEM image.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In the nc-OS, regularity is not observed in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an amorphous oxide semiconductor depending on an analysis method. For example, when structural analysis is performed on the nc-OS using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. When nc-OS is subjected to electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a larger probe diameter (eg, 50 nm or more) than the crystal part, a diffraction pattern such as a halo pattern is observed. The On the other hand, when nanobeam electron diffraction is performed on the nc-OS using an electron beam having a probe diameter that is close to or smaller than that of the crystal part, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS, a plurality of spots may be observed in the ring-shaped region.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS. Therefore, the laser light penetration length may be deeper than that of the amorphous OS.

Next, an amorphous oxide semiconductor will be described.

An amorphous oxide semiconductor is an oxide semiconductor in which atomic arrangement in a film is irregular and does not have a crystal part. An example is an oxide semiconductor having an amorphous state such as quartz.

In an amorphous oxide semiconductor, a crystal part cannot be confirmed in a high-resolution TEM image.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. In addition, when electron diffraction is performed on an amorphous oxide semiconductor, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor, no spot is observed and a halo pattern is observed.

Note that an oxide semiconductor may have a structure exhibiting physical properties between the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS: amorphous-Semiconductor).

In the a-like OS, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. The a-like OS may be crystallized due to a small amount of electron irradiation as observed by a TEM, and a crystal part may be grown. On the other hand, in the case of a good quality nc-OS, there is almost no crystallization due to a small amount of electron irradiation as observed by TEM.

Note that the crystal part size of the a-like OS and the nc-OS can be measured using high-resolution TEM images. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.

An oxide semiconductor may have a different density for each structure. For example, if the composition of a certain oxide semiconductor is known, the structure of the oxide semiconductor can be estimated by comparing with the density of a single crystal having the same composition as the composition. For example, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal. For example, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% with respect to the density of the single crystal. Note that it is difficult to form an oxide semiconductor whose density is lower than 78% with respect to that of a single crystal.

The above will be described using a specific example. For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that there may be no single crystal having the same composition. In that case, a density corresponding to a single crystal having a desired composition can be calculated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to calculate the density of the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably calculated by combining as few kinds of single crystals as possible.

Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS, for example.

The above is the description of the structure of the oxide semiconductor.

A semiconductor having a low density of defect states can obtain high efficiency and high reliability when used for a transistor, a photoelectric conversion element, a light-emitting element, or the like. For example, a semiconductor having a region in which the component τ1 that quickly decays in the lifetime of carriers by the above-described microwave photoconductive decay method is 30 nsec or more, preferably 40 nsec or more is suitable for a transistor, a photoelectric conversion element, a light-emitting element, or the like It is. Note that τ1 becomes shorter as carrier recombination easily occurs. Since carrier recombination is more likely to occur as the impurity level density is higher, longer τ1 is preferable.

<Transistor>
The transistor according to one embodiment of the present invention is described below.

<Transistor structure>
3A and 3B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. 3A is a top view, and FIG. 3B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 3A, some elements are omitted for clarity.

3A and 3B includes a conductor 413 over a substrate 400, an insulator 402 having a convex portion over the substrate 400 and the conductor 413, and a convex portion of the insulator 402. The semiconductor 406a, the semiconductor 406b over the semiconductor 406a, the layers 409a and 409b which are in contact with and spaced from the top and side surfaces of the semiconductor 406b, the conductor 416a over the layer 409a, and the conductive over the layer 409b. Body 416b, semiconductor 406b, layer 409a, layer 409b, semiconductor 406c on conductor 416a and conductor 416b, insulator 412 on semiconductor 406c, conductor 404 on insulator 412, and conductor An insulator 408 over the body 416a, over the conductor 416b, and over the conductor 404, and an insulator 418 over the insulator 408 are included. Note that although the conductor 413 is part of the transistor here, the invention is not limited to this. For example, the conductor 413 may be a component independent of the transistor.

Note that the semiconductor 406c is in contact with at least the top surface and the side surface of the semiconductor 406b in the A3-A4 cross section. In addition, the conductor 404 faces the top surface and the side surface of the semiconductor 406b through the semiconductor 406c and the insulator 412 in the A3-A4 cross section. The conductor 413 faces the lower surface of the semiconductor 406b with the insulator 402 interposed therebetween. Further, the insulator 402 may not have a convex portion. Further, the conductor 413 is not necessarily provided. Further, the semiconductor 406a may not be provided. Further, the semiconductor 406c may not be provided. Further, the insulator 408 is not necessarily provided. Further, the insulator 418 is not necessarily provided. Further, the layer 409a is not necessarily provided. Further, the layer 409b is not necessarily provided.

Note that the semiconductor 406b functions as a channel formation region of the transistor. The conductor 404 functions as a first gate electrode (also referred to as a front gate electrode) of the transistor. The conductor 413 functions as a second gate electrode (also referred to as a back gate electrode) of the transistor. The conductors 416a and 416b function as a source electrode and a drain electrode of the transistor. The insulator 408 functions as a barrier layer. The insulator 408 has a function of blocking oxygen or / and hydrogen, for example. Alternatively, the insulator 408 has a higher function of blocking oxygen or / and hydrogen than the semiconductor 406a and / or the semiconductor 406c, for example.

Note that the insulator 402 is preferably an insulator containing excess oxygen.

For example, an insulator containing excess oxygen is an insulator having a function of releasing oxygen by heat treatment. For example, a silicon oxide layer containing excess oxygen is a silicon oxide layer from which oxygen can be released by heat treatment or the like. Therefore, the insulator 402 is an insulator in which oxygen can move through the film. That is, the insulator 402 may be an insulator having oxygen permeability. For example, the insulator 402 may be an insulator having higher oxygen permeability than the semiconductor 406a.

An insulator containing excess oxygen may have a function of reducing oxygen vacancies in the semiconductor 406b. Oxygen deficiency in the semiconductor 406b forms DOS and becomes a hole trap or the like. Further, when hydrogen enters an oxygen deficient site, electrons as carriers may be generated. Therefore, stable electric characteristics can be imparted to the transistor by reducing oxygen vacancies in the semiconductor 406b.

Here, the insulator from which oxygen is released by heat treatment is 1 × 10 ¹⁸ atoms / cm ³ or more in the range of a surface temperature of 100 ° C. or more and 700 ° C. or less or 100 ° C. or more and 500 ° C. or less by TDS analysis. Oxygen (in terms of the number of oxygen atoms) of 10 ¹⁹ atoms / cm ³ or more or 1 × 10 ²⁰ atoms / cm ³ or more may be released.

Here, a method of measuring the amount of released oxygen using TDS analysis will be described below.

The total amount of gas released when the measurement sample is subjected to TDS analysis is proportional to the integrated value of the ionic strength of the released gas. The total amount of gas released can be calculated by comparison with a standard sample.

For example, from the TDS analysis result of a silicon substrate containing a predetermined density of hydrogen, which is a standard sample, and the TDS analysis result of the measurement sample, the amount of released oxygen molecules (N _O2 ) of the measurement sample is obtained by the following formula: Can do. Here, it is assumed that all the gases detected by the mass-to-charge ratio 32 obtained by TDS analysis are derived from oxygen molecules. The mass to charge ratio of CH ₃ OH is 32 but is not considered here as it is unlikely to exist. In addition, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.

N _O2 = N _H2 / S _H2 × S _O2 × α

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of ion intensity when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N _H2 / SH ₂ . S _O2 is an integrated value of ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ionic strength in the TDS analysis. For details of the above formula, refer to JP-A-6-275697. In addition, the amount of released oxygen is a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd., and a silicon substrate containing, for example, 1 × 10 ¹⁶ atoms / cm ² of hydrogen atoms is used as a standard sample. Use to measure.

In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.

Note that N _{2 O 2} is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.

Alternatively, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, it means that the spin density resulting from the peroxide radical is 5 × 10 ¹⁷ spins / cm ³ or more. Note that an insulator including a peroxide radical may have an asymmetric signal with a g value near 2.01 in ESR.

Alternatively, the insulator containing excess oxygen may be oxygen-excess silicon oxide (SiO _X (X> 2)). Oxygen-excess silicon oxide (SiO _X (X> 2)) contains oxygen atoms more than twice the number of silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by Rutherford Backscattering Spectroscopy (RBS: Rutherford Backscattering Spectrometry).

As shown in FIG. 3B, the side surface of the semiconductor 406b is in contact with the layer 409a and the layer 409b. In addition, the semiconductor 406b can be electrically surrounded by an electric field of the conductor 404 (a transistor structure that electrically surrounds the semiconductor by an electric field generated from the conductor is referred to as a surrounded channel (s-channel) structure). . Therefore, a channel may be formed in the entire semiconductor 406b (bulk). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) during conduction can be increased.

Since a high on-state current can be obtained, the s-channel structure can be said to be a structure suitable for a miniaturized transistor. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a region with a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, more preferably 30 nm or less, and more. Preferably, it has a region of 20 nm or less.

Alternatively, a voltage lower or higher than that of the source electrode may be applied to the conductor 413 to change the threshold voltage of the transistor in the positive direction or the negative direction. For example, by changing the threshold voltage of the transistor in the positive direction, normally-off in which the transistor is turned off (off state) even when the gate voltage is 0 V may be realized. Note that the voltage applied to the conductor 413 may be variable or fixed. In the case where the voltage applied to the conductor 413 is variable, a circuit for controlling the voltage may be electrically connected to the conductor 413.

Next, semiconductors applicable to the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, and the like are described. Note that, for example, the above-described wide gap semiconductor may be applied to the semiconductor 406a, the semiconductor 406b, the semiconductor 406c, and the like.

The semiconductor 406b is an oxide semiconductor containing indium, for example. For example, when the semiconductor 406b contains indium, the carrier mobility (electron mobility) increases. The semiconductor 406b preferably contains an element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The semiconductor 406b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.

Note that the semiconductor 406b is not limited to the oxide semiconductor containing indium. The semiconductor 406b may be an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide and gallium tin oxide.

For the semiconductor 406b, an oxide with a wide energy gap is used, for example. The energy gap of the semiconductor 406b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

For example, the semiconductor 406a and the semiconductor 406c are oxide semiconductors including one or more elements other than oxygen included in the semiconductor 406b or two or more elements. Since the semiconductor 406a and the semiconductor 406c are composed of one or more elements other than oxygen constituting the semiconductor 406b, or two or more elements, defect states are formed at the interface between the semiconductor 406a and the semiconductor 406b and at the interface between the semiconductor 406b and the semiconductor 406c. The position is difficult to form.

The semiconductor 406a, the semiconductor 406b, and the semiconductor 406c preferably contain at least indium. Note that when the semiconductor 406a is an In—M—Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is less than 25 atomic%. , M is higher than 75 atomic%. In the case where the semiconductor 406b is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, the In is preferably higher than 25 atomic%, the M is lower than 75 atomic%, and more preferably, In is higher than 34 atomic%. High, and M is less than 66 atomic%. In the case where the semiconductor 406c is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is less than 25 atomic%. , M is higher than 75 atomic%. Note that the semiconductor 406c may be formed using the same kind of oxide as the semiconductor 406a. Note that the semiconductor 406a and / or the semiconductor 406c may not contain indium in some cases. For example, the semiconductor 406a and / or the semiconductor 406c may be gallium oxide. Note that the number of atoms of each element included in the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c may not be a simple integer ratio.

As the semiconductor 406b, an oxide having an electron affinity higher than those of the semiconductor 406a and the semiconductor 406c is used. For example, as the semiconductor 406b, an oxide having an electron affinity higher than that of the semiconductor 406a and the semiconductor 406c by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV. Is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the semiconductor 406c preferably contains indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

At this time, when a gate voltage is applied, a channel is formed in the semiconductor 406b having high electron affinity among the semiconductors 406a, 406b, and 406c.

Here, a mixed region of the semiconductor 406a and the semiconductor 406b may be provided between the semiconductor 406a and the semiconductor 406b. Further, in some cases, there is a mixed region of the semiconductor 406b and the semiconductor 406c between the semiconductor 406b and the semiconductor 406c. The mixed region has a low density of defect states. Therefore, the stack of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c has a band diagram in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.

At this time, electrons move mainly in the semiconductor 406b, not in the semiconductor 406a and the semiconductor 406c. As described above, by reducing the defect level density at the interface between the semiconductor 406a and the semiconductor 406b and the defect level density at the interface between the semiconductor 406b and the semiconductor 406c, the movement of electrons in the semiconductor 406b is inhibited. And the on-state current of the transistor can be increased.

The on-state current of the transistor can be increased as the factor that hinders the movement of electrons is reduced. For example, when there is no factor that hinders the movement of electrons, it is estimated that electrons move efficiently. Electron movement is inhibited, for example, even when the physical unevenness of the channel formation region is large.

In order to increase the on-state current of the transistor, for example, the root mean square (RMS) roughness of the upper surface or the lower surface of the semiconductor 406b (formation surface, here, the semiconductor 406a) in a range of 1 μm × 1 μm is used. The thickness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm. The maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably less than 7 nm. The RMS roughness, Ra, and PV can be measured using a scanning probe microscope system SPA-500 manufactured by SII Nano Technology.

Alternatively, for example, even when the density of defect states in a region where a channel is formed is high, the movement of electrons is inhibited.

For example, in the case where the semiconductor 406b has oxygen vacancies (also referred to as V 2 _O ), donor levels may be formed when hydrogen enters oxygen vacancy sites. The following may be referred to a state that has entered the hydrogen to oxygen vacancies in the site as V _{O H.} Since V _O H scatters electrons, it causes a reduction in the on-state current of the transistor. Note that oxygen deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, the on-state current of the transistor can be increased in some cases by reducing oxygen vacancies in the semiconductor 406b.

In addition, when the density of defect states in a region where a channel is formed is high, the electrical characteristics of the transistor may be changed. For example, when the defect level becomes a carrier generation source, the threshold voltage of the transistor may be changed.

In order to reduce oxygen vacancies in the semiconductor 406b, for example, there is a method in which excess oxygen contained in the insulator 402 is moved to the semiconductor 406b through the semiconductor 406a. In this case, the semiconductor 406a is preferably a layer having oxygen permeability (a layer through which oxygen passes or permeates).

The density of defect states in the oxide semiconductor can be evaluated by, for example, a microwave photoconductive decay method or ESR. For example, in an oxide semiconductor having a defect level, the peak value of microwave reflectance observed by a microwave photoconductive decay method may be low. Further, a signal may appear when the g value is 1.89 or more and 1.96 or less (typically 1.93 or 1.94) depending on ESR.

Therefore, for example, when the semiconductor 406a and / or the semiconductor 406b has a region in which the component τ1 that quickly decays out of the lifetime of the carrier is 30 nsec to 200 nsec, preferably 40 nsec to 200 nsec, by the microwave photoconductive decay method. preferable.

Note that in the case where the transistor has an s-channel structure, a channel is formed in the entire semiconductor 406b. Accordingly, the thicker the semiconductor 406b, the larger the channel region. That is, the thicker the semiconductor 406b, the higher the on-state current of the transistor. For example, the semiconductor 406b may have a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more. However, since the productivity of the semiconductor device may be reduced, the semiconductor 406b having a region with a thickness of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used. Note that as the channel formation region is reduced, the electrical characteristics of the transistor may be improved as the semiconductor 606b is thinner. Therefore, the thickness of the semiconductor 606b may be less than 10 nm.

In order to increase the on-state current of the transistor, the thickness of the semiconductor 406c is preferably as small as possible. For example, the semiconductor 406c may have a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the semiconductor 406c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 406b where a channel is formed. Therefore, the semiconductor 406c preferably has a certain thickness. For example, the semiconductor 406c may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. The semiconductor 406c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulator 402 and the like.

In order to increase reliability, the semiconductor 406a is preferably thick and the semiconductor 406c is thin.
For example, the semiconductor 406a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor 406a, the distance from the interface between the adjacent insulator and the semiconductor 406a to the semiconductor 406b where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the semiconductor 406a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.

For example, between the semiconductor 406b and the semiconductor 406a, for example, in secondary ion mass spectrometry (SIMS), 1 × 10 ¹⁹ atoms / cm ³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³ Hereinafter, it preferably has a region having a silicon concentration of 2 × 10 ¹⁸ atoms / cm ³ or less. Further, between SIMS 406b and 406C, in SIMS, it is 1 × 10 ¹⁹ atoms / cm ³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 2 × 10 ¹⁸ atoms / cm ³ or less. It has a region having a silicon concentration.

In the SIMS, the semiconductor 406b is 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ²⁰ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ³ or less. Preferably, the region has a hydrogen concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less. . In order to reduce the hydrogen concentration of the semiconductor 406b, it is preferable to reduce the hydrogen concentration of the semiconductor 406a and the semiconductor 406c. The semiconductors 406a and 406c have a SIMS of 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and even more preferably 5 ×. The region has a hydrogen concentration of 10 ¹⁸ atoms / cm ³ or less. In SIMS, the semiconductor 406b is 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less. Preferably, it has a region having a nitrogen concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less. . In order to reduce the nitrogen concentration of the semiconductor 406b, it is preferable to reduce the nitrogen concentrations of the semiconductor 406a and the semiconductor 406c. The semiconductor 406a and the semiconductor 406c are 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × in SIMS. The region has a nitrogen concentration of 10 ¹⁷ atoms / cm ³ or less.

The above three-layer structure is an example. For example, a two-layer structure without the semiconductor 406a or the semiconductor 406c may be used. Alternatively, a four-layer structure including any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c above or below the semiconductor 406a or above or below the semiconductor 406c may be employed. Alternatively, an n-layer structure including any one of the semiconductors exemplified as the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c in any two or more positions over the semiconductor 406a, under the semiconductor 406a, over the semiconductor 406c, and under the semiconductor 406c. (N is an integer of 5 or more).

As the substrate 400, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon and germanium, or a compound semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

Further, a flexible substrate may be used as the substrate 400. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled off and transferred to the substrate 400 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 400. Further, the substrate 400 may have elasticity. Further, the substrate 400 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The thickness of the substrate 400 is, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 400 is thinned, the weight of the semiconductor device can be reduced. Further, by making the substrate 400 thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 400 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate 400 which is a flexible substrate, for example, a metal, an alloy, a resin, glass, or fiber thereof can be used. The substrate 400, which is a flexible substrate, is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower. For example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less is used as the substrate 400 that is a flexible substrate. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, acrylic, and polytetrafluoroethylene (PTFE). In particular, since aramid has a low coefficient of linear expansion, it is suitable as the substrate 400 that is a flexible substrate.

Examples of the conductor 413 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

As the insulator 402, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer. For example, as the insulator 402, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

The insulator 402 may have a role of preventing diffusion of impurities from the substrate 400. In the case where the semiconductor 406b is an oxide semiconductor, the insulator 402 can serve to supply oxygen to the semiconductor 406b.

As the layer 409a and the layer 409b, for example, a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor may be used. Examples of the layer 409a and the layer 409b include a layer containing indium, tin and oxygen, a layer containing indium and zinc, a layer containing indium, tungsten and zinc, a layer containing tin and zinc, a layer containing zinc and gallium, and zinc And a layer containing aluminum, a layer containing zinc and fluorine, a layer containing zinc and boron, a layer containing tin and antimony, a layer containing tin and fluorine, or a layer containing titanium and niobium may be used. Alternatively, these layers may contain hydrogen, carbon, nitrogen, silicon, germanium, or argon.

The layers 409a and 409b may have a property of transmitting visible light. Alternatively, the layers 409a and 409b may have a property of not transmitting visible light, ultraviolet light, infrared light, or X-rays by reflection or absorption. By having such a property, a change in electrical characteristics of the transistor due to stray light may be suppressed in some cases.

For the layers 409a and 409b, a layer that does not form a Schottky barrier with the semiconductor 406b or the like may be preferably used. Thus, the on-state characteristics of the transistor can be improved.

Examples of the conductor 416a and the conductor 416b include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor including one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

Note that for the layers 409a and 409b, it may be preferable to use layers having higher resistance than the conductors 416a and 416b. For the layers 409a and 409b, it may be preferable to use layers having lower resistance than the channel of the transistor. For example, the resistivity of the layers 409a and 409b may be 0.1 Ωcm to 100 Ωcm, 0.5 Ωcm to 50 Ωcm, or 1 Ωcm to 10 Ωcm. By setting the resistivity of the layers 409a and 409b in the above range, electric field concentration at the boundary between the channel and the drain can be reduced. Therefore, variation in electrical characteristics of the transistor can be reduced. In addition, the punch-through current due to the electric field generated from the drain can be reduced. Therefore, saturation characteristics can be improved even in a transistor with a short channel length. Note that in a circuit configuration in which the source and the drain are not interchanged, it may be preferable to dispose only one of the layers 409a and 409b (for example, the drain side).

As the insulator 412, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer. For example, as the insulator 412, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

Examples of the conductor 404 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

As the insulator 408, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer. The insulator 408 is preferably formed using a single layer or a stack of insulators containing aluminum oxide, silicon nitride oxide, silicon nitride, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Use it.

As the insulator 418, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer. For example, as the insulator 418, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

Note that although FIG. 3 illustrates an example in which the conductor 404 that is the first gate electrode of the transistor and the conductor 413 that is the second gate electrode are not electrically connected to each other, according to one embodiment of the present invention. The structure of the transistor is not limited to this. For example, as illustrated in FIG. 4A, a structure in which the conductor 404 and the conductor 413 are electrically connected to each other may be employed. With such a structure, since the same potential is supplied to the conductor 404 and the conductor 413, switching characteristics of the transistor can be improved. Alternatively, as illustrated in FIG. 4B, a structure without the conductor 413 may be employed.

FIG. 5A is an example of a top view of a transistor. FIG. 5B illustrates an example of a cross-sectional view corresponding to the dashed-dotted line F1-F2 and the dashed-dotted line F3-F4 in FIG. Note that in FIG. 5A, part of the insulator and the like is omitted for easy understanding.

3A and 3B and the like, the example in which the conductors 416a and 416b functioning as the source electrode and the drain electrode are in contact with the top and side surfaces of the semiconductor 406b, the top surface of the insulator 402, and the like is described. The structure of the transistor is not limited to this. For example, as illustrated in FIG. 5, the conductor 416a and the conductor 416b may be in contact with only the top surface of the semiconductor 406b.

Further, an insulator 428 may be provided over the insulator 418 as illustrated in FIG. The insulator 428 is preferably an insulator having a flat upper surface. Note that the insulator 428 includes, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. May be used in a single layer or stacked layers. For example, as the insulator 428, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used. In order to planarize the upper surface of the insulator 428, planarization treatment may be performed by a chemical mechanical polishing (CMP) method or the like.

Alternatively, the insulator 428 may be formed using a resin. For example, a resin containing polyimide, polyamide, acrylic, silicone, or the like may be used. By using resin, the top surface of the insulator 428 may not be planarized in some cases. In addition, since the resin can form a thick film in a short time, productivity can be increased.

Further, as illustrated in FIGS. 5A and 5B, a conductor 424a and a conductor 424b may be provided over the insulator 428. The conductor 424a and the conductor 424b have a function as a wiring, for example. Alternatively, the insulator 428 may have an opening, and the conductor 416a and the conductor 424a may be electrically connected through the opening. Alternatively, the insulator 428 may have another opening, and the conductor 416b and the conductor 424b may be electrically connected through the opening. At this time, the conductors 426a and 426b may be provided in the respective openings.

Examples of the conductor 424a and the conductor 424b include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor including one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

In the transistor illustrated in FIG. 5, the layers 409a and 409b are not in contact with the side surface of the semiconductor 406b. Therefore, an electric field applied from the conductor 404 functioning as the first gate electrode toward the side surface of the semiconductor 406b is difficult to be shielded by the layers 409a, 409b, and the like. The layers 409a and 409b are not in contact with the top surface of the insulator 402. Therefore, excess oxygen (oxygen) released from the insulator 402 is not consumed because the layers 409a and 409b are oxidized. Therefore, excess oxygen (oxygen) released from the insulator 402 can be efficiently used to reduce oxygen vacancies in the semiconductor 406b. In other words, the transistor having the structure illustrated in FIGS. 5A and 5B is a transistor with excellent electrical characteristics such as a high on-state current, a high field-effect mobility, a low subthreshold swing value, and high reliability.

6A and 6B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. 6A is a top view, and FIG. 6B is a cross-sectional view corresponding to a dashed-dotted line G1-G2 and a dashed-dotted line G3-G4 illustrated in FIG. 6A. Note that in the top view of FIG. 6A, some elements are omitted for clarity.

As illustrated in FIG. 6, the transistor does not include the layer 409a, the layer 409b, the conductor 416a, and the conductor 416b, and may have a structure in which the conductor 426a and the conductor 426b are in contact with the semiconductor 406b. . In this case, it is preferable that a low resistance region 423a (low resistance region 423b) be provided in a region of the semiconductor 406b and / or the semiconductor 406a that is in contact with at least 426a and the conductor 426b. The low resistance region 423a and the low resistance region 423b may be formed by adding impurities to the semiconductor 406b and / or the semiconductor 406a, for example, using the conductor 404 as a mask. Note that the conductor 426a and the conductor 426b may be provided in a hole (penetrating) or a depression (not penetrating) of the semiconductor 406b. By providing the conductor 426a and the conductor 426b in the hole or the depression of the semiconductor 406b, the contact area between the conductor 426a and the conductor 426b and the semiconductor 406b is increased, so that the influence of contact resistance can be reduced. it can. That is, the on-state current of the transistor can be increased.

7A and 7B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. 7A is a top view, and FIG. 7B is a cross-sectional view corresponding to the dashed-dotted line J1-J2 and the dashed-dotted line J3-J4 illustrated in FIG. 7A. Note that in the top view of FIG. 7A, some elements are omitted for clarity.

The transistor illustrated in FIGS. 7A and 7B includes a conductor 604 over a substrate 600, an insulator 612 over the conductor 604, a semiconductor 606a over the insulator 612, and a semiconductor 606b over the semiconductor 606a. A semiconductor 606c over the semiconductor 606b; a semiconductor 606a, a semiconductor 606b, and a semiconductor 606c that are in contact with and spaced from each other; a conductor 616a over the layer 609a; and a conductor over the layer 609b 616b, and an insulator 618 over the semiconductor 606c, the conductor 616a, and the conductor 616b. Note that the conductor 604 faces the lower surface of the semiconductor 606b with the insulator 612 interposed therebetween. The insulator 612 may have a convex portion. Further, an insulator may be provided between the substrate 600 and the conductor 604. For the insulator, the description of the insulator 402 and the insulator 408 is referred to. Further, the semiconductor 606a may not be provided. Further, the insulator 618 is not necessarily provided. Further, the layer 609a is not necessarily provided. Further, the layer 609b may not be provided.

Note that the semiconductor 606b functions as a channel formation region of the transistor. The conductor 604 functions as a first gate electrode (also referred to as a front gate electrode) of the transistor. The conductors 616a and 616b function as a source electrode and a drain electrode of the transistor.

Note that the insulator 618 is preferably an insulator containing excess oxygen.

Note that for the substrate 600, the description of the substrate 400 is referred to. For the conductor 604, the description of the conductor 404 is referred to. For the insulator 612, the description of the insulator 412 is referred to. For the semiconductor 606a, the description of the semiconductor 406c is referred to. For the semiconductor 606b, the description of the semiconductor 406b is referred to. For the semiconductor 606c, the description of the semiconductor 406a is referred to. For the layers 609a and 609b, the description of the layers 409a and 409b is referred to. For the conductor 616a and the conductor 616b, the description of the conductor 416a and the conductor 416b is referred to. For the insulator 618, the description of the insulator 402 is referred to.

Note that a display element may be provided over the insulator 618. For example, a pixel electrode, a liquid crystal layer, a common electrode, a light emitting layer, an organic EL layer, an anode, a cathode, and the like may be provided. The display element is connected to, for example, the conductor 616a.

FIG. 8A is an example of a top view of a transistor. FIG. 8B illustrates an example of a cross-sectional view corresponding to the dashed-dotted line K1-K2 and the dashed-dotted line K3-K4 in FIG. Note that in FIG. 8A, part of the insulator and the like is omitted for easy understanding.

Note that an insulator that can function as a channel protective film may be provided over the semiconductor. For example, as illustrated in FIG. 8, an insulator 620 may be provided between the layers 609a and 609b and the semiconductor 606c. In that case, the layer 609a (the layer 609b) and the semiconductor 606c are connected to each other through an opening in the insulator 620. For the insulator 620, the description of the insulator 618 may be referred to.

Note that the conductor 613 may be provided over the insulator 618 in FIGS. 7B and 8B. Examples of such cases are shown in FIGS. 9A and 9B. Note that for the conductor 613, the description of the conductor 413 is referred to. The conductor 613 may be supplied with the same potential or the same signal as the conductor 604, or may be supplied with a different potential or signal. For example, a certain potential may be supplied to the conductor 613 to control the threshold voltage of the transistor. That is, the conductor 613 can function as a second gate electrode. Further, an s-channel structure may be formed using the conductor 613 or the like.

<Transistor fabrication method>
A method for manufacturing the transistor illustrated in FIGS. 3A to 3C according to one embodiment of the present invention will be described below with reference to FIGS. Note that here, in order to facilitate understanding, an example in which the conductor 413, the layer 409a, and the layer 409b are not formed is shown. FIG. 3 illustrates an example having a stacked structure of the semiconductor 406a, the semiconductor 406b, and the semiconductor 406c, but here, an example having a single layer of the semiconductor 406 is shown instead.

First, the substrate 400 is prepared.

Next, the insulator 402 is formed. The insulator 402 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method or a pulse laser deposition (PLD: Pulsed Laser Deposition) method, an atomic layer. The deposition can be performed using an ALD (Atomic Layer Deposition) method or the like.

In addition, the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.

Next, a semiconductor 436 is formed (see FIG. 10A). The semiconductor 436 is a semiconductor that becomes the semiconductor 406 through a later step. The semiconductor 436 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the semiconductor 436 is evaluated using the above-described microwave photoconductive decay method. For the evaluation of the semiconductor 436, excitation light 430 is used (see FIG. 10B). Evaluation by the microwave photoconductive decay method is said to cause little damage to the semiconductor 436. However, depending on the evaluation conditions, the semiconductor 436 may be altered by irradiation with the excitation light 430. Therefore, it is preferable to irradiate the excitation light 430 while avoiding a region which is a channel formation region of the semiconductor 436. Further, the same evaluation may be performed on a predetermined region at a plurality of locations in the surface of the substrate 400.

Next, the semiconductor 436 is processed by a photolithography method or the like to form the semiconductor 406 (see FIG. 11A). Note that when the semiconductor 406 is formed, the insulator 402 is also etched, and part of the region may be thinned. In other words, the insulator 402 may have a shape having a protrusion in a region in contact with the semiconductor 406. At this time, the region of the semiconductor 436 irradiated with the excitation light 430 may be etched.

In the photolithography method, first, a resist is exposed through a photomask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, a photomask is not necessary. Note that the resist mask can be removed by dry etching such as ashing and / or wet etching.

Next, a conductor to be the conductor 416a and the conductor 416b is formed. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

Next, the conductor is processed by a photolithography method or the like, so that the conductor 416a and the conductor 416b are formed (see FIG. 11B).

Next, an insulator to be the insulator 412 is formed. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a conductor to be the conductor 404 is formed. The conductor can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

Next, the conductor is processed by a photolithography method or the like, so that the conductor 404 is formed.

Next, the insulator is processed by a photolithography method or the like to form the insulator 412. (See FIG. 12A.) Note that when the insulator 412 is formed, the insulator 402 is also etched, and part of the region may be thinned. That is, the insulator 402 may have a shape having a protrusion in a region in contact with the insulator 412.

Next, an insulator 408 is formed. The insulator 408 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a transistor can be manufactured by forming the insulator 418 (see FIG. 12B). The insulator 418 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As described above, a semiconductor which serves as a channel formation region of a transistor can be evaluated during the manufacturing process of the transistor. Therefore, quality control during manufacturing can be performed as part of the process. In addition, sampling evaluation is unnecessary. Therefore, a transistor can be manufactured with high yield. In addition, the transistor can be manufactured with high productivity. In addition, a semiconductor device including the transistor can be manufactured with high yield. In addition, a semiconductor device including the transistor can be manufactured with high productivity.

<Semiconductor device>
Hereinafter, a semiconductor device according to one embodiment of the present invention is illustrated.

<Circuit>
An example of a circuit using a transistor according to one embodiment of the present invention is described below.

<CMOS inverter>
The circuit diagram shown in FIG. 13A shows a structure of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.

<Structure 1 of Semiconductor Device>
FIG. 14 is a cross-sectional view of the semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 14 includes a transistor 2200 and a transistor 2100. The transistor 2100 is provided above the transistor 2200. Note that although the example in which the transistor illustrated in FIGS. 1A to 1C is used as the transistor 2100 is described, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, the transistor illustrated in FIGS. 3, 4, or 5 may be used as the transistor 2100. Therefore, for the transistor 2100, the above description of the transistor is referred to as appropriate.

A transistor 2200 illustrated in FIG. 14 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

In the transistor 2200, the region 472a and the region 472b function as a source region and a drain region. The insulator 462 functions as a gate insulator. The conductor 454 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 454. That is, conduction / non-conduction between the region 472a and the region 472b can be controlled by a potential applied to the conductor 454.

As the semiconductor substrate 450, for example, a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. A single crystal silicon substrate is preferably used as the semiconductor substrate 450.

As the semiconductor substrate 450, a semiconductor substrate having an impurity imparting n-type conductivity is used. However, as the semiconductor substrate 450, a semiconductor substrate having an impurity imparting p-type conductivity may be used. In that case, a well having an impurity imparting n-type conductivity may be provided in a region to be the transistor 2200. Alternatively, the semiconductor substrate 450 may be i-type.

The upper surface of the semiconductor substrate 450 preferably has a (110) plane. Thus, the on-state characteristics of the transistor 2200 can be improved.

The region 472a and the region 472b are regions having an impurity imparting p-type conductivity. In this manner, the transistor 2200 constitutes a p-channel transistor.

Note that the transistor 2200 is separated from an adjacent transistor by the region 460 or the like. The region 460 is a region having an insulating property.

14 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor. 478c, a conductor 476a, a conductor 476b, a conductor 474a, a conductor 474b, a conductor 474c, a conductor 496a, a conductor 496b, a conductor 496c, a conductor 496d, and a conductor 498a, a conductor 498b, a conductor 498c, an insulator 490, an insulator 492, and an insulator 494 are included.

The insulator 464 is provided over the transistor 2200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 490 is provided over the insulator 468. The transistor 2100 is provided over the insulator 490. The insulator 492 is provided over the transistor 2100. The insulator 494 is provided over the insulator 492.

The insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In addition, a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.

The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In addition, a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.

The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.

The insulator 490 includes an opening overlapping with a channel formation region of the transistor 2100, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In addition, a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.

The conductor 474a may function as a bottom gate electrode of the transistor 2100. Alternatively, for example, electrical characteristics such as a threshold voltage of the transistor 2100 may be controlled by applying a certain potential to the conductor 474a. Alternatively, for example, the conductor 474a and the conductor 404 that is the top gate electrode of the transistor 2100 may be electrically connected. Thus, the on-state current of the transistor 2100 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 2100 can be stabilized.

The insulator 492 includes an opening reaching the conductor 474b through the conductor 416b which is one of the source electrode and the drain electrode of the transistor 2100 and the conductor 416a which is the other of the source electrode and the drain electrode of the transistor 2100. , An opening reaching the conductor 404 which is a gate electrode of the transistor 2100, and an opening reaching the conductor 474c. In addition, a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. However, each opening may further pass through any of the components such as the transistor 2100.

The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b and the conductor 496d, and an opening reaching the conductor 496c. In addition, a conductor 498a, a conductor 498b, or a conductor 498c is embedded in each opening.

As the insulator 464, the insulator 466, the insulator 468, the insulator 490, the insulator 492, and the insulator 494, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, An insulator containing gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. For example, as the insulator 401, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.

One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 490, the insulator 492, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 2100, the electrical characteristics of the transistor 2100 can be stabilized.

Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

Conductor 480a, conductor 480b, conductor 480c, conductor 478a, conductor 478b, conductor 478c, conductor 476a, conductor 476b, conductor 474a, conductor 474b, conductor 474c, conductor 496a, conductor 496b, conductor 496c, conductor 496d, conductor 498a, conductor 498b, and conductor 498c include, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, A conductor including one or more of copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

Note that the semiconductor device illustrated in FIG. 15 is different only in the structure of the transistor 2200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 14 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 15 illustrates the case where the transistor 2200 is a Fin type. By setting the transistor 2200 to be a Fin type, an effective channel width can be increased, whereby the on-state characteristics of the transistor 2200 can be improved. In addition, since the contribution of the electric field of the gate electrode can be increased, off characteristics of the transistor 2200 can be improved.

Further, the semiconductor device shown in FIG. 16 is different only in the structure of the transistor 2200 of the semiconductor device shown in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 14 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 16 illustrates the case where the transistor 2200 is provided over an SOI substrate. FIG. 16 illustrates a structure in which the region 456 is separated from the semiconductor substrate 450 by an insulator 452. By using an SOI substrate, a punch-through phenomenon or the like can be suppressed, so that off characteristics of the transistor 2200 can be improved. Note that the insulator 452 can be formed by forming part of the semiconductor substrate 450 into an insulator. For example, as the insulator 452, silicon oxide can be used.

In the semiconductor device illustrated in FIGS. 14 to 16, a p-channel transistor is manufactured using a semiconductor substrate, and an n-channel transistor is formed thereabove, so that the area occupied by the element can be reduced. That is, the degree of integration of the semiconductor device can be increased. Further, since the process can be simplified as compared with the case where an n-channel transistor and a p-channel transistor are formed using the same semiconductor substrate, the productivity of the semiconductor device can be increased. In addition, the yield of the semiconductor device can be increased. In addition, a p-channel transistor can sometimes omit complicated processes such as an LDD (Lightly Doped Drain) region, a shallow trench structure, and a strain design. Therefore, productivity and yield may be increased as compared with the case where an n-channel transistor is manufactured using a semiconductor substrate.

<CMOS analog switch>
In addition, the circuit diagram illustrated in FIG. 13B illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called CMOS analog switch.

<Storage device 1>
FIG. 17 illustrates an example of a semiconductor device (memory device) using the transistor according to one embodiment of the present invention, which can hold stored data even in a state where power is not supplied and has no limitation on the number of writing times.

A semiconductor device illustrated in FIG. 17A includes a transistor 3200 including a first semiconductor, a transistor 3300 including a second semiconductor, and a capacitor 3400. Note that the above-described transistor can be used as the transistor 3300.

The transistor 3300 is preferably a transistor with low off-state current. As the transistor 3300, for example, a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.

In FIG. 17A, the first wiring 3001 is electrically connected to the source of the transistor 3200, and the second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Has been.

The semiconductor device illustrated in FIG. 17A has a characteristic that the potential of the gate of the transistor 3200 can be held; thus, information can be written, held, and read as described below.

Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to one of the gate of the transistor 3200 and the electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).

Since the off-state current of the transistor 3300 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node FG can be determined. For example, in the case where a high-level charge is applied to the node FG in writing, the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node FG, the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. In order not to read data in other memory cells, the fifth wiring 3005 is _{supplied with} a potential at which the transistor 3200 is in a “non-conducting state” regardless of the charge applied to the node FG, that is, a potential lower than V _{th_H.} To give. _{Alternatively} , the fifth wiring 3005 may be _{supplied with} a potential at which the transistor 3200 is in a “conducting state” regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L} .

<Structure 2 of Semiconductor Device>
18 is a cross-sectional view of the semiconductor device corresponding to FIG. A semiconductor device illustrated in FIG. 18 includes a transistor 3200, a transistor 3300, and a capacitor 3400. The transistor 3300 and the capacitor 3400 are provided above the transistor 3200. Note that as the transistor 3300, the above description of the transistor 2100 is referred to. For the transistor 3200, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 14 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.

A transistor 2200 illustrated in FIG. 18 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.

18 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, and a conductor. A conductor 478c, a conductor 476a, a conductor 476b, a conductor 474a, a conductor 474b, a conductor 474c, a conductor 496a, a conductor 496b, a conductor 496c, a conductor 496d, and a conductor A body 498a, a conductor 498b, a conductor 498c, a conductor 498d, an insulator 490, an insulator 492, and an insulator 494 are included.

The insulator 464 is provided over the transistor 3200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 490 is provided over the insulator 468. The transistor 2100 is provided over the insulator 490. The insulator 492 is provided over the transistor 2100. The insulator 494 is provided over the insulator 492.

The insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In addition, a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.

The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In addition, a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.

The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In addition, a conductor 476a or a conductor 476b is embedded in each opening.

The insulator 490 includes an opening overlapping with a channel formation region of the transistor 3300, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In addition, a conductor 474a, a conductor 474b, or a conductor 474c is embedded in each opening.

The conductor 474a may function as the bottom gate electrode of the transistor 3300. Alternatively, for example, electrical characteristics such as a threshold voltage of the transistor 3300 may be controlled by applying a certain potential to the conductor 474a. Alternatively, for example, the conductor 474a and the conductor 404 that is the top gate electrode of the transistor 3300 may be electrically connected. Thus, the on-state current of the transistor 3300 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 3300 can be stabilized.

The insulator 492 includes an opening reaching the conductor 474b through the conductor 416b which is one of the source electrode and the drain electrode of the transistor 3300 and the conductor 416a which is the other of the source electrode and the drain electrode of the transistor 3300. And an opening reaching the conductor 414 through the insulator 412, an opening reaching the conductor 404 which is a gate electrode of the transistor 3300, and a conductor 416 a which is the other of the source electrode and the drain electrode of the transistor 3300 And an opening reaching the conductor 474c. In addition, a conductor 496a, a conductor 496b, a conductor 496c, or a conductor 496d is embedded in each opening. Note that each opening may further pass through an opening included in any of the components such as the transistor 3300.

The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b, an opening reaching the conductor 496c, and an opening reaching the conductor 496d. In addition, a conductor 498a, a conductor 498b, a conductor 498c, or a conductor 498d is embedded in each opening.

One or more of the insulator 464, the insulator 466, the insulator 468, the insulator 490, the insulator 492, or the insulator 494 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 3300, electrical characteristics of the transistor 3300 can be stabilized.

Examples of the conductor 498d include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

The source or the drain of the transistor 3200 is a conductor that is one of a source electrode and a drain electrode of the transistor 3300 through the conductor 480b, the conductor 478b, the conductor 476a, the conductor 474b, and the conductor 496c. It is electrically connected to 416b. The conductor 454 which is a gate electrode of the transistor 3200 includes a conductor 480c, a conductor 478c, a conductor 476b, a conductor 474c, and a conductor 496d, and the source or drain electrode of the transistor 3300. Is electrically connected to the other conductor 416a.

The capacitor 3400 includes an electrode electrically connected to the other of the source electrode and the drain electrode of the transistor 3300, a conductor 414, and an insulator 412. Note that the insulator 412 can be formed through the same process as the gate insulator of the transistor 3300; In addition, when the layer formed through the same step as the gate electrode of the transistor 3300 is used as the conductor 414, productivity may be improved in some cases.

For other structures, the description of FIG. 14 and the like can be referred to as appropriate.

Note that the semiconductor device illustrated in FIG. 19 is different only in the structure of the transistor 3200 of the semiconductor device illustrated in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 18 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 19 illustrates the case where the transistor 3200 is a Fin type. For the Fin-type transistor 3200, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 15 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.

Further, the semiconductor device shown in FIG. 20 is different only in the structure of the transistor 3200 of the semiconductor device shown in FIG. Therefore, the description of the semiconductor device illustrated in FIG. 18 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 20 illustrates the case where the transistor 3200 is provided over a semiconductor substrate 450 which is an SOI substrate. For the transistor 3200 provided over the semiconductor substrate 450 which is an SOI substrate, the description of the transistor 2200 illustrated in FIGS. Note that although FIG. 16 illustrates the case where the transistor 2200 is a p-channel transistor, the transistor 3200 may be an n-channel transistor.

<Storage device 2>
The semiconductor device illustrated in FIG. 17B is different from the semiconductor device illustrated in FIG. 17A in that the transistor 3200 is not provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.

Information reading in the semiconductor device illustrated in FIG. 17B is described. When the transistor 3300 is turned on, the floating third wiring 3003 and the capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on one potential of the electrode of the capacitor 3400 (or charge accumulated in the capacitor 3400).

For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed. Assuming VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, if the potential of one of the electrodes of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. The potential (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + C × V0) / (CB + C)). I understand that

Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.

The semiconductor device described above can hold stored data for a long time by using a transistor with an off-state current that includes an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates. For example, unlike the conventional nonvolatile memory, since electrons are not injected into the floating gate and electrons are not extracted from the floating gate, there is no problem of deterioration of the insulator. In other words, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.

<Imaging device>
The imaging device according to one embodiment of the present invention is described below.

FIG. 21A is a plan view illustrating a configuration example of an imaging device 200 according to one embodiment of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel unit 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are connected to the plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211, respectively. Note that in this specification and the like, the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, and the like are all referred to as “peripheral circuits” or “driving circuits” in some cases. For example, the peripheral circuit 260 can be said to be part of the peripheral circuit.

The imaging apparatus 200 preferably includes a light source 291. The light source 291 can emit the detection light P1.

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. In addition, the peripheral circuit may be disposed on a substrate over which the pixel portion 210 is formed. The peripheral circuit may be partially or entirely mounted with a semiconductor device such as an IC. Note that one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted from the peripheral circuit.

In addition, as illustrated in FIG. 21B, in the pixel portion 210 included in the imaging device 200, the pixel 211 may be arranged to be inclined. By arranging the pixels 211 at an angle, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of imaging in the imaging apparatus 200 can be further improved.

<Pixel Configuration Example 1>
A single pixel 211 included in the imaging apparatus 200 is configured by a plurality of sub-pixels 212, and a color image display is realized by combining each sub-pixel 212 with a filter (color filter) that transmits light in a specific wavelength band. Information can be acquired.

FIG. 22A is a plan view illustrating an example of a pixel 211 for obtaining a color image. A pixel 211 illustrated in FIG. 22A includes a sub-pixel 212 (hereinafter, also referred to as “sub-pixel 212R”) provided with a color filter that transmits a red (R) wavelength band, and a green (G) wavelength band. Sub-pixel 212 (hereinafter also referred to as “sub-pixel 212G”) provided with a transparent color filter and sub-pixel 212 (hereinafter referred to as “sub-pixel 212B”) provided with a color filter that transmits the blue (B) wavelength band. Also called). The sub-pixel 212 can function as a photosensor.

The subpixel 212 (subpixel 212R, subpixel 212G, and subpixel 212B) is electrically connected to the wiring 231, the wiring 247, the wiring 248, the wiring 249, and the wiring 250. Further, the sub-pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 253. In this specification and the like, for example, the wiring 248 and the wiring 249 connected to the pixel 211 in the n-th row are referred to as a wiring 248 [n] and a wiring 249 [n], respectively. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253 [m]. Note that in FIG. 22A, the wiring 253 connected to the sub-pixel 212R included in the pixel 211 in the m-th column is the wiring 253 [m] R, the wiring 253 connected to the sub-pixel 212G is the wiring 253 [m] G, and A wiring 253 connected to the subpixel 212B is described as a wiring 253 [m] B. The subpixel 212 is electrically connected to a peripheral circuit through the wiring.

In addition, the imaging apparatus 200 has a configuration in which subpixels 212 provided with color filters that transmit the same wavelength band of adjacent pixels 211 are electrically connected to each other via a switch. In FIG. 22B, the sub-pixel 212 included in the pixel 211 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q) is adjacent to the pixel 211. A connection example of the sub-pixel 212 included in the pixel 211 arranged in n + 1 rows and m columns is shown. In FIG. 22B, a subpixel 212R arranged in n rows and m columns and a subpixel 212R arranged in n + 1 rows and m columns are connected via a switch 201. Further, the sub-pixel 212G arranged in n rows and m columns and the sub-pixel 212G arranged in n + 1 rows and m columns are connected via a switch 202. Further, the sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n + 1 rows and m columns are connected via a switch 203.

Note that the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively. A color filter may be used. A full color image can be acquired by providing the sub-pixel 212 that detects light of three different wavelength bands in one pixel 211.

Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits red (R), green (G), and blue (B) light, a color filter that transmits yellow (Y) light is provided. A pixel 211 having a sub-pixel 212 may be used. Alternatively, in addition to the sub-pixel 212 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, a color filter that transmits blue (B) light is provided. A pixel 211 having a sub-pixel 212 may be used. By providing the sub-pixel 212 that detects light of four different wavelength bands in one pixel 211, the color reproducibility of the acquired image can be further enhanced.

Further, for example, in FIG. 22A, the pixel number ratio of the sub-pixel 212 that detects the red wavelength band, the sub-pixel 212 that detects the green wavelength band, and the sub-pixel 212 that detects the blue wavelength band (or (Light receiving area ratio) may not be 1: 1: 1. For example, a Bayer array in which the pixel number ratio (light receiving area ratio) is red: green: blue = 1: 2: 1 may be used. Alternatively, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.

Note that the number of subpixels 212 provided in the pixel 211 may be one, but two or more are preferable. For example, by providing two or more sub-pixels 212 that detect the same wavelength band, redundancy can be increased and the reliability of the imaging apparatus 200 can be increased.

In addition, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, the imaging device 200 that detects infrared light can be realized.

Further, by using an ND (ND: Neutral Density) filter (a neutral density filter), it is possible to prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (light receiving element). By using a combination of ND filters having different light reduction amounts, the dynamic range of the imaging apparatus can be increased.

In addition to the filters described above, a lens may be provided in the pixel 211. Here, an arrangement example of the pixel 211, the filter 254, and the lens 255 will be described with reference to the cross-sectional view of FIG. By providing the lens 255, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 23A, the light 256 is supplied to the photoelectric conversion element 220 through the lens 255, the filter 254 (filter 254R, the filter 254G, and the filter 254B) formed in the pixel 211, the pixel circuit 230, and the like. It can be set as the structure made to enter.

However, as illustrated in the region surrounded by the two-dot chain line, part of the light 256 indicated by the arrow may be blocked by part of the wiring 257. Therefore, a structure in which a lens 255 and a filter 254 are disposed on the photoelectric conversion element 220 side as illustrated in FIG. 23B so that the photoelectric conversion element 220 receives light 256 efficiently is preferable. By making the light 256 incident on the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high detection sensitivity can be provided.

As the photoelectric conversion element 220 illustrated in FIG. 23, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.

Alternatively, the photoelectric conversion element 220 may be formed using a substance having a function of generating charges by absorbing radiation. Examples of the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 having a light absorption coefficient over a wide wavelength band such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.

Here, one pixel 211 included in the imaging device 200 may include a sub-pixel 212 including a first filter in addition to the sub-pixel 212 illustrated in FIG.

<Pixel Configuration Example 2>
Hereinafter, an example in which a pixel is formed using a transistor including silicon and a transistor including an oxide semiconductor will be described.

24A and 24B are cross-sectional views of elements included in the imaging device. The imaging device illustrated in FIG. 24A includes a transistor 151 using silicon provided over a silicon substrate 100, It includes a transistor 152 and a transistor 153 using an oxide semiconductor which are stacked over the transistor 151, and a photodiode 160 provided on the silicon substrate 100. Each transistor and photodiode 160 has electrical connection with various plugs 170 and wirings 171. Further, the anode 161 of the photodiode 160 is electrically connected to the plug 170 through the low resistance region 163.

In addition, the imaging device is provided in contact with the layer 110 including the transistor 151 and the photodiode 160 provided on the silicon substrate 100, the layer 120 including the wiring 171, and in contact with the layer 120. A layer 130 including a transistor 153 and a layer 140 provided in contact with the layer 130 and including a wiring 172 and a wiring 173.

Note that in the example of the cross-sectional view in FIG. 24A, the silicon substrate 100 has a light-receiving surface of the photodiode 160 on the surface opposite to the surface on which the transistor 151 is formed. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 160 may be the same as the surface on which the transistor 151 is formed.

Note that in the case where a pixel is formed using a transistor, the layer 110 may be a layer including a transistor. Alternatively, the layer 110 may be omitted, and the pixel may be formed using only transistors.

Note that in the case where a pixel is formed using a transistor, the layer 130 may be omitted. An example of a cross-sectional view in which the layer 130 is omitted is illustrated in FIG. When the layer 130 is omitted, the wiring 172 of the layer 140 can also be omitted.

Note that the silicon substrate 100 may be an SOI substrate. Further, instead of the silicon substrate 100, a substrate including germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor can be used.

Here, an insulator 180 is provided between the layer 110 including the transistor 151 and the photodiode 160 and the layer 130 including the transistor 152 and the transistor 153. However, the position of the insulator 180 is not limited.

Hydrogen in the insulator provided in the vicinity of the channel formation region of the transistor 151 has an effect of terminating dangling bonds of silicon and improving the reliability of the transistor 151. On the other hand, hydrogen in the insulator provided in the vicinity of the transistor 152, the transistor 153, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, the reliability of the transistor 152, the transistor 153, and the like may be reduced. Therefore, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor, an insulator 180 having a function of blocking hydrogen is preferably provided therebetween. By confining hydrogen below the insulator 180, the reliability of the transistor 151 can be improved. Further, since hydrogen can be prevented from diffusing from the lower layer than the insulator 180 to the upper layer from the insulator 180, reliability of the transistor 152, the transistor 153, and the like can be improved.

For the insulator 180, the description of the insulator 408 is referred to, for example.

In the cross-sectional view in FIG. 24A, the photodiode 160 provided in the layer 110 and the transistor provided in the layer 130 can be formed to overlap each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.

In addition, as illustrated in FIGS. 25A1 and 25B1, part or all of the imaging device may be curved. FIG. 25A1 illustrates a state in which the imaging device is bent in the direction of a two-dot chain line X1-X2. FIG. 25A2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X1-X2 in FIG. 25A3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y1-Y2 in FIG.

FIG. 25B1 illustrates a state in which the imaging device is bent in the direction of a two-dot chain line X3-X4 in the drawing and in the direction of a two-dot chain line Y3-Y4 in the drawing. FIG. 25B2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X3-X4 in FIG. 25B3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y3-Y4 in FIG.

By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for aberration correction can be reduced, it is possible to reduce the size and weight of an electronic device using an imaging device. In addition, the quality of the captured image can be improved.

<CPU>
Hereinafter, a CPU including a semiconductor device such as the above-described transistor or the above-described memory device will be described.

FIG. 26 is a block diagram illustrating a configuration example of a CPU in which some of the above-described transistors are used.

26 includes an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. A rewritable ROM 1199 and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 26 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 26 may be a single core, and a plurality of the cores may be included so that each core operates in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

In the CPU illustrated in FIG. 26, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-described transistor, memory device, or the like can be used.

In the CPU illustrated in FIG. 26, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

FIG. 27 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a selection function. Circuit 1220 having. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.

Here, the memory device described above can be used for the circuit 1202. When supply of power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.

The switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 corresponds to the gate of the transistor 1213. In accordance with the control signal RD input to the second terminal, conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand). A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). A second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD. A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207 One of the pair of electrodes is electrically connected. Here, the connection part is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 can have a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.

Note that the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.

A control signal WE is input to the gate of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 27 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .

Note that FIG. 27 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.

In FIG. 27, a transistor other than the transistor 1209 among the transistors used for the memory element 1200 can be a transistor whose channel is formed in a film or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon film or a silicon substrate can be used. Further, all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.

For the circuit 1201 in FIG. 27, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device according to one embodiment of the present invention, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.

In addition, a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.

Further, by providing the switch 1203 and the switch 1204, the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.

In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state of the transistor 1210 (a conductive state or a non-conductive state) and read from the circuit 1202 Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.

By using such a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.

Although the memory element 1200 has been described as an example of using the CPU, the memory element 1200 can also be applied to DSPs (Digital Signal Processors), custom LSIs, LSIs such as PLDs (Programmable Logic Devices), and RF-IDs (Radio Frequency Identification). It is.

<Display device>
Hereinafter, a display device according to one embodiment of the present invention will be described with reference to FIGS.

As a display element used for the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element), or the like can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electroluminescence), organic EL, and the like. Hereinafter, a display device using an EL element (an EL display device) and a display device using a liquid crystal element (a liquid crystal display device) will be described as examples of the display device.

Note that a display device described below includes a panel in which a display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.

The display device described below refers to an image display device or a light source (including a lighting device). The display device includes all connectors, for example, a module to which FPC and TCP are attached, a module having a printed wiring board at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG method.

FIG. 28 illustrates an example of an EL display device according to one embodiment of the present invention. FIG. 28A shows a circuit diagram of a pixel of an EL display device. FIG. 28B is a top view showing the entire EL display device. FIG. 28C is an MN cross section corresponding to part of the dashed-dotted line MN in FIG.

FIG. 28A is an example of a circuit diagram of a pixel used in the EL display device.

Note that in this specification and the like, a person skilled in the art can connect all terminals of an active element (a transistor, a diode, etc.), a passive element (a capacitor element, a resistance element, etc.) without specifying connection destinations. Thus, it may be possible to constitute an aspect of the invention. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when a plurality of locations are assumed as the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, it is possible to constitute one embodiment of the present invention by specifying connection destinations of only some terminals of active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements, etc.). There is a case.

Note that in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

An EL display device illustrated in FIG. 28A includes a switch element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.

Note that FIG. 28A is an example of a circuit configuration; therefore, a transistor can be further added. On the other hand, it is possible not to add a transistor, a switch, a passive element, or the like at each node in FIG.

A gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor 742. A source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and electrically connected to one electrode of the light-emitting element 719. The source of the transistor 741 is supplied with the power supply potential VDD. The other end of the switch element 743 is electrically connected to the signal line 744. A constant potential is applied to the other electrode of the light-emitting element 719. Note that the constant potential is set to the ground potential GND or lower.

As the switch element 743, a transistor is preferably used. By using a transistor, the area of a pixel can be reduced and an EL display device with high resolution can be obtained. In addition, when a transistor manufactured through the same process as the transistor 741 is used as the switch element 743, the productivity of the EL display device can be increased. Note that as the transistor 741 and / or the switch element 743, for example, the above-described transistor can be used.

FIG. 28B is a top view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732. The sealant 734 is disposed between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. Note that the drive circuit 735 and / or the drive circuit 736 may be disposed outside the sealant 734.

FIG. 28C is a cross-sectional view of the EL display device corresponding to part of the dashed-dotted line MN in FIG.

In FIG. 28C, the transistor 741 includes the conductor 704a over the substrate 700, the insulator 712a over the conductor 704a, the insulator 712b over the insulator 712a, and the conductor 704a over the insulator 712b. A semiconductor 706 overlapping with the semiconductor 706, a conductor 716a and a conductor 716b in contact with the semiconductor 706, an insulator 718a over the semiconductor 706, the conductor 716a and the conductor 716b, an insulator 718b over the insulator 718a, and an insulator A structure including an insulator 718c over 718b and a conductor 714a over the insulator 718c and overlapping with the semiconductor 706 is illustrated. Note that the structure of the transistor 741 is just an example, and a structure different from the structure illustrated in FIG.

Therefore, in the transistor 741 illustrated in FIG. 28C, the conductor 704a functions as a gate electrode, the insulators 712a and 712b function as gate insulators, and the conductor 716a includes a source electrode. The conductor 716b functions as a drain electrode, the insulator 718a, the insulator 718b, and the insulator 718c function as a gate insulator, and the conductor 714a functions as a gate electrode. It has a function. Note that the electrical characteristics of the semiconductor 706 may fluctuate when exposed to light. Therefore, it is preferable that one or more of the conductor 704a, the conductor 716a, the conductor 716b, and the conductor 714a have a light-blocking property.

Note that although the interface between the insulator 718a and the insulator 718b is represented by a broken line, this indicates that the boundary between them may not be clear. For example, when the same kind of insulator is used as the insulator 718a and the insulator 718b, the two may not be distinguished depending on the observation technique.

28C, the capacitor 742 includes a conductor 704b over the substrate, an insulator 712a over the conductor 704b, an insulator 712b over the insulator 712a, and the conductor 704b over the insulator 712b. A conductor 716a overlapping with the conductor 716a, an insulator 718a over the conductor 716a, an insulator 718b over the insulator 718a, an insulator 718c over the insulator 718b, and a conductor overlying the conductor 716a over the insulator 718c. 714b, and in the region where the conductor 716a and the conductor 714b overlap with each other, part of the insulator 718a and the insulator 718b is removed.

In the capacitor 742, the conductor 704b and the conductor 714b function as one electrode, and the conductor 716a functions as the other electrode.

Therefore, the capacitor 742 can be manufactured using a film in common with the transistor 741. The conductors 704a and 704b are preferably the same kind of conductors. In that case, the conductor 704a and the conductor 704b can be formed through the same process. The conductors 714a and 714b are preferably the same kind of conductors. In that case, the conductor 714a and the conductor 714b can be formed through the same process.

A capacitor 742 illustrated in FIG. 28C is a capacitor having a large capacitance per occupied area. Accordingly, FIG. 28C illustrates an EL display device with high display quality. Note that the capacitor 742 illustrated in FIG. 28C has a structure in which part of the insulator 718a and the insulator 718b is removed in order to reduce a region where the conductor 716a and the conductor 714b overlap with each other. The capacitor according to one embodiment is not limited to this. For example, in order to thin the region where the conductors 716a and 714b overlap with each other, a structure in which part of the insulator 718c is removed may be employed.

An insulator 720 is provided over the transistor 741 and the capacitor 742. Here, the insulator 720 may have an opening reaching the conductor 716a functioning as a source electrode of the transistor 741. A conductor 781 is provided over the insulator 720. The conductor 781 may be electrically connected to the transistor 741 through the opening of the insulator 720.

A partition 784 having an opening reaching the conductor 781 is provided over the conductor 781. A light-emitting layer 782 that is in contact with the conductor 781 through the opening of the partition 784 is provided over the partition 784. A conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light emitting layer 782, and the conductor 783 overlap with each other serves as the light emitting element 719.

Up to this point, an example of an EL display device has been described. Next, an example of a liquid crystal display device will be described.

FIG. 29A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. The pixel shown in FIG. 29 includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 filled with liquid crystal between a pair of electrodes.

In the transistor 751, one of a source and a drain is electrically connected to the signal line 755 and a gate is electrically connected to the scanning line 754.

In the capacitor 752, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.

In the liquid crystal element 753, one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential. Note that the common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected may be different from the common potential applied to the other electrode of the liquid crystal element 753.

Note that the top view of the liquid crystal display device is the same as that of the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed-dotted line MN in FIG. 28B is illustrated in FIG. In FIG. 29B, the FPC 732 is connected to a wiring 733 a through a terminal 731. Note that the wiring 733a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 751.

The description of the transistor 741 is referred to for the transistor 751. For the capacitor 752, the description of the capacitor 742 is referred to. Note that FIG. 29B illustrates a structure of the capacitor 752 corresponding to the capacitor 742 in FIG. 28C; however, the structure is not limited thereto.

Note that in the case where an oxide semiconductor is used for the semiconductor of the transistor 751, a transistor with extremely low off-state current can be obtained. Therefore, the charge held in the capacitor 752 is unlikely to leak, and the voltage applied to the liquid crystal element 753 can be maintained for a long time. Therefore, when a moving image or a still image with little movement is displayed, the transistor 751 is turned off, so that power for the operation of the transistor 751 is not necessary and a liquid crystal display device with low power consumption can be obtained. In addition, since the area occupied by the capacitor 752 can be reduced, a liquid crystal display device with a high aperture ratio or a liquid crystal display device with high definition can be provided.

An insulator 721 is provided over the transistor 751 and the capacitor 752. Here, the insulator 721 has an opening reaching the transistor 751. A conductor 791 is provided over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening of the insulator 721.

An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is provided over the insulator 792. An insulator 794 functioning as an alignment film is provided over the liquid crystal layer 793. A spacer 795 is provided over the insulator 794. A conductor 796 is provided over the spacer 795 and the insulator 794. A substrate 797 is provided over the conductor 796.

With the above structure, a display device including a capacitor with a small occupied area can be provided, or a display device with high display quality can be provided. Alternatively, a high-definition display device can be provided.

For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. A display element, a display device, a light emitting element, or a light emitting device includes, for example, an EL element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), a light emitting diode such as white, red, green, or blue (LED: Light). Emitting Diode, transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), MEMS (micro electro mechanical device) System) display element, digital micromirror device (DMD), DMS (digital micro shutter), IMOD (interference modulation) element, shutter type MEMS display element, optical interference type MEMS table Elements, electrowetting element, a piezoelectric ceramic display, has at least one carbon nanotube. A display medium in which contrast, luminance, reflectance, transmittance, or the like is changed by an electric or magnetic effect may be included.

An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

In addition, when using LED, you may arrange | position graphene or graphite under the electrode and nitride semiconductor of LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor such as an n-type GaN semiconductor having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor having a crystal or the like can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal. Note that the GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can be formed by a sputtering method.

<Electronic equipment>
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.

FIG. 30A illustrates a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, speakers 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 30A includes the two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

FIG. 30B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. In addition, a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 30C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

FIG. 30D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

FIG. 30E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image | video in the display part 943 according to the angle between the 1st housing | casing 941 and the 2nd housing | casing 942 in the connection part 946. FIG.

FIG. 30F illustrates an automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

In this example, an example in which an evaluation by ESR and an evaluation by a microwave photoconductive decay method are performed on a sample having an oxide semiconductor on a substrate and an insulator on the oxide semiconductor is shown.

First, a method for manufacturing Sample A1, Sample A2, Sample A3, Sample A4, Sample A5, and Sample A6 that have been evaluated by ESR will be described.

First, a quartz substrate having a thickness of 0.5 mm was prepared as a substrate. Next, an In—Ga—Zn oxide with a thickness of 50 nm was formed as the oxide semiconductor. Next, heat treatment was performed at 450 ° C. for 1 hour in a nitrogen atmosphere. Next, heat treatment was performed at 450 ° C. for 1 hour in an oxygen atmosphere. Next, samples A1 to A6 were formed by depositing silicon oxynitride as an insulator.

Note that the In—Ga—Zn oxide was formed by a sputtering method using an In—Ga—Zn oxide target with an atomic ratio of In: Ga: Zn = 1: 1: 1. As the film forming gas, a gas in which argon and oxygen were mixed so that the volume of oxygen was 33% was used. The pressure during film formation was adjusted to 0.7 Pa with a miniature gauge MG-2 manufactured by Canon Anelva. The deposition power was 0.5 kW using a DC power source. The substrate temperature was 300 ° C.

Further, silicon oxynitride was formed using a PECVD method. As a film forming gas, a gas in which monosilane was mixed with 1 in a volume ratio of 800 to nitrous oxide was used. The pressure during film formation was adjusted to 200 Pa. The deposition power was 150 W using a 60 MHz high frequency power source. The gap between the electrodes was 28 mm. The substrate temperature was 350 ° C.

Note that the thickness of the silicon oxynitride was 5 nm for sample A1, 7.5 nm for sample A2, 10 nm for sample A3, 12.5 nm for sample A4, 15 nm for sample A5, and 20 nm for sample A6. .

Next, samples A1 to A6 were evaluated by ESR. Note that Samples A1 to A6 were placed so that the film surface of the In—Ga—Zn oxide was perpendicular to the magnetic field. The spin density of the defect level related to the signal in which the g value in Samples A1 to A6 appears near 1.93 is quantified and is shown in FIG. In addition, evaluation by ESR used the electron spin resonance apparatus JES-FA300 by JEOL Ltd.

From FIG. 31, no signal appeared in the vicinity of the g value of 1.93 when the silicon oxynitride was thin or thick. That is, the spin density was below the lower limit of detection (here, 1.4 × 10 ¹⁷ spins / cm ³ ). Therefore, it was suggested that damage to the In—Ga—Zn oxide occurred in the initial stage of film formation of silicon oxynitride. In addition, it was suggested that the damage of the In—Ga—Zn oxide is recovered by forming a thick silicon oxynitride film.

Next, a method for manufacturing Sample B1, Sample B2, Sample B3, Sample B4, Sample B5, and Sample B6 that were evaluated by the microwave photoconductive decay method will be described.

First, a quartz substrate having a thickness of 1.1 mm was prepared as a substrate. Next, an In—Ga—Zn oxide with a thickness of 40 nm was formed as a first layer of the oxide semiconductor. Next, an In—Ga—Zn oxide with a thickness of 60 nm was formed as a second layer of the oxide semiconductor. Next, heat treatment was performed at 450 ° C. for 1 hour in a nitrogen atmosphere. Next, heat treatment was performed at 450 ° C. for 1 hour in an oxygen atmosphere. Next, samples B1 to B6 were formed by depositing silicon oxynitride as an insulator.

Note that the first layer of In—Ga—Zn oxide was formed by a sputtering method using an In—Ga—Zn oxide target with an atomic ratio of In: Ga: Zn = 1: 3: 4. As the film forming gas, a gas in which argon and oxygen were mixed so that the volume of oxygen was 11% was used. The pressure during film formation was adjusted to 0.7 Pa with a miniature gauge MG-2 manufactured by Canon Anelva. The deposition power was 0.5 kW using a DC power source. The substrate temperature was 200 ° C.

The second layer of In—Ga—Zn oxide was formed by a sputtering method using an In—Ga—Zn oxide target with an atomic ratio of In: Ga: Zn = 1: 1: 1. As the film forming gas, a gas in which argon and oxygen were mixed so that the volume of oxygen was 33% was used. The pressure during film formation was adjusted to 0.7 Pa with a miniature gauge MG-2 manufactured by Canon Anelva. The deposition power was 0.5 kW using a DC power source. The substrate temperature was 300 ° C.

Further, silicon oxynitride was formed using a PECVD method. As a film forming gas, a gas in which nitrous oxide was mixed at a volume ratio of 800 with respect to monosilane 1 was used. The pressure during film formation was adjusted to 200 Pa. The deposition power was 150 W using a 60 MHz high frequency power source. The gap between the electrodes was 28 mm. The substrate temperature was 350 ° C.

Note that the thickness of the silicon oxynitride was 5 nm for sample B1, 7.5 nm for sample B2, 10 nm for sample B3, 12.5 nm for sample B4, 15 nm for sample B5, and 20 nm for sample B6. .

Next, the samples B1 to B6 were evaluated by the microwave photoconductive decay method. FIG. 32 shows peak values of the reflectance of the microwaves in the samples B1 to B6. As excitation light, a third harmonic (YLF-3HG, wavelength 349 nm) of a laser using yttrium lithium fluoride added with neodymium as a laser medium was used. The microwave photoconductive decay method was evaluated using a low-temperature polysilicon / SiC evaluation apparatus LTA-1800SP manufactured by Kobelco Research Institute.

From FIG. 32, it was found that the peak value of the reflectance of the microwave changes depending on the thickness of silicon oxynitride.

Here, in the comparison between the sample A1 to the sample A6 and the sample B1 to the sample B6, if the samples have the same silicon oxynitride conditions, it is possible to evaluate the corresponding data. Therefore, the horizontal axis represents the spin density measured by ESR in samples A1 to A6, and the vertical axis represents the peak value of the microwave reflectivity measured by the microwave photoconductive decay method in samples B1 to B6. By plotting the obtained data, their correlation can be evaluated (see FIG. 33).

According to FIG. 33, even in a sample in which the spin density is evaluated to be below the detection limit by ESR, if the peak value of the reflectance of the microwave measured by the microwave photoconductive decay method can be measured, the spin density can be calculated by extrapolation. The possibility of calculation was suggested. That is, the microwave photoconductive decay method may be able to quantify the spin density with higher sensitivity than ESR.

In this embodiment, since excitation light having a wavelength of 349 nm is used, the sensitivity of the microwave photoconductive decay method may not be sufficient. For example, by using laser light with a wavelength of less than 337 nm, less than 315 nm, less than 300 nm, or less than 270 nm (typically, a wavelength of 266 nm), the spin density of the oxide semiconductor may be evaluated with higher sensitivity.

100 Silicon substrate 110 Layer 120 Layer 130 Layer 140 Layer 151 Transistor 152 Transistor 153 Transistor 160 Photodiode 161 Anode 163 Low resistance area 170 Plug 171 Wiring 172 Wiring 173 Wiring 180 Insulator 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 Pixel 212 Subpixel 212B Subpixel 212G Subpixel 212R Subpixel 220 Photoelectric conversion element 230 Pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 Light 257 Wiring 260 Peripheral circuit 270 Peripheral circuit 280 Peripheral circuit 290 Peripheral circuit 291 Light source 301 Pulse Laser oscillator 302 Microwave oscillator 303 Directional coupler 305 Waveguide 305a Waveguide 305b Waveguide 306 Mixer 307 Signal processing device 310 Spacer 311 Sample stage 313 Mirror 314 Lens 315 Phaser 320 Sample 320a Semiconductor 320b Substrate 400 Substrate 401 Insulator 402 insulator 404 conductor 406 semiconductor 406a semiconductor 406b semiconductor 406c semiconductor 408 insulator 409a layer 409b layer 412 insulator 413 conductor 414 conductor 416a conductor 416b conductor 418 insulator 423a low resistance region 423b low resistance region 424a Conductor 424b Conductor 426a Conductor 426b Conductor 428 Insulator 430 Excitation light 436 Semiconductor 450 Semiconductor substrate 452 Insulator 454 Conductor 45 6 region 460 region 462 insulator 464 insulator 466 insulator 468 insulator 472a region 472b region 474a conductor 474b conductor 474c conductor 476a conductor 476b conductor 478a conductor 478b conductor 478c conductor 480b conductor 480b conductor 480b 480c Conductor 490 Insulator 492 Insulator 494 Insulator 496a Conductor 496b Conductor 496c Conductor 496d Conductor 498a Conductor 498b Conductor 498c Conductor 498d Conductor 600 Substrate 604 Conductor 606a Semiconductor 606b Semiconductor 606b Semiconductor 609b 60 Layer 612 insulator 613 conductor 616a conductor 616b conductor 618 insulator 620 insulator 700 substrate 704a conductor 704b conductor 706 semiconductor 71 2a insulator 712b insulator 714a conductor 714b conductor 716a conductor 716b conductor 718a insulator 718b insulator 718c insulator 719 light emitting element 720 insulator 721 insulator 731 terminal 732 FPC
733a wiring 734 sealant 735 drive circuit 736 drive circuit 737 pixel 741 transistor 742 capacitor element 743 switch element 744 signal line 750 substrate 751 transistor 752 capacitor element 753 liquid crystal element 754 scan line 755 signal line 781 conductor 782 light emitting layer 783 conductor 784 Partition 791 Conductor 792 Insulator 793 Liquid crystal layer 794 Insulator 795 Spacer 796 Conductor 797 Substrate 901 Housing 902 Housing 903 Display portion 904 Display portion 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display portion 914 Display unit 915 Connection unit 916 Operation key 921 Case 922 Display unit 923 Keyboard 924 Pointing device 931 Case 932 Refrigerated room Door 933 a freezer door 941 housing 942 housing 943 display unit 944 operation keys 945 lens 946 connecting portions 951 body 952 wheel 953 dashboard 954 Light 1189 ROM interface 1190 substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 Memory element 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic element 1207 Capacitor element 1208 Capacitor element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistor 3300 Transistor 3400 Capacitor element

Claims (8)

1. An insulator, a semiconductor, and a conductor;
   The semiconductor has a region where the semiconductor and the conductor overlap with each other through the insulator,
   In the region, the semiconductor has a region in which the component that rapidly decays out of the lifetime of the carrier by the microwave photoconductive decay method is 30 nsec or more and 200 nsec or less,
   The microwave photoconductive decay method uses excitation light having a wavelength of less than 337 nm.
2. In claim 1,
   The microwave photoconductive decay method uses excitation light having a wavelength of less than 270 nm.
3. In claim 1 or claim 2,
   The semiconductor device is an oxide semiconductor.
4. In claim 3,
   The semiconductor device includes an oxide including one or more selected from indium, zinc, and an element M (the element M is aluminum, gallium, yttrium, or tin).
5. An insulator;
   A conductor;
   In a method for evaluating a semiconductor device having a semiconductor having a region overlapping with the conductor via the insulator,
   Measure the carrier lifetime in the region by microwave photoconductive decay method,
   The method for evaluating a semiconductor device, wherein the microwave photoconductive decay method uses excitation light having a wavelength of less than 337 nm.
6. In claim 5,
   In the microwave photoconductive decay method, excitation light having a wavelength of less than 270 nm is used.
7. In claim 5 or claim 6,
   The method for evaluating a semiconductor device, wherein the semiconductor is an oxide semiconductor.
8. In claim 7,
   The method for evaluating a semiconductor device, wherein the semiconductor includes an oxide having at least one selected from indium, zinc, and an element M (the element M is aluminum, gallium, yttrium, or tin).

Images