WO2016006115A1 - Design program, design device, and design method - Google Patents

Design program, design device, and design method Download PDF

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Publication number
WO2016006115A1
WO2016006115A1 PCT/JP2014/068635 JP2014068635W WO2016006115A1 WO 2016006115 A1 WO2016006115 A1 WO 2016006115A1 JP 2014068635 W JP2014068635 W JP 2014068635W WO 2016006115 A1 WO2016006115 A1 WO 2016006115A1
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Prior art keywords
delay value
signal line
width
design
calculated
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PCT/JP2014/068635
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French (fr)
Japanese (ja)
Inventor
吉田浩
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富士通株式会社
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Priority to JP2015531386A priority Critical patent/JP6028867B2/en
Priority to PCT/JP2014/068635 priority patent/WO2016006115A1/en
Publication of WO2016006115A1 publication Critical patent/WO2016006115A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]

Definitions

  • the present invention relates to a design program, a design apparatus, and a design method for designing a semiconductor device.
  • the semiconductor device includes a semiconductor integrated circuit element and a printed board on which the semiconductor integrated circuit element is mounted.
  • a semiconductor device is generally designed by a design device which is a computer system having a design program. The design of a semiconductor device relates not only to the arrangement of semiconductor integrated circuit elements but also to signal transmission paths.
  • FIG. 1 is a cross-sectional view of a general semiconductor device.
  • FIG. 2 is a plan view of a general semiconductor device.
  • the semiconductor device 1 has a semiconductor integrated circuit element 3 mounted on one surface (upper surface) 21 of a printed board 2.
  • An external connection terminal 4 is formed on the other surface (lower surface) 22 of the printed circuit board 2.
  • the semiconductor integrated circuit element 3 is connected to the external connection terminal 4 by a plurality of signal lines 5.
  • a timing verification simulation for checking the logic circuit operation may be executed. This timing verification is to confirm the operation of the semiconductor integrated circuit element 3 to which a signal is supplied based on the calculated delay time of the signal transmission path. At this time, a time difference (clock skew) may occur in the clock signal. This is due to the difference in the path length between the signal line 51 and the signal line 52. When clock skew occurs, delay time adjustment (skew adjustment) is performed.
  • the signal delays of the signal line 51 and the signal line 52 are matched by adopting a meander shape for the wiring.
  • the meander-shaped wiring is a wiring having a zigzag wiring pattern, and is a wiring laid while being alternately folded back in one direction and the other direction.
  • FIG. 3 is a diagram illustrating a meander-shaped signal line. As shown in FIG. 3, for example, the signal line 52 in FIG. 2 is changed to a meander-shaped meander signal line 52A. Thereby, the time difference between the clock signals of the signal line 51 and the meander signal line 52A is adjusted.
  • FIG. 4 is a flowchart showing the flow of conventional design processing.
  • the design process shown in FIG. 4 is executed by a design apparatus that is a computer system loaded with a design program. For example, it is executed as a CAD (Computer Aided Design) tool that operates on a personal computer.
  • CAD Computer Aided Design
  • step S401 data used for manufacturing a semiconductor device is input.
  • the input data includes the position information of the semiconductor integrated circuit elements of the CAD tool and the connection terminals of the printed circuit board.
  • step S402 the connection terminal of the semiconductor integrated circuit element and the connection terminal of the printed circuit board are connected.
  • step S403 it is determined whether or not the delays match between the connected signal lines.
  • step S403 If they match (step S403: Yes), the present design process is terminated. On the other hand, if they do not match (step S403: No), in step S404, the signal lines are formed in a meander shape on the wiring surface so that the delays match between the signals.
  • step S405 it is determined whether or not the delays match between the signal lines on which the meander shapes are formed.
  • step S405 Yes
  • step S405: No If they match, the present design process is terminated. On the other hand, if they do not match (step S405: No), in step S406, the signal lines are formed so as to be switched to another layer so that the delays match among the signals.
  • step S407 it is determined whether or not the delays match between the signal lines formed over the plurality of layers.
  • step S407: Yes If they match (step S407: Yes), the present design process is terminated. On the other hand, if they do not match (step S407: No), in step S408, it is examined whether adjustment is possible using another method. If adjustment is possible using another method, that method is executed, and the present design process ends.
  • the wiring board has first, third, and second three layers in order.
  • the first wiring is formed of only the first layer in the first region.
  • the second region around the first region is formed of first to third layers.
  • the second wiring is formed of first to third layers in the first region. In the second region, only the first layer is formed.
  • the first wiring and the second wiring intersect in the first region (see, for example, Patent Document 1).
  • Patent Document 2 a structure is disclosed in which two layers of conductors are connected by vertical electrodes and wirings are three-dimensionally crossed (see, for example, Patent Document 2).
  • the bent part of the two differential signal line pairs wired in parallel with each other is once divided, and a detour part having a delay wiring body with a predetermined plate thickness is provided there to eliminate the delay time difference in signal transmission.
  • a wiring board device is disclosed (for example, refer to Patent Document 3).
  • the substrate is revised, and reworking occurs in the subsequent process.
  • an object of the present invention is to prevent a variation in delay time of a transmission signal and reduce skew, thereby preventing deterioration of electrical characteristics in the semiconductor device and performing fine delay adjustment. It is an object of the present invention to provide a design program, a design apparatus, and a design method for designing a possible semiconductor device.
  • a design program configures the semiconductor device by partially overlapping conductors on a computer of the design device that designs the semiconductor device, based on data used to manufacture the semiconductor device. Forming a signal line connecting the semiconductor integrated circuit and the external connection terminal in a meander shape, calculating a delay value of the signal line, comparing the delay value and the input requested delay value, and the delay value is When the request delay value is matched, a process for outputting the signal line as a simulation result is executed.
  • FIG. 5 is a cross-sectional view of a semiconductor device having meander-shaped signal lines.
  • the semiconductor device 1A is designed by the design process of the present embodiment.
  • the semiconductor integrated circuit element 3 is mounted on one surface (upper surface) 21 of the printed board 2.
  • An external connection terminal 4 is formed on the other surface (lower surface) 22 of the printed circuit board 2.
  • the semiconductor integrated circuit element 3 is connected to the external connection terminal 4 by a plurality of meander signal lines 6.
  • the meander signal line 6 forms a meander shape designed by the design processing of the present embodiment.
  • FIG. 6 is a diagram for explaining a meander shape in the present embodiment.
  • the meander signal line 61 is formed in a meander shape by partially overlapping conductors in the same layer.
  • FIG. 7 is a diagram for explaining the overlap width and the wiring width.
  • the conductor 61A and the conductor 61B are partially overlapped to form the meander signal line 61 shown in FIG.
  • FIG. 7A shows the meander signal line 61 on the plane (XY plane) of the semiconductor device.
  • the widths of the conductors 61A and 61B constituting the meander signal line 61 in the width direction are indicated by arrows.
  • FIG. 7B shows the meander signal line 61 in the cross section of the semiconductor device.
  • the overlapping width (ov width) of the conductor 61A and the conductor 61B constituting the meander signal line 61 in the length direction is indicated by an arrow.
  • FIG. 8 is a diagram showing an overview of the present embodiment.
  • the board information DB (Data Base) 81 is basic information such as board outline, number of layers, material, thickness, SVG (signal, power supply, GND) type, electrical characteristics, drill diameter, pad diameter, clearance diameter, and the like. Is stored.
  • the mounted component information DB 82 stores mounted component information such as a die (Die) pin definition, a BGA (Ball Grid Array) pin definition, and a component definition such as a capacitor.
  • the connection information DB 83 stores connection information such as Netlist definition such as Die-BGA connection.
  • a DRC (Design Rule Check) information DB 84 stores design rule check information such as a line-via-shape clearance, a line width and layer restriction (no wiring designation), a differential wiring rule, a manufacturability rule, and the like.
  • the basic pattern design is based on the basic information stored in the board information DB 81, the mounted component information stored in the mounted component information DB 82, the connection information stored in the connection information DB 83, and the design rule check information stored in the DRC information DB 84. Based on. A power plane may be created or wiring may be added. After the basic pattern design, simulation such as transmission analysis and power supply analysis is executed. Thereafter, addition and deletion of layers and vias, correction of wiring and planes are performed, and basic pattern design is executed again. Then, the design rule is checked, and board manufacturing data such as a GBR file, component mounting data (mounter position information), and a board mounting diagram (board outer dimensions, pad dimensions, preliminary solder specifications, etc.) are output.
  • board manufacturing data such as a GBR file, component mounting data (mounter position information), and a board mounting diagram (board outer dimensions, pad dimensions, preliminary solder specifications, etc.) are output.
  • FIG. 9 is a diagram illustrating functional blocks of the design apparatus according to the present embodiment.
  • the design apparatus 90 includes a signal line forming unit 91, a delay value calculating unit 92, a first delay value comparing unit 93, a result output unit 94, a second delay value comparing unit 95, an overlap width changing unit 96, a third A delay value comparing unit 97 and an overlapping wiring width changing unit 98 are provided.
  • the design apparatus 90 is a computer system that includes a design program, and designs a semiconductor device that includes a semiconductor integrated circuit element and a printed circuit board that includes the semiconductor integrated circuit element.
  • the signal line forming unit 91 is a signal line that connects a semiconductor integrated circuit constituting the semiconductor device and an external connection terminal by partially overlapping conductors based on data used for manufacturing the semiconductor device. Is formed in a meander shape.
  • the delay value calculation unit 92 calculates the delay value of the signal line formed by the signal line forming unit 91.
  • the first delay value comparison unit 93 compares the delay value calculated by the delay value calculation unit 92 with the input requested delay value.
  • the result output unit 94 outputs the signal line as a simulation result when the delay value matches the required delay value as a result of the comparison by the first delay value comparison unit 93.
  • the second delay value comparison unit 95 compares the delay value with a first allowable delay value within a predetermined range when the delay value does not match the required delay value.
  • the overlap width changing unit 96 changes the overlap width in the length direction of the conductor.
  • the third delay value comparison unit 97 when the delay value calculated after the change of the overlap width does not match the required delay value, the delay value calculated after the change of the overlap width and a second allowable value within a predetermined range. Compare the delay value.
  • the overlapping wiring width changing unit 98 changes the wiring width in the width direction of the overlapping portion of the conductor when the delay value is within the range of the second allowable delay value as a result of the comparison by the third delay value comparing unit 97. To do.
  • the delay value calculation unit 92 calculates the delay value of the signal line after the overlap width is changed.
  • the first delay value comparison unit 93 compares the delay value calculated after the overlap width is changed with the input requested delay value.
  • the result output unit 94 outputs the signal line as a simulation result when the delay value calculated after the overlap width is changed matches the required delay value.
  • the delay value calculation unit 92 calculates the delay value of the signal line after the change of the wiring width.
  • the first delay value comparison unit 93 compares the delay value calculated after the change of the wiring width with the input requested delay value.
  • the result output unit 94 outputs the signal line as a simulation result when the delay value calculated after changing the wiring width matches the required delay value.
  • the second allowable delay value is within a range of the first allowable delay value.
  • the signal line is preferably formed in the same layer of the semiconductor device.
  • the required delay value preferably has a predetermined continuous numerical range.
  • the design apparatus 90 described with reference to FIG. 9 executes a design process using a design program.
  • delay adjustment has been performed by means of a meander shape, which can be performed only in a limited manner, but fine delay adjustment can be performed by this design process.
  • the meander wiring in the Z-axis direction is formed without changing the layer, and the overlap which is the overlapping portion in the length direction of the conductor by the three-stage design of the initial design, the first detailed design and the second detailed design.
  • the width and the wiring width, which is the overlapping part in the width direction of the conductor it is possible to finely adjust the delay.
  • FIG. 10 and 12 are flowcharts showing the flow of the design process according to the present embodiment.
  • FIG. 11 is a diagram for explaining the initial design.
  • FIG. 13 is a diagram illustrating the first detailed design.
  • FIG. 14 is a diagram for explaining the second detailed design.
  • steps S401 to S405 of the conventional design process described with reference to FIG. 10 are the same as steps S401 to S405 of the conventional design process described with reference to FIG.
  • step S1001 If it is determined in step S405 that the delay does not match between the signal lines in which the meander shape is formed (step S405: No), in step S1001, the upper and lower conductor patterns can be formed on the same layer. Perform layer definition on the tool.
  • step S1002 a meander-shaped signal line is formed on the XYZ plane in the same layer defined in step S1001, based on the position information of the connection terminal input in step S401.
  • the meander-shaped signal lines in the Z-axis direction are alternately connected so that the upper conductor pattern and the lower conductor pattern overlap with each other with the initial values shown on the horizontal axis of FIG.
  • step S1003 the delay value of the meander-shaped signal line formed in step S1002 is calculated.
  • the calculated delay value is an initial value shown on the vertical axis of FIG.
  • step S1004 it is determined whether or not the delay value calculated in step S1003 satisfies the request delay value input in advance.
  • the required delay value has a predetermined width as shown in FIG.
  • step S1004 When the calculated delay value satisfies the required delay value (step S1004: Yes), the design process is terminated. On the other hand, as shown in FIG. 11, when the calculated delay value does not satisfy the required delay value (step S1004: No), in step S1005, a first lower limit value that is a delay value in the minimum overlap width (ov width min). Then, a first upper limit value that is a delay value in the maximum overlap width (ov width max) is calculated.
  • step S1006 it is determined whether the required delay value is between the first upper limit value and the first lower limit value calculated in step S1005.
  • step S1006 If the requested delay value is not between the first upper limit value and the first lower limit value (step S1006: No), the process returns to step S1001.
  • the processes in steps S1001 to S1006 are called initial design.
  • first detailed design fine delay adjustment is performed by adjusting the overlap width (ov width). For example, by increasing the overlap width (ov width), the delay value increases because the capacity of the overlap portion increases. Further, by reducing the overlap width (ov width), the capacity of the overlap portion is reduced, so that the delay value is reduced.
  • step S1006 When the required delay value is between the first upper limit value and the first lower limit value (step S1006: Yes), in step S1201 of FIG. 12, the above-described initial design delay value and overlap width are taken in, and in step S1202, the first delay value is obtained. 1 Take in the required delay value that is the target in the detailed design. Usually, it is the same value as the required delay value in the initial design.
  • step S1203 the overlap width (ov width) to be changed is obtained.
  • the overlap width (ov width) is increased.
  • the overlap width (ov width) is reduced. In the example shown in FIG. 13, the overlap width (ov width) is increased.
  • step S1204 the delay value of the signal line having the changed overlap width (ov width) is calculated, and it is determined whether or not the required delay value is satisfied.
  • step S1204 When the calculated delay value satisfies the required delay value (step S1204: YES), after determining with the overlap width (ov width) obtained in step S1203 in step S1205, the design process is terminated. On the other hand, as shown in FIG. 13, when the calculated delay value does not satisfy the required delay value (step S1204: No), in step S1206, a second lower limit value that is a delay value in the minimum overlap width (ov width min). Then, a second upper limit value that is a delay value in the maximum overlap width (ov width max) is calculated.
  • step S1207 it is determined whether the required delay value is between the second upper limit value and the second lower limit value calculated in step S1206.
  • step S1207: No When the requested delay value is not between the second upper limit value and the second lower limit value (step S1207: No), the process returns to step S1203. On the other hand, when the requested delay value is between the second upper limit value and the second lower limit value (step S1207: Yes), in step S1208, the overlap width (ov width) obtained in step S1203 is determined.
  • steps S1209 to S1213 described below is referred to as second detailed design.
  • fine delay adjustment is performed by adjusting the wiring width (ov wiring width). For example, by increasing (thickening) the wiring width (ov wiring width), the capacity of the overlapping portion increases, so that the delay value increases. Further, by reducing (thinning) the wiring width (ov wiring width), the capacity of the overlapping portion is reduced, so that the delay value is reduced.
  • step S1207 When the required delay value is between the second upper limit value and the second lower limit value (step S1207: Yes), after the overlap width (ov width) is determined in step S1208, in step S1209, the first detailed design described above is performed. Capture delay value and overlap width. In step S1210, a required delay value targeted in the second detailed design is captured. Usually, it is the same value as the required delay value in the first detailed design.
  • step S1211 the wiring width to be changed (ov wiring width) is obtained.
  • the wiring width (ov wiring width) is increased.
  • the wiring width (ov wiring width) is decreased. In the example shown in FIG. 14, the wiring width (ov wiring width) is increased.
  • step S1212 the delay value of the signal line having the changed overlap width (ov width) is calculated, and it is determined whether or not the required delay value is satisfied.
  • step S1212: Yes When the calculated delay value satisfies the required delay value (step S1212: Yes), the design process is terminated after determining the wiring width (ov wiring width) obtained in step S1211 in step S1213. On the other hand, as shown in FIG. 14, when the calculated delay value does not satisfy the required delay value (step S1212: No), the process returns to step S1001 in FIG. 10 to perform redesign from the initial design.
  • the above design process enables fine delay adjustment without generating additional man-hours in the subsequent process and without affecting other wiring.
  • FIG. 15 is a diagram illustrating a first specific example.
  • FIG. 15A is a cross-sectional view of the first specific example.
  • the insulating layer thickness (b) 75 micrometers ( ⁇ m)
  • the conductor thickness (t) 15 ⁇ m
  • the distance between the upper conductor and the upper GND plane (h1) 22.5 ⁇ m
  • the lower conductor And the lower GND surface distance (h2) 22.5 ⁇ m
  • the distance from point M to point N is 2060 ⁇ m.
  • FIG. 16 is a diagram illustrating a second specific example.
  • FIGS. 16A and 16B are a second specific example, and FIGS. 16C and 16D are conventional examples.
  • the number of stacked conductors shown in the second specific example is one layer larger than the number of stacked conductors of the conventional example shown in FIG. It has become.
  • the insulating layer thickness (b) 75 ⁇ m
  • the conductor thickness (t) 15 ⁇ m
  • the distance between the upper conductor and the upper GND plane (h1) 15 ⁇ m
  • the lower conductor And the lower GND surface distance (h2) 15 ⁇ m.
  • the overlap portion ( ⁇ l) (overlap portion) and the impedance (Zo) before and after it (la, lb) are compared. Since the impedance (Zo) is calculated by the square root of the quotient of the inductance and the capacitance, a difference occurs.
  • the difference of Zo between the ⁇ l part and the la and lb parts is ⁇ 11.55 ⁇ as shown in FIG. 16B in the second specific example.
  • the conventional example has ⁇ 16.82 ⁇ as shown in FIG.
  • the present embodiment can suppress impedance discontinuity.
  • FIG. 17 is a diagram illustrating a third specific example.
  • FIG. 17A is a cross-sectional view of a third specific example.
  • the insulating layer thickness (b) 75 ⁇ m
  • the conductor thickness (t) 15 ⁇ m
  • the distance between the upper conductor and the upper GND plane (h1) 22.5 ⁇ m
  • the distance (h2) 22.5 ⁇ m
  • the distance from point M to point N is 2060 ⁇ m.
  • FIG. 18 is a diagram for explaining the manufacturing process of the semiconductor device designed by the design process of the present embodiment.
  • the semiconductor device designed as described above can be manufactured as shown in FIG.
  • a first insulating layer is formed by laminating a resin on the first conductor as the core layer.
  • a second lower conductor is formed on the first insulating layer.
  • a resin is laminated on the second lower conductor to form a second lower insulating layer.
  • the resin is polished to expose the second lower conductor.
  • a second upper conductor is formed on the exposed second lower conductor, and the upper and lower conductors are connected.
  • a third insulating layer is formed on the second upper conductor.
  • a third conductor is formed on the third insulating layer.
  • the second upper conductor and the second lower conductor can be overlapped and connected without using a vertical electrode, so that the thickness of the semiconductor device can be reduced.
  • the signal lines are meandered in the XYZ plane (X plane: substrate lateral direction, Y: substrate depth direction, Z: substrate cross-sectional direction) in the same layer without changing layers. I made it.
  • the Z-axis meandering shape is such that the upper conductor pattern and the lower conductor pattern are overlapped and connected without using a vertical electrode. As a result, fine delay adjustment is possible.
  • impedance discontinuity can be suppressed by reducing the conductor thickness of the overlapping portion.
  • the design process of the present embodiment can efficiently perform fine delay adjustment.
  • FIG. 9 can be implemented as a hardware circuit or can be realized by using an information processing apparatus (computer) as shown in FIG.
  • CPU 19 includes a central processing unit (CPU) 1901, a memory 1902, an input device 1903, an output device 1904, an external recording device 1905, a medium driving device 1906, and a network connection device 1907. These components are connected to each other by a bus 1908.
  • CPU central processing unit
  • the memory 1902 is, for example, a semiconductor memory such as a Read Only Memory (ROM), a Random Access Memory (RAM), or a flash memory, and stores programs and data used for design processing.
  • ROM Read Only Memory
  • RAM Random Access Memory
  • flash memory any type of non-volatile memory
  • the CPU 1901 executes a design program using the memory 1902 to thereby generate a signal line forming unit 91, a delay value calculating unit 92, a first delay value comparing unit 93, a result output unit 94,
  • the second delay value comparing unit 95, the overlapping width changing unit 96, the third delay value comparing unit 97, and the overlapping wiring width changing unit 98 are operated.
  • the input device 1903 is, for example, a keyboard, a pointing device, and the like, and is used for inputting instructions and information from a user or an operator.
  • the output device 1904 is, for example, a display device, a printer, a speaker, or the like, and is used to output an inquiry to a user or an operator or a processing result.
  • the external recording device 1905 is, for example, a magnetic disk device, an optical disk device, a magneto-optical disk device, a tape device, or the like.
  • the external recording device 1905 may be a hard disk drive.
  • the information processing apparatus can store programs and data in the external recording device 1905 and load them into the memory 1902 for use.
  • the medium driving device 1906 drives the portable recording medium 1909 and accesses the recorded contents.
  • the portable recording medium 1909 is a memory device, a flexible disk, an optical disk, a magneto-optical disk, or the like.
  • the portable recording medium 1909 may be a Compact Disk Read Only Memory (CD-ROM), Digital Versatile Disk (DVD), or Universal Serial Bus (USB) memory.
  • CD-ROM Compact Disk Read Only Memory
  • DVD Digital Versatile Disk
  • USB Universal Serial Bus
  • the computer-readable recording medium that stores the program and data used for processing includes physical (non-transitory) media such as the memory 1902, the external recording device 1905, and the portable recording medium 1909. A recording medium is included.
  • the network connection device 1907 is a communication interface that is connected to a communication network such as Local Area Network (LAN) or the Internet and performs data conversion accompanying communication.
  • the information processing apparatus can also receive a program and data from an external apparatus via the network connection apparatus 1907 and load them into the memory 1902 for use.
  • the information processing apparatus does not have to include all the components shown in FIG. 19, and some of the components can be omitted depending on the application and conditions. For example, when an interface with a user or an operator is unnecessary, the input device 1903 and the output device 1904 may be omitted. When the information processing apparatus does not access the portable recording medium 1909, the medium driving device 1906 may be omitted.

Abstract

Disclosed is a design program whereby: a signal line for connecting a semiconductor integrated circuit and an external connection terminal is formed in a meandering shape by having conductive bodies partially overlap each other on the basis of data to be used for the purpose of manufacturing a semiconductor device, said semiconductor integrated circuit and external connection terminal constituting the semiconductor device; a delay value of the signal line is calculated; the delay value and an inputted request delay value are compared with each other; and the signal line is outputted as a simulation result in the cases where the delay value matches the request delay value.

Description

設計プログラム、装置及び方法Design program, apparatus and method
　本発明は、半導体装置を設計する設計プログラム、設計装置及び設計方法に関する。 The present invention relates to a design program, a design apparatus, and a design method for designing a semiconductor device.
　半導体装置は、半導体集積回路素子と、半導体集積回路素子を搭載したプリント基板とを備える。半導体装置は、一般的には設計プログラムを搭載したコンピューターシステムである設計装置によって設計される。半導体装置の設計は、半導体集積回路素子の配列に関するだけではなく信号伝送経路にも関する。 The semiconductor device includes a semiconductor integrated circuit element and a printed board on which the semiconductor integrated circuit element is mounted. A semiconductor device is generally designed by a design device which is a computer system having a design program. The design of a semiconductor device relates not only to the arrangement of semiconductor integrated circuit elements but also to signal transmission paths.
　図１は、一般的な半導体装置の断面図である。図２は、一般的な半導体装置の平面図である。 FIG. 1 is a cross-sectional view of a general semiconductor device. FIG. 2 is a plan view of a general semiconductor device.
　図１及び図２において、半導体装置１は、プリント基板２の一の表面（上面）２１に半導体集積回路素子３が実装されている。また、プリント基板２の他の表面（下面）２２には外部接続端子４が形成されている。そして、半導体集積回路素子３は、複数の信号線５により外部接続端子４と接続されている。 1 and 2, the semiconductor device 1 has a semiconductor integrated circuit element 3 mounted on one surface (upper surface) 21 of a printed board 2. An external connection terminal 4 is formed on the other surface (lower surface) 22 of the printed circuit board 2. The semiconductor integrated circuit element 3 is connected to the external connection terminal 4 by a plurality of signal lines 5.
　例えば、半導体装置１の設計工程において、論理回路動作を確認するタイミング検証のシミュレーションを実行することがある。このタイミング検証は、算出した信号伝達経路の遅延時間に基づいて、信号が供給される半導体集積回路素子３の動作を確認するものである。この際、クロック信号に時間差（クロックスキュー）が生じる場合がある。これは、信号線５１と信号線５２の経路長の相違に起因するものである。クロックスキューが生じた場合、遅延時間の調整（スキュー調整）が行われる。 For example, in the design process of the semiconductor device 1, a timing verification simulation for checking the logic circuit operation may be executed. This timing verification is to confirm the operation of the semiconductor integrated circuit element 3 to which a signal is supplied based on the calculated delay time of the signal transmission path. At this time, a time difference (clock skew) may occur in the clock signal. This is due to the difference in the path length between the signal line 51 and the signal line 52. When clock skew occurs, delay time adjustment (skew adjustment) is performed.
　近年、信号伝送の高速化により、２つの信号間の時間差に対する要求は厳しい。そのため、半導体装置１における遅延時間の調整は非常に重要である。 In recent years, the demand for the time difference between two signals is severe due to the high speed of signal transmission. Therefore, adjustment of the delay time in the semiconductor device 1 is very important.
　従来、半導体装置１における遅延時間の調整は、配線にミアンダ形状を採用することにより、信号線５１と信号線５２の信号ディレイを一致させていた。ミアンダ形状の配線とは、ジグザグ状の配線パターンの配線であり、一方向と反対の他方向とに交互に折り返しながら敷設された配線である。 Conventionally, in the adjustment of the delay time in the semiconductor device 1, the signal delays of the signal line 51 and the signal line 52 are matched by adopting a meander shape for the wiring. The meander-shaped wiring is a wiring having a zigzag wiring pattern, and is a wiring laid while being alternately folded back in one direction and the other direction.
　図３は、ミアンダ形状の信号線を示す図である。
　図３に示すように、例えば、図２の信号線５２をミアンダ形状のミアンダ信号線５２Ａにする。これにより、信号線５１とミアンダ信号線５２Ａのクロック信号の時間差が調整される。 FIG. 3 is a diagram illustrating a meander-shaped signal line.
As shown in FIG. 3, for example, the signal line 52 in FIG. 2 is changed to a meander-shaped meander signal line 52A. Thereby, the time difference between the clock signals of the signal line 51 and the meander signal line 52A is adjusted.
　図４は、従来の設計処理の流れを示すフローチャートである。
　図４に示す設計処理は、設計プログラムを搭載したコンピューターシステムである設計装置によって実行される。例えば、パソコン上で動作するＣＡＤ（Computer Aided Design）ツールとして実行される。 FIG. 4 is a flowchart showing the flow of conventional design processing.
The design process shown in FIG. 4 is executed by a design apparatus that is a computer system loaded with a design program. For example, it is executed as a CAD (Computer Aided Design) tool that operates on a personal computer.
　まず、ステップＳ４０１において、半導体装置を製造するために用いられるデータを入力する。入力するデータは、ＣＡＤツールの半導体集積回路素子及びプリント基板の接続端子の位置情報を含む。ステップＳ４０２において、半導体集積回路素子の接続端子とプリント基板の接続端子を結線する。 First, in step S401, data used for manufacturing a semiconductor device is input. The input data includes the position information of the semiconductor integrated circuit elements of the CAD tool and the connection terminals of the printed circuit board. In step S402, the connection terminal of the semiconductor integrated circuit element and the connection terminal of the printed circuit board are connected.
　そして、ステップＳ４０３において、結線された信号線間でディレイが一致するか否かを判断する。 In step S403, it is determined whether or not the delays match between the connected signal lines.
　一致すれば（ステップＳ４０３：Ｙｅｓ）、本設計処理を終了する。他方、一致しなければ（ステップＳ４０３：Ｎｏ）、ステップＳ４０４において、各信号間でディレイが一致するように、信号線を配線面でミアンダ形状に形成する。 If they match (step S403: Yes), the present design process is terminated. On the other hand, if they do not match (step S403: No), in step S404, the signal lines are formed in a meander shape on the wiring surface so that the delays match between the signals.
　ステップＳ４０５において、ミアンダ形状が形成された信号線間でディレイが一致するか否かを判断する。 In step S405, it is determined whether or not the delays match between the signal lines on which the meander shapes are formed.
　一致すれば（ステップＳ４０５：Ｙｅｓ）、本設計処理を終了する。他方、一致しなければ（ステップＳ４０５：Ｎｏ）、ステップＳ４０６において、各信号間でディレイが一致するように、信号線を他の層に乗り換えるように形成する。 If they match (step S405: Yes), the present design process is terminated. On the other hand, if they do not match (step S405: No), in step S406, the signal lines are formed so as to be switched to another layer so that the delays match among the signals.
　ステップＳ４０７において、複数の層に渡って形成された信号線間でディレイが一致するか否かを判断する。 In step S407, it is determined whether or not the delays match between the signal lines formed over the plurality of layers.
　一致すれば（ステップＳ４０７：Ｙｅｓ）、本設計処理を終了する。他方、一致しなければ（ステップＳ４０７：Ｎｏ）、ステップＳ４０８において、他の方法で調整できないかを検討し、他の方法で調整可能であればその方法を実行し、本設計処理を終了する。 If they match (step S407: Yes), the present design process is terminated. On the other hand, if they do not match (step S407: No), in step S408, it is examined whether adjustment is possible using another method. If adjustment is possible using another method, that method is executed, and the present design process ends.
　また、以下のような従来技術が開示されている。
　配線レイアウトの自由度を高め、伝送信号の劣化を抑制するために、２つの配線を立体的に交差する技術が開示されている。例えば、下記のように構成されている。配線基板は、順に第１、第３、第２の３層を有する。１つ目の配線は、第１領域においては第１の層のみで形成されている。第１領域周辺の第２領域においては第１乃至第３の層で形成されている。２つ目の配線は、第１領域においては第１乃至第３の層で形成されている。第２領域においては第１の層のみで形成されている。そして、１つ目の配線と２つ目の配線は、第１の領域で交差する（例えば、特許文献１を参照。）。 The following prior art is disclosed.
In order to increase the degree of freedom of the wiring layout and suppress the deterioration of the transmission signal, a technique for crossing two wirings in a three-dimensional manner is disclosed. For example, it is configured as follows. The wiring board has first, third, and second three layers in order. The first wiring is formed of only the first layer in the first region. The second region around the first region is formed of first to third layers. The second wiring is formed of first to third layers in the first region. In the second region, only the first layer is formed. The first wiring and the second wiring intersect in the first region (see, for example, Patent Document 1).
　また、２層の導体間を垂直電極で接続し、立体的に配線を交差する構造が開示されている（例えば、特許文献２を参照。）。 Further, a structure is disclosed in which two layers of conductors are connected by vertical electrodes and wirings are three-dimensionally crossed (see, for example, Patent Document 2).
　また、互いに並行して配線される２本の差動信号線対の屈曲部を一度分断させ、そこに所定板厚の遅延配線体を実装した迂回部を設け、信号伝送の遅延時間差を解消した配線基板装置が開示されている（例えば、特許文献３を参照。）。 In addition, the bent part of the two differential signal line pairs wired in parallel with each other is once divided, and a detour part having a delay wiring body with a predetermined plate thickness is provided there to eliminate the delay time difference in signal transmission. A wiring board device is disclosed (for example, refer to Patent Document 3).
特開２０１１－１００８７１号公報JP 2011-1000087 A1 特開２０１２－１９９９０４号公報JP 2012-199904 A 特開２００９－２２４４８９号公報JP 2009-224489 A
　しかしながら、上述した従来の技術には、以下のような問題がある。
　導体を３層使用して立体交差を実現した場合、３層部分と１層部分とでインピーダンスの乖離が発生してしまうため、信号品質が悪化してしまう。 However, the conventional techniques described above have the following problems.
When three-layered conductors are used to realize a three-dimensional intersection, a difference in impedance occurs between the three-layer portion and the first-layer portion, so that the signal quality is deteriorated.
　また、導体パターンとの間に垂直電極を設けている場合、２層間を垂直電極で接続するため、ディレイが大きくなり、木目細かなディレイ調整ができない。 Also, when a vertical electrode is provided between the conductor pattern and the two layers are connected by the vertical electrode, the delay becomes large and fine delay adjustment cannot be performed.
　また、製造された基板において差動信号線対の屈曲部を分断させている場合、基板改版が発生し、後工程において手戻りが発生してしまう。 Further, when the bent portion of the differential signal line pair is divided in the manufactured substrate, the substrate is revised, and reworking occurs in the subsequent process.
　１つの側面において、本発明の目的は、伝送信号の遅延時間のばらつきを防止してスキューを低減する半導体装置の設計において、半導体装置内での電気特性の劣化を防ぐとともに木目細かなディレイ調整を可能とする半導体装置を設計する設計プログラム、設計装置及び設計方法を提供することを目的とする。 In one aspect, an object of the present invention is to prevent a variation in delay time of a transmission signal and reduce skew, thereby preventing deterioration of electrical characteristics in the semiconductor device and performing fine delay adjustment. It is an object of the present invention to provide a design program, a design apparatus, and a design method for designing a possible semiconductor device.
　１つの案では、設計プログラムは、半導体装置を設計する設計装置のコンピュータに、前記半導体装置を製造するために用いられるデータに基づいて、導体を部分的に重なり合わせることにより、前記半導体装置を構成する半導体集積回路と外部接続端子を接続する信号線をミアンダ形状に形成し、前記信号線のディレイ値を算出し、前記ディレイ値と入力された要求ディレイ値とを比較し、前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する処理を実行させることを特徴とする。 In one proposal, a design program configures the semiconductor device by partially overlapping conductors on a computer of the design device that designs the semiconductor device, based on data used to manufacture the semiconductor device. Forming a signal line connecting the semiconductor integrated circuit and the external connection terminal in a meander shape, calculating a delay value of the signal line, comparing the delay value and the input requested delay value, and the delay value is When the request delay value is matched, a process for outputting the signal line as a simulation result is executed.
　実施形態の設計プログラムによれば、半導体装置内での電気特性の劣化を防ぐとともに木目細かなディレイ調整を行うことができる。 According to the design program of the embodiment, it is possible to prevent the deterioration of electrical characteristics in the semiconductor device and perform fine delay adjustment.
一般的な半導体装置の断面図である。It is sectional drawing of a common semiconductor device. 一般的な半導体装置の平面図である。It is a top view of a common semiconductor device. ミアンダ形状の信号線を示す図である。It is a figure which shows a meander-shaped signal line. 従来の設計処理の流れを示すフローチャートである。It is a flowchart which shows the flow of the conventional design processing. ミアンダ形状の信号線を有する半導体装置の断面図である。It is sectional drawing of the semiconductor device which has a meander-shaped signal line. 本実施の形態におけるミアンダ形状を説明するための図である。It is a figure for demonstrating the meander shape in this Embodiment. 重なり幅及び配線幅を説明するための図である。It is a figure for demonstrating the overlap width and wiring width. 本実施の形態の全体像を示す図である。It is a figure which shows the whole image of this Embodiment. 本実施の形態の設計装置の機能ブロックを示す図である。It is a figure which shows the functional block of the design apparatus of this Embodiment. 本実施の形態の設計処理の流れを示すフローチャート（その１）である。It is a flowchart (the 1) which shows the flow of the design processing of this Embodiment. 初期設計を説明する図である。It is a figure explaining initial design. 本実施の形態の設計処理の流れを示すフローチャート（その２）である。It is a flowchart (the 2) which shows the flow of the design processing of this Embodiment. 第１詳細設計を説明する図である。It is a figure explaining the 1st detailed design. 第２詳細設計を説明する図である。It is a figure explaining the 2nd detailed design. 第１の具体例を示す図である。It is a figure which shows the 1st specific example. 第２の具体例を示す図である。It is a figure which shows the 2nd specific example. 第３の具体例を示す図である。It is a figure which shows the 3rd specific example. 本実施の形態の設計処理により設計された半導体装置の製造過程を説明する図である。It is a figure explaining the manufacturing process of the semiconductor device designed by the design process of this Embodiment. 情報処理装置の構成図である。It is a block diagram of information processing apparatus.
　以下、図面を参照しながら、実施形態を詳細に説明する。
　図５は、ミアンダ形状の信号線を有する半導体装置の断面図である。 Hereinafter, embodiments will be described in detail with reference to the drawings.
FIG. 5 is a cross-sectional view of a semiconductor device having meander-shaped signal lines.
　図５において、半導体装置１Ａは、本実施の形態の設計処理により設計される。半導体装置１Ａは、プリント基板２の一の表面（上面）２１に半導体集積回路素子３が実装されている。また、プリント基板２の他の表面（下面）２２には外部接続端子４が形成されている。そして、半導体集積回路素子３は、複数のミアンダ信号線６により外部接続端子４と接続されている。ミアンダ信号線６は、本実施の形態の設計処理により設計されたミアンダ形状を形成している。 In FIG. 5, the semiconductor device 1A is designed by the design process of the present embodiment. In the semiconductor device 1 </ b> A, the semiconductor integrated circuit element 3 is mounted on one surface (upper surface) 21 of the printed board 2. An external connection terminal 4 is formed on the other surface (lower surface) 22 of the printed circuit board 2. The semiconductor integrated circuit element 3 is connected to the external connection terminal 4 by a plurality of meander signal lines 6. The meander signal line 6 forms a meander shape designed by the design processing of the present embodiment.
　図６は、本実施の形態におけるミアンダ形状を説明するための図である。
　図６において、ミアンダ信号線６１は、同一層内で導体を部分的に重なり合わせることによりミアンダ形状が形成されている。 FIG. 6 is a diagram for explaining a meander shape in the present embodiment.
In FIG. 6, the meander signal line 61 is formed in a meander shape by partially overlapping conductors in the same layer.
　図７は、重なり幅及び配線幅を説明するための図である。
　図７において、導体６１Ａと導体６１Ｂは、部分的に重なり合わせられ、図６に示したミアンダ信号線６１が形成される。図７（Ａ）は、半導体装置の平面（ＸＹ平面）でのミアンダ信号線６１を示す。ミアンダ信号線６１を構成する導体６１Ａと導体６１Ｂの幅方向の配線幅を矢印で示す。図７（Ｂ）は、半導体装置の断面でのミアンダ信号線６１を示す。ミアンダ信号線６１を構成する導体６１Ａと導体６１Ｂの長さ方向の重なり幅（ｏｖ幅）を矢印で示す。 FIG. 7 is a diagram for explaining the overlap width and the wiring width.
In FIG. 7, the conductor 61A and the conductor 61B are partially overlapped to form the meander signal line 61 shown in FIG. FIG. 7A shows the meander signal line 61 on the plane (XY plane) of the semiconductor device. The widths of the conductors 61A and 61B constituting the meander signal line 61 in the width direction are indicated by arrows. FIG. 7B shows the meander signal line 61 in the cross section of the semiconductor device. The overlapping width (ov width) of the conductor 61A and the conductor 61B constituting the meander signal line 61 in the length direction is indicated by an arrow.
　図８は、本実施の形態の全体像を示す図である。
　図８において、基板情報ＤＢ（Data Base）８１は、基板外形、層数、材料、厚さ、ＳＶＧ（信号、電源、ＧＮＤ）種別、電気特性、ドリル径、パッド径、逃げ径等の基本情報を格納する。搭載部品情報ＤＢ８２は、ダイ（Die）ピン定義、ＢＧＡ（Ball Grid Array）ピン定義、コンデンサなど部品定義等の搭載部品情報を格納する。接続情報ＤＢ８３は、Die－ＢＧＡ間接続などのNetlist定義等の接続情報を格納する。ＤＲＣ（Design Rule Check）情報ＤＢ８４は、ライン－ビア－シェイプ間のクリアランス、ライン幅とレイヤーの制限（配線不可指定）、差動配線ルール、製造性ルール等のデザインルールチェック情報を格納する。 FIG. 8 is a diagram showing an overview of the present embodiment.
In FIG. 8, the board information DB (Data Base) 81 is basic information such as board outline, number of layers, material, thickness, SVG (signal, power supply, GND) type, electrical characteristics, drill diameter, pad diameter, clearance diameter, and the like. Is stored. The mounted component information DB 82 stores mounted component information such as a die (Die) pin definition, a BGA (Ball Grid Array) pin definition, and a component definition such as a capacitor. The connection information DB 83 stores connection information such as Netlist definition such as Die-BGA connection. A DRC (Design Rule Check) information DB 84 stores design rule check information such as a line-via-shape clearance, a line width and layer restriction (no wiring designation), a differential wiring rule, a manufacturability rule, and the like.
　基本パターン設計は、基板情報ＤＢ８１に格納された基本情報、搭載部品情報ＤＢ８２に格納された搭載部品情報、接続情報ＤＢ８３に格納された接続情報、及びＤＲＣ情報ＤＢ８４に格納されたデザインルールチェック情報に基づいて実行される。電源プレーンの作成や配線の追加が行われることもある。基本パターン設計の後、伝送解析、電源解析等のシミュレーションを実行する。その後、レイヤー及びビアの追加や削除、更に、配線及びプレーンの修正を行い、再度、基本パターン設計を実行する。そして、デザインルールのチェックを実行し、ＧＢＲファイル等の基板製造用データ、部品実装データ（マウンタ位置情報）、基板実装図（基板外形寸法、パッド寸法、予備半田仕様など）を出力する。 The basic pattern design is based on the basic information stored in the board information DB 81, the mounted component information stored in the mounted component information DB 82, the connection information stored in the connection information DB 83, and the design rule check information stored in the DRC information DB 84. Based on. A power plane may be created or wiring may be added. After the basic pattern design, simulation such as transmission analysis and power supply analysis is executed. Thereafter, addition and deletion of layers and vias, correction of wiring and planes are performed, and basic pattern design is executed again. Then, the design rule is checked, and board manufacturing data such as a GBR file, component mounting data (mounter position information), and a board mounting diagram (board outer dimensions, pad dimensions, preliminary solder specifications, etc.) are output.
　図９は、本実施の形態の設計装置の機能ブロックを示す図である。
　図９において、設計装置９０は、信号線形成部９１、ディレイ値算出部９２、第１ディレイ値比較部９３、結果出力部９４、第２ディレイ値比較部９５、重なり幅変更部９６、第３ディレイ値比較部９７及び重なり配線幅変更部９８を備える。設計装置９０は、設計プログラムを搭載したコンピューターシステムであり、半導体集積回路素子及び、その半導体集積回路素子を搭載したプリント基板を備えた半導体装置を設計する。 FIG. 9 is a diagram illustrating functional blocks of the design apparatus according to the present embodiment.
9, the design apparatus 90 includes a signal line forming unit 91, a delay value calculating unit 92, a first delay value comparing unit 93, a result output unit 94, a second delay value comparing unit 95, an overlap width changing unit 96, a third A delay value comparing unit 97 and an overlapping wiring width changing unit 98 are provided. The design apparatus 90 is a computer system that includes a design program, and designs a semiconductor device that includes a semiconductor integrated circuit element and a printed circuit board that includes the semiconductor integrated circuit element.
　信号線形成部９１は、前記半導体装置を製造するために用いられるデータに基づいて、導体を部分的に重なり合わせることにより、前記半導体装置を構成する半導体集積回路と外部接続端子を接続する信号線をミアンダ形状に形成する。ディレイ値算出部９２は、前記信号線形成部９１によって形成された信号線のディレイ値を算出する。第１ディレイ値比較部９３は、前記ディレイ値算出部９２によって算出されたディレイ値と入力された要求ディレイ値とを比較する。結果出力部９４は、前記第１ディレイ値比較部９３による比較の結果、前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する。第２ディレイ値比較部９５は、前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記ディレイ値と所定範囲の第１許容ディレイ値とを比較する。重なり幅変更部９６は、前記第２ディレイ値比較部９５による比較の結果、前記ディレイ値が前記第１許容ディレイ値の範囲内の場合、前記導体の長さ方向の重なり幅を変更する。第３ディレイ値比較部９７は、前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記重なり幅の変更後に算出した前記ディレイ値と所定範囲の第２許容ディレイ値とを比較する。重なり配線幅変更部９８は、前記第３ディレイ値比較部９７による比較の結果、前記ディレイ値が前記第２許容ディレイ値の範囲内の場合、前記導体の重なり部分の幅方向の配線幅を変更する。 The signal line forming unit 91 is a signal line that connects a semiconductor integrated circuit constituting the semiconductor device and an external connection terminal by partially overlapping conductors based on data used for manufacturing the semiconductor device. Is formed in a meander shape. The delay value calculation unit 92 calculates the delay value of the signal line formed by the signal line forming unit 91. The first delay value comparison unit 93 compares the delay value calculated by the delay value calculation unit 92 with the input requested delay value. The result output unit 94 outputs the signal line as a simulation result when the delay value matches the required delay value as a result of the comparison by the first delay value comparison unit 93. The second delay value comparison unit 95 compares the delay value with a first allowable delay value within a predetermined range when the delay value does not match the required delay value. When the delay value is within the range of the first allowable delay value as a result of the comparison by the second delay value comparison unit 95, the overlap width changing unit 96 changes the overlap width in the length direction of the conductor. The third delay value comparison unit 97, when the delay value calculated after the change of the overlap width does not match the required delay value, the delay value calculated after the change of the overlap width and a second allowable value within a predetermined range. Compare the delay value. The overlapping wiring width changing unit 98 changes the wiring width in the width direction of the overlapping portion of the conductor when the delay value is within the range of the second allowable delay value as a result of the comparison by the third delay value comparing unit 97. To do.
　また、前記ディレイ値算出部９２は、前記重なり幅の変更後の前記信号線のディレイ値を算出する。前記第１ディレイ値比較部９３は、前記重なり幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較する。前記結果出力部９４は、前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する。 The delay value calculation unit 92 calculates the delay value of the signal line after the overlap width is changed. The first delay value comparison unit 93 compares the delay value calculated after the overlap width is changed with the input requested delay value. The result output unit 94 outputs the signal line as a simulation result when the delay value calculated after the overlap width is changed matches the required delay value.
　また、前記ディレイ値算出部９２は、前記配線幅の変更後の前記信号線のディレイ値を算出する。前記第１ディレイ値比較部９３は、前記配線幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較する。前記結果出力部９４は、前記配線幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する。 Also, the delay value calculation unit 92 calculates the delay value of the signal line after the change of the wiring width. The first delay value comparison unit 93 compares the delay value calculated after the change of the wiring width with the input requested delay value. The result output unit 94 outputs the signal line as a simulation result when the delay value calculated after changing the wiring width matches the required delay value.
　ここで、前記第２許容ディレイ値は、前記第１許容ディレイ値の範囲内であることが望ましい。前記信号線は、前記半導体装置の同一層内で形成されることが望ましい。前記要求ディレイ値は、所定の連続的数値範囲を有することが望ましい。 Here, it is preferable that the second allowable delay value is within a range of the first allowable delay value. The signal line is preferably formed in the same layer of the semiconductor device. The required delay value preferably has a predetermined continuous numerical range.
　図９を用いて説明した設計装置９０は、設計プログラムにより設計処理を実行する。従来は限定的にしか行えなかったミアンダ形状によるディレイ調整であったが、本設計処理により木目細かなディレイ調整を行うことができる。 The design apparatus 90 described with reference to FIG. 9 executes a design process using a design program. Conventionally, delay adjustment has been performed by means of a meander shape, which can be performed only in a limited manner, but fine delay adjustment can be performed by this design process.
　本実施の形態では、層乗り換えせずにＺ軸方向のミアンダ配線を形成し、初期設計、第１詳細設計及び第２詳細設計の３段階設計によって、導体の長さ方向の重なり部分である重なり幅や、導体の幅方向の重なり部分である配線幅を変更することにより、木目細かなディレイ調整することを可能とした。 In this embodiment, the meander wiring in the Z-axis direction is formed without changing the layer, and the overlap which is the overlapping portion in the length direction of the conductor by the three-stage design of the initial design, the first detailed design and the second detailed design. By changing the width and the wiring width, which is the overlapping part in the width direction of the conductor, it is possible to finely adjust the delay.
　図１０及び図１２は、本実施の形態の設計処理の流れを示すフローチャートである。図１１は、初期設計を説明する図である。図１３は、第１詳細設計を説明する図である。図１４は、第２詳細設計を説明する図である。 10 and 12 are flowcharts showing the flow of the design process according to the present embodiment. FIG. 11 is a diagram for explaining the initial design. FIG. 13 is a diagram illustrating the first detailed design. FIG. 14 is a diagram for explaining the second detailed design.
　図１０のステップＳ４０１乃至Ｓ４０５は、図４を用いて説明した従来の設計処理のステップＳ４０１乃至Ｓ４０５と同様であるので、説明を省略する。 10 are the same as steps S401 to S405 of the conventional design process described with reference to FIG.
　ステップＳ４０５で、ミアンダ形状が形成された信号線間でディレイが一致しないと判断された場合（ステップＳ４０５：Ｎｏ）、ステップＳ１００１において、同一層に上部及び下部の導体パターンが形成できるように、ＣＡＤツール上で層定義を行う。 If it is determined in step S405 that the delay does not match between the signal lines in which the meander shape is formed (step S405: No), in step S1001, the upper and lower conductor patterns can be formed on the same layer. Perform layer definition on the tool.
　ステップＳ１００２において、ステップＳ４０１で入力した接続端子の位置情報に基づいて、ステップＳ１００１で定義した同一層内のＸＹＺ面でミアンダ形状の信号線を形成する。このとき、Ｚ軸方向のミアンダ形状の信号線は、図１１の横軸に示す初期値で上部の導体パターンと下部の導体パターンを重ね合わせるように交互に接続する。 In step S1002, a meander-shaped signal line is formed on the XYZ plane in the same layer defined in step S1001, based on the position information of the connection terminal input in step S401. At this time, the meander-shaped signal lines in the Z-axis direction are alternately connected so that the upper conductor pattern and the lower conductor pattern overlap with each other with the initial values shown on the horizontal axis of FIG.
　ステップＳ１００３において、ステップＳ１００２で形成したミアンダ形状の信号線のディレイ値を算出する。算出したディレイ値は、図１１の縦軸に示す初期値となる。 In step S1003, the delay value of the meander-shaped signal line formed in step S1002 is calculated. The calculated delay value is an initial value shown on the vertical axis of FIG.
　ステップＳ１００４において、ステップＳ１００３で算出したディレイ値が、予め入力された要求ディレイ値を満足するか否かを判断する。要求ディレイ値は、図１１に示すように、所定の幅を有する。 In step S1004, it is determined whether or not the delay value calculated in step S1003 satisfies the request delay value input in advance. The required delay value has a predetermined width as shown in FIG.
　算出したディレイ値が要求ディレイ値を満足する場合（ステップＳ１００４：Ｙｅｓ）、本設計処理を終了する。他方、図１１に示すように、算出したディレイ値が要求ディレイ値を満足しない場合（ステップＳ１００４：Ｎｏ）、ステップＳ１００５において、最小の重なり幅（ｏｖ幅ｍｉｎ）におけるディレイ値である第１下限値と、最大の重なり幅（ｏｖ幅ｍａｘ）におけるディレイ値である第１上限値を計算する。 When the calculated delay value satisfies the required delay value (step S1004: Yes), the design process is terminated. On the other hand, as shown in FIG. 11, when the calculated delay value does not satisfy the required delay value (step S1004: No), in step S1005, a first lower limit value that is a delay value in the minimum overlap width (ov width min). Then, a first upper limit value that is a delay value in the maximum overlap width (ov width max) is calculated.
　そして、ステップＳ１００６において、要求ディレイ値がステップＳ１００５で計算した第１上限値と第１下限値の間にあるか否かを判断する。 In step S1006, it is determined whether the required delay value is between the first upper limit value and the first lower limit value calculated in step S1005.
　要求ディレイ値が第１上限値と第１下限値の間にない場合（ステップＳ１００６：Ｎｏ）、ステップＳ１００１に戻る。以上のステップＳ１００１乃至Ｓ１００６の処理を初期設計と呼ぶ。 If the requested delay value is not between the first upper limit value and the first lower limit value (step S1006: No), the process returns to step S1001. The processes in steps S1001 to S1006 are called initial design.
　以下に説明するステップＳ１２０１乃至Ｓ１２０８の処理を第１詳細設計と呼ぶ。第１詳細設計では、重なり幅（ｏｖ幅）を調整することで、木目細かなディレイ調整を行う。例えば、重なり幅（ｏｖ幅）を増加することにより、重なり部分の容量が増加するためディレイ値が増加する。また、重なり幅（ｏｖ幅）を減少することにより、重なり部分の容量が減少するためディレイ値が減少する。 The processing of steps S1201 to S1208 described below is referred to as first detailed design. In the first detailed design, fine delay adjustment is performed by adjusting the overlap width (ov width). For example, by increasing the overlap width (ov width), the delay value increases because the capacity of the overlap portion increases. Further, by reducing the overlap width (ov width), the capacity of the overlap portion is reduced, so that the delay value is reduced.
　要求ディレイ値が第１上限値と第１下限値の間にある場合（ステップＳ１００６：Ｙｅｓ）、図１２のステップＳ１２０１において、上述の初期設計のディレイ値と重なり幅を取り込み、ステップＳ１２０２において、第１詳細設計でターゲットとする要求ディレイ値を取り込む。通常は、初期設計での要求ディレイ値と同様の値である。 When the required delay value is between the first upper limit value and the first lower limit value (step S1006: Yes), in step S1201 of FIG. 12, the above-described initial design delay value and overlap width are taken in, and in step S1202, the first delay value is obtained. 1 Take in the required delay value that is the target in the detailed design. Usually, it is the same value as the required delay value in the initial design.
　ステップＳ１２０３において、変更する重なり幅（ｏｖ幅）を求める。初期設計で算出したディレイ値が要求ディレイ値に満たない場合には、重なり幅（ｏｖ幅）を増加させる。他方、初期設計で算出したディレイ値が要求ディレイ値を超える場合には、重なり幅（ｏｖ幅）を減少させる。図１３に示した例では、重なり幅（ｏｖ幅）を増加させている。 In step S1203, the overlap width (ov width) to be changed is obtained. When the delay value calculated in the initial design is less than the required delay value, the overlap width (ov width) is increased. On the other hand, when the delay value calculated in the initial design exceeds the required delay value, the overlap width (ov width) is reduced. In the example shown in FIG. 13, the overlap width (ov width) is increased.
　ステップＳ１２０４において、変更した重なり幅（ｏｖ幅）の信号線のディレイ値を算出し、要求ディレイ値を満足するか否かを判断する。 In step S1204, the delay value of the signal line having the changed overlap width (ov width) is calculated, and it is determined whether or not the required delay value is satisfied.
　算出したディレイ値が要求ディレイ値を満足する場合（ステップＳ１２０４：Ｙｅｓ）、ステップＳ１２０５において、ステップＳ１２０３で求めた重なり幅（ｏｖ幅）で決定した後、本設計処理を終了する。他方、図１３に示すように、算出したディレイ値が要求ディレイ値を満足しない場合（ステップＳ１２０４：Ｎｏ）、ステップＳ１２０６において、最小の重なり幅（ｏｖ幅ｍｉｎ）におけるディレイ値である第２下限値と、最大の重なり幅（ｏｖ幅ｍａｘ）におけるディレイ値である第２上限値を計算する。 When the calculated delay value satisfies the required delay value (step S1204: YES), after determining with the overlap width (ov width) obtained in step S1203 in step S1205, the design process is terminated. On the other hand, as shown in FIG. 13, when the calculated delay value does not satisfy the required delay value (step S1204: No), in step S1206, a second lower limit value that is a delay value in the minimum overlap width (ov width min). Then, a second upper limit value that is a delay value in the maximum overlap width (ov width max) is calculated.
　そして、ステップＳ１２０７において、要求ディレイ値がステップＳ１２０６で計算した第２上限値と第２下限値の間にあるか否かを判断する。 In step S1207, it is determined whether the required delay value is between the second upper limit value and the second lower limit value calculated in step S1206.
　要求ディレイ値が第２上限値と第２下限値の間にない場合（ステップＳ１２０７：Ｎｏ）、ステップＳ１２０３に戻る。他方、要求ディレイ値が第２上限値と第２下限値の間にある場合（ステップＳ１２０７：Ｙｅｓ）、ステップＳ１２０８において、ステップＳ１２０３で求めた重なり幅（ｏｖ幅）で決定する。 When the requested delay value is not between the second upper limit value and the second lower limit value (step S1207: No), the process returns to step S1203. On the other hand, when the requested delay value is between the second upper limit value and the second lower limit value (step S1207: Yes), in step S1208, the overlap width (ov width) obtained in step S1203 is determined.
　以下に説明するステップＳ１２０９乃至Ｓ１２１３の処理を第２詳細設計と呼ぶ。第２詳細設計では、配線幅（ｏｖ配線幅）を調整することで、木目細かなディレイ調整を行う。例えば、配線幅（ｏｖ配線幅）を増加する（太らせる）ことにより、重なり部分の容量が増加するためディレイ値が増加する。また、配線幅（ｏｖ配線幅）を減少する（細らせる）ことにより、重なり部分の容量が減少するためディレイ値が減少する。 The processing of steps S1209 to S1213 described below is referred to as second detailed design. In the second detailed design, fine delay adjustment is performed by adjusting the wiring width (ov wiring width). For example, by increasing (thickening) the wiring width (ov wiring width), the capacity of the overlapping portion increases, so that the delay value increases. Further, by reducing (thinning) the wiring width (ov wiring width), the capacity of the overlapping portion is reduced, so that the delay value is reduced.
　要求ディレイ値が第２上限値と第２下限値の間にある場合（ステップＳ１２０７：Ｙｅｓ）、ステップＳ１２０８で重なり幅（ｏｖ幅）が決定した後、ステップＳ１２０９において、上述の第１詳細設計のディレイ値と重なり幅を取り込む。そして、ステップＳ１２１０において、第２詳細設計でターゲットとする要求ディレイ値を取り込む。通常は、第１詳細設計での要求ディレイ値と同様の値である。 When the required delay value is between the second upper limit value and the second lower limit value (step S1207: Yes), after the overlap width (ov width) is determined in step S1208, in step S1209, the first detailed design described above is performed. Capture delay value and overlap width. In step S1210, a required delay value targeted in the second detailed design is captured. Usually, it is the same value as the required delay value in the first detailed design.
　ステップＳ１２１１において、変更する配線幅（ｏｖ配線幅）を求める。第１詳細設計で算出したディレイ値が要求ディレイ値に満たない場合には、配線幅（ｏｖ配線幅）を増加させる。他方、第１詳細設計で算出したディレイ値が要求ディレイ値を超える場合には、配線幅（ｏｖ配線幅）を減少させる。図１４に示した例では、配線幅（ｏｖ配線幅）を増加させている。 In step S1211, the wiring width to be changed (ov wiring width) is obtained. When the delay value calculated in the first detailed design is less than the required delay value, the wiring width (ov wiring width) is increased. On the other hand, when the delay value calculated in the first detailed design exceeds the required delay value, the wiring width (ov wiring width) is decreased. In the example shown in FIG. 14, the wiring width (ov wiring width) is increased.
　ステップＳ１２１２において、変更した重なり幅（ｏｖ幅）の信号線のディレイ値を算出し、要求ディレイ値を満足するか否かを判断する。 In step S1212, the delay value of the signal line having the changed overlap width (ov width) is calculated, and it is determined whether or not the required delay value is satisfied.
　算出したディレイ値が要求ディレイ値を満足する場合（ステップＳ１２１２：Ｙｅｓ）、ステップＳ１２１３において、ステップＳ１２１１で求めた配線幅（ｏｖ配線幅）で決定した後、本設計処理を終了する。他方、図１４に示すように、算出したディレイ値が要求ディレイ値を満足しない場合（ステップＳ１２１２：Ｎｏ）、図１０のステップＳ１００１に戻り、初期設計から再設計を行う。 When the calculated delay value satisfies the required delay value (step S1212: Yes), the design process is terminated after determining the wiring width (ov wiring width) obtained in step S1211 in step S1213. On the other hand, as shown in FIG. 14, when the calculated delay value does not satisfy the required delay value (step S1212: No), the process returns to step S1001 in FIG. 10 to perform redesign from the initial design.
　以上の設計処理により、後工程での追加工数を発生させることなく、また、他配線にも影響させることなく、木目細かなディレイ調整と可能となる。 The above design process enables fine delay adjustment without generating additional man-hours in the subsequent process and without affecting other wiring.
　図１５は、第１の具体例を示す図である。
　図１５（Ａ）は、第１の具体例の断面図である。 FIG. 15 is a diagram illustrating a first specific example.
FIG. 15A is a cross-sectional view of the first specific example.
　図１５（Ｂ）に示すように、絶縁層厚（ｂ）＝７５マイクロメートル（μｍ）、導体厚（ｔ）＝１５μｍ、上部導体と上部ＧＮＤ面間距離(ｈ１)＝２２．５μｍ、下部導体と下部ＧＮＤ面間距離（ｈ２）＝２２．５μｍ、Ｍ点からＮ点までの距離を２０６０μｍの断面構造とする。 As shown in FIG. 15B, the insulating layer thickness (b) = 75 micrometers (μm), the conductor thickness (t) = 15 μm, the distance between the upper conductor and the upper GND plane (h1) = 22.5 μm, the lower conductor And the lower GND surface distance (h2) = 22.5 μm, and the distance from point M to point N is 2060 μm.
　重なり部分の長さ（Δｌ）を６０μｍ、８０μｍ、１００μｍ、２００μｍ、５００μｍ、１０６０μｍとした場合、Ｍ点からＮ点までのディレイ値を算出すると、６０μｍ＝１３．７１１ピコ秒（ｐｓ）（＋０．０００ｐｓ）、８０μｍ＝１３．７６８ｐｓ（＋０．０５７ｐｓ）、１００μｍ＝１３．８５ｐｓ（＋０．１３９ｐｓ）、２００μｍ＝１４．２４５ｐｓ（＋０．５３４ｐｓ）、５００μｍ＝１４．７９７ｐｓ（＋１．０８６ｐｓ）、１０６０μｍ＝１５．１６４ｐｓ（＋１．４５３ｐｓ）となる。これは、Δｌを長くすることにより、容量が大きくなるためである。このように重なり部分の長さを任意に変えることで、ディレイ値の調整と可能である。 When the length (Δl) of the overlapping portion is 60 μm, 80 μm, 100 μm, 200 μm, 500 μm, and 1060 μm, the delay value from the M point to the N point is calculated, and 60 μm = 13.711 picoseconds (ps) (+0. 000 ps), 80 μm = 13.768 ps (+0.057 ps), 100 μm = 13.85 ps (+0.139 ps), 200 μm = 14.245 ps (+0.534 ps), 500 μm = 14.797 ps (+1.086 ps), 1060 μm = 15 164 ps (+1.453 ps). This is because the capacity increases by increasing Δl. In this way, the delay value can be adjusted by arbitrarily changing the length of the overlapping portion.
　図１６は、第２の具体例を示す図である。
　図１６（Ａ）及び（Ｂ）は、第２の具体例であり、図１６（Ｃ）及び（Ｄ）は従来例である。 FIG. 16 is a diagram illustrating a second specific example.
FIGS. 16A and 16B are a second specific example, and FIGS. 16C and 16D are conventional examples.
　図１６（Ａ）の断面図に示したように、第２の具体例に示す導体の積層数は、図１６（Ｃ）に示す従来例の導体の積層数よりも１層多い、３層構造となっている。図１６（Ｂ）に示すように、第２の具体例は、絶縁層厚（ｂ）＝７５μｍ、導体厚（ｔ）＝１５μｍ、上部導体と上部ＧＮＤ面間距離(ｈ１)＝２２．５μｍ、下部導体と下部ＧＮＤ面間距離（ｈ２）＝２２．５μｍの断面構造である。一方、図１６（Ｄ）に示すように、従来の技術では、絶縁層厚（ｂ）＝７５μｍ、導体厚（ｔ）＝１５μｍ、上部導体と上部ＧＮＤ面間距離(ｈ１)＝１５μｍ、下部導体と下部ＧＮＤ面間距離（ｈ２）＝１５μｍの断面構造である。重なり部分（Δｌ）（オーバーラップ部）とその前後（ｌａ、ｌｂ）のインピーダンス（Ｚｏ）について、両者を比較する。インピーダンス（Ｚｏ）は、インダクタンスとキャパシタンスの商の平方根で算出されるため、差が生じる。Δｌ部とｌａ、ｌｂ部のＺｏの差が、第２の具体例は、図１６（Ｂ）に示すように、Δ１１．５５Ωである。これに対して、従来例は、図１６（Ｄ）に示すように、Δ１６．８２Ωとなる。このことにより、本実施の形態は、インピーダンス不連続を抑制することが可能とある。 As shown in the cross-sectional view of FIG. 16A, the number of stacked conductors shown in the second specific example is one layer larger than the number of stacked conductors of the conventional example shown in FIG. It has become. As shown in FIG. 16B, the second specific example includes an insulating layer thickness (b) = 75 μm, a conductor thickness (t) = 15 μm, a distance between the upper conductor and the upper GND plane (h1) = 22.5 μm, The cross-sectional structure is a distance between the lower conductor and the lower GND plane (h2) = 22.5 μm. On the other hand, as shown in FIG. 16D, in the conventional technique, the insulating layer thickness (b) = 75 μm, the conductor thickness (t) = 15 μm, the distance between the upper conductor and the upper GND plane (h1) = 15 μm, the lower conductor And the lower GND surface distance (h2) = 15 μm. The overlap portion (Δl) (overlap portion) and the impedance (Zo) before and after it (la, lb) are compared. Since the impedance (Zo) is calculated by the square root of the quotient of the inductance and the capacitance, a difference occurs. The difference of Zo between the Δl part and the la and lb parts is Δ11.55Ω as shown in FIG. 16B in the second specific example. In contrast, the conventional example has Δ16.82Ω as shown in FIG. Thus, the present embodiment can suppress impedance discontinuity.
　重なり部分とその前後でのインピーダンス不連続を解決するためには、重なり部分の導体厚を薄くすることで解決する。これにより、従来例よりもインピーダンスの乖離を抑制し、信号品質の劣化を抑えることが可能となる。 ¡To solve the impedance discontinuity between the overlapped part and its front and back, it is solved by reducing the conductor thickness of the overlapped part. As a result, the impedance divergence can be suppressed more than the conventional example, and the deterioration of the signal quality can be suppressed.
　図１７は、第３の具体例を示す図である。
　図１７（Ａ）は、第３の具体例の断面図である。 FIG. 17 is a diagram illustrating a third specific example.
FIG. 17A is a cross-sectional view of a third specific example.
　図１７（Ｂ）に示すように、絶縁層厚（ｂ）＝７５μｍ、導体厚（ｔ）＝１５μｍ、上部導体と上部ＧＮＤ面間距離（ｈ１）＝２２．５μｍ、下部導体と下部ＧＮＤ面間距離（ｈ２）＝２２．５μｍ、Ｍ点からＮ点までの距離を２０６０μｍの断面構造とする。重なり部分の長さ（ｌ）を６０μｍ及び２００μｍとした場合、重なり部分の配線幅（Δｗ）を変化したときのＭ点からＮ点までのディレイ値を算出した。ｌ＝６０μｍ時では、Δｗ＝１５μｍ基準としたときに、Δｗ＝２０μｍでΔｔ＝０．００５ｐｓ、Δｗ＝４０μｍでΔｔ＝０．０９６ｐｓとなり、配線幅は２倍の変化に対し、ディレイ値は１９．２倍の変化となる。 As shown in FIG. 17B, the insulating layer thickness (b) = 75 μm, the conductor thickness (t) = 15 μm, the distance between the upper conductor and the upper GND plane (h1) = 22.5 μm, and between the lower conductor and the lower GND plane The distance (h2) = 22.5 μm, and the distance from point M to point N is 2060 μm. When the length (l) of the overlapping portion was 60 μm and 200 μm, the delay value from the M point to the N point when the wiring width (Δw) of the overlapping portion was changed was calculated. At l = 60 μm, when Δw = 15 μm, Δt = 0.005 ps when Δw = 20 μm, Δt = 0.096 ps when Δw = 40 μm, and the delay value is 19 while the wiring width is doubled. .2 times the change.
　また、図１７（Ｃ）に示すように、ｌ＝２００μｍの時は、Δｗ＝１５μｍ基準としたときに、Δｗ＝２０μｍでΔｔ＝０．０１５ｐｓ、Δｗ＝４０μｍでΔｔ＝０．２１８ｐｓとなり、配線幅の２倍変化に対し、ディレイ値は１４．５倍の変化となる。これは、配線幅を太くすることで、容量が大きくなるためである。このように重なり部分の配線幅を任意に変えることで、ディレイ値の微調整が可能となる。 As shown in FIG. 17C, when l = 200 μm, when Δw = 15 μm, Δt = 0.015 ps when Δw = 20 μm, Δt = 0.218 ps when Δw = 40 μm, and wiring The delay value changes 14.5 times with respect to a change of 2 times the width. This is because the capacitance increases by increasing the wiring width. Thus, the delay value can be finely adjusted by arbitrarily changing the wiring width of the overlapping portion.
　図１８は、本実施の形態の設計処理により設計された半導体装置の製造過程を説明する図である。 FIG. 18 is a diagram for explaining the manufacturing process of the semiconductor device designed by the design process of the present embodiment.
　上述のようにして設計された半導体装置は、図１８に示すようにして製造することが出来る。 The semiconductor device designed as described above can be manufactured as shown in FIG.
　まず、図１８（Ａ）に示すように、コア層である第一導体の上に樹脂を積層し第一絶縁層を形成する。図１８（Ｂ）に示すように、第一絶縁層の上に第二下部導体を形成する。図１８（Ｃ）に示すように、第二下部導体の上に樹脂を積層し第二下部絶縁層を形成する。図１８（Ｄ）に示すように、樹脂を研磨し第二下部導体を露出させる。図１８（Ｅ）に示すように、露出した第二下部導体に第二上部導体を形成し、上下の導体を接続させる。図１８（Ｆ）に示すように、第二上部導体の上に第三絶縁層を形成する。そして、図１８（Ｇ）に示すように、第三絶縁層の上に第三導体を形成する。 First, as shown in FIG. 18A, a first insulating layer is formed by laminating a resin on the first conductor as the core layer. As shown in FIG. 18B, a second lower conductor is formed on the first insulating layer. As shown in FIG. 18C, a resin is laminated on the second lower conductor to form a second lower insulating layer. As shown in FIG. 18D, the resin is polished to expose the second lower conductor. As shown in FIG. 18E, a second upper conductor is formed on the exposed second lower conductor, and the upper and lower conductors are connected. As shown in FIG. 18F, a third insulating layer is formed on the second upper conductor. Then, as shown in FIG. 18G, a third conductor is formed on the third insulating layer.
　このようにして製造された半導体装置の構造により、垂直電極を使用せずに、第二上部導体と第二下部導体を重ね合わせて接続できるため、半導体装置の板厚を薄くすることが可能となる。 With the structure of the semiconductor device manufactured in this way, the second upper conductor and the second lower conductor can be overlapped and connected without using a vertical electrode, so that the thickness of the semiconductor device can be reduced. Become.
　以上説明したように、本実施の形態は、層乗り換えをせずに同一層内でＸＹＺ面（Ｘ面：基板横方向、Ｙ：基板奥行方向、Ｚ：基板断面方向）で信号線をミアンダ形状にした。このときの、Ｚ軸のミアンダ形状は、垂直電極を使用せずに、上部導体パターンと下部導体パターンを、相互に重ね合わせて接続する構造とした。これにより、木目細かなディレイ調整が可能となった。 As described above, in the present embodiment, the signal lines are meandered in the XYZ plane (X plane: substrate lateral direction, Y: substrate depth direction, Z: substrate cross-sectional direction) in the same layer without changing layers. I made it. In this case, the Z-axis meandering shape is such that the upper conductor pattern and the lower conductor pattern are overlapped and connected without using a vertical electrode. As a result, fine delay adjustment is possible.
　また、基板リリース直前でディレイ値の微調整が必要な場合でも、重ね合わせの量を変えることによりディレイ調整が可能であるため、他配線の設計変更を行わずに、手戻りを最小限で調整することが可能である。 Even if the delay value needs to be finely adjusted just before the board is released, it is possible to adjust the delay by changing the amount of overlap. Therefore, the rework can be adjusted to the minimum without changing the design of other wiring. Is possible.
　また、重ねあわせ部分の導体厚を薄くすることにより、インピーダンス不連続を抑制することもできる。 Also, impedance discontinuity can be suppressed by reducing the conductor thickness of the overlapping portion.
　以上説明したように、３次元ミアンダ形状を有することにより、本実施の形態の設計処理は、効率的に、木目細かなディレイ調整が可能となる。 As described above, by having the three-dimensional meander shape, the design process of the present embodiment can efficiently perform fine delay adjustment.
　図９の設計装置９０は、ハードウェア回路として実装することもでき、図１９に示すような情報処理装置（コンピュータ）を用いて実現することもできる。 9 can be implemented as a hardware circuit or can be realized by using an information processing apparatus (computer) as shown in FIG.
　図１９の情報処理装置は、Central Processing Unit（ＣＰＵ）１９０１、メモリ１９０２、入力装置１９０３、出力装置１９０４、外部記録装置１９０５、媒体駆動装置１９０６、及びネットワーク接続装置１９０７を備える。これらの構成要素はバス１９０８により互いに接続されている。 19 includes a central processing unit (CPU) 1901, a memory 1902, an input device 1903, an output device 1904, an external recording device 1905, a medium driving device 1906, and a network connection device 1907. These components are connected to each other by a bus 1908.
　メモリ１９０２は、例えば、Read Only Memory（ＲＯＭ）、Random Access Memory（ＲＡＭ）、フラッシュメモリ等の半導体メモリであり、設計処理に用いられるプログラム及びデータを格納する。 The memory 1902 is, for example, a semiconductor memory such as a Read Only Memory (ROM), a Random Access Memory (RAM), or a flash memory, and stores programs and data used for design processing.
　ＣＰＵ１９０１（プロセッサ）は、例えば、メモリ１９０２を利用して設計プログラムを実行することにより、図９の信号線形成部９１、ディレイ値算出部９２、第１ディレイ値比較部９３、結果出力部９４、第２ディレイ値比較部９５、重なり幅変更部９６、第３ディレイ値比較部９７及び重なり配線幅変更部９８として動作する。 For example, the CPU 1901 (processor) executes a design program using the memory 1902 to thereby generate a signal line forming unit 91, a delay value calculating unit 92, a first delay value comparing unit 93, a result output unit 94, The second delay value comparing unit 95, the overlapping width changing unit 96, the third delay value comparing unit 97, and the overlapping wiring width changing unit 98 are operated.
　入力装置１９０３は、例えば、キーボード、ポインティングデバイス等であり、ユーザ又はオペレータからの指示や情報の入力に用いられる。出力装置１９０４は、例えば、表示装置、プリンタ、スピーカ等であり、ユーザ又はオペレータへの問い合わせや処理結果の出力に用いられる。 The input device 1903 is, for example, a keyboard, a pointing device, and the like, and is used for inputting instructions and information from a user or an operator. The output device 1904 is, for example, a display device, a printer, a speaker, or the like, and is used to output an inquiry to a user or an operator or a processing result.
　外部記録装置１９０５は、例えば、磁気ディスク装置、光ディスク装置、光磁気ディスク装置、テープ装置等である。外部記録装置１９０５は、ハードディスクドライブであってもよい。情報処理装置は、外部記録装置１９０５にプログラム及びデータを格納しておき、それらをメモリ１９０２にロードして使用することができる。 The external recording device 1905 is, for example, a magnetic disk device, an optical disk device, a magneto-optical disk device, a tape device, or the like. The external recording device 1905 may be a hard disk drive. The information processing apparatus can store programs and data in the external recording device 1905 and load them into the memory 1902 for use.
　媒体駆動装置１９０６は、可搬型記録媒体１９０９を駆動し、その記録内容にアクセスする。可搬型記録媒体１９０９は、メモリデバイス、フレキシブルディスク、光ディスク、光磁気ディスク等である。可搬型記録媒体１９０９は、Compact Disk Read Only Memory（ＣＤ－ＲＯＭ）、Digital Versatile Disk（ＤＶＤ）、又はUniversal Serial Bus（ＵＳＢ）メモリであってもよい。ユーザ又はオペレータは、この可搬型記録媒体１９０９にプログラム及びデータを格納しておき、それらをメモリ１９０２にロードして使用することができる。 The medium driving device 1906 drives the portable recording medium 1909 and accesses the recorded contents. The portable recording medium 1909 is a memory device, a flexible disk, an optical disk, a magneto-optical disk, or the like. The portable recording medium 1909 may be a Compact Disk Read Only Memory (CD-ROM), Digital Versatile Disk (DVD), or Universal Serial Bus (USB) memory. A user or an operator can store programs and data in the portable recording medium 1909 and load them into the memory 1902 for use.
　このように、処理に用いられるプログラム及びデータを格納するコンピュータ読み取り可能な記録媒体には、メモリ１９０２、外部記録装置１９０５、及び可搬型記録媒体１９０９のような、物理的な（非一時的な）記録媒体が含まれる。 As described above, the computer-readable recording medium that stores the program and data used for processing includes physical (non-transitory) media such as the memory 1902, the external recording device 1905, and the portable recording medium 1909. A recording medium is included.
　ネットワーク接続装置１９０７は、Local Area Network（ＬＡＮ）、インターネット等の通信ネットワークに接続され、通信に伴うデータ変換を行う通信インタフェースである。情報処理装置は、プログラム及びデータを外部の装置からネットワーク接続装置１９０７を介して受け取り、それらをメモリ１９０２にロードして使用することもできる。 The network connection device 1907 is a communication interface that is connected to a communication network such as Local Area Network (LAN) or the Internet and performs data conversion accompanying communication. The information processing apparatus can also receive a program and data from an external apparatus via the network connection apparatus 1907 and load them into the memory 1902 for use.
　なお、情報処理装置が図１９のすべての構成要素を含む必要はなく、用途や条件に応じて一部の構成要素を省略することも可能である。例えば、ユーザ又はオペレータとのインタフェースが不要の場合は、入力装置１９０３及び出力装置１９０４を省略してもよい。また、情報処理装置が可搬型記録媒体１９０９にアクセスしない場合は、媒体駆動装置１９０６を省略してもよい。 Note that the information processing apparatus does not have to include all the components shown in FIG. 19, and some of the components can be omitted depending on the application and conditions. For example, when an interface with a user or an operator is unnecessary, the input device 1903 and the output device 1904 may be omitted. When the information processing apparatus does not access the portable recording medium 1909, the medium driving device 1906 may be omitted.
　開示の実施形態とその利点について詳しく説明したが、当業者は、特許請求の範囲に明確に記載した本発明の範囲から逸脱することなく、様々な変更、追加、省略をすることができるであろう。 Although the disclosed embodiments and their advantages have been described in detail, those skilled in the art can make various modifications, additions and omissions without departing from the scope of the present invention as explicitly set forth in the claims. Let's go.

Claims (12)

  1. 　半導体装置を設計する設計装置のコンピュータに、
    　前記半導体装置を製造するために用いられるデータに基づいて、導体を部分的に重なり合わせることにより、前記半導体装置を構成する半導体集積回路と外部接続端子を接続する信号線をミアンダ形状に形成し、
    　前記信号線のディレイ値を算出し、
    　前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　処理を実行させることを特徴とする設計プログラム。     To the computer of the design equipment that designs the semiconductor device,
    Based on data used for manufacturing the semiconductor device, by partially overlapping conductors, a signal line connecting the semiconductor integrated circuit constituting the semiconductor device and an external connection terminal is formed in a meander shape,
    Calculate the delay value of the signal line,
    Compare the delay value with the input requested delay value,
    When the delay value matches the required delay value, the signal line is output as a simulation result.
    A design program characterized by causing processing to be executed.
  2. 　前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記ディレイ値と所定範囲の第１許容ディレイ値とを比較し、
    　前記ディレイ値が前記第１許容ディレイ値の範囲内の場合、前記導体の長さ方向の重なり幅を変更し、
    　前記重なり幅の変更後の前記信号線のディレイ値を算出し、
    　前記重なり幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　処理を実行させることを特徴とする請求項１に記載の設計プログラム。     If the delay value does not match the required delay value, the delay value is compared with a first allowable delay value within a predetermined range;
    When the delay value is within the range of the first allowable delay value, the overlapping width in the length direction of the conductor is changed,
    Calculate the delay value of the signal line after changing the overlap width,
    Compare the delay value calculated after changing the overlap width and the input requested delay value,
    When the delay value calculated after changing the overlap width matches the required delay value, the signal line is output as a simulation result.
    The design program according to claim 1, wherein processing is executed.
  3. 　前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記重なり幅の変更後に算出した前記ディレイ値と所定範囲の第２許容ディレイ値とを比較し、
    　前記ディレイ値が前記第２許容ディレイ値の範囲内の場合、前記導体の重なり部分の幅方向の配線幅を変更し、
    　前記配線幅の変更後の前記信号線のディレイ値を算出し、
    　前記配線幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記配線幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　処理を実行させることを特徴とする請求項２に記載の設計プログラム。     If the delay value calculated after the change of the overlap width does not match the required delay value, the delay value calculated after the change of the overlap width is compared with a second allowable delay value within a predetermined range;
    When the delay value is within the range of the second allowable delay value, the wiring width in the width direction of the overlapping portion of the conductor is changed,
    Calculate the delay value of the signal line after changing the wiring width,
    Compare the delay value calculated after the change of the wiring width and the input requested delay value,
    When the delay value calculated after changing the wiring width matches the required delay value, the signal line is output as a simulation result.
    The design program according to claim 2, wherein processing is executed.
  4. 　前記第２許容ディレイ値は、前記第１許容ディレイ値の範囲内である、
    　ことを特徴とする請求項３に記載の設計プログラム。     The second allowable delay value is within the range of the first allowable delay value.
    The design program according to claim 3.
  5. 　前記信号線は、前記半導体装置の同一層内で形成される、
    　ことを特徴とする請求項１乃至４の何れか１項に記載の設計プログラム。     The signal line is formed in the same layer of the semiconductor device.
    The design program according to any one of claims 1 to 4, wherein:
  6. 　前記要求ディレイ値は、所定の連続的数値範囲を有する、
    　ことを特徴とする請求項１乃至５の何れか１項に記載の設計プログラム。     The required delay value has a predetermined continuous numerical range;
    The design program according to any one of claims 1 to 5, wherein:
  7. 　半導体装置を設計する設計装置のコンピュータが実行する設計方法であって、
    　前記半導体装置を製造するために用いられるデータに基づいて、導体を部分的に重なり合わせることにより、前記半導体装置を構成する半導体集積回路と外部接続端子を接続する信号線をミアンダ形状に形成し、
    　前記信号線のディレイ値を算出し、
    　前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　ことを特徴とする設計方法。     A design method executed by a computer of a design apparatus for designing a semiconductor device,
    Based on data used for manufacturing the semiconductor device, by partially overlapping conductors, a signal line connecting the semiconductor integrated circuit constituting the semiconductor device and an external connection terminal is formed in a meander shape,
    Calculate the delay value of the signal line,
    Compare the delay value with the input requested delay value,
    When the delay value matches the required delay value, the signal line is output as a simulation result.
    A design method characterized by that.
  8. 　前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記ディレイ値と所定範囲の第１許容ディレイ値とを比較し、
    　前記ディレイ値が前記第１許容ディレイ値の範囲内の場合、前記導体の長さ方向の重なり幅を変更し、
    　前記重なり幅の変更後の前記信号線のディレイ値を算出し、
    　前記重なり幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　ことを特徴とする請求項７に記載の設計方法。     If the delay value does not match the required delay value, the delay value is compared with a first allowable delay value within a predetermined range;
    When the delay value is within the range of the first allowable delay value, the overlapping width in the length direction of the conductor is changed,
    Calculate the delay value of the signal line after changing the overlap width,
    Compare the delay value calculated after changing the overlap width and the input requested delay value,
    When the delay value calculated after changing the overlap width matches the required delay value, the signal line is output as a simulation result.
    The design method according to claim 7.
  9. 　前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記重なり幅の変更後に算出した前記ディレイ値と所定範囲の第２許容ディレイ値とを比較し、
    　前記ディレイ値が前記第２許容ディレイ値の範囲内の場合、前記導体の重なり部分の幅方向の配線幅を変更し、
    　前記配線幅の変更後の前記信号線のディレイ値を算出し、
    　前記配線幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記配線幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　ことを特徴とする請求項８に記載の設計方法。     If the delay value calculated after the change of the overlap width does not match the required delay value, the delay value calculated after the change of the overlap width is compared with a second allowable delay value within a predetermined range;
    When the delay value is within the range of the second allowable delay value, the wiring width in the width direction of the overlapping portion of the conductor is changed,
    Calculate the delay value of the signal line after changing the wiring width,
    Compare the delay value calculated after the change of the wiring width and the input requested delay value,
    When the delay value calculated after changing the wiring width matches the required delay value, the signal line is output as a simulation result.
    The design method according to claim 8.
  10. 　半導体装置を設計する設計装置において、
    　前記半導体装置を製造するために用いられるデータに基づいて、導体を部分的に重なり合わせることにより、前記半導体装置を構成する半導体集積回路と外部接続端子を接続する信号線をミアンダ形状に形成する信号線形成部と、
    　前記信号線形成部によって形成された信号線のディレイ値を算出するディレイ値算出部と、
    　前記ディレイ値算出部によって算出されたディレイ値と入力された要求ディレイ値とを比較する第１ディレイ値比較部と、
    　前記第１ディレイ値比較部による比較の結果、前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する結果出力部と、
    　を備えることを特徴とする設計装置。     In design equipment for designing semiconductor devices,
    Based on data used to manufacture the semiconductor device, a signal that forms a signal line connecting a semiconductor integrated circuit constituting the semiconductor device and an external connection terminal in a meander shape by partially overlapping conductors A line forming section;
    A delay value calculating unit for calculating a delay value of the signal line formed by the signal line forming unit;
    A first delay value comparison unit that compares the delay value calculated by the delay value calculation unit and the input requested delay value;
    As a result of the comparison by the first delay value comparison unit, when the delay value matches the required delay value, a result output unit that outputs the signal line as a simulation result;
    A design apparatus comprising:
  11. 　前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記ディレイ値と所定範囲の第１許容ディレイ値とを比較する第２ディレイ値比較部と、
    　前記第２ディレイ値比較部による比較の結果、前記ディレイ値が前記第１許容ディレイ値の範囲内の場合、前記導体の長さ方向の重なり幅を変更する重なり幅変更部と、
    　を更に備え、
    　前記ディレイ値算出部は、前記重なり幅の変更後の前記信号線のディレイ値を算出し、
    　前記第１ディレイ値比較部は、前記重なり幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記結果出力部は、前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　ことを特徴とする請求項１０に記載の設計装置。     A second delay value comparison unit that compares the delay value with a first allowable delay value within a predetermined range when the delay value does not match the required delay value;
    As a result of the comparison by the second delay value comparison unit, when the delay value is within the range of the first allowable delay value, an overlapping width changing unit that changes the overlapping width in the length direction of the conductor;
    Further comprising
    The delay value calculation unit calculates a delay value of the signal line after the overlap width is changed,
    The first delay value comparison unit compares the delay value calculated after the overlap width is changed with the input requested delay value,
    The result output unit outputs the signal line as a simulation result when the delay value calculated after the overlap width is changed matches the required delay value.
    The design apparatus according to claim 10.
  12. 　前記重なり幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致しなかった場合、前記重なり幅の変更後に算出した前記ディレイ値と所定範囲の第２許容ディレイ値とを比較する第３ディレイ値比較部と、
    　前記第３ディレイ値比較部による比較の結果、前記ディレイ値が前記第２許容ディレイ値の範囲内の場合、前記導体の重なり部分の幅方向の配線幅を変更する重なり配線幅変更部と、
    　を更に備え、
    　前記ディレイ値算出部は、前記配線幅の変更後の前記信号線のディレイ値を算出し、
    　前記第１ディレイ値比較部は、前記配線幅の変更後に算出した前記ディレイ値と入力された要求ディレイ値とを比較し、
    　前記結果出力部は、前記配線幅の変更後に算出した前記ディレイ値が前記要求ディレイ値と一致した場合、前記信号線をシミュレーション結果として出力する、
    　ことを特徴とする請求項１１に記載の設計装置。     A third delay for comparing the delay value calculated after the change of the overlap width with a second allowable delay value within a predetermined range when the delay value calculated after the change of the overlap width does not match the required delay value. A value comparison unit;
    As a result of the comparison by the third delay value comparison unit, when the delay value is within the range of the second allowable delay value, an overlapping wiring width changing unit that changes the wiring width in the width direction of the overlapping portion of the conductor;
    Further comprising
    The delay value calculation unit calculates a delay value of the signal line after changing the wiring width,
    The first delay value comparison unit compares the delay value calculated after the wiring width is changed with the input requested delay value,
    The result output unit outputs the signal line as a simulation result when the delay value calculated after the change in the wiring width matches the required delay value.
    The design apparatus according to claim 11, wherein:
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CN107506515A (en) * 2017-06-29 2017-12-22 广州兴森快捷电路科技有限公司 PCB adds throwing rate computing model construction method and device
CN107506515B (en) * 2017-06-29 2019-12-24 广州兴森快捷电路科技有限公司 Method and device for constructing calculation model of PCB (printed Circuit Board) adding rate

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