JPH09213806A - Wiring device and wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable easy setting of a delay time generated in wiring to a value prescribed by the specification, by evaluating simulation results of the delay time generated in the wiring, changing the shape or position of the wiring of fixed potential in response to the results, adjusting the spacing from a signal wiring, and finding an optimum wiring. SOLUTION: Circuit simulation means 5 finds a delay time generated in wiring of a wiring pattern based on the wiring capacitance and wiring resistance. Delay time evaluation means 6 compares a delay time prescribed by the specification with the delay time found by simulation, and judges whether the resulting delay time of the wiring pattern is longer or shorter than the delay time of the specification. Fixed potential wiring change means 7 changes the wiring of fixed potential in accordance with the resulting delay time of the wiring pattern. When the delay time is to be shortened, the wiring spacing from a signal wiring is broadened. When the delay time is to be elongated, the wiring spacing from the signal wiring is narrowed. Thus, the delay time may be easily set in conformity with the specification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring device and a wiring method for obtaining a wiring pattern of an LSI (Large Scale Integrated Circuit) using a computer.

Wiring patterns of LSIs, MCMs (multi-chip modules), printed circuit boards, etc. can be efficiently obtained by a wiring device using a computer. However, as the number of circuit elements increases, the wiring becomes finer, and the wiring width and wiring interval tend to become smaller.
Therefore, the delay time associated with wiring also increases, and it is necessary to accurately control the wiring design.

[0003]

2. Description of the Related Art FIG. 8 is an explanatory view of a conventional wiring device and wiring method. In FIG. 8, 110 is a wiring device,
It is composed of a CPU, a memory, a program, etc., and obtains the wiring pattern layout, the wiring capacitance and the wiring resistance, and simulates the wiring delay time.

Reference numeral 110 'is a database having a database of wiring capacitance, wiring resistance, etc. per unit length of wiring. Reference numeral 111 denotes an estimation data creation unit that creates estimation data of wiring capacitance and wiring resistance before wiring is laid out.

Reference numeral 112 denotes a data input section for inputting data such as wiring length and wiring width based on the estimated data so as to satisfy requirements such as wiring delay. 1
Reference numeral 13 is a wiring means for extracting the wiring route, the wiring pattern layout, the wiring capacitance and the wiring resistance.

Reference numeral 114 denotes a wiring route determination process, which is a process for determining the wiring route based on data such as the wiring length and the wiring width. Reference numeral 115 is a wiring pattern layout process, in which a wiring pattern is obtained based on the determined wiring path (the wiring is meandered by a given wiring width, etc.), wiring pattern layout data is generated, and the wiring pattern layout data is generated. The data is output to output means such as a display.

Reference numeral 116 denotes wiring capacitance and wiring resistance extraction (LPE
(Layout Parasitic Extraction)). 1
Reference numeral 17 is a circuit simulation means for inputting test data and performing circuit simulation to obtain a delay time or the like caused in wiring.

An input unit 131 is an input unit for inputting wiring data such as wiring length and wiring width (keyboard or the like). Reference numeral 132 denotes a test data input means, which is means for inputting test data necessary for circuit simulation (such as a magnetic disk device holding a test pattern).

An output unit 133 is a display, a printer or the like. FIG. 9 is an example of a wiring pattern. In FIG. 9, 140 is a circuit board.

Reference numeral 141 denotes a wiring, which is an example obtained by the processing of the wiring pattern layout, in which the wiring is meandered in order to increase the wiring capacitance and wiring resistance between the node A and the node B. It is a wiring pattern obtained based on data such as the wiring length and wiring width between the node A and the node B.

The operation of the configuration shown in FIG. 8 will be described. The worker is
An approximate wiring route is obtained based on the circuit diagram, and the wiring capacitance generated in the wiring of the route and the wiring resistance and the like are estimated by the estimation data creation unit 111. Based on the estimated data, the wiring length and the wiring width that satisfy the requirements of the wiring delay time are determined, and the input unit 131 inputs the wiring length and the wiring width to the data input unit 112 for each wiring.

The wiring means 113 determines a wiring path connecting the nodes at both ends of the wiring based on the wiring length and the wiring width (for example, straight connection, meandering, bypassing an obstacle, etc. (step 114)). Then, the wiring pattern having the given width is laid out on the determined route (Process 11).
5)). Once the wiring pattern is obtained, the wiring capacitance for each wiring,
Extract the wiring resistance.

The circuit simulation means 117 inputs the test data (step signal or the like) for testing the delay time by the obtained test data input means 132 and performs circuit simulation to obtain the delay time. Then, the test result is output to the output means 133 such as a display or a printer.

The operator looks at the simulation result of the delay time occurring in the wiring, finds the wiring whose wiring pattern needs to be changed, and changes the wiring width, wiring length, and the like. Then, the data such as the wiring length and the wiring width to be changed is input by the input means 13.
1 is input again to the wiring device 110. Thereafter, the wiring device 110 performs the same processing as described above, and the simulation result is output. Therefore, the operator sees the simulation result, changes the wiring width, the wiring length, etc. for the wiring that needs to be changed, and performs the circuit simulation. This process is repeated to find the wiring pattern with the optimum delay time.

[0015]

In the conventional wiring device and wiring method, the optimum wiring pattern is obtained while repeatedly changing the wiring width and the wiring length and adjusting the delay time as described above. Changing the wiring width and wiring length changes both wiring capacitance and wiring resistance at the same time.
It was difficult to determine the time constant that determines the delay time, and it was not possible to easily find a wiring pattern with an acceptable delay time.

Further, conventionally, there has been considered a method of reducing the influence of wiring capacitance by arranging a wiring whose potential is fixed adjacent to the wiring of interest (Japanese Patent Laid-Open No. 2-51252). Also in this case, the wiring capacitance after laying out the wiring pattern is different from the estimated value. Therefore, the optimum wiring pattern is obtained by changing the wiring length and the wiring width including the wiring whose potential changes after the wiring layout, and changing the wiring interval as in the present invention is not considered. . Therefore, with any conventional wiring device and wiring method, it was not easy in the past to set the delay time to a value that meets the specifications by wiring. Alternatively, it may be necessary to re-determine the wiring route, and it is not easy to obtain the wiring pattern.

It is an object of the present invention to provide a wiring device and a wiring method capable of easily setting a delay time caused by wiring to a value determined by specifications.

[0018]

SUMMARY OF THE INVENTION According to the present invention, wiring data input means, wiring means for laying out wiring on the basis of wiring data to obtain wiring capacitance and wiring resistance, and circuit simulation of the laid-out wiring are performed. In a wiring device provided with a circuit simulation means and a simulation result output means, a delay time evaluation means for evaluating a simulation result of a delay time generated in wiring,
A fixed potential wiring changing means for determining an optimum wiring by changing the shape or position of the fixed potential wiring according to the delay time evaluation result obtained by the delay time evaluation means, and adjusting the interval with the signal wiring; It has a configuration including.

FIG. 1 is a diagram showing the basic configuration of the present invention.
In FIG. 1, S is a wiring device, which is composed of a CPU, a memory, a program, etc., a layout of wiring patterns, wiring capacitance, extraction of resistance, simulation of delay time generated in wiring, simulation evaluation, wiring of fixed potential The changes are to be made.

Reference numeral 1 is a data input section for inputting data which is an initial wiring pattern created based on a circuit diagram. Reference numeral 2 is a wiring means for determining a wiring route, laying out a wiring pattern, and obtaining a wiring capacitance and a wiring resistance.

A wiring pattern layout means 3 lays out a wiring pattern. Reference numeral 4 is a wiring capacitance / wiring resistance extraction means for obtaining the wiring capacitance and wiring resistance of the wiring pattern laid out by the wiring pattern layout means 3.

Reference numeral 5 is a circuit simulation means,
It is intended to simulate the delay time generated in wiring. A delay time evaluation unit 6 evaluates the delay time of the simulation result.

Reference numeral 7 is a fixed potential wiring changing means for changing a wiring having a fixed potential (for example, a wiring determined to be a ground potential, a power supply potential, etc.) and changing a distance between the wiring and the signal wiring. is there.

The operation of the basic configuration of the present invention shown in FIG. 1 will be described. Based on the circuit diagram, estimate the wiring capacitance and wiring resistance, create data for the initial wiring pattern, and input it. The wiring pattern layout means 3 lays out a wiring pattern based on the data, and the wiring capacitance / wiring resistance extraction means 4 obtains the wiring capacitance and wiring resistance of the wiring pattern.

The circuit simulation means 5 has a wiring capacitance,
The delay time caused in the wiring of the wiring pattern is obtained based on the wiring resistance. The delay time evaluation means 6 compares the delay time given as the specification with the delay time obtained by simulation, and determines whether the obtained delay time of the wiring pattern is longer or shorter than the specified delay time.

The fixed potential wiring changing means 7 changes the wiring whose potential is fixed (for example, the wiring which is fixed to the ground potential or the power supply potential) depending on whether the delay time of the obtained wiring pattern is long or short. Then, narrow or widen the interval with the signal wiring. When it is necessary to shorten the delay time, the wiring interval is widened. The method of widening the wiring interval is to narrow the width of all or part of the wiring of fixed potential. Alternatively, the entire fixed potential wiring is moved away from the signal wiring. On the other hand, when increasing the delay time, narrow the wiring interval. The method to narrow the wiring interval is
Widen the whole or part of the fixed potential wiring. Alternatively, the entire fixed potential wiring is moved toward the signal wiring.

The wiring method of the present invention will be described in detail with reference to FIGS. FIG. 2A shows the wiring pattern before the change. FIG. 2 (b) is a sectional view of FIG. 2 (a).

In FIGS. 2 (a) and 2 (b), reference numeral 21 is a signal wiring, which is the wiring 1 in which the potential fluctuates. Reference numeral 22 denotes a fixed potential wiring, which is a fixed potential wiring 2 adjacent to the signal wiring 1 (21).

Reference numeral 23 denotes a fixed potential wiring, which is a fixed potential wiring 3 adjacent to the signal wiring 1 (21). Reference numeral 25 is a substrate.

C ₁₁ is a wiring capacitance between the wiring 1 (21) and the substrate 25. C ₁₂ is a wiring capacitance between the wiring 2 (22) and the substrate 25. C ₁₃ is a wiring capacitance between the wiring 3 (23) and the substrate 25.

C ₂₀ is the wiring capacitance between the wiring 2 (22) and the wiring 21 (1). C ₂₁ is wiring 3 (23) and wiring 2
1 (1) is the wiring capacitance. The present invention provides a wiring capacitance C ₂₀ between the fixed potential wiring 2 (22) and its signal wiring 1 (21), or a wiring capacitance between the fixed potential wiring 3 (23) and its signal wiring 1 (21). Focusing on C ₂₁ and changing the wiring capacitance thereof, the delay time is adjusted.

FIG. 3 is an explanatory diagram of an example of the wiring method of the present invention. In FIG. 3, reference numeral 21 is a signal wiring, which is the wiring 1 whose potential changes.

Reference numeral 22 denotes a fixed potential wiring, which is a fixed potential wiring 2 adjacent to the signal wiring 1 (21). Reference numeral 23 denotes a fixed potential wiring, which is a fixed potential wiring 3 adjacent to the signal wiring 1 (21).

FIG. 3A shows an example in which the delay time is extended from the wiring pattern before the change in FIG. 2A. The widths of both the fixed potential wiring 2 (22) and the fixed potential wiring 3 (23) are increased to narrow the wiring distance A and the wiring distance B of the wiring pattern before the change, and the wiring distance E and the wiring distance F, respectively. It is what

FIG. 3B shows an example in which the delay time is extended from the wiring pattern before the change in FIG. 2A. By widening a part of the width of the fixed potential wiring 2 (22), the wiring distance A of the wiring pattern before the change is narrowed to the wiring distance G.

FIG. 3C is an example of a case where the delay time is shortened from the wiring pattern before the change of FIG. 2A. The entire fixed potential wiring 2 (22) and fixed potential wiring 3 (23) are moved toward the signal wiring 1 (21) to widen the wiring interval A and the wiring interval B of the wiring pattern before the change, respectively. The wiring interval C and the wiring interval D are used. Although not shown, in order to shorten the delay time, the wiring interval G is made wider than the wiring interval A of the wiring pattern before the change.

The wiring changed in the present invention has a fixed potential.
Therefore, the factor that influences the change of the delay time is substantially the wiring capacitance (C ₂₀ , C ₂₁ ) between the changed wiring and the signal wiring, and there is no resistance change due to the wiring change. Since only the wiring capacitance (C ₂₀ , C ₂₁ ) needs to be considered for the adjustment of the delay time,
The wiring design can be facilitated.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows an embodiment of the apparatus configuration of the present invention. In FIG. 4, reference numeral 51 is an estimation data creation unit for creating estimation data of wiring capacitance and wiring resistance based on the circuit diagram.

Reference numeral 51 'is a database for holding a database of wiring capacitance, resistance, etc. per unit length. A data input unit 52 is for inputting data (wiring length, wiring width, etc.) that defines an initial wiring pattern that satisfies requirements such as delay time.

Reference numeral 53 is a wiring means for determining a wiring route, extracting a wiring pattern layout, a wiring capacitance, and a wiring resistance. Reference numeral 54 denotes a wiring route determination process, which determines the wiring route based on the wiring width and the wiring length.

Reference numeral 55 denotes a wiring pattern layout process for laying out a wiring pattern and outputting it to the output means 62 such as a display. 56 is the wiring capacitance,
This is a process for extracting the wiring resistance, which is to obtain the wiring capacitance and wiring resistance of the obtained wiring pattern.

Reference numeral 57 is a circuit simulation means for simulating the delay time generated in the wiring. Reference numeral 58 is a delay time evaluation means, which compares the delay time given by the specification with the delay time obtained by the simulation and determines whether the delay time obtained by the simulation is appropriate or not. It is a thing.

Reference numeral 59 is a fixed potential wiring changing means,
According to the evaluation result of the delay time, the interval between the fixed potential wiring and the signal wiring is changed so that the delay time approaches the reference value (specification).

Reference numeral 61 is an input means for inputting wiring data, delay time of specifications, and the like. Reference numeral 62 denotes an output means, which is a display, a printer, or the like.

Reference numeral 63 is a test data input means for inputting test data for testing the delay time. The operation of the configuration of FIG. 4 will be described.

Based on the circuit diagram, the estimation data creating section 51 is used to estimate the wiring capacitance, the wiring resistance and the like. The input means 61 is used to input a wiring path, wiring width, wiring length, etc., which gives an initial wiring pattern to the data input section 52.

The wiring means 53 determines the wiring route. A wiring pattern is laid out based on the data input by the wiring pattern layout process 55. The obtained wiring pattern is output to the output means 62. Next, the wiring capacitance and resistance are extracted from the obtained wiring pattern layout (wiring capacitance and wiring resistance extraction processing 56).

The circuit simulation means 57 inputs the test data from the test data input means 63 and obtains the delay time caused in the wiring due to the wiring capacitance and the wiring resistance of the wiring pattern. The simulation result is output by the output means 6
Output to 2.

The delay time evaluation means 58 compares the delay time obtained by the simulation with the delay time of the given specifications. The fixed potential wiring changing means 59 changes the fixed potential wiring according to the evaluation result of the delay time evaluation means 58.

In accordance with the wiring change of the fixed potential wiring changing means 59, the wiring pattern is changed by the wiring pattern layout processing 55. Wiring capacitance and wiring resistance extraction process 5
The wiring capacitance and wiring resistance of the wiring pattern changed by 6 are obtained. The circuit simulation means 57 obtains the delay time again from the wiring capacitance and wiring resistance of the changed wiring pattern. The delay time evaluation unit 58 evaluates the simulation result of the delay time, and the fixed potential wiring changing unit 59.
Changes the wiring according to the evaluation result. Alternatively, when the evaluation result of the delay time is considered to meet the specifications,
Do not change the wiring.

This process is repeated to find the optimum wiring pattern. FIG. 5 shows Embodiment 1 of the fixed potential wiring changing means of the present invention. In the first embodiment, the distance between the signal wiring and the signal wiring is changed by widening or narrowing the wiring of the fixed potential.

In FIG. 5, reference numeral 59 is a fixed potential wiring changing means. S1 Evaluation delay time is longer than the required delay time.

By reducing the width of the wiring of S2 fixed potential, the distance between the wiring and the signal wiring is increased. As a result, the wiring capacitance between the wiring and the signal wiring becomes small and the delay time becomes short.

S11 The evaluation delay time is smaller than the required delay time. S12 By increasing the width of the fixed potential wiring, the distance between the wiring and the signal wiring is narrowed. As a result, the wiring capacitance between the wiring and the signal wiring becomes large, and the delay time becomes long.

S21 The evaluation delay time is equal to the required delay time. S22 Since the wiring delay time meets the required specifications,
Do not change the wiring. FIG. 6 is a second embodiment of the fixed potential wiring changing means of the present invention. The second embodiment is to change the interval between the signal wiring and the wiring by widening or narrowing a part of the wiring of fixed potential.

In FIG. 6, reference numeral 59 is a fixed potential wiring changing means. S1 Evaluation delay time is longer than the required delay time.

By reducing the width of a part of the wiring of S2 fixed potential, the distance between the wiring and the signal wiring is increased. As a result, the wiring capacitance between the wiring and the signal wiring becomes small and the delay time becomes short.

S11 The evaluation delay time is shorter than the required delay time. S12 By increasing the width of part of the fixed potential wiring, the distance between the wiring and the signal wiring is narrowed. As a result, the wiring capacitance between the wiring and the signal wiring becomes large, and the delay time becomes long.

S21 The evaluation delay time is equal to the required delay time. S22 Since the wiring delay time meets the required specifications,
Do not change the wiring. FIG. 7 shows Embodiment 3 of the fixed potential wiring changing means of the present invention. In the third embodiment, the distance to the signal wiring is changed by moving the wiring of fixed potential.

In FIG. 7, reference numeral 59 is a fixed potential wiring changing means. S1 Evaluation delay time is longer than the required delay time.

S2 The whole wiring of the fixed potential is moved in the direction away from the signal wiring. As a result, the distance between the signal wiring and the wiring becomes wide, the wiring capacitance between the wiring and the signal wiring becomes small, and the delay time becomes short.

S11 The evaluation delay time is smaller than the required delay time. S12 The wiring of the fixed potential is moved in the direction of approaching the entire wiring from the signal wiring. As a result, the distance between the wiring and the signal wiring becomes narrow, the wiring capacitance between the wiring and the signal wiring becomes large, and the delay time becomes long.

S21 The evaluation delay time and the delay time of the required specifications are equal. S22 Since the wiring delay time meets the required specifications,
Do not change the wiring.

[0064]

According to the present invention, the wiring of fixed potential is changed.
Therefore, the factors that affect the delay time by changing the wiring are
Wiring capacitance between the changed wiring and signal wiring (C₂₀, C_{twenty one})
There is no change in resistance due to wiring changes. Therefore,
Adjust the delay time by adjusting the wiring capacitance (C ₂₀, C_{twenty one}) Only
Therefore, it is easy to find the wiring with the delay time according to the specifications.
Will be able to Moreover, the wiring route is calculated again.
There is no need to do so.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a wiring method of the present invention.

FIG. 3 is a diagram showing an example of a wiring method of the present invention.

FIG. 4 is a diagram showing a device configuration of the present invention.

FIG. 5 is a diagram showing a first embodiment of a fixed potential wiring changing means of the present invention.

FIG. 6 is a diagram showing a second embodiment of a fixed potential wiring changing means of the present invention.

FIG. 7 is a diagram showing a third embodiment of a fixed potential wiring changing means of the present invention.

FIG. 8 is an explanatory diagram of a conventional wiring device and wiring method.

FIG. 9 is a diagram showing an example of a wiring pattern.

[Explanation of symbols]

 S: Wiring device 1: Initial wiring pattern 2: Wiring means 3: Wiring pattern layout means 4: Wiring capacitance and wiring resistance extraction means 5: Circuit simulation means 6: Delay time evaluation means 7: Wiring change means of fixed potential

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/82 W

Claims (5)

[Claims] 1. Wiring data input means, wiring means for laying out wiring based on the wiring data to obtain wiring capacitance and wiring resistance, circuit simulation means for performing circuit simulation of the laid out wiring, and simulation results In a wiring device including an output means, a delay time evaluation means for evaluating a simulation result of a delay time occurring in a wiring, and a shape of a wiring of a fixed potential according to the delay time evaluation result obtained by the delay time evaluation means or A wiring device having a fixed potential wiring changing means for obtaining an optimum wiring by changing a position and adjusting a distance between the wiring and the signal wiring. 2. Wiring data input means, wiring means for laying out wiring based on the wiring data to obtain wiring capacitance and wiring resistance, circuit simulation means for performing circuit simulation of the laid-out wiring, and simulation results In a wiring method for obtaining a wiring layout including an output means, a delay time evaluation means for evaluating a simulation result of a delay time occurring in the wiring, and a wiring shape or a wiring whose potential is fixed based on the delay time simulation evaluation result. Equipped with a fixed potential wiring changing means for changing the position, the wiring capacitance and resistance of the wiring are obtained, circuit simulation is performed, and the delay time generated in the simulation is evaluated.
A wiring method characterized in that an optimum wiring is obtained by repeating the above wiring change and simulation based on an evaluation result. 3. The fixed potential wiring changing means changes the wiring by changing the wiring width of the fixed potential wiring, and changes the wiring interval with the signal wiring.
Wiring method described in. 4. The fixed potential wiring changing means changes the wiring by changing the wiring width of a part of the fixed potential wiring, and changes the wiring interval with the signal wiring. Wiring method described in. 5. The wiring method according to claim 2, wherein the fixed potential wiring changing means changes the wiring interval with the signal wiring by moving the fixed potential wiring.