JP5928220B2 - Electrical characteristic extraction method and apparatus - Google Patents

Description

  The present invention relates to accurately modeling a semiconductor package on which a plurality of semiconductor chips are mounted.

  With the recent increase in speed and capacity of electronic devices, transmission that requires an ultra-wide bandwidth exceeding 10 Gbps with the following chip-to-chip connection has been required.

-Between a logic chip (logic chip) and a logic chip-As a technique for realizing this between a logic chip and a wide band memory (wide band memory) chip, a plurality of chips are connected via an interposer (relay substrate). A 2.5-dimensional mounting module mounted on one package (PKG) is used.

JP 2010-205004 A JP 2007-004418 A JP 2008-082842 A JP 2000-028665 A

  However, as shown in FIG. 1, inter-chip transmission in a 2.5-dimensional mounting module 7 in which a logic chip 2c and a wideband memory chip (or logic chip) 2d are mounted as one semiconductor package 2a is performed by a bus 2e. A technique of performing transmission using hundreds or more signals by (super multi-bus) is required, and it is difficult to realize it by a semiconductor package wiring technique.

  Therefore, attention is paid to transmission by a fine redistribution (RDL) technique using an interposer (silicon interposer 2b) manufactured by a silicon process.

  When transmitting between chips of several millimeters or more and several hundred Mbps or more per pin, it is necessary to consider RDL as a transmission line and extract and model electrical characteristics with high accuracy.

  Therefore, an object of the present invention is to accurately model a semiconductor package on which a plurality of semiconductor chips are mounted.

  The disclosed technology is an electrical characteristic extraction method executed by a computer, and a single-layer semiconductor package in which a plurality of chips are arranged in a single layer on a silicon interposer in which a virtual ground plane is inserted, which is stored in a storage unit The first inductance value of the virtual ground plane is extracted and stored in the storage unit, and the signal line connecting the plurality of chips and the second inductance value of the virtual ground plane are extracted. And storing the first inductance value and the second inductance value from the storage unit, and subtracting the first inductance value from the second inductance value. 2 is corrected to obtain the inductance value of the signal line between the plurality of chips.

  Further, as means for solving the above-described problems, an electrical characteristic extraction device, a program for causing a computer to function as the electrical characteristic extraction device, and a recording medium on which the program is recorded can be used.

  In the disclosed technique, an equivalent circuit model such as RLC is used to accurately extract the inductance value of a signal line between a plurality of chips in a semiconductor package in which a plurality of semiconductor chips connected via a silicon interposer are mounted in a single layer. Can be created with high accuracy.

It is a figure which shows the example of a 2.5-dimensional mounting module. It is a figure which shows the example of wiring drawing. It is a figure which shows the example of single layer RDL self / mutual inductance (L) distribution. It is a figure for demonstrating the principle of a 2.5-dimensional electromagnetic field solver. It is a figure which shows the hardware constitutions of an electrical property extraction apparatus. It is a figure which shows the function structural example of an electrical property extraction apparatus. It is a figure for demonstrating the process by an input part. It is a figure for demonstrating the process by the virtual ground plane setting part. It is a figure for demonstrating the process by the height setting part. It is a figure for demonstrating the process by a virtual ground plane insertion part. It is a figure for demonstrating the process by a 1st extraction part. It is a figure for demonstrating the process by a 2nd extraction part. It is a figure for demonstrating the process by a correction | amendment calculation part. It is a figure for demonstrating the correction calculation method in step S82. It is a figure for demonstrating the process by a result output part. It is a figure which shows the example of an equivalent circuit model. It is a figure which shows the comparison result of a waveform analysis. It is a figure which shows the comparison result of processing capability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In SiP (System in a Package), a silicon interposer for wiring between a plurality of chips is mounted. Although the silicon interposer can be designed and manufactured with a plurality of layers, it needs to be designed and manufactured with a single layer in order to reduce costs such as mask costs. For example, a 2.5-dimensional mounting module 7 as shown in FIG. 1 is designed.

  In the design using the 2.5-dimensional mounting module 7, when extracting electrical characteristics of RDL (Re-distributed Line) (hereinafter simply referred to as single-layer RDL) wired in a single layer, 3 It is common to use a dimensional electromagnetic simulator.

  FIG. 2 is a diagram illustrating an example of a wiring drawing. When the electrical characteristics of several hundred or more signals are collectively extracted by a three-dimensional electromagnetic field simulator, extraction time may be enormous, extraction may not be possible in a realistic time, or convergence may be very poor.

  As a countermeasure, for example, by cutting out a part of the bus 2e between the logic chip 2c and the memory chip 2d from the wiring diagram 3 shown in FIG. Extract characteristics. Wiring information corresponding to the cut-out portion 3p is a target for analyzing electrical characteristics with a three-dimensional electromagnetic field simulator.

  FIG. 3 is a diagram illustrating an example of a single-layer RDL self / mutual inductance (L) distribution. As shown in FIG. 3, the self L3a indicating the self-inductance and a part of the mutual L3b indicating the mutual inductance due to the peripheral wiring are considered. However, depending on the size of the cutout portion 3p, most of the mutual L3b is not yet present. Therefore, there is a case where the coupling between wirings cannot be properly considered.

  On the other hand, as a tool for extracting a large-scale signal wiring model at high speed, there is a 2.5-dimensional electromagnetic field solver. However, a ground plane is always required below the signal line in order to correctly extract the electrical characteristics of the signal.

  FIG. 4 is a diagram for explaining the principle of the 2.5-dimensional electromagnetic field solver. In FIG. 4A, when the signal 4b and the ground plane surface 4a are uniform according to the electromagnetic field distribution as shown in FIG. 4B, the mesh generated on the XY plane is swept in the Z direction (FIG. 4 (C)), the number of meshes can be reduced and high-speed electromagnetic field analysis can be performed. This is the principle of the 2.5-dimensional electromagnetic field solver.

  When a slit or the like is inserted and the ground plane 4a disappears under the signal 4b, the electromagnetic field distribution becomes non-uniform and mesh generation in the Z direction is required. In this case, the accuracy of the 2.5-dimensional electromagnetic field solver is very poor, and it is necessary to analyze with a three-dimensional electromagnetic field solver. The 2.5-dimensional electromagnetic field solver is not suitable for extracting the electric characteristics of the single-layer RDL having no ground plane, but the extraction time is enormous for the 3-dimensional electromagnetic field solver.

  Below, it is possible to extract electrical characteristics while maintaining the accuracy of all wirings at once, even in a single-layer RDL without a ground solid surface by using a 2.5-dimensional electromagnetic field solver efficiently, and A mechanism that enables simulation in a short time will be described.

  The electrical property extraction apparatus for performing electrical property extraction processing of the single layer RDL that automatically extracts the electrical properties of the single layer RDL according to the present embodiment at high speed has a hardware configuration as shown in FIG. In FIG. 5, an electrical characteristic extraction device 100 is a terminal controlled by a computer and includes a CPU (Central Processing Unit) 11, a main storage device 12, an auxiliary storage device 13, an input device 14, and a display device 15. And an output device 16, a communication I / F (interface) 17, and a drive 18, which are connected to the bus B.

  The CPU 11 controls the electrical characteristic extraction device 100 according to a program stored in the main storage device 12. The main storage device 12 uses a RAM (Random Access Memory) or the like, and stores a program executed by the CPU 11, data necessary for processing by the CPU 11, data obtained by processing by the CPU 11, and the like. A part of the main storage device 12 is allocated as a work area used for processing by the CPU 11.

  The auxiliary storage device 13 uses a hard disk drive and stores data such as programs for executing various processes. A part of the program stored in the auxiliary storage device 13 is loaded into the main storage device 12 and executed by the CPU 11, whereby various processes are realized. The storage unit 130 includes the main storage device 12 and / or the auxiliary storage device 13.

  The input device 14 includes a mouse, a keyboard, and the like, and is used for a user to input various information necessary for processing by the electrical characteristic extraction device 100. The display device 15 displays various information required under the control of the CPU 11. The output device 16 has a printer or the like and is used for outputting various types of information in accordance with instructions from the user. The communication I / F 17 is a device that is connected to, for example, the Internet, a LAN (Local Area Network), etc., and controls communication with an external device.

  A program that realizes the processing performed by the electrical characteristic extraction apparatus 100 is provided to the electrical characteristic extraction apparatus 100 by a storage medium 19 such as a CD-ROM (Compact Disc Read-Only Memory). That is, when the storage medium 19 storing the program is set in the drive 18, the drive 18 reads the program from the storage medium 19, and the read program is installed in the auxiliary storage device 13 via the bus B. . When the program is activated, the CPU 11 starts its processing according to the program installed in the auxiliary storage device 13. The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.

  FIG. 6 is a diagram illustrating a functional configuration example of the electrical characteristic extraction device. In FIG. 6, the electrical characteristic extraction unit 100 includes an input unit 20 and an electrical characteristic extraction unit 120. The electrical characteristic extraction unit 120 includes a virtual ground plane setting unit 30, a height setting unit 40, a virtual ground plane insertion unit 50, a first extraction unit 60, a second extraction unit 70, a correction calculation unit 80, The result output unit 90 is included as a processing unit. The processing units 20, 30, 40, 50, 60, 70, 80, and 90 are realized by processing by the CPU 11 executing a corresponding program.

  The storage unit 130 of the electrical characteristic extraction unit 100 stores setting information 22, simulation data 24 before insertion of the virtual ground plane, simulation data 52 after insertion of the virtual ground plane, inductance value 62 of the virtual ground plane, and electrical characteristics of all RDL signals. 71, an inductance value 72 of all RDL signals, an RDL inductance value 82, an equivalent circuit model 92, and the like are stored.

  The input unit 20 is a processing unit that inputs setting information 22 necessary for simulation and creates RDL simulation data 24. The setting information 22 and the RDL simulation data 24 are stored in the storage unit 130. The simulation data 24 is data before insertion of the virtual ground plane. The processing by the input unit 20 will be described later with reference to FIG.

  The virtual ground plane setting unit 30 is a processing unit that derives and sets a distance D at which the inductance of the RDL is not affected by the virtual ground plane. The processing by the virtual ground plane setting unit 30 will be described later with reference to FIG.

  The height setting unit 40 is a processing unit that derives and sets a height H at which the inductance of the RDL is not affected by the virtual ground plane. The processing by the height setting unit 40 will be described later with reference to FIG.

  The virtual ground plane insertion unit 50 is a processing unit that automatically inserts a virtual ground plane at a distance D and automatically inserts a via at a height H to create simulation data 52 after insertion of the virtual ground plane. The simulation data 52 after the virtual ground plane is inserted is stored in the storage unit 130. The processing by the virtual ground plane insertion unit 50 will be described later with reference to FIG.

  The first extraction unit 60 is a processing unit that extracts the inductance of the virtual ground plane. The extracted inductance value 62 is stored in the storage unit 130. The processing by the first extraction unit 60 will be described later with reference to FIG.

  The second extraction unit 70 is a processing unit that extracts electrical characteristics of all RDL signals. An electrical characteristic 71 including an inductance value 72 of all RDL signals is stored in the storage unit 130. The processing by the second extraction unit 70 will be described later with reference to FIG.

  The correction calculation unit 80 corrects the inductance value 72 of the RDL total signal extracted by the second extraction unit 70 using the inductance value 62 of the virtual ground plane extracted by the first extraction unit 60, thereby obtaining an RDL inductance value. 82 is a processing unit that acquires 82. The RDL inductance value 82 is stored in the storage unit 130. The processing by the correction calculation unit 80 will be described later with reference to FIG.

  The result output unit 90 is a processing unit that generates an equivalent circuit model 92 of all RDL signals. The generated equivalent circuit model 92 is stored in the storage unit 130. The processing by the result output unit 90 will be described later with reference to FIG.

  FIG. 7 is a diagram for explaining processing by the input unit. In FIG. 7, the input unit 20 inputs setting information 22 for RDL wiring (step S21). The setting information 22 includes design rules (RDL wiring width, wiring interval, etc.) applied to the single-layer RDL design, conductor thickness of the virtual ground plane, dielectric thickness, RDL conductor material, and dielectric constant of the dielectric. And dielectric loss tangent. The setting information 22 further includes an analysis frequency for analyzing the single RDL design. The setting information 22 is set using the input device 14 from the input screen of the setting information 22 displayed on the display device 15 by the designer. The setting information 22 is stored in the storage unit 130.

  Next, the input unit 20 creates RDL wiring simulation data 24 based on the setting information 22 (step S22). The created simulation data 24 is stored in the storage unit 130. And the input part 20 performs the electrical property extraction process of single layer RDL (step S23).

  The processing by the virtual ground plane setting unit 30 will be described with reference to FIG. FIG. 8A is a diagram for explaining a first processing example by the virtual ground plane setting unit. In FIG. 8A, when executed from the input unit 20, the virtual ground plane setting unit 30 activates a two-dimensional electromagnetic field analysis program (step S31a).

  Then, the virtual ground plane setting unit 30 uses the setting information 22 stored in the storage unit 130 to design the RDL 30r (wiring width, wiring interval) and dielectric information about the dielectric 30d (dielectric thickness, relative dielectric constant, The dielectric tangent), the conductor material of the RDL 30r, the analysis frequency, etc. are read out, and the cross-sectional shape 5a and the analysis setting 5b are automatically generated (step S32a).

  The cross-sectional shape 5a is automatically generated using design rules, dielectric information, conductor thickness of the virtual ground plane 30g, and the like. The analysis setting 5b is automatically generated using the RDL conductor material, analysis frequency, and the like.

  Next, the virtual ground plane setting unit 30 determines the distance D at which the inductance of the RDL 30r (RDL inductance) is not affected by the virtual ground plane 30g from the relationship between the RDL 30r and the virtual ground plane 30g by the two-dimensional electromagnetic field analysis program. Derived and determined (step S33a).

  Then, the virtual ground plane setting unit 30 exports the distance D to the virtual ground plane insertion unit 50 (step S34a).

  In the processing by the virtual ground plane setting unit 30 described above, a distance from the virtual ground plane 30d of the RDL 30r is obtained by incorporating a two-dimensional electromagnetic field analysis program for extracting the electrical characteristics of the signal wiring from the cross-sectional shape 5a into the virtual ground plane setting unit 30. D can be derived.

  In determining the distance D, if the conductor material, relative dielectric constant, dielectric loss tangent, and analysis frequency are the same, the processing can be simplified by incorporating a lookup table. FIG. 8B is a diagram for explaining a second processing example by the virtual ground plane setting unit.

  In FIG. 8B, the virtual ground plane setting unit 30 determines the RDL 30r design rules (wiring width and wiring interval), the conductor thickness of the RDL 30r, and the setting information 22 from the input unit 20 stored in the storage unit 130. Is acquired (step S31b).

  The virtual ground plane setting unit 30 refers to the built-in lookup table T6 prepared in advance in the storage unit 130, and determines the distance D at which the RDL 30r is not affected by the virtual ground plane 30g (step S32b).

  The built-in lookup table T6 is a table in which the distance D and the height H are associated with each wiring interval for each conductor thickness and wiring width of the RDL 30r. The distance D and the height H indicate the distance and the height at which the RDL inductance is not affected by the virtual ground plane 30g.

  For example, for the conductor thickness “1 μm” and the wiring width “1 μm”, the wiring intervals “1 μm”, “2 μm”, “3 μm”, “4 μm”, and “5 μm” are set to “2.5 μm”, “3 μm”. ”,“ 3 μm ”,“ 3 μm ”, and“ 3 μm ”distances D are associated with heights“ 10 μm ”,“ 15 μm ”,“ 15 μm ”,“ 15 μm ”, and“ 15 μm ”, respectively. .

  The virtual ground plane setting unit 30 exports the determined distance D to the virtual ground plane insertion unit 50 (step S33b).

  The processing by the height setting unit 40 will be described with reference to FIG. FIG. 9A is a diagram for describing a first processing example by the height setting unit. 9A, when the height setting unit 40 is executed from the input unit 20, the height setting unit 40 starts a two-dimensional electromagnetic field analysis program (step S41a).

  Then, the height setting unit 40 uses the setting information 22 stored in the storage unit 130 to design the RDL 30r (wiring width, wiring interval) and dielectric information about the dielectric 30d (dielectric thickness, relative dielectric constant, dielectric constant). Tangent), the conductor material of RDL 30r, the analysis frequency, and the like are read, and the cross-sectional shape 5a and the analysis setting 5b are automatically generated (step S42a). A predetermined value may be used for the conductor thickness of the virtual ground plane 30g. The generation of the cross-sectional shape 5a and the analysis setting 5b is the same as that in step S32a in FIG.

  Next, the height setting unit 40 determines a height H at which the inductance of the RDL 30r (RDL inductance) is not affected by the virtual ground plane 30g from the relationship between the RDL 30r and the virtual ground plane 30g by the two-dimensional electromagnetic field analysis program. Derived and determined (step S43a).

  Then, the height setting unit 40 exports the height H to the height setting unit 40 (step S44a).

  In the processing by the height setting unit 40 described above, the height setting unit 400 incorporates a two-dimensional electromagnetic field analysis program for extracting the electrical characteristics of the signal wiring from the cross-sectional shape 5a, thereby increasing the height H from the virtual ground plane 30d of the RDL 30r. Can be derived.

  In determining the height H, if the conductor material, relative dielectric constant, dielectric loss tangent, and analysis frequency are the same, the processing can be simplified by incorporating a lookup table. FIG. 9B is a diagram for explaining a second processing example by the virtual ground plane setting unit.

  In FIG. 9B, the height setting unit 40 determines the design rule (wiring width, wiring interval) of the RDL 30r and the conductor thickness of the RDL 30r from the setting information 22 by the input unit 20 stored in the storage unit 130. Obtain (step S41b).

  The height setting unit 40 refers to the built-in lookup table T6 prepared in advance in the storage unit 130, and determines the height H at which the RDL 30r is not affected by the virtual ground plane 30g (step S42b). The built-in lookup table T6 is the same as the table referred to by the virtual ground plane setting unit 30 in FIG.

  The height setting unit 40 exports the determined height H to the virtual ground plane insertion unit 50 (step S43b).

  FIG. 10 is a diagram for explaining processing by the virtual ground plane insertion unit. In FIG. 10, the virtual ground plane insertion unit 50 reads the distance D, the height H, and the simulation data 24 (step S51).

  Based on the distance D, the virtual ground plane insertion unit 50 automatically inserts the virtual ground plane 30g into the simulation data 24 (step S52). A virtual ground plane is inserted below the RDL as a virtual ground plane 30g. As the thickness of the virtual ground plane 30g, the conductor thickness set by the input unit 20 is used.

In addition, the virtual ground plane insertion unit 50 automatically inserts the via 5v between the RDL 30r and the virtual ground plane 30g (step S53). Insert vias
It is automatically performed between the ground pad on the logic chip 2c side and the virtual ground plane 30g and between the ground pad on the wide band memory chip 2d side and the virtual ground plane 30g. The via shape may be the same size and the same diameter as the pad.

  Through the above-described steps S52 and S53, simulation data 52 including the RDL 30r and the virtual ground 30g is generated and stored in the storage unit 130. After the simulation data 52 is generated, a process in the first extraction unit 60 that extracts the inductance of the virtual ground plane 30g is performed.

  FIG. 11 is a diagram for explaining processing by the first extraction unit. 11, the first extraction unit 60 automatically selects only the virtual ground plane data 52-2 from the simulation data 52 including the RDL 30r and the virtual ground 30g generated by the virtual ground plane insertion unit 50 (step S61). A two-dimensional electromagnetic field analysis program is activated (step S62). The three-dimensional electromagnetic field analysis program is a program that performs electromagnetic field simulation from a three-dimensional shape, and is incorporated in the first extraction unit 60.

  The first extraction unit 60 reads a value necessary for analysis from the setting information 22 stored in the storage unit 130, and analyzes the inductance of the virtual ground plane 30g (step S63). The relative permittivity, dielectric loss tangent, conductor material, and analysis frequency are read from the setting information 22. The first extraction unit 60 stores the inductance value 62 of the virtual ground plane 30g extracted by the three-dimensional electromagnetic field analysis program in the storage unit 130 (step S64). After the process in the first extraction unit 60, the process by the second extraction unit 70 is performed.

  FIG. 12 is a diagram for explaining processing by the second extraction unit. In FIG. 12, the second extraction unit 70 reads the simulation data 52 including the RDL 30r and the virtual ground 30g generated by the virtual ground plane insertion unit 50 from the storage unit 130 (step S71), and the 2.5-dimensional electromagnetic field analysis program Is activated (step S72). The 2.5-dimensional electromagnetic field analysis program is incorporated in the second extraction unit 70.

  The second extraction unit 70 reads a value necessary for analysis from the setting information 22 stored in the storage unit 130, and uses the virtual ground plane 30g as a return path, and the electrical characteristics 71 (inductance, capacitance, resistance) of all the RDL signals. Are analyzed and extracted (step S73). The second extraction unit 70 stores the electrical characteristics 71 including the inductance value 72 of all the extracted RDL signals in the storage unit 130 (step S74).

  In this embodiment, the virtual ground plane is arranged in the lower layer of the RDL signal, so that the electrical characteristics of the signal line can be extracted with high accuracy.

  After the processing in the second extraction unit 70, the process proceeds to the processing by the correction calculation unit 80 that corrects the RDL inductance.

  FIG. 13 is a diagram for explaining processing by the correction calculation unit. In FIG. 13, the correction calculation unit 80 uses the inductance value 62 of the virtual ground plane 30 g extracted by the first extraction unit 60 and the inductance value 72 of all RDL signals extracted by the second extraction unit 70 from the storage unit 130. Read (step S81).

  The correction calculation unit 80 deletes the inductance value 62 of the virtual ground plane 30g from the inductance value 72 of the RDL all signals including the RDL self-inductance value and the RDL mutual inductance value by the inductance matrix calculation described later in FIG. The inductance value 72 of all RDL signals is corrected (step S82).

  Then, the correction calculation unit 80 outputs the RDL inductance value 82 indicating the corrected inductance value of all RDL signals to the storage unit (step S83).

  FIG. 14 is a diagram for explaining the correction calculation method in step S82. In FIG. 14, for the sake of simplicity of explanation, two RDL signal lines RDL1 and RDL2 and a virtual ground plane 30g will be described as an example.

  The inductance L11 is the inductance of the RDL signal line RDL1, and the inductance L22 is the inductance of the RDL signal line RDL2.

  The inductance L13 is a mutual inductance between the RDL signal line RDL1 and the virtual ground plane 30g, and the inductance L23 is a mutual inductance between the RDL signal line RDL2 and the virtual ground plane 30g. The inductances L13 and L23 are extracted by the second extraction unit 70.

  The inductances L13 and L23 extracted by the second extraction unit 70 are not affected by the height H derived by the height setting unit 40 (mutual inductance coupling) and are almost zero.

  Further, the inductance L33 is an inductance of the virtual ground plane 30g and is a value extracted in advance by the first extraction unit 60. By subtracting L33 from the diagonal and non-diagonal terms of the matrix 8m, the self-inductance values L11 and L22 of the single-layer RDL signal lines RDL1 and RDL2 can be obtained.

  Even if the number of RDL signals increases, the calculation load is substantially the same, and this correction calculation can be applied to several hundred or more RDL signal wirings. An RDL inductance value 82 indicating the inductance value of all corrected RDL signals is output to and stored in the storage unit 130.

  FIG. 15 is a diagram for explaining processing by the result output unit. In FIG. 15, the result output unit 90 reads out the RC value 73 included in the electrical characteristic 71 extracted by the second extraction unit 70 and the RDL inductance value 82 extracted by the correction calculation unit 80 from the storage unit 130 (step S <b> 15). S91). The RC value 73 indicates the resistance value (R) of the RDL signal line and the capacitance (C) between the RDL signals.

  Then, the result output unit 90 generates an equivalent circuit model 92 of all RDL signals that can be read by the circuit simulator (step S92). The generated equivalent circuit model 92 is stored in the storage unit 130.

  The result output unit 90 displays the equivalent circuit model 92 stored in the storage unit 130 as the electrical characteristic extraction result on the display device 15 or outputs it to the output device 16 (step S93).

  FIG. 16 is a diagram illustrating an example of an equivalent circuit model. In FIG. 16, an equivalent circuit model 92 for all RDL signals is an equivalent circuit model that can be handled by a circuit simulator such as SPICE (Simulation Program with Integrated Circuit Emphasis).

  16 shows a configuration example of RDL signal lines RDL1, RDL2, RDL3,... The inductance, capacitance, and resistance of the signal line RDL1 are indicated by L11, C11, and R11, respectively, and the inductance, capacitance, and resistance of the signal line RDL2 are indicated by L22, C22, and R22, respectively, and the signal line The inductance, capacitance, and resistance of RDL3 are indicated by L33, C33, and R33, respectively.

  The capacitance between RDL signals is indicated by C12, C13, and C23, and the mutual inductance is indicated by L12, L13, and L23. Thus, it is possible to consider the mutual inductance between RDL signals even with a single layer RDL.

  In the following, when the inductance value of a single layer RDL is extracted using a three-dimensional electromagnetic field solver (three-dimensional electromagnetic field analysis program) in the related technology (hereinafter simply referred to as related technology), FIG. 17 shows a comparison result of waveform analysis by SPICE using an equivalent circuit model.

  FIG. 17 is a diagram showing a comparison result of waveform analysis. In the inductance distribution diagram shown in FIG. 17A, the self-inductance 9a almost completely matches, and the mutual inductance 9b almost completely matches up to five adjacent ones.

  The inventor conducted waveform analysis using the RLC equivalent circuit model extracted in the present embodiment and related technology. The comparison result is shown in FIG. FIG. 17B shows a signal waveform when 42 signals are simultaneously operated at the analysis frequency “200 MHz”. As shown in FIG. 17B, the waveform shapes of the present example and the related technology are almost completely the same, indicating that the present example has no problem in accuracy compared to the related technology. ing.

  FIG. 18 is a diagram illustrating a comparison result of processing capabilities. Assuming the connection between the logic chip and the wideband memory, the processing capability of the related technology and the electrical characteristic extraction apparatus 100 in this embodiment were compared with a model in which 828 single-layer RDL signals were connected by bus.

  As shown in FIG. 18, in the analysis based on the large-scale electromagnetic field simulation, an attempt was made to extract the electrical characteristics of the entire 828 signals by the related technique, but the analysis was NG due to a lack of memory in the computer device. On the other hand, with the program that implements the electrical characteristic extraction unit 120 in the present embodiment, it was possible to execute the entire output of 828 RLC equivalent circuit models in about one hour.

  As for the analysis time, when 42 signals were modeled and the time taken to extract the electrical characteristics was compared, it took 24 hours 56 minutes 29 seconds in the related technique, whereas in this example, 18 minutes 20 minutes. Second. The program according to the present embodiment can be analyzed about 100 times faster than the related art.

  From the above, in the electrical characteristic extraction method according to the present embodiment or the electrical characteristic extraction apparatus in which the program is mounted, the analysis is NG in the related technology, and the level of several hundreds wired in a single layer on the silicon interposer. With respect to RDL (single layer RDL), it is possible to extract electrical characteristics at high speed without reducing accuracy.

  Also, by making it possible to extract the electrical characteristics of the entire single-layer RDL signal, it is not necessary to manually cut out the model, and an RLC equivalent circuit model that includes all interconnections that can be analyzed by a circuit simulator such as SPICE is output. be able to.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The following additional notes are further disclosed with respect to the embodiment including the above examples.
(Appendix 1)
An electrical property extraction method executed by a computer,
Read simulation data related to a semiconductor package in which multiple chips are arranged in a single layer on a silicon interposer with a virtual ground plane inserted, stored in the storage unit,
Extracting the first inductance value of the virtual ground plane and storing it in the storage unit;
Extracting the signal line connecting the plurality of chips and the second inductance value of the virtual ground plane and storing them in the storage unit;
Reading the first inductance value and the second inductance value from the storage unit, correcting the second inductance value by subtracting the first inductance value from the second inductance value, An electrical characteristic extraction method comprising obtaining an inductance value of a signal line between the plurality of chips.
(Appendix 2)
Read the simulation data of the signal line stored in the storage unit,
Using the distance and height at which the inductance of the signal line is not affected by the virtual ground plane, the virtual ground plane is inserted into the simulation data, and a via is formed between the signal line and the virtual ground plane. The electrical characteristic extraction method according to supplementary note 1, wherein the simulation data into which the virtual ground plane is inserted is created by insertion and stored in the storage unit.
(Appendix 3)
The electrical characteristic extraction method according to appendix 2, wherein the mutual inductance between the signal line and the virtual ground plane is substantially zero due to the height.
(Appendix 4)
The electrical characteristic extraction method according to any one of appendices 1 to 3, wherein the first inductance value of the virtual ground plane is extracted by executing a three-dimensional electromagnetic field analysis program.
(Appendix 5)
The signal lines connecting the plurality of chips and the second inductance value of the virtual ground plane are extracted by executing a 2.5-dimensional electromagnetic field analysis program. The electrical property extraction method described.
(Appendix 6)
A storage unit that stores simulation data related to a semiconductor package in which a plurality of chips are arranged in a single layer on a silicon interposer in which a virtual ground plane is inserted, which is stored in the storage unit;
A first extraction unit that extracts a first inductance value of the virtual ground plane and stores the first inductance value in the storage unit;
A second extraction unit for extracting a signal line connecting the plurality of chips and a second inductance value of the virtual ground plane and storing the second inductance value in the storage unit;
Reading the first inductance value and the second inductance value from the storage unit, correcting the second inductance value by subtracting the first inductance value from the second inductance value, An electrical characteristic extraction apparatus comprising: a correction calculation unit that acquires an inductance value of a signal line between the plurality of chips.
(Appendix 7)
Read simulation data related to a semiconductor package in which multiple chips are arranged in a single layer on a silicon interposer with a virtual ground plane inserted, stored in the storage unit,
Extracting the first inductance value of the virtual ground plane and storing it in the storage unit;
Extracting the signal line connecting the plurality of chips and the second inductance value of the virtual ground plane and storing them in the storage unit;
Reading the first inductance value and the second inductance value from the storage unit, correcting the second inductance value by subtracting the first inductance value from the second inductance value, An electrical characteristic extraction program for acquiring an inductance value of a signal line between the plurality of chips.

11 CPU
12 Main storage device 13 Auxiliary storage device 14 Input device 15 Display device 16 Output device 17 Communication I / F
18 drive 19 storage medium 20 input unit 30 virtual ground plane setting unit 40 height setting unit 50 virtual ground plane insertion unit 60 first extraction unit (virtual ground plane)
70 Second extraction unit (RDL + virtual ground plane)
80 Correction calculator (RDL inductance)
90 result output unit 100 electrical characteristic extraction device

Claims (5)

An electrical property extraction method executed by a computer,
Read simulation data related to a semiconductor package in which multiple chips are arranged in a single layer on a silicon interposer with a virtual ground plane inserted, stored in the storage unit,
Extracting the inductance value of the virtual ground plane and storing it in the storage unit,
Extracting the inductance value of the virtual ground plane and the signal line connecting the plurality of chips, and storing it in the storage unit,
Electrical characteristic extraction, wherein the second inductance value is corrected by subtracting the first inductance value from the second inductance value to obtain an inductance value of a signal line between the plurality of chips. Method. Read the simulation data of the signal line stored in the storage unit,
Using the distance and height at which the inductance of the signal line is not affected by the virtual ground plane, the virtual ground plane is inserted into the simulation data, and a via is formed between the signal line and the virtual ground plane. The electrical property extraction method according to claim 1, wherein the simulation data into which the virtual ground plane is inserted is created by insertion and stored in the storage unit.   3. The electrical characteristic extraction method according to claim 1, wherein the inductance value of the virtual ground plane is extracted by executing a three-dimensional electromagnetic field analysis program.   4. The signal line connecting the plurality of chips and the inductance value of the virtual ground plane are extracted by executing a 2.5-dimensional electromagnetic field analysis program. 5. Electrical property extraction method. A storage unit for storing simulation data to a semiconductor package in which a plurality of chips on a silicon interposer to the virtual ground plane is inserted in a single layer,
A first extraction unit that extracts an inductance value of the virtual ground plane from the simulation data and stores the inductance value in the storage unit;
A second extraction unit that extracts a signal line connecting the plurality of chips and an inductance value of the virtual ground plane from the simulation data and stores the inductance value in the storage unit;
A correction calculation unit that corrects the second inductance value by subtracting the first inductance value from the second inductance value and obtains an inductance value of a signal line between the plurality of chips. A characteristic electrical property extraction device.