WO2015199638A1 - Method of depositing a layer, method of manufacturing a transistor, layer stack for an electronic device, and an electronic device - Google Patents

Method of depositing a layer, method of manufacturing a transistor, layer stack for an electronic device, and an electronic device Download PDF

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Publication number
WO2015199638A1
WO2015199638A1 PCT/US2014/043587 US2014043587W WO2015199638A1 WO 2015199638 A1 WO2015199638 A1 WO 2015199638A1 US 2014043587 W US2014043587 W US 2014043587W WO 2015199638 A1 WO2015199638 A1 WO 2015199638A1
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WIPO (PCT)
Prior art keywords
layer
deposition
substrate
depositing
columnar growth
Prior art date
Application number
PCT/US2014/043587
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French (fr)
Inventor
Dharam GOSAIN
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to CN201480079468.2A priority Critical patent/CN106415790B/en
Priority to PCT/US2014/043587 priority patent/WO2015199638A1/en
Priority to KR1020177001886A priority patent/KR102140210B1/en
Priority to JP2016574886A priority patent/JP6526071B6/en
Priority to TW104119743A priority patent/TWI655677B/en
Publication of WO2015199638A1 publication Critical patent/WO2015199638A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/225—Oblique incidence of vaporised material on substrate
    • C23C14/226—Oblique incidence of vaporised material on substrate in order to form films with columnar structure
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24—Vacuum evaporation
    • C23C14/26—Vacuum evaporation by resistance or inductive heating of the source
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C23C14/352—Sputtering by application of a magnetic field, e.g. magnetron sputtering using more than one target
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/56—Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
    • C23C14/568—Transferring the substrates through a series of coating stations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
    • H01J37/3402—Gas-filled discharge tubes operating with cathodic sputtering using supplementary magnetic fields
    • H01J37/3405—Magnetron sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • Embodiments relate to deposition of a layer with columnar growth, devices manufactured with columnar growth and apparatus for depositing a layer with columnar growth. Particularly, the embodiments relate to methods of depositing a layer of a material over a substrate, methods of manufacturing a transistor on a substrate, layer stacks for an electronic device, and electronic devices.
  • a substrate e.g. on a glass substrate
  • the substrates are coated in different chambers of a coating apparatus.
  • the substrates are coated in a vacuum using a vapor deposition technique.
  • vapor deposition technique Several methods are known for depositing a material on a substrate.
  • substrates may be coated by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or a plasma enhanced chemical vapor deposition (PECVD) process, etc.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the process is performed in a process apparatus or process chamber where the substrate to be coated is located.
  • LTPS-TFT which can be used e.g. for LCD or AMOLED displays.
  • the gate electrode can be used as a mask for doping of the contact area of the active layer to the source and the drain of the transistor.
  • the quality of this self-aligned doping can determine the yield of the manufacturing process. Accordingly, it is a desire to improve this process.
  • other self-aligned doping applications i.e. other than manufacturing of a LTPS- TFT, can benefit from an improved process.
  • a method of depositing a layer of a material over a substrate includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
  • a method of manufacturing a transistor on a substrate includes depositing an active channel layer over the substrate, and depositing a layer of a material over a substrate, wherein the layer of the material provides a gate of the transistor over the active channel layer.
  • the deposition of a layer of a material over a substrate includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
  • the method of manufacturing a transistor on a substrate further includes conducting an ion implantation, wherein the gate is used as a mask.
  • a layer stack for an electronic device includes a layer of a material deposited over a substrate, which is manufactured by a method of depositing a layer of a material over a substrate.
  • the method includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
  • an electronic device includes a layer stack.
  • the layer stack includes a layer of a material deposited over a substrate, which is manufactured by a method of depositing a layer of a material over a substrate.
  • the method includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
  • FIGS. 1A to IE show schematic views of a portion of the substrate, wherein layer stack according to embodiments is deposited on the substrate;
  • FIG. 2 shows a flowchart illustrating a method of depositing a layer of material over substrate according to embodiments described herein and corresponding to FIGS. 1A to IE;
  • FIG. 3 A shows a schematic view of an apparatus for depositing a layer of the material in a first processing condition according to embodiments described herein;
  • FIG. 3B shows a schematic view of an apparatus for depositing a layer of the material in a second processing condition according to embodiments described herein;
  • FIGS. 4 A and 4B illustrate the first and the second processing condition according to embodiments described herein;
  • FIGS. 5 A and 5B show a schematic result of the layer deposited, wherein FIG. 5 A shows the first portion of the layer and FIG. 5B shows the first and the second portion of layer according to embodiments described herein;
  • FIG. 6 shows an image of an electron microscope of the layer of material over the substrate according to embodiments described herein.
  • FIG. 7 shows a flowchart illustrating a method of depositing a layer of material over substrate according to embodiments described herein.
  • a layer stack is provided, wherein a portion of the layer stack is utilized for self-aligned doping and particularly wherein the portion of the layer stack, i.e. the portion acting as a mask during ion implantation for the self-align doping process, is deposited to reduce channeling of ions through the portion of the layer stack.
  • FIG. 1A shows a layer stack 150 after a first deposition process 202 (see FIG. 2).
  • An active channel layer 152 is deposited over the substrate 151.
  • the active channel layer 152 includes the active channel 152a, a source region 152s, and a drain region 152d.
  • the active channel layer 152 can be a polysilicon layer.
  • the polysilicon layer can be manufactured by deposition of silicon, for example from a sputtering cathode, and crystallization of the deposited silicon layer.
  • the crystallization process can be conducted by laser processing, by a catalytic process, or by another process.
  • excimer laser annealing can be used.
  • enhanced metal-induced lateral crystallization MILC
  • PRTA pulsed rapid thermal annealing
  • CGS continuous grain silicon
  • CW continuous wave
  • SLS sequential lateral solidification
  • the techniques for manufacturing TFT on the glass substrate include the amorphous silicon (a-Si) process and the low temp polysilicon (LTPS) process.
  • the major differences between the a-Si process and the LTPS process are the electrical characteristics of the devices and the complexity of the processes.
  • the LTPS TFT possesses higher mobility but the process for fabricating the LTPS TFT is more complicated.
  • the a-Si TFT possesses lower mobility, the process for fabricating the a-Si TFT is simple. According to embodiments described herein, the LTPS TFT process can be improved.
  • the LTPS TFT process is one example for which embodiments described herein can be beneficially utilized.
  • a gate insulator layer 153 is provided over the active channel layer 152 (see box 204 in FIG. 2).
  • some of the layers described herein, such as the active channel layer 152, the layer of the material forming the gate, and other layers are structured during the LTPS TFT process.
  • the structuring for example due to etching, can be conducted according to any of the methods known to a person skilled in the art and are not described within the present disclosure. It will be apparent for a person skilled in the art whether or not a structuring process is utilized between subsequent deposition processes described herein.
  • FIG. 1C shows a first portion 162 of the layer.
  • the first portion 162 is deposited (see box 206 in FIG. 2) with a first deposition direction of the material to be deposited on the substrate and with columnar growth.
  • the first deposition direction results in a first columnar growth direction.
  • FIG. ID shows a second portion 164 of the layer.
  • the second portion 164 is deposited (see box 208 in FIG. 2) with a second deposition direction of the material to be deposited on the substrate and with columnar growth.
  • the second deposition direction results in a second columnar growth direction.
  • a deposition direction can be referred to as a main deposition direction or an average deposition direction.
  • the deposition distribution typically has a main or average direction of the materials, even though the deposition distribution may have some directional spread.
  • a layer of material is deposited over the substrate, i.e. a layer with physical characteristics of a single layer, wherein the layer of material includes a first columnar growth direction and a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
  • the process parameters for the columnar growth can be as follows.
  • the exemplary process parameters refer to deposition of molybdenum and the position of other materials may have other process parameters for columnar growth of such other materials.
  • Columnar growth as referred to herein is understood as a morphology with columnar grains, wherein the grains have a significantly longer length in one direction, i.e. along the columns, which is referred to as the columnar growth direction.
  • a columnar growth can be provided for a film thickness of 40 nm to 500 nm, or above, particularly 100 nm to 400 nm.
  • further process parameters can be selected from the group of: a deposition pressure of 0.1 to 1 Pa, particularly 0.2 to 0.5 Pa, a deposition power, which may depend on the system geometry of 10 kW to 60 kW per cathode, mores specifically, 20 kW to 40 kW per cathode.
  • an ion implantation process is conducted.
  • the ion implantation is also illustrated by arrows 90 in FIG. IE.
  • the ion implantation process provides doping for the source region 152s and the drain region 152d.
  • the gate electrode of the transistor is used as a mask during the ion implantation process. Accordingly, a self- aligned doping process is conducted.
  • the likelihood of ions to channel through the mask, i.e. the gate electrode is significantly reduced. The reduction of channeling of ions through the gate electrode reduces undesired doping of the active channel region.
  • FIG. 3A shows a schematic cross-sectional view of a deposition apparatus 100 according to embodiments as described herein.
  • a deposition apparatus 100 e.g. the gate-forming layer over a substrate.
  • FIG. 3A shows a schematic cross-sectional view of a deposition apparatus 100 according to embodiments as described herein.
  • one vacuum chamber 102 for deposition of layers therein is shown.
  • further chambers 102 can be provided adjacent to the chamber 102.
  • the vacuum chamber 102 can be separated from adjacent chambers by a valve having a valve housing 104 and a valve unit 105.
  • the valve unit 105 can be closed. Accordingly, the atmosphere in the vacuum chambers 102 and 103 can be individually controlled by generating a technical vacuum, for example, with vacuum pumps connected to the chamber 102 and 103, and/or by inserting processing gases in the deposition region in the chamber 102. As described above, for many large area processing applications, the large area substrates are supported by a carrier. However, embodiments described herein are not limited thereto and other transportation elements for transporting a substrate through a processing apparatus or processing system may be used.
  • a transport system is provided in order to transport the carrier 114, having the substrate 14 thereon, into and out of the chamber 102.
  • substrate as used herein shall embrace substrates such as a glass substrate, a wafer, slices of transparent crystal such as sapphire or the like, or a glass plate.
  • deposition sources e.g. cathodes 122
  • the deposition sources can, for example, be rotatable cathodes having targets of the material to be deposited on the substrate.
  • the cathodes can be rotatable cathodes with a magnet assembly 121 therein. Magnetron sputtering can be conducted for deposition of the layers.
  • each pair of neighboring cathodes can be connected to a power supply 123a-c.
  • each pair of neighboring cathodes can be connected to an AC power supply or each cathode can be connected to a DC power supply.
  • a DC power supply is shown in FIG. 3 A, wherein anodes 116 are further connected to the power supply.
  • the cathodes 122 are connected to an AC power supply such that the cathodes can be biased in an alternating manner.
  • AC power supplies such as MF power supplies can, for example, be provided for depositing layers of A1203.
  • the cathodes can operate without additional anodes, which can e.g. be removed, as a complete circuit including cathode and anode is provided by a pair of cathodes 122.
  • a first outer deposition assembly 301 may be connected to a first group of gas tanks 141 for providing a first composition of reactive gases
  • the second outer deposition assembly 302 may be connected to a second group of gas tanks 142 for providing a second composition of reactive gases
  • the inner deposition assembly 303 may be connected to a third group 143 of gas tanks for providing a third composition of reactive gases to the inner deposition assembly.
  • all deposition assemblies may also be connected to the same group of gas tanks for providing the processing gas.
  • the controller 500 is configured for controlling one or more of the power supplies commonly or individually.
  • the controller 500 is configured for controlling a first power supply for supplying a first power to the first outer deposition assembly and the second outer deposition assembly.
  • the controller can also be configured for controlling a second power supply 123b for supplying a second power to the inner deposition assembly.
  • the first power supply for supplying a first power to the first outer deposition assembly and the second outer deposition assembly can include two separate power supplies 123 a, 123 c for supplying the first power to the first outer deposition assembly and the second outer deposition assembly.
  • deposition sources e.g. cathodes 122
  • the deposition sources can, for example, be rotatable cathodes having targets of the material to be deposited on the substrate.
  • the cathodes can be rotatable cathodes with a magnet assembly 121 therein.
  • magnetron sputtering can be conducted for the deposition of material on a substrate.
  • the deposition process can be conducted with rotary cathodes and a rotatable magnet assembly, i.e. a rotatable magnet yoke therein.
  • magnet sputtering refers to sputtering performed using a magnetron, i.e. a magnet assembly, that is, a unit capable of generating a magnetic field.
  • a magnet assembly consists of one or more permanent magnets.
  • permanent magnets are typically arranged within a rotatable target or coupled to a planar target in a manner such that the free electrons are trapped within the generated magnetic field generated below the rotatable target surface.
  • Such a magnet assembly may also be arranged coupled to a planar cathode.
  • magnetron sputtering can be realized by a double magnetron cathode, i.e.
  • cathodes 122 such as, but not limited to, a TwinMagTM cathode assembly.
  • target assemblies including double cathodes can be applied.
  • the cathodes in a deposition chamber may be interchangeable. Accordingly, the targets are changed after the material to be sputtered has been consumed.
  • sputtering can be conducted as DC sputtering, MF (middle frequency) sputtering, as RF sputtering, or as pulse sputtering.
  • MF middle frequency
  • RF RF
  • pulse sputtering some deposition processes might beneficially apply MF, DC or pulsed sputtering.
  • other sputtering methods can also be applied.
  • FIGS. 3A and 3B a plurality of cathodes 122 with a magnet assembly 121 or magnetron provided in the cathodes are shown.
  • the sputtering according to the described embodiments can be conducted with three or more cathodes.
  • an array of cathodes or cathode pairs can be provided.
  • three or more cathodes or cathode pairs e.g. three, four, five, six or even more cathodes or cathode pairs can be provided.
  • the array can be provided in one vacuum chamber.
  • an array can typically be defined such that adjacent cathodes or cathode pairs influence each other, e.g. by having interacting plasma confinement.
  • the magnet assemblies are rotated such that a deposition direction is provided, which is indicated by arrows 300 A.
  • a first deposition direction is provided, which results in a first columnar growth direction.
  • the magnet assemblies are rotated such that a deposition direction is provided, which is indicated by arrows 300B.
  • a second deposition direction is provided, which results in a second columnar growth direction.
  • Embodiments described herein which relate to manufacturing of the transistor on a substrate, particularly a LPS-TFT, wherein the gate electrode is used as a mask for self- aligned doping can for example utilize a DC sputtering process for depositing molybdenum (Mo), molybdenum-tungsten (MoW), titanium (Ti), aluminum (Al), copper (Cu) and alloys containing one or more of the above elements.
  • the deposited layer is provided with columnar growth.
  • sputtering can be conducted as DC (direct current) sputtering, MF (middle frequency) sputtering, RF sputtering, or as pulse sputtering.
  • DC direct current
  • MF middle frequency
  • RF RF
  • pulse sputtering some deposition processes might beneficially apply MF, DC or pulsed sputtering.
  • middle frequency is a frequency in the range of 0.5 kHz to 350 kHz, for example, 10 kHz to 50 kHz.
  • the sputtering according to the described embodiments can be conducted with three or more cathodes.
  • an array of cathodes having 6 or more cathodes, e.g. 10 or more cathodes, can be provided.
  • the array can be provided in one vacuum chamber.
  • an array can typically be defined such that adjacent cathodes or cathode pairs influence each other, e.g. by having interacting plasma confinement.
  • the sputtering can be conducted by a rotary cathode array, such as, but not limited to, a system such as PiVot of Applied Materials Inc..
  • the embodiments described herein can be utilized for Display PVD, i.e. sputter deposition on large area substrates for the display market.
  • a flat panel display or mobile phone displays can be manufactured on large area substrates.
  • large area substrates or respective carriers, wherein the carriers have a plurality of substrates may have a size of at least 0.67 m 2 .
  • the size can be about 0.67m 2 (0.73x0.92m - Gen 4.5) to about 8 m 2 , more typically about 2 m 2 to about 9 m 2 or even up to 12 m 2 .
  • a large area substrate or a respective carrier can have a size of 1.4 m 2 or above.
  • the substrates or carriers, for which the structures, apparatuses, such as cathode assemblies, and methods according to embodiments described herein are provided are large area substrates as described herein.
  • a large area substrate or carrier can be GEN 4.5, which corresponds to about 0.67 m 2 substrates (0.73x0.92m), GEN 5, which corresponds to about 1.4 m 2 substrates (1.1 m x 1.3 m), GEN 7.5, which corresponds to about 4.29 m 2 substrates (1.95 m x 2.2 m), GEN 8.5, which corresponds to about 5.7m 2 substrates (2.2 m x 2.5 m), or even GEN 10, which corresponds to about 8.7 m 2 substrates (2.85 m x 3.05 m). Even larger generations such as GEN 11 and GEN 12 and corresponding substrate areas can similarly be implemented.
  • the target material can be selected from the group consisting of: aluminum, silicon, tantalum, molybdenum, niobium, titanium, indium, gallium, zinc, tin, silver and copper. Particularly, the target material can be selected from the group consisting of indium, gallium and zinc.
  • the reactive sputter processes provide typically deposited oxides of these target materials. However, nitrides or oxi-nitrides might be deposited as well.
  • the methods provide a sputter deposition for a positioning of the substrate for a static deposition process.
  • large area substrate processing such as processing of vertically oriented large area substrates
  • it can be distinguished between static deposition and dynamic deposition.
  • the substrates and/or the carriers described herein and the apparatuses for utilizing the gas distribution systems described herein can be configured for vertical substrate processing.
  • the term vertical substrate processing is understood to distinguish over horizontal substrate processing. That is, vertical substrate processing relates to an essentially vertical orientation of the carrier and the substrate during substrate processing, wherein a deviation of a few degrees, e.g.
  • a vertical substrate orientation with a small inclination can, for example, result in a more stable substrate handling or a reduced risk of particles contaminating a deposited layer.
  • a horizontal substrate orientation may be possible.
  • the cathode array would, for example, also be essentially horizontal.
  • a vertical substrate orientation e.g. within -15° to +15° from the vertical orientation, reduces the floor space for large area substrate processing and, thus, the cost of ownership (CoO).
  • a static deposition process can be understood as a deposition process with a static position, a deposition process with an essentially static position, or a deposition process with a partially static position of the substrate.
  • a static deposition process, as described herein, can be clearly distinguished from a dynamic deposition process without the necessity that the substrate position for the static deposition process is fully without any movement during deposition.
  • a deviation from a fully static substrate position e.g.
  • oscillating, wobbling or any other movement of substrates as described above can additionally or alternatively be provided by a movement of the cathodes or the cathode array, e.g. wobbling, oscillating or the like.
  • the substrate and the cathodes (or the cathode array) can move relative to each other, e.g. in the substrate transport direction, in a lateral direction essentially perpendicular to the substrate transport direction or both.
  • the manufacturing of a layer having a first portion with a first columnar growth direction and a second portion with a second, different columnar growth direction can also be conducted in a dynamic deposition system, wherein the substrate is moved by two or more sources.
  • the transportation speed of the substrate may be taken into consideration when determining the deposition directions for the manufacturing processes.
  • a directional growth e.g. a columnar growth
  • Angular sputtering as described in more detail with respect to FIGS. 4A, 4B, 5A and 5B can reduce one-directional columnar growth, particularly a vertical columnar growth, wherein ions might tunnel through or channel through a mask having a vertical columnar growth.
  • FIG. 4A shows the cathode 122 having a magnet assembly 121 provided in the cathode, for example within a backing tube supporting the target material.
  • the magnet assembly 121 can be rotated to deviate from the vertical deposition direction, i.e. to have a first angular coordinate.
  • the vertical direction i.e. the direction perpendicular to the surface of the substrate 451, is shown by line 471.
  • the angle 470 can be 10° or above, for example 20° to 60°, such as about 25° to 40°, for example about 30°.
  • FIG. 4A illustrates confined plasma tubes 407 and the deposition direction (see arrow 300 A) resulting from the angular position of the magnet assembly 121 relative to line 471 or the substrate 451, respectively.
  • a first portion 462 of the layer is grown on the substrate 451 , wherein the columnar growth direction is tilted with respect to the direction vertical to the substrate surface.
  • the substrate 451 shown in FIGS. 4A to 5B can be a substrate as described above but may also be the substrate having one or more layers provided thereon.
  • FIGS. 4A to 5B schematically shows only that layer having the first portion 462 and the second portion 464 with the first columnar growth direction and a second, different columnar growth direction.
  • the magnet assembly 121 After deposition of the first portion 462 of the layer, the magnet assembly 121 is rotated to the second position shown exemplary in FIG. 4B, i.e. to a second angular coordinate. A second deposition direction indicated by arrow 300B is provided by the second position of the magnet assembly 121. As a result, as shown in FIG. 5B, a second portion 464 of the layer is grown on the first portion 462 of the layer. The second portion 464 has a columnar growth with a second columnar growth direction, which is different from the first columnar growth direction. According to embodiments described herein, the grain boundaries of the grown columns can be decoupled by changing the magnet position between a first and a second deposition process.
  • the cathode can be switched off after depositing in the first deposition direction, the magnet assembly 121 can be rotated while the cathode is in is switched off state, and the cathode is switched on after the magnet assembly 121 is provided in the second position, i.e. the position for the second deposition direction.
  • the magnet assembly 121 can be provided at an essentially constant position and/or can be positioned to provide an essentially constant deposition direction during depositing the first portion 462 of the layer and/or the second portion 464 of the layer.
  • switching between the first position of the magnet assembly and the second position of the magnet assembly or vice versa is provided one or more times, for example 1 to 4 times. Accordingly, the zig-zag profile can be provided for the columnar grown claims.
  • the thickness of the first portion of the layer and/or the thickness of the second portion of the layer can be 40 nm or above, particularly 100 nm or above.
  • the thickness of the layer, i.e. including at least the first portion and the second portion can be 200 nm or above, particularly 300 nm or above. Accordingly, the thickness of one or more portions of the layer is sufficiently large such that ions cannot channel through the layer.
  • the layer of the material includes a plurality of first grain boundaries in the first portion of the layer and a plurality of second grain boundaries in the second portion and wherein the plurality of second grain boundaries have a different orientation as compared to the plurality of first grain boundaries.
  • the layer can be a metallic layer, particularly the layer can be a MoW layer, a Mo layer, a Ti layer, a Al layer, a Cu layer, a layer comprising two or more of MoW, Mo, Ti, Al, Cu, or a layer comprising an alloy of one or more of MoW, Mo, Ti, Al, Cu.
  • FIG. 6 shows an electron microscope image, wherein the layer having a first portion with a first columnar growth direction and a second portion with the second columnar growth direction, i.e. grain boundaries having a first and a second orientation, is shown.
  • the white lines illustrate the orientation of the columnar growth direction and/or the grain boundaries.
  • the dashed arrow shows an impact direction of ions, which can be utilized during ion implantation. It can be seen that ions have an improved likelihood to be blocked by the layer, which can be a mask during the ion implantation process, based upon the inclination of the grain boundary direction and the direction of the ions.
  • FIG. 7 shows a method of depositing a layer of a material over a substrate, wherein the first portion of the layer is deposited with the first deposition direction and resulting in the first columnar growth direction (see 701) and a second portion of the layer is deposited with a second deposition direction resulting in a second columnar growth direction (see 702), wherein the second columnar growth direction is different from the first columnar growth direction, for example the angle between the first columnar growth direction and the second columnar growth direction is 30° or above, for example about 60°.

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Abstract

A method of depositing a layer of a material over a substrate is described. The method includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.

Description

METHOD OF DEPOSITING A LAYER, METHOD OF MANUFACTURING A TRANSISTOR, LAYER STACK FOR AN ELECTRONIC DEVICE, AND AN
ELECTRONIC DEVICE
TECHNICAL FIELD
[0001] Embodiments relate to deposition of a layer with columnar growth, devices manufactured with columnar growth and apparatus for depositing a layer with columnar growth. Particularly, the embodiments relate to methods of depositing a layer of a material over a substrate, methods of manufacturing a transistor on a substrate, layer stacks for an electronic device, and electronic devices.
BACKGROUND
[0002] In many applications, deposition of thin layers on a substrate, e.g. on a glass substrate is desired. Conventionally, the substrates are coated in different chambers of a coating apparatus. For some applications, the substrates are coated in a vacuum using a vapor deposition technique. Several methods are known for depositing a material on a substrate. For instance, substrates may be coated by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or a plasma enhanced chemical vapor deposition (PECVD) process, etc. Usually, the process is performed in a process apparatus or process chamber where the substrate to be coated is located.
[0003] Over the last few years, electronic devices and particularly opto-electronic devices have reduced significantly in price. Further, the pixel density in displays is continuously increased. For TFT displays, a high density TFT integration is desired. However, the yield is attempted to be increased and the manufacturing costs are attempted to be reduced in spite of the increased number of thin-film transistors (TFT) within a device.
[0004] One aspect to increase the pixel density is the utilization of LTPS-TFT, which can be used e.g. for LCD or AMOLED displays. During manufacturing of a LTPS-TFT, the gate electrode can be used as a mask for doping of the contact area of the active layer to the source and the drain of the transistor. The quality of this self-aligned doping can determine the yield of the manufacturing process. Accordingly, it is a desire to improve this process. Yet, also other self-aligned doping applications, i.e. other than manufacturing of a LTPS- TFT, can benefit from an improved process.
SUMMARY
[0005] In light of the above, a method of depositing a layer of a material over a substrate, a method of manufacturing a transistor on a substrate, a layer stack for an electronic device, and an electronic device are provided.
[0006] According to one embodiment, a method of depositing a layer of a material over a substrate is provided. The method includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
[0007] According to another embodiment, a method of manufacturing a transistor on a substrate is provided. The method includes depositing an active channel layer over the substrate, and depositing a layer of a material over a substrate, wherein the layer of the material provides a gate of the transistor over the active channel layer. The deposition of a layer of a material over a substrate includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction. The method of manufacturing a transistor on a substrate further includes conducting an ion implantation, wherein the gate is used as a mask.
[0008] According to yet another embodiment, a layer stack for an electronic device is provided. The layer stack includes a layer of a material deposited over a substrate, which is manufactured by a method of depositing a layer of a material over a substrate. The method includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
[0009] According to yet another embodiment, an electronic device is provided. The electronic device includes a layer stack. The layer stack includes a layer of a material deposited over a substrate, which is manufactured by a method of depositing a layer of a material over a substrate. The method includes depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
[0010] Further advantages, features, aspects and details are evident from the dependent claims, the description and the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments. The accompanying drawings relate to embodiments of the invention and are described in the following:
[0012] FIGS. 1A to IE show schematic views of a portion of the substrate, wherein layer stack according to embodiments is deposited on the substrate;
[0013] FIG. 2 shows a flowchart illustrating a method of depositing a layer of material over substrate according to embodiments described herein and corresponding to FIGS. 1A to IE; [0014] FIG. 3 A shows a schematic view of an apparatus for depositing a layer of the material in a first processing condition according to embodiments described herein;
[0015] FIG. 3B shows a schematic view of an apparatus for depositing a layer of the material in a second processing condition according to embodiments described herein;
[0016] FIGS. 4 A and 4B illustrate the first and the second processing condition according to embodiments described herein;
[0017] FIGS. 5 A and 5B show a schematic result of the layer deposited, wherein FIG. 5 A shows the first portion of the layer and FIG. 5B shows the first and the second portion of layer according to embodiments described herein;
[0018] FIG. 6 shows an image of an electron microscope of the layer of material over the substrate according to embodiments described herein; and
[0019] FIG. 7 shows a flowchart illustrating a method of depositing a layer of material over substrate according to embodiments described herein.
DETAILED DESCRIPTION OF EMBODIMENTS
[0020] Reference will now be made in detail to the various embodiments of the invention, one or more examples of which are illustrated in the figures. Within the following description of the drawings, the same reference numbers refer to same components. In the following, only the differences with respect to individual embodiments are described. Each example is provided by way of explanation of the invention and is not meant as a limitation of the invention. Further, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the description includes such modifications and variations.
[0021] According to embodiments described herein, a layer stack is provided, wherein a portion of the layer stack is utilized for self-aligned doping and particularly wherein the portion of the layer stack, i.e. the portion acting as a mask during ion implantation for the self-align doping process, is deposited to reduce channeling of ions through the portion of the layer stack.
[0022] FIG. 1A shows a layer stack 150 after a first deposition process 202 (see FIG. 2). An active channel layer 152 is deposited over the substrate 151. The active channel layer 152 includes the active channel 152a, a source region 152s, and a drain region 152d. According to typical embodiments the active channel layer 152 can be a polysilicon layer. The polysilicon layer can be manufactured by deposition of silicon, for example from a sputtering cathode, and crystallization of the deposited silicon layer. According to typical examples, the crystallization process can be conducted by laser processing, by a catalytic process, or by another process.
[0023] According to one example, excimer laser annealing (EL A) can be used. According to another example, enhanced metal-induced lateral crystallization (MILC) using a pulsed rapid thermal annealing (PRTA) technique can be used. Yet further techniques include a continuous grain silicon (CGS) method, continuous wave (CW) laser method and sequential lateral solidification (SLS). Typically, these processes include an annealing process wherein the energy impact is short enough to avoid damages to the substrate 151.
[0024] The techniques for manufacturing TFT on the glass substrate include the amorphous silicon (a-Si) process and the low temp polysilicon (LTPS) process. The major differences between the a-Si process and the LTPS process are the electrical characteristics of the devices and the complexity of the processes. The LTPS TFT possesses higher mobility but the process for fabricating the LTPS TFT is more complicated. Although the a-Si TFT possesses lower mobility, the process for fabricating the a-Si TFT is simple. According to embodiments described herein, the LTPS TFT process can be improved. The LTPS TFT process is one example for which embodiments described herein can be beneficially utilized.
[0025] In FIG. IB, a gate insulator layer 153 is provided over the active channel layer 152 (see box 204 in FIG. 2). As can be seen in FIGS. 1A to IE some of the layers described herein, such as the active channel layer 152, the layer of the material forming the gate, and other layers are structured during the LTPS TFT process. The structuring, for example due to etching, can be conducted according to any of the methods known to a person skilled in the art and are not described within the present disclosure. It will be apparent for a person skilled in the art whether or not a structuring process is utilized between subsequent deposition processes described herein.
[0026] FIG. 1C shows a first portion 162 of the layer. According to embodiments described herein, the first portion 162 is deposited (see box 206 in FIG. 2) with a first deposition direction of the material to be deposited on the substrate and with columnar growth. The first deposition direction results in a first columnar growth direction. FIG. ID shows a second portion 164 of the layer. According to embodiments described herein, the second portion 164 is deposited (see box 208 in FIG. 2) with a second deposition direction of the material to be deposited on the substrate and with columnar growth. The second deposition direction results in a second columnar growth direction. According to embodiments described herein, a deposition direction can be referred to as a main deposition direction or an average deposition direction. For example, the deposition distribution typically has a main or average direction of the materials, even though the deposition distribution may have some directional spread.
[0027] According to embodiments described herein, a layer of material is deposited over the substrate, i.e. a layer with physical characteristics of a single layer, wherein the layer of material includes a first columnar growth direction and a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction. According to embodiments described herein, the process parameters for the columnar growth can be as follows. The exemplary process parameters refer to deposition of molybdenum and the position of other materials may have other process parameters for columnar growth of such other materials.
[0028] Columnar growth as referred to herein is understood as a morphology with columnar grains, wherein the grains have a significantly longer length in one direction, i.e. along the columns, which is referred to as the columnar growth direction. According to some embodiments, a columnar growth can be provided for a film thickness of 40 nm to 500 nm, or above, particularly 100 nm to 400 nm. Yet further process parameters can be selected from the group of: a deposition pressure of 0.1 to 1 Pa, particularly 0.2 to 0.5 Pa, a deposition power, which may depend on the system geometry of 10 kW to 60 kW per cathode, mores specifically, 20 kW to 40 kW per cathode.
[0029] As shown in box 210 of FIG. 2, an ion implantation process is conducted. The ion implantation is also illustrated by arrows 90 in FIG. IE. The ion implantation process provides doping for the source region 152s and the drain region 152d. The gate electrode of the transistor is used as a mask during the ion implantation process. Accordingly, a self- aligned doping process is conducted. In light of the first columnar growth direction and the second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction, the likelihood of ions to channel through the mask, i.e. the gate electrode, is significantly reduced. The reduction of channeling of ions through the gate electrode reduces undesired doping of the active channel region.
[0030] According to embodiments, which can be combined with other embodiments described herein, an apparatus for depositing the layer, e.g. the gate-forming layer over a substrate can be provided as described with respect to FIGS. 3A and 3B. FIG. 3A shows a schematic cross-sectional view of a deposition apparatus 100 according to embodiments as described herein. Exemplarily, one vacuum chamber 102 for deposition of layers therein is shown. As indicated in FIG. 3 A, further chambers 102 can be provided adjacent to the chamber 102. The vacuum chamber 102 can be separated from adjacent chambers by a valve having a valve housing 104 and a valve unit 105. After the carrier 114 with the substrate 151 thereon is inserted in to the vacuum chamber 102, as indicated by arrow 1, the valve unit 105 can be closed. Accordingly, the atmosphere in the vacuum chambers 102 and 103 can be individually controlled by generating a technical vacuum, for example, with vacuum pumps connected to the chamber 102 and 103, and/or by inserting processing gases in the deposition region in the chamber 102. As described above, for many large area processing applications, the large area substrates are supported by a carrier. However, embodiments described herein are not limited thereto and other transportation elements for transporting a substrate through a processing apparatus or processing system may be used.
[0031] Within the chamber 102, a transport system is provided in order to transport the carrier 114, having the substrate 14 thereon, into and out of the chamber 102. The term "substrate" as used herein shall embrace substrates such as a glass substrate, a wafer, slices of transparent crystal such as sapphire or the like, or a glass plate.
[0032] As illustrated in FIG. 3 A, within the chamber 102, deposition sources, e.g. cathodes 122, are provided. The deposition sources can, for example, be rotatable cathodes having targets of the material to be deposited on the substrate. According to embodiments, which can be combined with other embodiments described herein, the cathodes can be rotatable cathodes with a magnet assembly 121 therein. Magnetron sputtering can be conducted for deposition of the layers. As exemplarily shown in FIG. 3A, each pair of neighboring cathodes can be connected to a power supply 123a-c. Depending on the nature of the deposition process within the target array either each pair of neighboring cathodes can be connected to an AC power supply or each cathode can be connected to a DC power supply. A DC power supply is shown in FIG. 3 A, wherein anodes 116 are further connected to the power supply. According to some embodiments, which can be combined with other embodiments described herein, the cathodes 122 are connected to an AC power supply such that the cathodes can be biased in an alternating manner. AC power supplies such as MF power supplies can, for example, be provided for depositing layers of A1203. In such a case, the cathodes can operate without additional anodes, which can e.g. be removed, as a complete circuit including cathode and anode is provided by a pair of cathodes 122.
[0033] As exemplary shown in FIG. 3 A, a first outer deposition assembly 301 may be connected to a first group of gas tanks 141 for providing a first composition of reactive gases, the second outer deposition assembly 302 may be connected to a second group of gas tanks 142 for providing a second composition of reactive gases, and the inner deposition assembly 303 may be connected to a third group 143 of gas tanks for providing a third composition of reactive gases to the inner deposition assembly. However, all deposition assemblies may also be connected to the same group of gas tanks for providing the processing gas.
[0034] According to embodiments, which can be combined with other embodiments described herein, the controller 500 is configured for controlling one or more of the power supplies commonly or individually. As one example, the controller 500 is configured for controlling a first power supply for supplying a first power to the first outer deposition assembly and the second outer deposition assembly. The controller can also be configured for controlling a second power supply 123b for supplying a second power to the inner deposition assembly. With reference to the exemplary embodiments of FIGS. 3 A and 3B, the first power supply for supplying a first power to the first outer deposition assembly and the second outer deposition assembly can include two separate power supplies 123 a, 123 c for supplying the first power to the first outer deposition assembly and the second outer deposition assembly.
[0035] As illustrated in FIGS. 3A and 3B, within the chamber 102, deposition sources, e.g. cathodes 122, are provided. The deposition sources can, for example, be rotatable cathodes having targets of the material to be deposited on the substrate. Typically, the cathodes can be rotatable cathodes with a magnet assembly 121 therein. Accordingly, magnetron sputtering can be conducted for the deposition of material on a substrate. As exemplarily shown in FIGS. 3A and 3B, the deposition process can be conducted with rotary cathodes and a rotatable magnet assembly, i.e. a rotatable magnet yoke therein.
[0036] As used herein, "magnetron sputtering" refers to sputtering performed using a magnetron, i.e. a magnet assembly, that is, a unit capable of generating a magnetic field. Typically, such a magnet assembly consists of one or more permanent magnets. These permanent magnets are typically arranged within a rotatable target or coupled to a planar target in a manner such that the free electrons are trapped within the generated magnetic field generated below the rotatable target surface. Such a magnet assembly may also be arranged coupled to a planar cathode. According to typical implementations, magnetron sputtering can be realized by a double magnetron cathode, i.e. cathodes 122, such as, but not limited to, a TwinMagTM cathode assembly. Particularly, for MF sputtering (middle frequency sputtering) from a target, target assemblies including double cathodes can be applied. According to typical embodiments, the cathodes in a deposition chamber may be interchangeable. Accordingly, the targets are changed after the material to be sputtered has been consumed.
[0037] According to different embodiments, which can be combined with other embodiments described herein, sputtering can be conducted as DC sputtering, MF (middle frequency) sputtering, as RF sputtering, or as pulse sputtering. As described herein, some deposition processes might beneficially apply MF, DC or pulsed sputtering. However, other sputtering methods can also be applied.
[0038] In FIGS. 3A and 3B a plurality of cathodes 122 with a magnet assembly 121 or magnetron provided in the cathodes are shown. According to some embodiments, which can be combined with other embodiments described herein, the sputtering according to the described embodiments can be conducted with three or more cathodes. However, particularly for applications for large area deposition, an array of cathodes or cathode pairs can be provided. For example, three or more cathodes or cathode pairs, e.g. three, four, five, six or even more cathodes or cathode pairs can be provided. The array can be provided in one vacuum chamber. Further, an array can typically be defined such that adjacent cathodes or cathode pairs influence each other, e.g. by having interacting plasma confinement.
[0039] As shown in FIG. 3A, the magnet assemblies are rotated such that a deposition direction is provided, which is indicated by arrows 300 A. A first deposition direction is provided, which results in a first columnar growth direction. As shown in FIG. 3B, the magnet assemblies are rotated such that a deposition direction is provided, which is indicated by arrows 300B. A second deposition direction is provided, which results in a second columnar growth direction.
[0040] Embodiments described herein, which relate to manufacturing of the transistor on a substrate, particularly a LPS-TFT, wherein the gate electrode is used as a mask for self- aligned doping can for example utilize a DC sputtering process for depositing molybdenum (Mo), molybdenum-tungsten (MoW), titanium (Ti), aluminum (Al), copper (Cu) and alloys containing one or more of the above elements. The deposited layer is provided with columnar growth. However, also other materials, which are for example sputtered with an MF sputtering process or an RF sputtering process, or which can be deposited with a CVD process can be utilized for a self-aligned masking, wherein a first columnar growth direction and a second, different columnar growth direction are provided for the layer forming the mask. Embodiments, for which a first columnar growth direction and a second, different columnar growth direction are provided by moving the magnet assembly of the magnetron sputter cathodes from a first position to a second position are beneficially used in light of the cost efficient control of growth direction. [0041] According to different embodiments, which can be combined with other embodiments described herein, sputtering can be conducted as DC (direct current) sputtering, MF (middle frequency) sputtering, RF sputtering, or as pulse sputtering. As described herein, some deposition processes might beneficially apply MF, DC or pulsed sputtering. However, other sputtering methods can also be applied. According to embodiments herein, middle frequency is a frequency in the range of 0.5 kHz to 350 kHz, for example, 10 kHz to 50 kHz.
[0042] According to some embodiments, which can be combined with other embodiments described herein, the sputtering according to the described embodiments can be conducted with three or more cathodes. However, particularly for applications for large area deposition, an array of cathodes having 6 or more cathodes, e.g. 10 or more cathodes, can be provided. The array can be provided in one vacuum chamber. Further, an array can typically be defined such that adjacent cathodes or cathode pairs influence each other, e.g. by having interacting plasma confinement. According to typical implementations, the sputtering can be conducted by a rotary cathode array, such as, but not limited to, a system such as PiVot of Applied Materials Inc..
[0043] According to some embodiments, which can be combined with other embodiments described herein, the embodiments described herein can be utilized for Display PVD, i.e. sputter deposition on large area substrates for the display market. A flat panel display or mobile phone displays can be manufactured on large area substrates. According to some embodiments, large area substrates or respective carriers, wherein the carriers have a plurality of substrates, may have a size of at least 0.67 m2. Typically, the size can be about 0.67m2 (0.73x0.92m - Gen 4.5) to about 8 m2, more typically about 2 m2 to about 9 m2 or even up to 12 m2. According to some embodiments, a large area substrate or a respective carrier can have a size of 1.4 m2 or above. Typically, the substrates or carriers, for which the structures, apparatuses, such as cathode assemblies, and methods according to embodiments described herein are provided, are large area substrates as described herein. For instance, a large area substrate or carrier can be GEN 4.5, which corresponds to about 0.67 m2 substrates (0.73x0.92m), GEN 5, which corresponds to about 1.4 m2 substrates (1.1 m x 1.3 m), GEN 7.5, which corresponds to about 4.29 m2 substrates (1.95 m x 2.2 m), GEN 8.5, which corresponds to about 5.7m2 substrates (2.2 m x 2.5 m), or even GEN 10, which corresponds to about 8.7 m2 substrates (2.85 m x 3.05 m). Even larger generations such as GEN 11 and GEN 12 and corresponding substrate areas can similarly be implemented.
[0044] According to yet further embodiments, which can be combined with other embodiments described herein, the target material can be selected from the group consisting of: aluminum, silicon, tantalum, molybdenum, niobium, titanium, indium, gallium, zinc, tin, silver and copper. Particularly, the target material can be selected from the group consisting of indium, gallium and zinc. The reactive sputter processes provide typically deposited oxides of these target materials. However, nitrides or oxi-nitrides might be deposited as well.
[0045] According to embodiments described herein, the methods provide a sputter deposition for a positioning of the substrate for a static deposition process. Typically, particularly for large area substrate processing, such as processing of vertically oriented large area substrates, it can be distinguished between static deposition and dynamic deposition. According to some embodiments, which can be combined with other embodiments described herein, the substrates and/or the carriers described herein and the apparatuses for utilizing the gas distribution systems described herein can be configured for vertical substrate processing. The term vertical substrate processing is understood to distinguish over horizontal substrate processing. That is, vertical substrate processing relates to an essentially vertical orientation of the carrier and the substrate during substrate processing, wherein a deviation of a few degrees, e.g. up to 10° or even up to 15°, from an exact vertical orientation is still considered as vertical substrate processing. A vertical substrate orientation with a small inclination can, for example, result in a more stable substrate handling or a reduced risk of particles contaminating a deposited layer. Alternatively, a horizontal substrate orientation may be possible. For a horizontal substrate orientation the cathode array would, for example, also be essentially horizontal. Yet, a vertical substrate orientation, e.g. within -15° to +15° from the vertical orientation, reduces the floor space for large area substrate processing and, thus, the cost of ownership (CoO).
[0046] Accordingly, a static deposition process can be understood as a deposition process with a static position, a deposition process with an essentially static position, or a deposition process with a partially static position of the substrate. A static deposition process, as described herein, can be clearly distinguished from a dynamic deposition process without the necessity that the substrate position for the static deposition process is fully without any movement during deposition. According to yet further embodiments, which can be combined with other embodiments described herein, a deviation from a fully static substrate position, e.g. oscillating, wobbling or any other movement of substrates as described above, which is still considered a static deposition by a person skilled in the art, can additionally or alternatively be provided by a movement of the cathodes or the cathode array, e.g. wobbling, oscillating or the like. The substrate and the cathodes (or the cathode array) can move relative to each other, e.g. in the substrate transport direction, in a lateral direction essentially perpendicular to the substrate transport direction or both.
[0047] According to yet further, embodiments the manufacturing of a layer having a first portion with a first columnar growth direction and a second portion with a second, different columnar growth direction can also be conducted in a dynamic deposition system, wherein the substrate is moved by two or more sources. In such a case, the transportation speed of the substrate may be taken into consideration when determining the deposition directions for the manufacturing processes.
[0048] According to embodiments described herein, which can be combined with other embodiments described herein, a directional growth, e.g. a columnar growth, can be decoupled by depositing the material in a tilted manner or angular manner. Angular sputtering as described in more detail with respect to FIGS. 4A, 4B, 5A and 5B can reduce one-directional columnar growth, particularly a vertical columnar growth, wherein ions might tunnel through or channel through a mask having a vertical columnar growth.
[0049] FIG. 4A shows the cathode 122 having a magnet assembly 121 provided in the cathode, for example within a backing tube supporting the target material. As indicated by axis 410 and shown by the arrow, the magnet assembly 121 can be rotated to deviate from the vertical deposition direction, i.e. to have a first angular coordinate. The vertical direction, i.e. the direction perpendicular to the surface of the substrate 451, is shown by line 471. According to typical embodiments, which can be combined with other embodiments described herein, the angle 470 can be 10° or above, for example 20° to 60°, such as about 25° to 40°, for example about 30°. [0050] FIG. 4A illustrates confined plasma tubes 407 and the deposition direction (see arrow 300 A) resulting from the angular position of the magnet assembly 121 relative to line 471 or the substrate 451, respectively. As a result, as shown in FIG. 5 A, a first portion 462 of the layer is grown on the substrate 451 , wherein the columnar growth direction is tilted with respect to the direction vertical to the substrate surface. The substrate 451 shown in FIGS. 4A to 5B can be a substrate as described above but may also be the substrate having one or more layers provided thereon. FIGS. 4A to 5B schematically shows only that layer having the first portion 462 and the second portion 464 with the first columnar growth direction and a second, different columnar growth direction.
[0051] After deposition of the first portion 462 of the layer, the magnet assembly 121 is rotated to the second position shown exemplary in FIG. 4B, i.e. to a second angular coordinate. A second deposition direction indicated by arrow 300B is provided by the second position of the magnet assembly 121. As a result, as shown in FIG. 5B, a second portion 464 of the layer is grown on the first portion 462 of the layer. The second portion 464 has a columnar growth with a second columnar growth direction, which is different from the first columnar growth direction. According to embodiments described herein, the grain boundaries of the grown columns can be decoupled by changing the magnet position between a first and a second deposition process.
[0052] According to embodiments described herein, which can be combined with other embodiments described herein, the cathode can be switched off after depositing in the first deposition direction, the magnet assembly 121 can be rotated while the cathode is in is switched off state, and the cathode is switched on after the magnet assembly 121 is provided in the second position, i.e. the position for the second deposition direction. Yet further, additionally or alternatively, the magnet assembly 121 can be provided at an essentially constant position and/or can be positioned to provide an essentially constant deposition direction during depositing the first portion 462 of the layer and/or the second portion 464 of the layer.
[0053] According to yet further embodiments, which can be combined with other embodiments described herein, switching between the first position of the magnet assembly and the second position of the magnet assembly or vice versa is provided one or more times, for example 1 to 4 times. Accordingly, the zig-zag profile can be provided for the columnar grown claims. The thickness of the first portion of the layer and/or the thickness of the second portion of the layer can be 40 nm or above, particularly 100 nm or above. The thickness of the layer, i.e. including at least the first portion and the second portion, can be 200 nm or above, particularly 300 nm or above. Accordingly, the thickness of one or more portions of the layer is sufficiently large such that ions cannot channel through the layer.
[0054] As shown in FIG. 5 B, the layer of the material includes a plurality of first grain boundaries in the first portion of the layer and a plurality of second grain boundaries in the second portion and wherein the plurality of second grain boundaries have a different orientation as compared to the plurality of first grain boundaries.
[0055] According to some embodiments, which can be combined with other embodiments described herein, the layer can be a metallic layer, particularly the layer can be a MoW layer, a Mo layer, a Ti layer, a Al layer, a Cu layer, a layer comprising two or more of MoW, Mo, Ti, Al, Cu, or a layer comprising an alloy of one or more of MoW, Mo, Ti, Al, Cu.
[0056] FIG. 6 shows an electron microscope image, wherein the layer having a first portion with a first columnar growth direction and a second portion with the second columnar growth direction, i.e. grain boundaries having a first and a second orientation, is shown. The white lines illustrate the orientation of the columnar growth direction and/or the grain boundaries. The dashed arrow shows an impact direction of ions, which can be utilized during ion implantation. It can be seen that ions have an improved likelihood to be blocked by the layer, which can be a mask during the ion implantation process, based upon the inclination of the grain boundary direction and the direction of the ions.
[0057] Even though some embodiments described herein referred to the manufacture of a transistor such as a LTPS-TFT, for which embodiments described herein can be beneficially utilized, other applications may as well benefit from embodiments described herein. FIG. 7 shows a method of depositing a layer of a material over a substrate, wherein the first portion of the layer is deposited with the first deposition direction and resulting in the first columnar growth direction (see 701) and a second portion of the layer is deposited with a second deposition direction resulting in a second columnar growth direction (see 702), wherein the second columnar growth direction is different from the first columnar growth direction, for example the angle between the first columnar growth direction and the second columnar growth direction is 30° or above, for example about 60°.
[0058] While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of depositing a layer of a material over a substrate, the method comprising: depositing a first portion of the layer with a first deposition direction resulting in a first columnar growth direction; and depositing a second portion of the layer with a second deposition direction resulting in a second columnar growth direction, wherein the second columnar growth direction is different from the first columnar growth direction.
2. The method according to claim 1, wherein the first deposition direction is essentially constant during the deposition of the first portion of the layer and/or wherein the second deposition direction is essentially constant during the deposition of the second portion of the layer.
3. The method according to any of claims 1 to 2, wherein the first deposition direction is defined by a first angular coordinate of a magnet arrangement of a magnetron sputter cathode and/or wherein the second deposition direction is defined by a second angular coordinate of the magnet arrangement of the magnetron sputter cathode.
4. The method according to claim 3, wherein the magnetron sputter cathode is a rotatable magnetron sputter cathode.
5. The method according to any of claims 1 to 4, wherein the thickness of the layer is 200 nm or above, particularly 300 nm or above.
6. The method according to any of claims 1 to 5, wherein the thickness of the first portion of the layer and/or the thickness of the second portion of the layer is 40 nm or above, particularly 100 nm or above.
7. The method according to any of claims 1 to 6, wherein the layer is a metallic layer, particularly wherein the layer is a MoW layer, a Mo layer, a Ti layer, a Al layer, a Cu layer, a layer comprising two or more of MoW, Mo, Ti, Al, Cu, or a layer comprising an alloy of one or more of MoW, Mo, Ti, Al, Cu.
8. A method of manufacturing a transistor on a substrate, comprising: depositing an active channel layer over the substrate; depositing a layer of a material over a substrate according to any of claims 1 to 7, wherein the layer of the material provides a gate of the transistor over the active channel layer; and conducting an ion implantation, wherein the gate is used as a mask.
9. The method according to claim 8, wherein the ion implantation provides a doping of a contact area of the active channel layer to a source of the transistor and a doping of a further contact area of the active channel layer to a drain of the transistor.
10. The method according to any of claims 8 to 9, further comprising: depositing a gate insulator over the substrate, such that the gate insulator layer is provided between the active channel layer and the gate.
11. The method according to any of claims 8 to 9, further comprising: structuring the layer of the material after depositing the layer of material and before conducting the ion implantation.
12. A layer stack for an electronic device, comprising: a layer of a material deposited over a substrate, which is manufactured by a method according to any of claims 1 to 11.
13. The layer stack according to claim 12, wherein the layer of the material includes a plurality of first grain boundaries in the first portion of the layer and a plurality of second grain boundaries in the second portion and wherein the plurality of second grain boundaries have a different orientation as compared to the plurality of first grain boundaries.
14. An electronic device, comprising: a layer stack according to any of claims 12 to 13.
15. The electronic device according to claim 14, wherein the electronic device is an opto-electronic device, particularly a flat panel display or a mobile phone display.
PCT/US2014/043587 2014-06-23 2014-06-23 Method of depositing a layer, method of manufacturing a transistor, layer stack for an electronic device, and an electronic device WO2015199638A1 (en)

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