WO2015184659A1 - 驱动电路及液晶显示装置 - Google Patents

驱动电路及液晶显示装置 Download PDF

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Publication number
WO2015184659A1
WO2015184659A1 PCT/CN2014/080841 CN2014080841W WO2015184659A1 WO 2015184659 A1 WO2015184659 A1 WO 2015184659A1 CN 2014080841 W CN2014080841 W CN 2014080841W WO 2015184659 A1 WO2015184659 A1 WO 2015184659A1
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Prior art keywords
signal
main
driving circuit
sub
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/080841
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English (en)
French (fr)
Inventor
戴超
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/404,637 priority Critical patent/US9613581B2/en
Publication of WO2015184659A1 publication Critical patent/WO2015184659A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects

Definitions

  • the present invention relates to the field of liquid crystal technology, and in particular to a driving circuit and a liquid crystal display device.
  • the drive circuit of the existing liquid crystal display device can adopt the GOA structure (Gate Driver On Array, the gate drive on the array substrate, that is, the thin film transistor in the gate drive signal circuit is fabricated on the array substrate, thereby implementing progressive scan of the gate in the drive circuit.
  • GOA structure Gate Driver On Array
  • each pixel generally includes a main sub-pixel and a sub-sub-pixel, and the main sub-pixel and the sub-sub-pixel display different degrees of brightness when displaying the same picture, thereby realizing multi-domain display of the pixel, and solving the problem.
  • the vertical array type liquid crystal display has a color deviation problem at a large viewing angle.
  • the main scanning line is used in the prior art (Gate The line or the main scan line) and the corresponding clock signal drive the main sub-pixel, and the sub-pixel is driven using a sub-scanning line and a corresponding clock signal.
  • the specific process may input a high level to the main scanning line, and the corresponding data line simultaneously charges the main liquid crystal capacitor of the main sub-pixel and the sub-liquid crystal capacitor of the sub-sub-pixel, and the brightness of the main sub-pixel and the sub-sub-pixel are the same;
  • the scan line input is low, and the corresponding data line stops charging the liquid crystal capacitor; then the secondary scan line inputs a high level, and the main sub-pixel and the sub-sub-pixel are the main storage capacitor capacity of the main sub-pixel and the sub-storage capacitance of the sub-sub-pixel.
  • the capacity of the main liquid crystal capacitor and the sub liquid crystal capacitor are different, so that the voltages of the main liquid crystal capacitor and the sub liquid crystal capacitor are different (generally, the voltage of the main liquid crystal capacitor is greater than the voltage of the sub liquid crystal capacitor), so that the brightness of the main sub-pixel and the sub-sub-pixel are Inconsistent, multi-domain display of pixels is achieved.
  • FIG. 1 is a schematic diagram of signal transmission of a driving circuit of a conventional liquid crystal display device.
  • Clock signals CK1, CK2, CK3, and CK4 pass through the GOA of the scan line driver circuit (Gate On Array, array substrate row drive) sends drive signals to the main scan line and the sub-scan line, respectively.
  • the STV provides a drive start signal and a drive end signal.
  • the clock signal for driving the main scanning line and the clock signal for driving the sub-scanning line are the same, the clock signal is easily affected by the line resistance of the main scanning line and the line resistance of the sub-scanning line, thereby causing The generation of the main scan signal based on the clock signal has a certain signal delay, thereby affecting the display quality of the liquid crystal display device.
  • An object of the present invention is to provide a driving circuit and a liquid crystal display device which solve the technical problem that the display quality of the conventional liquid crystal display device is low due to a signal delay of a driving signal of a main scanning line (i.e., a main scanning signal).
  • An embodiment of the present invention provides a driving circuit, which is disposed in a liquid crystal display device, the liquid crystal display device includes a liquid crystal display panel and a driving circuit, and the liquid crystal display panel includes a data line, a scan line, and the data line and the a plurality of pixel units, wherein each of the pixel units includes a main pixel and a sub-pixel, the scan line includes a main scan line and a sub-scan line; wherein the driving circuit comprises:
  • a first clock signal driving circuit configured to generate a first clock signal
  • a second clock signal driving circuit configured to generate a second clock signal
  • a data line driving circuit for generating a data signal and transmitting to the data line
  • a scan line driving circuit configured to generate a main scan signal according to the first clock signal and transmit the scan signal to the main scan line, generate a sub scan signal according to the second clock signal, and transmit the scan signal to the sub scan line ;
  • the frequency of the second clock signal is higher than the frequency of the first clock signal
  • the scan line driving circuit includes:
  • a main scan signal generating module configured to generate a main scan signal of the current stage according to the first clock signal and the main cascade signal of the previous stage;
  • a main cascade signal generating module configured to generate a main cascade signal of the current level
  • a main drive end module configured to end the main scan signal of the current stage according to a main scan signal of the next stage
  • a main scan signal maintaining module for maintaining a low potential of the main scanning signal of the current stage
  • the scan driving circuit comprises:
  • a sub-scanning signal generating module configured to generate a sub-scanning signal of the current level according to the second clock signal and the secondary combined signal of the previous stage
  • a secondary signal generation module for generating a secondary signal of the current level
  • a sub-drive end module configured to end the sub-scanning signal of the current stage according to the sub-scanning signal of the next stage;
  • the sub-scanning signal maintaining module is configured to maintain a low potential of the sub-scanning signal of the current stage.
  • the second clock signal driving circuit when the liquid crystal display device performs three-dimensional image display, the second clock signal driving circuit generates a constant low level signal such that the brightness of the main pixel and the sub-pixel is darkened. the same.
  • An embodiment of the present invention provides a driving circuit, which is disposed in a liquid crystal display device, the liquid crystal display device includes a liquid crystal display panel and a driving circuit, and the liquid crystal display panel includes a data line, a scan line, and the data line and the a plurality of pixel units, wherein each of the pixel units includes a main pixel and a sub-pixel, the scan line includes a main scan line and a sub-scan line; wherein the driving circuit comprises:
  • a first clock signal driving circuit configured to generate a first clock signal
  • a second clock signal driving circuit configured to generate a second clock signal
  • a data line driving circuit for generating a data signal and transmitting to the data line
  • a scan line driving circuit configured to generate a main scan signal according to the first clock signal and transmit the scan signal to the main scan line, generate a sub scan signal according to the second clock signal, and transmit the scan signal to the sub scan line .
  • the frequency of the second clock signal is higher than the frequency of the first clock signal.
  • the second clock signal driving circuit when the liquid crystal display device performs three-dimensional image display, the second clock signal driving circuit generates a constant low level signal such that the brightness of the main pixel and the sub-pixel is darkened. the same.
  • the driving circuit further includes:
  • a first start circuit for generating a first enable signal and a first end signal; the first enable signal and the first end signal being used by the scan line drive circuit to generate the main scan signal;
  • a second start circuit for generating a second start signal and a second end signal, wherein the second start signal and the second end signal are used by the scan line driving circuit to generate the second scan signal.
  • the second starting circuit when the liquid crystal display device performs three-dimensional image display, the second starting circuit does not generate the second enable signal and the second end signal.
  • the scan line driving circuit includes:
  • a main scan signal generating module configured to generate a main scan signal of the current stage according to the first clock signal and the main cascade signal of the previous stage;
  • a main cascade signal generating module configured to generate a main cascade signal of the current level
  • a main drive end module configured to end the main scan signal of the current stage according to a main scan signal of the next stage
  • the main scan signal maintaining module is configured to maintain a low potential of the main scan signal of the stage.
  • the main driving end module ends the main scanning signal of the current stage by pulling down the potential of the main scanning signal of the current stage.
  • the scan driving circuit includes:
  • a sub-scanning signal generating module configured to generate a sub-scanning signal of the current level according to the second clock signal and the secondary combined signal of the previous stage
  • a secondary signal generation module for generating a secondary signal of the current level
  • a sub-drive end module configured to end the sub-scanning signal of the current stage according to the sub-scanning signal of the next stage;
  • the sub-scanning signal maintaining module is configured to maintain a low potential of the sub-scanning signal of the current stage.
  • the sub-drive end module ends the sub-scanning signal of the current stage by pulling down the potential of the sub-scanning signal of the current stage.
  • An embodiment of the present invention further provides a liquid crystal display device including a liquid crystal display panel and a driving circuit, the liquid crystal display panel including a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line
  • the pixel units includes a main pixel and a sub-pixel
  • the scan line includes a main scan line and a sub-scan line
  • the driving circuit includes:
  • a first clock signal driving circuit configured to generate a first clock signal
  • a second clock signal driving circuit configured to generate a second clock signal
  • a data line driving circuit for generating a data signal and transmitting to the data line
  • a scan line driving circuit configured to generate a main scan signal according to the first clock signal and transmit the scan signal to the main scan line, generate a sub scan signal according to the second clock signal, and transmit the scan signal to the sub scan line .
  • the frequency of the second clock signal is higher than the frequency of the first clock signal.
  • the second clock signal driving circuit when the liquid crystal display device performs three-dimensional image display, the second clock signal driving circuit generates a constant low level signal such that the main pixel and the sub-pixel are light and dark. The same level.
  • the driving circuit further includes:
  • a first start circuit for generating a first enable signal and a first end signal; the first enable signal and the first end signal being used by the scan line drive circuit to generate the main scan signal;
  • a second start circuit for generating a second start signal and a second end signal, wherein the second start signal and the second end signal are used by the scan line driving circuit to generate the second scan signal.
  • the second activation circuit when the liquid crystal display device performs three-dimensional image display, the second activation circuit does not generate the second activation signal and the second end signal.
  • the scan line driving circuit includes:
  • a main scan signal generating module configured to generate a main scan signal of the current stage according to the first clock signal and the main cascade signal of the previous stage;
  • a main cascade signal generating module configured to generate a main cascade signal of the current level
  • a main drive end module configured to end the main scan signal of the current stage according to a main scan signal of the next stage
  • the main scan signal maintaining module is configured to maintain a low potential of the main scan signal of the stage.
  • the main drive end module ends the main scanning signal of the current stage by pulling down the potential of the main scanning signal of the current stage.
  • the scan driving circuit includes:
  • a sub-scanning signal generating module configured to generate a sub-scanning signal of the current level according to the second clock signal and the secondary combined signal of the previous stage
  • a secondary signal generation module for generating a secondary signal of the current level
  • a sub-drive end module configured to end the sub-scanning signal of the current stage according to the sub-scanning signal of the next stage;
  • the sub-scanning signal maintaining module is configured to maintain a low potential of the sub-scanning signal of the current stage.
  • the sub-drive end module ends the sub-scanning signal of the current stage by pulling down the potential of the sub-scanning signal of the current stage.
  • the driving circuit and the liquid crystal display device of the present invention generate a main scanning signal according to the first clock signal, and generate a sub-scanning signal according to the second clock signal, thereby avoiding signal delay of the main scanning signal.
  • the technical problem that the display quality of the conventional liquid crystal display device is low due to the signal delay of the main scanning signal is solved.
  • FIG. 1 is a schematic diagram of signal transmission of a driving circuit of a conventional liquid crystal display device
  • FIG. 2 is a schematic structural view of a first preferred embodiment of a driving circuit of a liquid crystal display device of the present invention
  • FIG. 3 is a schematic diagram of signal transmission of a first preferred embodiment of a driving circuit of a liquid crystal display device of the present invention
  • FIG. 4 is a schematic diagram showing signal timing of a first preferred embodiment of a driving circuit of a liquid crystal display device of the present invention
  • FIG. 5 is a schematic structural view of a second preferred embodiment of a driving circuit of a liquid crystal display device of the present invention.
  • FIG. 6 is a schematic diagram of signal transmission of a second preferred embodiment of a driving circuit of a liquid crystal display device of the present invention.
  • FIG. 7 is a timing chart showing signals of a second preferred embodiment of a driving circuit of a liquid crystal display device of the present invention.
  • Fig. 8 is a view showing the configuration of a scanning line driving circuit of a driving circuit of a liquid crystal display device of the present invention.
  • FIG. 2 is a schematic structural view of a first preferred embodiment of a driving circuit of a liquid crystal display device of the present invention.
  • the liquid crystal display device includes a liquid crystal display panel and a driving circuit 20, and the liquid crystal display panel includes a data line 25, a scan line, and a plurality of pixel units which are formed by interleaving the data line 25 and the scan line, each pixel unit including the main pixel 23 and the second
  • the pixel 24 includes a main scanning line 21 and a sub-scanning line 22.
  • the driving circuit 20 includes a first clock signal driving circuit 201, a second clock signal driving circuit 202, a data line driving circuit 203, a scanning line driving circuit 204, and a first starting circuit 205.
  • the first clock signal driving circuit 201 is configured to generate a first clock signal;
  • the second clock signal driving circuit 202 is configured to generate a second clock signal;
  • the data line driving circuit 203 is configured to generate a data signal and transmit the data signal to the data line 25;
  • the driving circuit 204 is configured to generate a main scanning signal according to the first clock signal and transmit it to the main scanning line 21; according to the second clock signal, generate a sub-scanning signal and transmit it to the sub-scanning line 22;
  • the first starting circuit 205 is used for A first enable signal and a first end signal are generated, and the first enable signal and the first end signal are used by the scan line drive circuit 204 to generate a main scan signal and a sub-scan signal.
  • the scanning line driving circuit 204 generates a
  • FIG. 3 is a schematic diagram of signal transmission of a first preferred embodiment of a driving circuit of a liquid crystal display device of the present invention
  • FIG. 4 is a first preferred embodiment of a driving circuit of the liquid crystal display device of the present invention. Signal timing diagram.
  • the first clock signal driving circuit 201 of the driving circuit generates a first clock signal CK1, a first clock signal CK2, a first clock signal CK3, and a first clock signal CK4; and a second clock signal driving circuit 202 generates a second clock signal CK and The second clock signal XCK; the first start circuit 205 generates a first enable signal STV and a first end signal STV.
  • the number of first clock signals may be set according to the specific design of the liquid crystal display panel and the load.
  • the second clock signal can be a high frequency clock signal with two opposite phases.
  • the first clock signal CK1 is input to the main GOA1 (or the main GOA (4N+1)) of the scan line driving circuit 204, and the main GOA1 (or the main GOA (4N+1)) generates the main scanning signal PG1 (or the main scanning signal) PG (4N+1)) is transmitted to the main scanning line 21 to control the main pixel 23 and the sub-pixel 24 of the pixel unit of the first (or 4N+1) row to input corresponding data signals, respectively.
  • the first clock signal CK2 is input to the main GOA2 (or the main GOA (4N+2)) of the scanning line driving circuit 204, and the main GOA2 (or the main GOA (4N+2)) generates the main scanning signal PG2 (or the main scanning signal PG) (4N+2)) and transmitted to the main scanning line 21 to control the main pixel 23 and the sub-pixel 24 of the pixel unit of the second (or 4N+2) row to input corresponding data signals.
  • the first clock signal CK3 is input to the main GOA3 (or the main GOA (4N+3)) of the scanning line driving circuit 204, and the main GOA3 (or the main GOA (4N+3)) generates the main scanning signal PG3 (or the main scanning signal PG) (4N+3)) and transmitted to the main scanning line 21 to control the main data 23 and the sub-pixel 24 of the pixel unit of the third (or 4N+3) row to input corresponding data signals.
  • the first clock signal CK4 is input to the main GOA 4 (or the main GOA (4N+4)) of the scanning line driving circuit 204, and the main GOA 4 (or the main GOA (4N+4)) generates the main scanning signal PG4 (or the main scanning signal PG) (4N+4)), and transmitted to the main scanning line 21 to control the main data 23 and the sub-pixel 24 of the pixel unit of the fourth (or 4N+4) row to input corresponding data signals.
  • the second clock signal CK is input to the secondary GOA1 (or the secondary GOA (2N+1)) of the scan line driving circuit 204, and the secondary GOA1 (or the secondary GOA (2N+1)) generates the secondary scanning signal SG1 (or the secondary scanning signal SG) (2N+1)), and transmitted to the sub-scanning line 21, the amount of the liquid crystal capacitor corresponding to the sub-pixel 24 of the pixel unit of the first (or 2N+1) row and the amount of the liquid crystal capacitor corresponding to the main pixel 23.
  • the redistribution is performed such that the degree of shading of the main pixel 23 and the sub-pixel 24 is inconsistent.
  • the second clock signal CKX is input to the secondary GOA2 (or the secondary GOA (2N+2)) of the scanning line driving circuit 204, and the secondary GOA2 (or the secondary GOA (2N+2)) generates the secondary scanning signal SG2 (or the secondary scanning signal SG ( 2N+2)) and transmitted to the sub-scanning line 21 to perform the electric quantity of the liquid crystal capacitor corresponding to the sub-pixel 24 of the pixel unit of the second (or 2N+2) row and the electric quantity of the liquid crystal capacitor corresponding to the main pixel 23.
  • the redistribution causes the degree of shading of the main pixel 23 and the sub-pixel 24 to be inconsistent.
  • the first enable signal STV of the first start circuit 205 is input to the main GOA1 and the secondary GOA1 of the scan signal of the scan line drive circuit 204 that controls the pixel unit of the first row, and the scan of the second row of pixel units of the scan line drive circuit 204 is controlled.
  • the primary GOA2 and the secondary GOA2 of the signal, the first end signal STV of the first enable circuit 205 is input to the main GOA (last) and the secondary GOA (last) of the last row of pixel units of the scan line drive circuit 204, and the scan line drive circuit 204 controls the primary GOA (last-1) and the secondary GOA (last-1) of the penultimate row of pixel units.
  • the frequency of the second clock signal is higher than the frequency of the first clock signal.
  • the first startup signal 205 is first sent by the first startup circuit 205 to the scan line driving circuit 204, because the scanning corresponding to each row of pixel units
  • the line driving circuit 204 generates a cascade signal for driving the pixel unit of the next row, so in the preferred embodiment, the first enable signal STV is input only to the main GOA1 and the secondary GOA1 that control the pixel unit of the first row, and the second row of pixels is controlled.
  • the first end signal STV of the first startup circuit 205 only needs to be input to the main GOA (last) and the secondary GOA (last) controlling the last row of pixel units, and the main GOA (last-1) controlling the pixel unit of the second to last row. ) and secondary GOA (last-1).
  • a second clock signal is generated using a second clock signal having a higher frequency, and is generated using a first clock signal having a lower frequency.
  • the scanning signal is independently controlled by the second clock signal and is not affected by the line resistance of the main scanning line 21; the main scanning signal is independently controlled by the first clock signal and is not affected by the line resistance of the sub-scanning line 22. The influence, therefore, greatly reduces the signal delay of the main scanning signal of the main scanning line 21 and the sub-scanning signal of the sub-scanning line 22.
  • the first startup circuit 205 sends the first enable signal STV to the scan line drive circuit 204, and then the scan line drive circuit 204 starts receiving the first clock signal CK1 generated by the first clock signal drive circuit 201.
  • the clock signal CK2, the first clock signal CK3, and the first clock signal CK4, and further the main GOA of the scan line driving circuit 204 sequentially generates a main scan signal PG1, a main scan signal PG2, a main scan signal PG3, and a main scan signal PG4;
  • the startup circuit 205 transmits a first end signal STV (not shown) to the scan line drive circuit 204, and the scan line drive circuit 204 stops receiving the first clock signal generated by the first clock signal drive circuit 204, thereby scanning the line drive circuit 204. Stop generating the main scan signal.
  • the scan line driving circuit 204 starts receiving the second clock signal CK and the second clock signal XCK generated by the second clock signal driving circuit 202 according to the first enable signal STV, and the secondary GOA of the scan line driving circuit 204 sequentially generates the sub-scanning signal. SG1, sub-scanning signal SG2, sub-scanning signal SG3 and sub-scanning signal SG4; finally, the first starting circuit 205 sends a first end signal STV (not shown) to the scanning line driving circuit 204, and the scanning line driving circuit 204 stops receiving The second clock signal drives the second clock signal generated by the circuit 202 such that the scan line drive circuit 204 stops generating the sub-scan signal.
  • the second clock signal is driven.
  • the circuit 202 can generate a constant low level signal, that is, the scan line driving circuit 204 does not emit a sub-scanning signal, and the power of the main liquid crystal capacitor and the sub liquid crystal capacitor in the pixel unit are not redistributed.
  • the main pixels 23 and the sub-pixels 24 have the same degree of brightness and darkness, which can effectively avoid the occurrence of crosstalk.
  • the driving circuit of the preferred embodiment generates a main scanning signal according to the first clock signal, and generates a sub-scanning signal according to the second clock signal, thereby avoiding signal delay of the main scanning signal.
  • FIG. 5 is a schematic structural view of a second preferred embodiment of a driving circuit of a liquid crystal display device of the present invention.
  • the driving circuit 50 includes a first clock signal driving circuit 501, a second clock signal driving circuit 502, a data line driving circuit 503, a scanning line driving circuit 504, a first starting circuit 505, and a second starting circuit 506.
  • the preferred embodiment differs from the first preferred embodiment in that the first enable circuit 505 is configured to generate a first enable signal and a first end signal, the first enable signal and the first end signal being used by the scan line drive circuit 504 to generate a master The scan signal is used; the second enable circuit 506 is configured to generate a second enable signal and a second end signal, and the second enable signal and the second end signal are used by the scan line drive circuit 504 to generate a secondary scan signal.
  • FIG. 6 is a schematic diagram of signal transmission of a second preferred embodiment of a driving circuit of a liquid crystal display device of the present invention
  • FIG. 7 is a second preferred embodiment of a driving circuit of the liquid crystal display device of the present invention. Signal timing diagram.
  • the process of driving the liquid crystal display device to perform two-dimensional image display by the driving circuit 50 of the preferred embodiment is different from that of the first preferred embodiment in that the scan line driving circuit 504 starts receiving the first clock signal driving circuit 501 according to the first enable signal STV1.
  • the first clock signal stops receiving the first clock signal generated by the first clock signal driving circuit 501 according to the first end signal STV1.
  • the scan line driving circuit 504 starts receiving the second clock signal generated by the second clock signal driving circuit 502 according to the second enable signal STV2, and stops receiving the second clock signal generated by the second clock signal driving circuit 502 according to the second technical signal STV2.
  • the second startup circuit 206 does not generate the first crosstalk phenomenon in order to avoid the crosstalk phenomenon of the left and right eye images caused by the excessive difference in luminance between the main pixels 23 and the sub-pixels 24.
  • the second enable signal and the second turn off signal that is, the second start circuit 206 is turned off.
  • the scan line driving circuit 504 does not receive the second clock signal, that is, the sub-scanning signal is not emitted, and the amounts of the main liquid crystal capacitor and the sub liquid crystal capacitor in the pixel unit are not redistributed.
  • the main pixels 23 and the sub-pixels 24 have the same degree of brightness and darkness, which can effectively avoid the occurrence of crosstalk.
  • the driving circuit of the preferred embodiment generates a main scanning signal according to the first clock signal, and generates a sub-scanning signal according to the second clock signal, thereby avoiding signal delay of the main scanning signal.
  • the scan line driving circuit of the preferred embodiment includes a main scan signal generating module, a main concatenated signal generating module, and a main driving end module.
  • the main scan signal generating module is configured to generate a main scan signal of the current stage according to the first clock signal and the main concatenated signal of the upper stage;
  • the main concatenated signal generating module is configured to generate a main concatenation signal of the current stage;
  • the main driving end module For ending the main scanning signal of the current stage according to the main scanning signal of the next stage, specifically, the main scanning signal of the current stage is ended by pulling down the potential of the main scanning signal of the current stage.
  • the scan driving circuit of the preferred embodiment further includes a sub-scanning signal generating module, a secondary combined signal generating module, and a secondary driving end module.
  • the secondary scan signal generating module is configured to generate a secondary scan signal of the current stage according to the second clock signal and the secondary combined signal of the previous stage; the secondary combined signal generating module is configured to generate the secondary scan signal of the current stage; and the secondary driving end module For ending the sub-scanning signal of the current stage according to the sub-scanning signal of the next stage, specifically, the sub-scanning signal of the current stage is ended by pulling down the potential of the sub-scanning signal of the current stage.
  • FIG. 8 is a schematic structural diagram of a scanning line driving circuit of a driving circuit of a liquid crystal display device of the present invention.
  • 801 is a main scan signal generating module, which generates the current level according to the first clock signal CKn, the main cascade signal PST(N-1) of the previous stage, and the main scan signal PG(N-1) of the previous stage.
  • 802 is a main concatenated signal generating module, which also generates the current level according to the first clock signal CKn, the main concatenated signal PST(N-1) of the previous stage, and the main scanning signal PG(N-1) of the previous stage.
  • the main cascade signal PST(N) is sent to the next level.
  • a main drive end module that pulls down the potential of PQ(N) and the potential of PG(N) according to the main scanning signal PG(N+1) of the next stage to end the main scanning signal PG(N) of the current stage.
  • 804 is a sub-scanning signal generating module, which generates a copy according to the second clock signal CK or XCK, the secondary combined signal SST(N-1) of the previous stage, and the main scanning signal SG(N-1) of the previous stage.
  • the sub-scanning signal SGN of the stage. 805 is a secondary joint signal generating module, which is also generated according to the second clock signal CK or XCK, the secondary combined signal SST(N-1) of the previous stage, and the secondary scanning signal SG(N-1) of the previous stage.
  • the secondary signal of this stage is connected to the SSTN and sent to the next stage.
  • a sub-drive end module which pulls down the potential of the main scanning signal SQ(N) of the current stage and the potential of the SG(N) according to the sub-scanning signal SG(N+1) of the next stage to end the level of the level. Scan the signal.
  • the scan driving circuit of the preferred embodiment may further include a main scan signal maintaining module 807 and a sub-scanning signal maintaining module 808.
  • the main scan signal maintaining module 807 is for maintaining the low potentials of PQ(N) and PG(N)
  • the sub-scanning signal maintaining module 808 is for maintaining the low potentials of SQ(N) and SG(N).
  • the present invention also provides a liquid crystal display device including the above-mentioned driving circuit.
  • the working principle of the liquid crystal display device is the same as that of the driving circuit described above. For details, refer to the related description in the preferred embodiment of the driving circuit.
  • the driving circuit and the liquid crystal display device of the present invention generate a main scanning signal according to the first clock signal, generate a sub-scanning signal according to the second clock signal, and avoid signal delay of the main scanning signal; and solve the main scanning signal of the existing liquid crystal display device The signal delay caused by the technical problems of poor display quality.

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Abstract

一种驱动电路以及液晶显示装置，该驱动电路包括第一时钟信号驱动电路、第二时钟信号驱动电路、数据线驱动电路以及扫描线驱动电路。上述驱动电路以及液晶显示装置避免了主扫描信号的信号延迟，解决了现有的液晶显示装置由于主扫描信号的信号延迟造成的显示品质低下的技术问题。

Description

驱动电路及液晶显示装置 技术领域
本发明涉及液晶技术领域，特别是涉及一种驱动电路及液晶显示装置。
 背景技术
随着液晶显示技术的发展，越来越多的用户开始使用液晶显示装置进行社交娱乐活动。现有的液晶显示装置的驱动电路可采用GOA结构（Gate Driver On Array，阵列基板上的栅极驱动），也就是将栅极驱动信号电路中的薄膜晶体管制作到阵列基板上，从而实现对驱动电路中的栅极实现逐行扫描。
同时在现有的大尺寸液晶显示装置中，每个像素一般会包括主子像素和次子像素，主子像素和次子像素显示同一画面时的明暗程度不同，从而实现像素的多畴显示，解决了垂直阵列型液晶显示器存在的大视角下的颜色偏差问题。
现有技术中使用主扫描线（Gate line或主扫描线）以及相应的时钟信号对主子像素进行驱动，使用次扫描线（Sharing line）以及相应的时钟信号对次子像素进行驱动。
具体过程可为主扫描线输入高电平，相应的数据线对主子像素的主液晶电容和次子像素的次液晶电容同时进行充电，这时主子像素和次子像素的明暗程度一致；随后主扫描线输入低电平，相应的数据线停止对液晶电容进行充电；然后次扫描线输入高电平，主子像素和次子像素按主子像素的主存储电容的容量和次子像素的次存储电容的容量分配主液晶电容和次液晶电容的电量，使得主液晶电容和次液晶电容两端电压不同（一般主液晶电容的电压大于次液晶电容的电压），这样主子像素和次子像素的明暗程度不一致，实现了像素的多畴显示。
如图1所示，图1为现有的液晶显示装置的驱动电路的信号传输示意图。时钟信号CK1、CK2、CK3以及CK4通过扫描线驱动电路的GOA（Gate on Array，阵列基板行驱动）向主扫描线和次扫描线分别发送驱动信号。其中STV提供驱动开始信号以及驱动结束信号。
驱动电路在使用过程中，由于驱动主扫描线的时钟信号和驱动次扫描线的时钟信号相同，因此该时钟信号易同时受到主扫描线的线阻和次扫描线的线阻的影响，从而造成根据该时钟信号生成主扫描信号会有一定的信号延迟，从而影响液晶显示装置的显示品质。
故，有必要提供一种驱动电路及液晶显示装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种驱动电路及液晶显示装置，以解决现有的液晶显示装置由于主扫描线的驱动信号（即主扫描信号）的信号延迟造成的显示品质低下的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种驱动电路，其设置在液晶显示装置中，所述液晶显示装置包括液晶显示面板以及驱动电路，所述液晶显示面板包括数据线、扫描线以及由所述数据线和所述扫描线交错构成的多个像素单元，每个像素单元包括主像素以及次像素，所述扫描线包括主扫描线以及次扫描线；其中所述驱动电路包括：
第一时钟信号驱动电路，用于生成第一时钟信号；
第二时钟信号驱动电路，用于生成第二时钟信号；
数据线驱动电路，用于生成数据信号并传输到所述数据线上；以及
扫描线驱动电路，用于根据所述第一时钟信号，生成主扫描信号并传输到所述主扫描线上，根据所述第二时钟信号，生成次扫描信号并传输到所述次扫描线上；
所述第二时钟信号的频率高于所述第一时钟信号的频率；
其中所述扫描线驱动电路包括：
主扫描信号生成模块，用于根据所述第一时钟信号以及上一级的主级联信号，生成本级的主扫描信号；
主级联信号生成模块，用于生成本级的主级联信号；
主驱动结束模块，用于根据下一级的主扫描信号，结束所述本级的主扫描信号；以及
主扫描信号维持模块，用于维持本级的所述主扫描信号的低电位；
其中所述扫描驱动电路包括：
次扫描信号生成模块，用于根据所述第二时钟信号以及上一级的次级联信号，生成本级的次扫描信号；
次级联信号生成模块，用于生成本级的次级联信号；
次驱动结束模块，用于根据下一级的次扫描信号，结束所述本级的次扫描信号；以及
次扫描信号维持模块，用于维持本级的所述次扫描信号的低电位。
在本发明所述的驱动电路中，所述液晶显示装置进行三维图像显示时，所述第二时钟信号驱动电路生成一恒低电平信号，使得所述主像素和所述次像素的明暗程度相同。
本发明实施例提供一种驱动电路，其设置在液晶显示装置中，所述液晶显示装置包括液晶显示面板以及驱动电路，所述液晶显示面板包括数据线、扫描线以及由所述数据线和所述扫描线交错构成的多个像素单元，每个像素单元包括主像素以及次像素，所述扫描线包括主扫描线以及次扫描线；其中所述驱动电路包括：
第一时钟信号驱动电路，用于生成第一时钟信号；
第二时钟信号驱动电路，用于生成第二时钟信号；
数据线驱动电路，用于生成数据信号并传输到所述数据线上；以及
扫描线驱动电路，用于根据所述第一时钟信号，生成主扫描信号并传输到所述主扫描线上，根据所述第二时钟信号，生成次扫描信号并传输到所述次扫描线上。
在本发明所述的驱动电路中，所述第二时钟信号的频率高于所述第一时钟信号的频率。
在本发明所述的驱动电路中，所述液晶显示装置进行三维图像显示时，所述第二时钟信号驱动电路生成一恒低电平信号，使得所述主像素和所述次像素的明暗程度相同。
在本发明所述的驱动电路中，所述驱动电路还包括：
第一启动电路，用于生成第一启动信号以及第一结束信号；所述第一启动信号以及所述第一结束信号用于所述扫描线驱动电路生成所述主扫描信号；以及
第二启动电路，用于生成第二启动信号以及第二结束信号，所述第二启动信号以及所述第二结束信号用于所述扫描线驱动电路生成所述次扫描信号。
在本发明所述的驱动电路中，所述液晶显示装置进行三维图像显示时，所述第二启动电路不生成所述第二启动信号以及所述第二结束信号。
在本发明所述的驱动电路中，所述扫描线驱动电路包括：
主扫描信号生成模块，用于根据所述第一时钟信号以及上一级的主级联信号，生成本级的主扫描信号；
主级联信号生成模块，用于生成本级的主级联信号；
主驱动结束模块，用于根据下一级的主扫描信号，结束所述本级的主扫描信号；以及
主扫描信号维持模块，用于维持本级的所述主扫描信号的低电位。
在本发明所述的驱动电路中，所述主驱动结束模块通过下拉所述本级的主扫描信号的电位，结束所述本级的主扫描信号。
在本发明所述的驱动电路中，所述扫描驱动电路包括：
次扫描信号生成模块，用于根据所述第二时钟信号以及上一级的次级联信号，生成本级的次扫描信号；
次级联信号生成模块，用于生成本级的次级联信号；
次驱动结束模块，用于根据下一级的次扫描信号，结束所述本级的次扫描信号；以及
次扫描信号维持模块，用于维持本级的所述次扫描信号的低电位。
在本发明所述的驱动电路中，所述次驱动结束模块通过下拉所述本级的次扫描信号的电位，结束所述本级的次扫描信号。
本发明实施例还提供一种液晶显示装置，其包括液晶显示面板以及驱动电路，所述液晶显示面板包括数据线、扫描线以及由所述数据线和所述扫描线交错构成的多个像素单元，每个像素单元包括主像素以及次像素，所述扫描线包括主扫描线以及次扫描线；其中所述驱动电路包括：
第一时钟信号驱动电路，用于生成第一时钟信号；
第二时钟信号驱动电路，用于生成第二时钟信号；
数据线驱动电路，用于生成数据信号并传输到所述数据线上；以及
扫描线驱动电路，用于根据所述第一时钟信号，生成主扫描信号并传输到所述主扫描线上，根据所述第二时钟信号，生成次扫描信号并传输到所述次扫描线上。
在本发明所述的液晶显示装置中，所述第二时钟信号的频率高于所述第一时钟信号的频率。
在本发明所述的液晶显示装置中，所述液晶显示装置进行三维图像显示时，所述第二时钟信号驱动电路生成一恒低电平信号，使得所述主像素和所述次像素的明暗程度相同。
在本发明所述的液晶显示装置中，所述驱动电路还包括：
第一启动电路，用于生成第一启动信号以及第一结束信号；所述第一启动信号以及所述第一结束信号用于所述扫描线驱动电路生成所述主扫描信号；以及
第二启动电路，用于生成第二启动信号以及第二结束信号，所述第二启动信号以及所述第二结束信号用于所述扫描线驱动电路生成所述次扫描信号。
在本发明所述的液晶显示装置中，所述液晶显示装置进行三维图像显示时，所述第二启动电路不生成所述第二启动信号以及所述第二结束信号。
在本发明所述的液晶显示装置中，所述扫描线驱动电路包括：
主扫描信号生成模块，用于根据所述第一时钟信号以及上一级的主级联信号，生成本级的主扫描信号；
主级联信号生成模块，用于生成本级的主级联信号；
主驱动结束模块，用于根据下一级的主扫描信号，结束所述本级的主扫描信号；以及
主扫描信号维持模块，用于维持本级的所述主扫描信号的低电位。
在本发明所述的液晶显示装置中，所述主驱动结束模块通过下拉所述本级的主扫描信号的电位，结束所述本级的主扫描信号。
在本发明所述的液晶显示装置中，所述扫描驱动电路包括：
次扫描信号生成模块，用于根据所述第二时钟信号以及上一级的次级联信号，生成本级的次扫描信号；
次级联信号生成模块，用于生成本级的次级联信号；
次驱动结束模块，用于根据下一级的次扫描信号，结束所述本级的次扫描信号；以及
次扫描信号维持模块，用于维持本级的所述次扫描信号的低电位。
在本发明所述的液晶显示装置中，所述次驱动结束模块通过下拉所述本级的次扫描信号的电位，结束所述本级的次扫描信号。
 有益效果
相较于现有的驱动电路及液晶显示装置，本发明的驱动电路以及液晶显示装置根据第一时钟信号生成主扫描信号，根据第二时钟信号生成次扫描信号，避免了主扫描信号的信号延迟；解决了现有的液晶显示装置由于主扫描信号的信号延迟造成的显示品质低下的技术问题。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
图1为现有的液晶显示装置的驱动电路的信号传输示意图；
图2为本发明的液晶显示装置的驱动电路的第一优选实施例的结构示意图；
图3为本发明的液晶显示装置的驱动电路的第一优选实施例的信号传输示意图；
图4为本发明的液晶显示装置的驱动电路的第一优选实施例的信号时序示意图；
图5为本发明的液晶显示装置的驱动电路的第二优选实施例的结构示意图；
图6为本发明的液晶显示装置的驱动电路的第二优选实施例的信号传输示意图；
图7为本发明的液晶显示装置的驱动电路的第二优选实施例的信号时序示意图；
图8为本发明的液晶显示装置的驱动电路的扫描线驱动电路的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明的液晶显示装置的驱动电路的第一优选实施例的结构示意图。该液晶显示装置包括液晶显示面板以及驱动电路20，该液晶显示面板包括数据线25、扫描线以及由数据线25和扫描线交错构成的多个像素单元，每个像素单元包括主像素23和次像素24，扫描线包括主扫描线21和次扫描线22。
其中该驱动电路20包括第一时钟信号驱动电路201、第二时钟信号驱动电路202、数据线驱动电路203、扫描线驱动电路204以及第一启动电路205。第一时钟信号驱动电路201用于生成第一时钟信号；第二时钟信号驱动电路202用于生成第二时钟信号；数据线驱动电路203用于生成数据信号并传输到数据线25上；扫描线驱动电路204用于根据第一时钟信号，生成主扫描信号并传输到主扫描线21上；根据第二时钟信号，生成次扫描信号并传输到次扫描线22上；第一启动电路205用于生成第一启动信号以及第一结束信号，该第一启动信号以及第一结束信号用于扫描线驱动电路204生成主扫描信号以及次扫描信号。扫描线驱动电路204在每帧画面中根据第一启动信号生成主扫描信号以及次扫描信号，根据第一结束信号结束主扫描信号以及次扫描信号。
本优选实施例的驱动电路20可较好的避免主扫描信号受到像素内部的RC负载的影响。请参照图3和图4，图3为本发明的液晶显示装置的驱动电路的第一优选实施例的信号传输示意图，图4为本发明的液晶显示装置的驱动电路的第一优选实施例的信号时序示意图。
该驱动电路的第一时钟信号驱动电路201生成第一时钟信号CK1、第一时钟信号CK2、第一时钟信号CK3以及第一时钟信号CK4；第二时钟信号驱动电路202生成第二时钟信号CK以及第二时钟信号XCK；第一启动电路205生成第一启动信号STV以及第一结束信号STV。第一时钟信号的数量可能根据液晶显示面板的具体设计以及负载进行设置。第二时钟信号可为两个相位完全相反的高频时钟信号。
其中第一时钟信号CK1输入到扫描线驱动电路204的主GOA1（或主GOA（4N+1））上，主GOA1（或主GOA（4N+1））生成主扫描信号PG1（或主扫描信号PG（4N+1）），并传输到主扫描线21上，以控制第一（或4N+1）行的像素单元的主像素23和次像素24分别输入相应的数据信号。
第一时钟信号CK2输入到扫描线驱动电路204的主GOA2（或主GOA（4N+2））上，主GOA2（或主GOA（4N+2））生成主扫描信号PG2（或主扫描信号PG（4N+2）），并传输到主扫描线21上，以控制第二（或4N+2）行的像素单元的主像素23和次像素24输入相应的数据信号。
第一时钟信号CK3输入到扫描线驱动电路204的主GOA3（或主GOA（4N+3））上，主GOA3（或主GOA（4N+3））生成主扫描信号PG3（或主扫描信号PG（4N+3）），并传输到主扫描线21上，以控制第三（或4N+3）行的像素单元的主像素23和次像素24输入相应的数据信号。
第一时钟信号CK4输入到扫描线驱动电路204的主GOA4（或主GOA（4N+4））上，主GOA4（或主GOA（4N+4））生成主扫描信号PG4（或主扫描信号PG（4N+4）），并传输到主扫描线21上，以控制第四（或4N+4）行的像素单元的主像素23和次像素24输入相应的数据信号。
其中第二时钟信号CK输入到扫描线驱动电路204的次GOA1（或次GOA（2N+1）），次GOA1（或次GOA（2N+1））生成次扫描信号SG1（或次扫描信号SG（2N+1）），并传输到次扫描线21上，以对第一（或2N+1）行的像素单元的次像素24对应的液晶电容的电量和主像素23对应的液晶电容的电量进行重新分配，使得主像素23和次像素24的明暗程度不一致。
第二时钟信号CKX输入到扫描线驱动电路204的次GOA2（或次GOA（2N+2）），次GOA2（或次GOA（2N+2））生成次扫描信号SG2（或次扫描信号SG（2N+2）），并传输到次扫描线21上，以对第二（或2N+2）行的像素单元的次像素24对应的液晶电容的电量和主像素23对应的液晶电容的电量进行重新分配，使得主像素23和次像素24的明暗程度不一致。
第一启动电路205的第一启动信号STV输入到扫描线驱动电路204的控制第一行像素单元的扫描信号的主GOA1和次GOA1，以及扫描线驱动电路204的控制第二行像素单元的扫描信号的主GOA2和次GOA2，第一启动电路205的第一结束信号STV输入到扫描线驱动电路204的控制最后一行像素单元的主GOA（last）和次GOA（last），以及扫描线驱动电路204的控制倒数第二行像素单元的主GOA（last-1）和次GOA（last-1）。
在本优选实施例的驱动电路20中，第二时钟信号的频率高于第一时钟信号的频率。
当本优选实施例的驱动电路20用于驱动液晶显示装置进行二维图像显示时，首先由第一启动电路205向扫描线驱动电路204发送第一启动信号STV，由于每一行像素单元对应的扫描线驱动电路204会生成驱动下一行像素单元的级联信号，因此在本优选实施例中第一启动信号STV只输入到控制第一行像素单元的主GOA1和次GOA1，以及控制第二行像素单元的主GOA2和次GOA2。同样第一启动电路205的第一结束信号STV也只需要输入到控制最后一行像素单元的主GOA（last）和次GOA（last），以及控制倒数第二行像素单元的主GOA（last-1）和次GOA（last-1）。
驱动电路20的扫描线驱动电路204启动后，为了实现主像素23和次像素24的多畴显示，使用频率较高的第二时钟信号生成次扫描信号，使用频率较低的第一时钟信号生成主扫描信号。这样次扫描信号受到第二时钟信号的独立控制，不会受到主扫描线21的线阻的影响；主扫描信号受到第一时钟信号的独立控制，也不会受到次扫描线22的线阻的影响，因此大大降低了主扫描线21的主扫描信号和次扫描线22的次扫描信号的信号延迟。
具体请参照图4，首先第一启动电路205发送第一启动信号STV至扫描线驱动电路204，然后扫描线驱动电路204开始接收第一时钟信号驱动电路201生成的第一时钟信号CK1、第一时钟信号CK2、第一时钟信号CK3以及第一时钟信号CK4，进而扫描线驱动电路204的主GOA依次生成主扫描信号PG1、主扫描信号PG2、主扫描信号PG3以及主扫描信号PG4；最后第一启动电路205发送第一结束信号STV（图中未示出）至扫描线驱动电路204，扫描线驱动电路204停止接收第一时钟信号驱动电路204生成的第一时钟信号，从而扫描线驱动电路204停止生成主扫描信号。
同时扫描线驱动电路204根据第一启动信号STV，开始接收第二时钟信号驱动电路202生成的第二时钟信号CK以及第二时钟信号XCK，进而扫描线驱动电路204的次GOA依次生成次扫描信号SG1、次扫描信号SG2、次扫描信号SG3以及次扫描信号SG4；最后第一启动电路205发送第一结束信号STV（图中未示出）至扫描线驱动电路204，扫描线驱动电路204停止接收第二时钟信号驱动电路202生成的第二时钟信号，从而扫描线驱动电路204停止生成次扫描信号。
当本优选实施例的驱动电路20用于驱动液晶显示装置进行三维图像显示时，为了避免主像素23和次像素24亮度差异过大导致左右眼画面的串扰（crosstalk）现象，第二时钟信号驱动电路202可生成一恒低电平信号，即扫描线驱动电路204不会发出次扫描信号，像素单元中的主液晶电容和次液晶电容的电量不会进行重新分配。这样主像素23和次像素24的明暗程度一致，可有效的避免串扰现象的发生。
这样即完成了本优选实施例的液晶显示装置的驱动电路20的驱动过程。
本优选实施例的驱动电路根据第一时钟信号生成主扫描信号，根据第二时钟信号生成次扫描信号，避免了主扫描信号的信号延迟。
请参照图5，图5为本发明的液晶显示装置的驱动电路的第二优选实施例的结构示意图。该驱动电路50包括第一时钟信号驱动电路501、第二时钟信号驱动电路502、数据线驱动电路503、扫描线驱动电路504、第一启动电路505以及第二启动电路506。本优选实施例与第一优选实施例的区别在于，第一启动电路505用于生成第一启动信号以及第一结束信号，第一启动信号以及第一结束信号用于扫描线驱动电路504生成主扫描信号；第二启动电路506用于生成第二启动信号以及第二结束信号，第二启动信号以及第二结束信号用于扫描线驱动电路504生成次扫描信号。
请参照图6和图7，图6为本发明的液晶显示装置的驱动电路的第二优选实施例的信号传输示意图，图7为本发明的液晶显示装置的驱动电路的第二优选实施例的信号时序示意图。
本优选实施例的驱动电路50驱动液晶显示装置进行二维图像显示的过程与第一优选实施例的区别在于，扫描线驱动电路504根据第一启动信号STV1开始接收第一时钟信号驱动电路501生成的第一时钟信号，根据第一结束信号STV1停止接收第一时钟信号驱动电路501生成的第一时钟信号。扫描线驱动电路504根据第二启动信号STV2开始接收第二时钟信号驱动电路502生成的第二时钟信号，根据第二技术信号STV2停止接收第二时钟信号驱动电路502生成的第二时钟信号。
本优选实施例的驱动电路50驱动液晶显示装置进行三维图像显示时，为了避免主像素23和次像素24亮度差异过大导致左右眼画面的串扰（crosstalk）现象，第二启动电路206不生成第二启动信号以及第二关闭信号，即关闭第二启动电路206。这样扫描线驱动电路504不会接收第二时钟信号，即不会发出次扫描信号，像素单元中的主液晶电容和次液晶电容的电量不会进行重新分配。这样主像素23和次像素24的明暗程度一致，可有效的避免串扰现象的发生。
这样即完成了本优选实施例的液晶显示装置的驱动电路的驱动过程。
本优选实施例的驱动电路根据第一时钟信号生成主扫描信号，根据第二时钟信号生成次扫描信号，避免了主扫描信号的信号延迟。
优选的，本优选实施例的扫描线驱动电路包括主扫描信号生成模块、主级联信号生成模块以及主驱动结束模块。主扫描信号生成模块用于根据第一时钟信号以及上一级的主级联信号生成本级的主扫描信号；主级联信号生成模块用于生成本级的主级联信号；主驱动结束模块用于根据下一级的主扫描信号，结束本级的主扫描信号，具体可为通过下拉本级的主扫描信号的电位，结束本级的主扫描信号。
优选的，本优选实施例的扫描驱动电路还包括次扫描信号生成模块、次级联信号生成模块以及次驱动结束模块。次扫描信号生成模块用于根据第二时钟信号以及上一级的次级联信号，生成本级的次扫描信号；次级联信号生成模块用于生成本级的次扫描信号；次驱动结束模块用于根据下一级的次扫描信号，结束本级的次扫描信号，具体可为通过下拉本级的次扫描信号的电位，结束本级的次扫描信号。
请参照图8，图8为本发明的液晶显示装置的驱动电路的扫描线驱动电路的结构示意图。
其中801为主扫描信号生成模块，其根据第一时钟信号CKn、上一级的主级联信号PST（N-1）以及上一级的主扫描信号PG（N-1），生成本级的主扫描信号PG（N）。802为主级联信号生成模块，其同样根据第一时钟信号CKn、上一级的主级联信号PST（N-1）以及上一级的主扫描信号PG（N-1），生成本级的主级联信号PST（N），并发送至下一级。803为主驱动结束模块，其根据下一级的主扫描信号PG（N+1），下拉PQ（N）的电位以及PG（N）的电位，以结束本级的主扫描信号PG（N）。
其中804为次扫描信号生成模块，其根据第二时钟信号CK或XCK、上一级的次级联信号SST（N-1）以及上一级的主扫描信号SG（N-1），生成本级的次扫描信号SGN。805为次级联信号生成模块，其同样根据第二时钟信号CK或XCK、上一级的次级联信号SST（N-1）以及上一级的次扫描信号SG（N-1），生成本级的次级联信号SSTN，并发送至下一级。806为次驱动结束模块，其根据下一级的次扫描信号SG（N+1），下拉本级的主扫描信号SQ（N）的电位以及SG（N）的电位，以结束本级的次扫描信号。
优选的，本优选实施例的扫描驱动电路还可包括主扫描信号维持模块807以及次扫描信号维持模块808。主扫描信号维持模块807用于维持PQ（N）以及PG（N）的低电位，次扫描信号维持模块808用于维持SQ（N）以及SG（N）的低电位。
本发明还提供一种包括上述驱动电路的液晶显示装置，该液晶显示装置的工作原理与上述的驱动电路的工作原理相同，具体可参见上述驱动电路的优选实施例中的相关描述。
本发明的驱动电路以及液晶显示装置根据第一时钟信号生成主扫描信号，根据第二时钟信号生成次扫描信号，避免了主扫描信号的信号延迟；解决了现有的液晶显示装置由于主扫描信号的信号延迟造成的显示品质低下的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (20)

  1. 一种驱动电路，其设置在液晶显示装置中，所述液晶显示装置包括液晶显示面板以及驱动电路，所述液晶显示面板包括数据线、扫描线以及由所述数据线和所述扫描线交错构成的多个像素单元，每个像素单元包括主像素以及次像素，所述扫描线包括主扫描线以及次扫描线；其中所述驱动电路包括：
    第一时钟信号驱动电路，用于生成第一时钟信号；
    第二时钟信号驱动电路，用于生成第二时钟信号；
    数据线驱动电路，用于生成数据信号并传输到所述数据线上；以及
    扫描线驱动电路，用于根据所述第一时钟信号，生成主扫描信号并传输到所述主扫描线上，根据所述第二时钟信号，生成次扫描信号并传输到所述次扫描线上；
    所述第二时钟信号的频率高于所述第一时钟信号的频率；
    其中所述扫描线驱动电路包括：
    主扫描信号生成模块，用于根据所述第一时钟信号以及上一级的主级联信号，生成本级的主扫描信号；
    主级联信号生成模块，用于生成本级的主级联信号；
    主驱动结束模块，用于根据下一级的主扫描信号，结束所述本级的主扫描信号；以及
    主扫描信号维持模块，用于维持本级的所述主扫描信号的低电位；
    其中所述扫描驱动电路包括：
    次扫描信号生成模块，用于根据所述第二时钟信号以及上一级的次级联信号，生成本级的次扫描信号；
    次级联信号生成模块，用于生成本级的次级联信号；
    次驱动结束模块，用于根据下一级的次扫描信号，结束所述本级的次扫描信号；以及
    次扫描信号维持模块，用于维持本级的所述次扫描信号的低电位。
  2. 根据权利要求1所述的驱动电路，其中所述液晶显示装置进行三维图像显示时，所述第二时钟信号驱动电路生成一恒低电平信号，使得所述主像素和所述次像素的明暗程度相同。
  3. 一种驱动电路，其设置在液晶显示装置中，所述液晶显示装置包括液晶显示面板以及驱动电路，所述液晶显示面板包括数据线、扫描线以及由所述数据线和所述扫描线交错构成的多个像素单元，每个像素单元包括主像素以及次像素，所述扫描线包括主扫描线以及次扫描线；其中所述驱动电路包括：
    第一时钟信号驱动电路，用于生成第一时钟信号；
    第二时钟信号驱动电路，用于生成第二时钟信号；
    数据线驱动电路，用于生成数据信号并传输到所述数据线上；以及
    扫描线驱动电路，用于根据所述第一时钟信号，生成主扫描信号并传输到所述主扫描线上，根据所述第二时钟信号，生成次扫描信号并传输到所述次扫描线上。
  4. 根据权利要求3所述的驱动电路，其中所述第二时钟信号的频率高于所述第一时钟信号的频率。
  5. 根据权利要求3所述的驱动电路，其中所述液晶显示装置进行三维图像显示时，所述第二时钟信号驱动电路生成一恒低电平信号，使得所述主像素和所述次像素的明暗程度相同。
  6. 根据权利要求3所述的驱动电路，其中所述驱动电路还包括：
    第一启动电路，用于生成第一启动信号以及第一结束信号；所述第一启动信号以及所述第一结束信号用于所述扫描线驱动电路生成所述主扫描信号；以及
    第二启动电路，用于生成第二启动信号以及第二结束信号，所述第二启动信号以及所述第二结束信号用于所述扫描线驱动电路生成所述次扫描信号。
  7. 根据权利要求6所述的驱动电路，其中所述液晶显示装置进行三维图像显示时，所述第二启动电路不生成所述第二启动信号以及所述第二结束信号。
  8. 根据权利要求3所述的驱动电路，其中所述扫描线驱动电路包括：
    主扫描信号生成模块，用于根据所述第一时钟信号以及上一级的主级联信号，生成本级的主扫描信号；
    主级联信号生成模块，用于生成本级的主级联信号；
    主驱动结束模块，用于根据下一级的主扫描信号，结束所述本级的主扫描信号；以及
    主扫描信号维持模块，用于维持本级的所述主扫描信号的低电位。
  9. 根据权利要求8所述的驱动电路，其中所述主驱动结束模块通过下拉所述本级的主扫描信号的电位，结束所述本级的主扫描信号。
  10. 根据权利要求3所述的驱动电路，其中所述扫描驱动电路包括：
    次扫描信号生成模块，用于根据所述第二时钟信号以及上一级的次级联信号，生成本级的次扫描信号；
    次级联信号生成模块，用于生成本级的次级联信号；
    次驱动结束模块，用于根据下一级的次扫描信号，结束所述本级的次扫描信号；以及
    次扫描信号维持模块，用于维持本级的所述次扫描信号的低电位。
  11. 根据权利要求10所述的驱动电路，其中所述次驱动结束模块通过下拉所述本级的次扫描信号的电位，结束所述本级的次扫描信号。
  12. 一种液晶显示装置，其包括液晶显示面板以及驱动电路，所述液晶显示面板包括数据线、扫描线以及由所述数据线和所述扫描线交错构成的多个像素单元，每个像素单元包括主像素以及次像素，所述扫描线包括主扫描线以及次扫描线；其中所述驱动电路包括：
    第一时钟信号驱动电路，用于生成第一时钟信号；
    第二时钟信号驱动电路，用于生成第二时钟信号；
    数据线驱动电路，用于生成数据信号并传输到所述数据线上；以及
    扫描线驱动电路，用于根据所述第一时钟信号，生成主扫描信号并传输到所述主扫描线上，根据所述第二时钟信号，生成次扫描信号并传输到所述次扫描线上。
  13. 根据权利要求12所述的液晶显示装置，其中所述第二时钟信号的频率高于所述第一时钟信号的频率。
  14. 根据权利要求12所述的液晶显示装置，其中所述液晶显示装置进行三维图像显示时，所述第二时钟信号驱动电路生成一恒低电平信号，使得所述主像素和所述次像素的明暗程度相同。
  15. 根据权利要求12所述的液晶显示装置，其中所述驱动电路还包括：
    第一启动电路，用于生成第一启动信号以及第一结束信号；所述第一启动信号以及所述第一结束信号用于所述扫描线驱动电路生成所述主扫描信号；以及
    第二启动电路，用于生成第二启动信号以及第二结束信号，所述第二启动信号以及所述第二结束信号用于所述扫描线驱动电路生成所述次扫描信号。
  16. 根据权利要求15所述的液晶显示装置，其中所述液晶显示装置进行三维图像显示时，所述第二启动电路不生成所述第二启动信号以及所述第二结束信号。
  17. 根据权利要求12所述的液晶显示装置，其中所述扫描线驱动电路包括：
    主扫描信号生成模块，用于根据所述第一时钟信号以及上一级的主级联信号，生成本级的主扫描信号；
    主级联信号生成模块，用于生成本级的主级联信号；
    主驱动结束模块，用于根据下一级的主扫描信号，结束所述本级的主扫描信号；以及
    主扫描信号维持模块，用于维持本级的所述主扫描信号的低电位。
  18. 根据权利要求17所述的液晶显示装置，其中所述主驱动结束模块通过下拉所述本级的主扫描信号的电位，结束所述本级的主扫描信号。
  19. 根据权利要求12所述的液晶显示装置，其中所述扫描驱动电路包括：
    次扫描信号生成模块，用于根据所述第二时钟信号以及上一级的次级联信号，生成本级的次扫描信号；
    次级联信号生成模块，用于生成本级的次级联信号；
    次驱动结束模块，用于根据下一级的次扫描信号，结束所述本级的次扫描信号；以及
    次扫描信号维持模块，用于维持本级的所述次扫描信号的低电位。
  20. 根据权利要求12所述的液晶显示装置，其中所述次驱动结束模块通过下拉所述本级的次扫描信号的电位，结束所述本级的次扫描信号。
PCT/CN2014/080841 2014-06-07 2014-06-26 驱动电路及液晶显示装置 Ceased WO2015184659A1 (zh)

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