WO2015184623A1 - 可重配的发射机和接收机及其重配方法 - Google Patents

可重配的发射机和接收机及其重配方法 Download PDF

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Publication number
WO2015184623A1
WO2015184623A1 PCT/CN2014/079270 CN2014079270W WO2015184623A1 WO 2015184623 A1 WO2015184623 A1 WO 2015184623A1 CN 2014079270 W CN2014079270 W CN 2014079270W WO 2015184623 A1 WO2015184623 A1 WO 2015184623A1
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Prior art keywords
signal
digital
analog
circuit
system clock
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PCT/CN2014/079270
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English (en)
French (fr)
Inventor
窦蕴甫
田廷剑
赵延青
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201480079145.3A priority Critical patent/CN106464281B/zh
Priority to PCT/CN2014/079270 priority patent/WO2015184623A1/zh
Publication of WO2015184623A1 publication Critical patent/WO2015184623A1/zh
Priority to US15/369,532 priority patent/US10560132B2/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H04B1/0475—Circuits with means for limiting noise, interference or distortion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/13—Monitoring; Testing of transmitters for calibration of power amplifiers, e.g. gain or non-linearity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08—Access point devices
    • H04W88/085—Access point devices with remote components

Definitions

  • the present invention relates to the field of communications, and in particular to a reconfigurable transmitter and receiver and a reconfiguration method thereof.
  • Radio remote unit Radio Remote Unit
  • RRU Radio Remote Unit
  • Analog partial digitization and support for ultra-wideband, multi-band and multi-standard will be the mainstream trend.
  • the digital IF processing function of the transceiver is becoming more and more complex, replacing some of the analog processing functions and meeting the processing requirements of ultra-wideband, multi-band and multi-standard.
  • the maximum digital intermediate frequency processing rate required by the system is generally configured to support the bandwidth, frequency band, and system variation of the processed signals.
  • the transceiver always maintains a high digital IF processing rate, which will inevitably result in some narrowband or In a scenario where the number of bands is small, RRU delay and power consumption increase, and hardware resources are wasted.
  • the embodiments of the present invention provide a reconfigurable transmitter and receiver and a reconfiguration method thereof, which can effectively reduce the digital intermediate frequency processing rate, reduce system delay, save resources, and ensure processing performance.
  • a first aspect provides a reconfigurable transmitter, comprising: a system adaptive control circuit for generating a control signal according to frequency band information of an input signal, wherein the control signal includes configuration information required for transmitter reconfiguration; and a system clock circuit a method for generating a system clock according to a control signal generated by the system adaptive control circuit; a pre-processing circuit for pre-processing the received baseband signal according to the system clock and the control signal to generate a frequency band signal; and a digital intermediate frequency processing circuit for The system clock and the control signal process the frequency band signal generated by the preprocessing circuit to generate a digital intermediate frequency signal; the digital to analog conversion circuit is configured to process the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit according to the system clock and the control signal to generate an analog signal.
  • An analog transmitting circuit for transmitting an analog signal generated by a digital to analog conversion circuit.
  • configuration information required for transmitter reconfiguration includes at least one of the following:
  • the transmitter further includes a feedback analog-to-digital conversion circuit for processing the feedback analog signal according to the system clock and the control signal to generate a digital intermediate frequency signal.
  • the digital intermediate frequency processing circuit includes a digital pre-distortion coefficient training circuit, configured to: feedback analog-to-digital conversion circuit according to system clock and control signal The generated digital intermediate frequency signal is trained in digital predistortion coefficients to generate digital predistortion coefficients.
  • the digital intermediate frequency processing circuit further includes a digital predistortion circuit, configured to: pre-predict the system clock, the control signal, and the digital pre-distortion coefficient The frequency band signal generated by the processing circuit performs digital predistortion processing to generate a digital intermediate frequency signal.
  • the system adaptive control circuit if the frequency band information of the input signal includes the frequency band information of the at least two frequency bands, the system adaptive control circuit generates the configuration information according to the at least two frequency band information respectively. .
  • the pre-processing circuit is further configured to: Generating a frequency band signal corresponding to any of the baseband signals according to a system clock and a control signal corresponding to any one of the at least two baseband signals.
  • the second aspect provides a method for reconfiguring a transmitter, including: Generating a control signal according to the frequency band information of the input signal, wherein the control signal includes configuration information required for transmitter reconfiguration; generating a system clock according to the control signal; and preprocessing the received baseband signal according to the system clock and the control signal to generate a frequency band signal;
  • the frequency band signal is processed according to the system clock and the control signal to generate a digital intermediate frequency signal;
  • the digital intermediate frequency signal is processed according to the system clock and the control signal to generate an analog signal; and the analog signal is transmitted.
  • configuration information required for transmitter reconfiguration includes at least one of the following:
  • the method further includes: processing the feedback analog signal according to the system clock and the control signal to generate a digital intermediate frequency signal.
  • the method further includes: performing digital pre-distortion coefficient training on the digital intermediate frequency signal according to the system clock and the control signal, and generating a digital pre-distortion coefficient .
  • the frequency band signal is processed according to the system clock and the control signal
  • the step of generating the digital intermediate frequency signal includes: according to the system clock, the control signal, and The digital pre-distortion coefficient performs digital pre-distortion processing on the band signal to generate a digital intermediate frequency signal.
  • the step of generating the control signal according to the frequency band information of the input signal includes: according to at least two The frequency band information respectively generates configuration information.
  • Performing pre-processing to generate a frequency band signal includes generating a frequency band signal corresponding to any of the baseband signals according to a system clock and a control signal corresponding to any one of the at least two baseband signals.
  • a third aspect provides a reconfigurable receiver, comprising: a system adaptive control circuit, configured to generate a control signal according to frequency band information of an input signal, wherein the control signal includes configuration information required for receiver reconfiguration; a circuit for generating a system clock according to a control signal generated by the system adaptive control circuit; an analog receiving circuit for receiving the analog signal; and a receiving analog-to-digital conversion circuit for simulating the receiving of the analog receiving circuit according to the system clock and the control signal
  • the signal is processed to generate a digital intermediate frequency signal;
  • the post-processing circuit is configured to process the digital intermediate frequency signal generated by the receiving analog-to-digital conversion circuit according to the system clock and the control signal to generate a baseband signal.
  • configuration information required for receiver reconfiguration includes at least one of the following:
  • the system adaptive control circuit separately generates the configuration information according to the at least two frequency band information.
  • a fourth aspect provides a reconfiguration method for a receiver, comprising: generating a control signal according to frequency band information of an input signal, wherein the control signal includes configuration information required for receiver reconfiguration; and generating according to a control signal generated by the system adaptive control circuit System clock; receiving analog signal; processing analog signal received by analog receiving circuit according to system clock and control signal to generate digital intermediate frequency signal; processing digital IF signal generated by receiving analog-to-digital conversion circuit according to system clock and control signal, generating Baseband signal.
  • the configuration information required for receiver reconfiguration includes at least one of the following:
  • the step of generating the control signal according to the frequency band information of the input signal includes: according to at least two The frequency band information respectively generates configuration information.
  • the invention generates a control signal according to the frequency band information of the input signal by the system adaptive control circuit, wherein the control signal includes configuration information required for transmitter reconfiguration, and the system clock circuit generates a system clock according to the control signal; Flexible configuration of system clock and digital IF processing rate, such as frequency and bandwidth.
  • the pre-processing circuit preprocesses the received baseband signal according to the system clock and the control signal to generate a frequency band signal;
  • the digital intermediate frequency processing circuit processes the frequency band signal generated by the pre-processing circuit according to the system clock and the control signal to generate a digital intermediate frequency signal;
  • the conversion circuit processes the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit according to the system clock and the control signal to generate an analog signal;
  • the analog transmitting circuit transmits the analog signal generated by the digital-to-analog conversion circuit, so that in any scene, for each frequency band signal
  • the processing is at the lowest possible digital intermediate frequency processing rate, which can effectively reduce the digital intermediate frequency processing rate, reduce system delay, save resources, and ensure processing performance.
  • FIG. 1 is a schematic structural view of a transmitter according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a transmitter according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a preprocessing circuit of a transmitter according to a second embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a receiver according to a first embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a receiver according to a second embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a post-processing circuit of a receiver according to a second embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a transceiver according to a first embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a transceiver according to a second embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a transmitter according to a third embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a preprocessing circuit of a transmitter according to a third embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a receiver according to a third embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a post-processing circuit of a receiver according to a third embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of a transceiver according to a third embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a transmitter according to a fourth embodiment of the present invention.
  • 15 is a schematic diagram of a pre-processing circuit at 40 MHz of a transmitter according to a fourth embodiment of the present invention.
  • 16 is a schematic diagram of a preprocessing circuit at 100 MHz of a transmitter according to a fourth embodiment of the present invention.
  • FIG. 17 is a schematic structural diagram of a receiver according to a fourth embodiment of the present invention.
  • FIG. 18 is a schematic diagram of a post-processing circuit at 40 MHz of a receiver according to a fourth embodiment of the present invention.
  • 19 is a schematic diagram of a post-processing circuit at 100 MHz of a receiver according to a fourth embodiment of the present invention.
  • FIG. 20 is a schematic structural diagram of a transceiver according to a fourth embodiment of the present invention.
  • 21 is a schematic structural diagram of a transmitter according to a fifth embodiment of the present invention.
  • Figure 22 is a schematic diagram of a pre-processing circuit at 20 MHz of the transmitter of the fifth embodiment of the present invention.
  • FIG. 23 is a schematic diagram of a pre-processing circuit at 60 MHz of a transmitter according to a fifth embodiment of the present invention.
  • Figure 24 is a block diagram showing the structure of a receiver in accordance with a fifth embodiment of the present invention.
  • 25 is a schematic diagram of a post-processing circuit at 20 MHz of the transceiver of the fifth embodiment of the present invention.
  • 26 is a schematic diagram of a post-processing circuit at 60 MHz of the transceiver of the fifth embodiment of the present invention.
  • Figure 27 is a schematic structural diagram of a transceiver according to a fifth embodiment of the present invention.
  • 29 is a flow chart showing a method of reconfiguring a receiver according to a first embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a reconfigurable transmitter according to a first embodiment of the present invention.
  • the reconfigurable transmitter 100 includes: a system adaptive control circuit 11, a system clock circuit 12, a preprocessing circuit 13, a digital intermediate frequency processing circuit 14, a digital to analog conversion circuit 15, an analog transmission circuit 18, and an antenna. 103 and circulator 104.
  • the system adaptive control circuit 11 is configured to generate a control signal according to the frequency band information of the input signal, wherein the control signal includes configuration information required for the transmitter 100 to reconfigure.
  • the system clock circuit 12 is for generating a system clock based on a control signal generated by the system adaptive control circuit 11.
  • the pre-processing circuit 13 is configured to pre-process the received baseband signal according to the system clock and the control signal to generate a frequency band signal.
  • the digital intermediate frequency processing circuit 14 is configured to process the frequency band signal generated by the preprocessing circuit 13 based on the system clock and the control signal to generate a digital intermediate frequency signal.
  • the digital-to-analog conversion circuit 15 is configured to process the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit 14 based on the system clock and the control signal to generate an analog signal.
  • the analog transmitting circuit 18 is for transmitting an analog signal generated by the digital to analog conversion circuit 15.
  • the system clock includes the clock required for digital intermediate frequency processing and the clock required for digital-to-analog conversion and analog-to-digital conversion.
  • the digital-to-analog conversion circuit 15 converts the digital intermediate frequency signal into an analog signal, and then performs analog processing on the analog signal through the analog transmitting circuit 18, including filtering, attenuation, etc., and is controlled to be transmitted from the antenna 103 via the circulator 104.
  • the input signal may be a single-band signal or a dual-band signal or even a multi-band signal, that is, the frequency band information of the input signal includes frequency band information of at least one frequency band, such as frequency band information including a single frequency band, or a frequency band of a dual frequency band.
  • the information may even be multi-band frequency band information, and the system clock and digital intermediate frequency processing rate corresponding to the frequency band information of different frequency bands may be different.
  • the control signal generated by the system adaptive control circuit 11 based on the frequency band information of the input signal includes a system clock and a digital intermediate frequency processing rate corresponding to the band information required for the transmitter 100 to reconfigure.
  • the pre-processing circuit 12 preprocesses the received baseband signal according to the system clock and the control signal to generate a frequency band signal for the digital intermediate frequency processing circuit 14 to perform subsequent digital intermediate frequency processing.
  • the present invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to different frequency band signals, so that in any scene, the processing of each frequency band signal is at the lowest possible digital intermediate frequency processing rate, and the digital intermediate frequency can be effectively reduced. Processing rate, reducing system latency, saving resources while ensuring processing performance.
  • the frequency band information of the input signal includes frequency band information of at least one frequency band.
  • the input signal is LTE (Long Term Evolution, long-term evolution) single-band signal as an example, as shown in Figure 2, the input signal bandwidth is 100MHz, the frequency is 2.35GHz, in the case of pre-distortion processing of the signal, the transmitter 200 includes: system adaptive control circuit 21.
  • the configuration process of the transmitter 200 is described as follows:
  • the digital intermediate frequency processing rate should be greater than 100 Msps, taking an integer multiple of the LTE baseband signal rate of 30.72 Msps and leaving a sufficient transition band for the digital filter to set the digital intermediate frequency processing rate to 153.6 Msps;
  • the digital-to-analog conversion sampling rate and the analog-to-digital conversion sampling rate should be greater than the signal frequency.
  • the sampling rate of the digital-to-analog conversion and the sampling rate of the analog-to-digital conversion are set at 2611.2 Msps.
  • the system adaptive control circuit 21 determines the above-described configuration information required by the transmitter 200 based on the frequency band information of the input signal, and generates a corresponding control signal.
  • the configuration information includes at least one of the following: including a system clock, or a digital intermediate frequency processing rate, or a digital-to-analog conversion sampling rate, or an analog-to-digital conversion sampling rate, specifically a digital intermediate frequency processing rate of 153.6 Msps, a digital-to-analog conversion sampling rate, and a mode.
  • the number conversion sampling rate is 2611.2Msps.
  • the system adaptive control circuit 21 can obtain the above configuration information by means of table lookup or online calculation.
  • the control signal can be a strobe signal or a configuration signal.
  • the system clock circuit 22 outputs two system clocks of 153.6 MHz and 2611.2 MHz in accordance with the control signal.
  • the pre-processing circuit 23 preprocesses the received baseband signal based on the system clock and the control signal to generate a band signal.
  • the pre-processing circuit 23 includes a second up-conversion filtering module 231 and a third spectrum shifting module 232.
  • the number of the second up-conversion filtering module 231 and the third spectrum shifting module 232 is related to the input signal bandwidth and the baseband signal bandwidth.
  • the baseband signal bandwidth is 20 MHz with an input signal bandwidth of 100 MHz Therefore, the pre-processing circuit 23 has five second up-conversion filtering modules 231 and five third spectrum shifting modules 232.
  • the pre-processing circuit 23 can have other numbers of second up-conversion filtering modules 231 and third spectrum shifting modules 232.
  • the five second up-conversion filtering modules 231 respectively up-convert the five single-carrier LTE baseband signal rates by 30.72 Msps to a sampling rate of 153.6 Msps according to the system clock and the control signal to ensure subsequent combining. There is enough processing speed.
  • the LTE baseband signal is from the indoor baseband processing unit (Building Base band Unit, BBU) is transmitted at 20MHz.
  • BBU Building Base band Unit
  • the five second up-conversion filtering modules 231 perform 5 times upsampling and then perform filtering before up-converting the LTE baseband signal.
  • the pass band of the filter can be set to [-10MHz, 10MHz]
  • the stop band is set to [-70MHz, 70MHz]
  • the attenuation is 80dBc.
  • the five third spectrum shifting modules 232 respectively move the five single-carrier baseband signals to [-40 MHz according to the system clock and the control signal. -20MHz, 0, 20MHz, At 40MHz], then combine. The bandwidth of the band signal generated after the combination becomes 100 MHz.
  • the digital intermediate frequency processing circuit 24 processes the combined frequency band signal based on the system clock and the control signal, and mainly performs peak clipping processing to obtain a digital intermediate frequency signal of 100 MHz.
  • the method of peak clipping is not limited, and may be any one of the prior art, and the digital intermediate frequency processing circuit 24 only needs to operate under the system clock of 153.6 MHz according to the control signal.
  • the digital-to-analog conversion circuit 25 processes the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit 24 based on a system clock of 153.6 MHz and a control signal to generate an analog signal.
  • the digital-to-analog conversion circuit 25 includes a first up-conversion filtering module 251, a first spectrum shifting module 252, a first digital-to-analog conversion module 253, and a first analog filtering module 254.
  • the first up-conversion filtering module 251 up-converts the digital intermediate frequency signal to the RF processing rate according to the system clock and the control signal, that is, up-converting to 2611.2 Msps at 153.6 Msps.
  • the first up-conversion filtering module 251 performs 17 times upsampling and then filters.
  • the pass band of the filter is set to [-50MHz, 50MHz], and the stop band is set to [-1250MHz, 1250MHz].
  • the RF processing rate includes a digital to analog conversion sampling rate and an analog to digital conversion sampling rate.
  • the first spectrum shifting module 252 moves the filtered signal to a frequency of 2.35 GHz.
  • the first digital to analog conversion module 253 performs digital to analog conversion on the signal of the first spectral shifting module 252 at a system clock of 2611.2 MHz.
  • the first analog filtering module 254 filters the signal output by the first digital to analog conversion module 253 to filter out the clock image.
  • the passband of the filter is [2300MHz, 2400MHz], and to filter out the image at 2611.2MHz and 1305.6MHz, the stopband of the filter is [2100MHz, 2600MHz], and the attenuation above 30dBc is guaranteed at the mirror.
  • the digital-to-analog conversion circuit 25 thus processes the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit 24 to generate an analog signal.
  • the analog transmitting circuit 28 performs analog processing on the analog signal generated by the digital-to-analog converting circuit 25, including amplification, filtering, and the like, and then transmits it through the circulator 203 and the antenna 204. In this way, the configuration of the transmitter 200 is completed.
  • the transmitter 200 uses a direct radio frequency (Direct Radio Frequency (DRF) architecture, of course, other radio frequency architectures may be employed in other embodiments of the invention.
  • DRF Direct Radio Frequency
  • the transmitter 200 may further include a feedback analog-to-digital conversion circuit (not shown) for simulating the analog transmission circuit 28 according to the system clock and the control signal.
  • the signal is processed to generate a digital signal and downconverted to a digital intermediate frequency signal of the corresponding frequency band for digital intermediate frequency processing circuit 24 to perform digital predistortion processing.
  • digital intermediate frequency processing circuit 24 also includes a digital pre-distortion coefficient training circuit and a digital pre-distortion circuit.
  • the digital pre-distortion coefficient training circuit performs digital pre-distortion coefficient training on the digital intermediate frequency signal generated by the feedback analog-to-digital conversion circuit according to the system clock and the control signal to generate a digital pre-distortion coefficient.
  • the digital predistortion circuit performs peak preprocessing on the frequency band signal generated by the preprocessing circuit according to the system clock, the control signal and the digital predistortion coefficient, and then performs digital predistortion processing to generate a digital intermediate frequency signal.
  • FIG. 4 is a schematic structural diagram of a reconfigurable receiver according to a first embodiment of the present invention.
  • the reconfigurable receiver 101 includes a system adaptive control circuit 11, a system clock circuit 12, a receiving analog to digital conversion circuit 16, a post processing circuit 17, an analog receiving circuit 19, an antenna 103, and a circulator 104.
  • the system adaptive control circuit 11 is configured to generate a control signal according to the frequency band information of the input signal, wherein the control signal includes configuration information required for the receiver 101 to reconfigure.
  • the system clock circuit 12 is for generating a system clock based on a control signal generated by the system adaptive control circuit 11.
  • the analog receiving circuit 19 is for receiving an analog signal.
  • the receiving analog-to-digital conversion circuit 16 is configured to process the analog signal received by the analog receiving circuit 19 according to the system clock and the control signal to generate a digital intermediate frequency signal.
  • the post-processing circuit 17 is operative to process the digital intermediate frequency signal generated by the received analog-to-digital conversion circuit 16 based on the system clock and the control signal to generate a baseband signal.
  • the system clock includes the clock required for analog-to-digital conversion and the clock required for post-processing.
  • the received analog signal is received from the antenna 103 and transmitted to the analog receiving circuit 19 through the circulator 104.
  • the analog receiving circuit 19 performs analog processing including filtering, amplification, and the like on the analog signal, and then transmits the analog signal to the receiving analog converting circuit 16 for further processing. .
  • the input signal may be a single-band signal or a dual-band signal or even a multi-band signal, that is, the frequency band information of the input signal includes frequency band information of at least one frequency band, such as frequency band information including a single frequency band, or a frequency band of a dual frequency band.
  • the information may even be multi-band frequency band information, and the system clock and digital intermediate frequency processing rate corresponding to the frequency band information of different frequency bands may be different.
  • the control signal generated by the system adaptive control circuit 11 based on the frequency band information of the input signal includes a system clock and a digital intermediate frequency processing rate corresponding to the band information required for the receiver 101 to reconfigure.
  • the invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to different frequency band signals, so that in any scenario, the processing of each frequency band signal is at the lowest possible digital intermediate frequency processing rate, and the digital intermediate frequency can be effectively reduced. Processing rate, reducing system latency, saving resources while ensuring processing performance.
  • the input signal is an LTE single-band signal as an example. As shown in FIG. 5, the input signal bandwidth is 100 MHz, and the frequency is 2.35 GHz.
  • the receiver 201 includes: a system adaptive control circuit 21, a system clock circuit 22, and a receiving.
  • the configuration process of the receiver 201 is described as follows:
  • the analog-to-digital conversion sampling rate should be greater than the signal frequency.
  • the LTE baseband signal rate of 30.72Msps and the analog filter transition band, digital-to-analog conversion sampling rate and analog-to-digital conversion sampling rate. It is 2611.2Msps.
  • the system adaptive control circuit 21 determines the above configuration information required by the transceiver based on the frequency band information of the input signal, and generates a corresponding control signal.
  • the configuration information includes at least one of the following: a system clock, or a digital intermediate frequency processing rate, or a digital-to-analog conversion sampling rate, or an analog-to-digital conversion sampling rate, specifically a digital intermediate frequency processing rate of 153.6 Msps, and an analog-to-digital conversion sampling rate of 2611.2 Msps.
  • the system adaptive control circuit 21 can obtain the above configuration information by means of table lookup or online calculation.
  • the control signal can be a strobe signal or a configuration signal.
  • the system clock circuit 22 outputs two system clocks of 153.6 MHz and 2611.2 MHz in accordance with the control signal.
  • the analog signal received through the antenna 203 is transmitted to the analog receiving circuit 29 via the circulator 204, and the analog receiving circuit 29 performs analog processing on the received analog signal, including filtering, amplification, and the like.
  • the receiving analog-to-digital conversion circuit 26 then converts the analog signal received by the analog receiving circuit 29 into a digital signal based on the system clock and the control signal, and performs down-conversion processing to generate a digital intermediate frequency signal.
  • the receiving analog-to-digital conversion circuit 26 includes a first down conversion filter module 261, a second spectrum shifting module 262, a first analog to digital conversion circuit 263, and a second analog filtering module 264.
  • the second analog filtering module 264 performs analog filtering on the analog signal processed by the analog receiving circuit 29, and has the same analog filtering effect as the first analog filtering module 254 in the first digital-to-analog conversion circuit 25, and the parameter settings are the same, no longer Narration.
  • the first analog-to-digital conversion circuit 263 performs analog-to-digital conversion on the analog-filtered analog signal according to a system clock of 2611.2 MHz and a control signal.
  • the second spectrum shifting module 262 moves the sampled digital signal on the 2.35 GHz carrier frequency to zero frequency.
  • the first down conversion filter module 261 downconverts the digital signal at zero frequency to a processing rate of 153.6 Msps.
  • the first down-conversion filter module 261 filters first, and then performs 17-times extraction to obtain a digital intermediate frequency signal.
  • the bandwidth of the digital intermediate frequency signal is 100 MHz
  • the passband of the filter is [-50 MHz, 50 MHz]
  • the stop band is set to [-70MHz, 70MHz]
  • the attenuation is 80dBc.
  • the post-processing circuit 27 is operative to process the digital intermediate frequency signal generated by the received analog-to-digital conversion circuit 26 based on the system clock and the control signal to generate a baseband signal.
  • the post-processing circuit 27 includes a fourth spectrum shifting module 271 and a second down-conversion filtering module 272.
  • the number of the fourth spectrum shifting module 271 and the second down-conversion filtering module 272 is related to the input signal bandwidth and the baseband signal bandwidth.
  • the baseband signal bandwidth is 20 MHz with an input signal bandwidth of 100 MHz Therefore, the post-processing circuit 27 has five fourth spectrum shifting modules 271 and five second down-conversion filtering modules 272.
  • the post-processing circuit 27 may have other numbers of fourth spectrum shifting modules 271 and second down-conversion filtering modules 272.
  • the second down-conversion filtering module 272 performs signal separation on the 100 MHz digital intermediate frequency signal generated by the receiving analog-to-digital conversion circuit 26, that is, the five second down-conversion filtering modules 272 respectively perform spectrum shifting on the digital intermediate frequency signal, and the frequency of the moving frequency is respectively separated. For [-40MHz, -20MHz, 0, 20MHz, 40MHz], then the five signals are filtered separately, and other carrier signals are filtered out to obtain five single carrier signals.
  • the passband of the filter is [-9.015MHz, 9.015MHz], the stopband is [-10MHz, 10MHz], and the attenuation is 80dBc.
  • the five fourth spectrum shifting modules 271 respectively extract the five single-carrier signals by 5 times, down-convert to a baseband processing rate of 30.72 Msps, and obtain a baseband signal for transmission to the BBU, thus completing the configuration of the receiver 201.
  • the transmitter and receiver can also be integrated in one transceiver.
  • the transmitter 100 and the receiver 101 are integrated as a transceiver 10.
  • the system adaptive control circuit 11 generates a control signal according to the frequency band information of the input signal, wherein the control signal includes configuration information required for the reconfiguration of the transceiver 10, specifically, the frequency band information required for the reconfiguration of the transceiver 10 System clock and digital IF processing rate.
  • the system clock circuit 12 generates a system clock based on a control signal generated by the system adaptive control circuit 11.
  • the system clock includes the clock required for digital IF processing and the clock required for digital to analog conversion and analog to digital conversion.
  • the reconfiguration of the transceiver 10 is referred to the transmitter 100 and the receiver 101, and details are not described herein.
  • the structure of the transceiver 20 is as shown in FIG. 8 without pre-distortion processing the signal, wherein the system adaptive control circuit 21 generates the frequency band information based on the input signal.
  • the control signal wherein the control signal includes configuration information required for transceiver 20 reconfiguration.
  • the system clock circuit 22 generates a system clock based on the control signal generated by the system adaptive control circuit 21.
  • the reconfiguration of the transceiver 20 is referred to the transmitter 200 and the receiver 201, and details are not described herein.
  • the system adaptive control circuit 31 When the signal bandwidth becomes 40MHz and the frequency becomes 1.9GHz, the digital intermediate frequency processing rate becomes 61.44MHz, and the digital-to-analog conversion sampling rate and the module analog-to-digital conversion sampling rate are 221. Msps, therefore requires two system clocks: 61.44MHz and 2211.84MHz, and reconfigures the transmitter according to the above configuration information.
  • the system adaptive control circuit 31 generates a control signal based on the frequency band information of the input signal, wherein the control signal includes configuration information required for the reconfiguration of the transmitter 300.
  • the system clock circuit 32 generates two system clocks of 61.44 MHz and 2611.2 MHz based on the above configuration information.
  • the pre-processing circuit 33 preprocesses the received baseband signal according to a system clock of 61.44 MHz and a control signal to generate a band signal.
  • the pre-processing circuit 33 includes a second up-conversion filter module 331 and a third spectrum shift module 332.
  • the number of the second up-conversion filtering module 331 and the third spectrum shifting module 332 is related to the input signal bandwidth and the baseband signal bandwidth.
  • the input signal bandwidth is 40 MHz, so the pre-processing circuit 27 has two second up-conversion filtering modules 331 and two third spectrum shifting modules 332.
  • the two second up-conversion filtering modules 331 respectively up-convert two 20MHz single-carrier LTE baseband signal rates of 30.72Msps to a sampling rate of 61.44Msps according to the system clock and the control signal to ensure sufficient processing after the subsequent combining. rate.
  • the two second up-conversion filtering modules 331 perform up-times upsampling and then perform filtering before upconverting the LTE baseband signal.
  • the passband of the filter can be set to [-10MHz, 10MHz]
  • the stopband is set to [-30MHz, 30MHz]
  • the attenuation is 80dBc.
  • the two third spectrum shifting modules 332 respectively move the two single-carrier baseband signals to [-10 MHz according to the system clock and the control signal. At 10MHz], then combine.
  • the bandwidth of the band signal generated after the combination becomes 40 MHz.
  • the digital intermediate frequency processing circuit 34 processes the frequency band signal generated after the combination according to the system clock and the control signal to generate a digital intermediate frequency signal, mainly performing peak clipping processing to generate a 40 MHz digital intermediate frequency signal.
  • the method of peak clipping is not limited, and may be any one of the prior art, and the digital intermediate frequency processing circuit 34 only needs to operate under the system clock of 61.44 MHz according to the control signal.
  • the digital-to-analog conversion circuit 35 processes the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit 34 based on the system clock and the control signal of 61.44 MHz to generate an analog signal.
  • the first digital-to-analog conversion circuit 35 includes a first up-conversion filtering module 351, a first spectrum shifting module 352, a first digital-to-analog conversion module 353, and a first analog filtering module 354.
  • the first up-conversion filter module 351 up-converts the digital intermediate frequency signal to the RF processing rate according to the 61.44 MHz system clock and the control signal, that is, 61.44 Msps upconversion to 2211.84 Msps.
  • the first up-conversion filtering module 351 performs 36 times upsampling and then filters.
  • the pass band of the filter is set to [-20MHz, 20MHz], and the stop band is set to [-1050MHz, 1050MHz].
  • the RF processing rate includes a digital to analog conversion sampling rate and an analog to digital conversion sampling rate.
  • the first spectrum shifting module 352 moves the filtered signal to a frequency of 1.9 GHz.
  • the first digital-to-analog conversion module 353 performs digital-to-analog conversion on the signal of the first spectrum shifting module 352 at a system clock of 2211.84 MHz.
  • the first analog filtering module 354 filters the signal output by the first digital to analog conversion module 353 to filter out the clock image.
  • the passband of the filter is [1880MHz, 1920MHz], the stopband of the filter is [1600MHz, 2200MHz], and the attenuation above 30dBc is guaranteed at the mirror.
  • the first digital-to-analog conversion circuit 35 processes the digital intermediate frequency signal to the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit 34 to generate an analog signal, and the analog transmitting circuit 38 performs analog processing on the analog signal generated by the digital-to-analog conversion circuit 35, including Amplification, filtering, etc. are then transmitted through circulator 304 and antenna 303.
  • the transmitter 300 adopts a direct radio frequency architecture. Of course, other radio frequency architectures may be used in other embodiments of the present invention. The configuration of the transmitter 200 is thus completed.
  • the digital IF processing rate is reduced from the original 153.6Msps to 61.144Msps, and the digital-to-analog conversion sampling rate is reduced from 2611.2Msps to 2211.84Msps.
  • the processing rate is greatly reduced and the implementation is simpler. It can be seen that the present invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to the carrier frequency and bandwidth of signals of different frequency bands, so that the processing of each frequency band signal can be reduced at the lowest possible digital intermediate frequency processing rate to effectively reduce the number.
  • the IF processing rate reduces system latency, saves resources, and guarantees processing performance.
  • the transmitter 300 may further include a feedback analog-to-digital conversion circuit (not shown) for simulating the analog transmission circuit 38 according to the system clock and the control signal.
  • the signal is processed to generate a digital signal and downconverted to a digital intermediate frequency signal of the corresponding frequency band for digital intermediate frequency processing circuit 34 to perform digital predistortion processing.
  • digital intermediate frequency processing circuit 34 also includes a digital pre-distortion coefficient training circuit and a digital pre-distortion circuit.
  • the digital pre-distortion coefficient training circuit performs digital pre-distortion coefficient training on the digital IF signal generated by the feedback analog-to-digital conversion circuit according to the system clock and the control signal, and generates a digital pre-distortion coefficient.
  • the digital predistortion circuit performs peak preprocessing on the frequency band signal generated by the preprocessing circuit according to the system clock, the control signal and the digital predistortion coefficient, and then performs digital predistortion processing to generate a digital intermediate frequency signal.
  • the system adaptive control circuit 31 When the signal bandwidth becomes 40MHz and the frequency becomes 1.9GHz, the receiver is reconfigured, and the module analog-to-digital conversion sampling rate is 221. . Msps.
  • the system adaptive control circuit 31 generates a control signal based on the frequency band information of the input signal, wherein the control signal includes configuration information required for the receiver 301 to reconfigure.
  • the system clock circuit 32 generates two system clocks of 61.44 MHz and 2611.2 MHz according to the control signal generated by the system adaptive control circuit 31.
  • the receiver 301 When receiving the signal, the receiver 301 transmits the analog signal received through the antenna 303 to the analog receiving circuit 39 via the circulator 304, and receives the analog signal received by the analog-to-digital conversion circuit 36 from the analog receiving circuit 39 according to the system clock and control signal of 221. . Processing is performed to generate a digital signal and downconverted to a digital intermediate frequency signal.
  • the receiving analog-to-digital conversion circuit 36 includes a first down conversion filter module 361, a second spectrum shifting module 362, a first analog to digital conversion circuit 363, and a second analog filtering module 364.
  • the second analog filtering module 364 performs analog filtering on the analog signal received by the analog receiving circuit 39 according to the system clock and control signal of 2211.84 MHz, which is the same as the analog filtering function of the first analog filtering module 354 in the first digital-to-analog conversion circuit 35.
  • the parameter settings are also the same and will not be described again.
  • the first analog-to-digital conversion circuit 363 performs analog-to-digital conversion on the analog-filtered analog signal according to a system clock of 2211.84 MHz and a control signal.
  • the second spectrum shifting module 362 moves the sampled digital signal on the 1.9 GHz carrier frequency to zero frequency according to the system clock and control signal of 221. .88 MHz.
  • the first down conversion filter module 361 downconverts the digital signal at zero frequency to a processing rate of 61.44 Msps according to a system clock of 2211.84 MHz and a control signal.
  • the first down-conversion filter module 361 filters first, and then performs 36-times extraction to obtain a digital intermediate frequency signal with a bandwidth of 40 MHz.
  • the passband of the filter is [-20 MHz, 20 MHz], and the stopband is set to [-30 MHz, 30MHz], the attenuation is 80dBc.
  • the post-processing circuit 37 is operative to process the digital intermediate frequency signal generated by the received analog-to-digital conversion circuit 36 based on the system clock and control signal of 61.44 MHz to generate a baseband signal.
  • the post-processing circuit 37 includes a fourth spectrum shifting module 371 and a second down-conversion filtering module 372.
  • the number of the fourth spectrum shifting module 371 and the second down-conversion filtering module 372 is related to the input signal bandwidth and the baseband signal bandwidth.
  • the input signal bandwidth is 40 MHz, so the post-processing circuit 37 has two fourth spectrum shifting modules 371 and two second down-conversion filtering modules 372.
  • the second down-conversion filtering module 372 performs signal separation on the 40 MHz digital intermediate frequency signal generated by the receiving analog-to-digital conversion circuit 36 according to the system clock control and control signal of 61.44 MHz, that is, the two second down-conversion filtering modules 372 respectively respectively perform the digital intermediate frequency.
  • the signal is shifted by the spectrum, and the frequency of the shift is [-10MHz, 10MHz], then filter the two signals separately, filter out other carrier signals, and get two single carrier signals.
  • the passband of the filter is [-9.015MHz, 9.015MHz], the stopband is [-10MHz, 10MHz], and the attenuation is 80dBc.
  • the two fourth spectrum shifting modules 371 respectively extract the two single carrier signals by two times according to the system clock and the control signal of 61.44 MHz, down-convert to a baseband processing rate of 30.72 Msps, and generate a baseband signal for transmission to the BBU.
  • the analog-to-digital conversion sampling rate is reduced from 2611.2 Msps to 2211.84 Msps, and the processing rate is greatly reduced, and the implementation is simpler.
  • the present invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to the carrier frequency and bandwidth of signals of different frequency bands, so that the processing of each frequency band signal can be reduced at the lowest possible digital intermediate frequency processing rate to effectively reduce the number.
  • the IF processing rate reduces system latency, saves resources, and guarantees processing performance.
  • the transmitter 300 and the receiver 301 can be integrated into the transceiver 30 as shown in FIG.
  • the system adaptive control circuit 31 generates a control signal according to the frequency band information of the input signal, wherein the control signal includes configuration information required for the transceiver 30 to reconfigure.
  • the system clock circuit 32 generates a system clock based on the control signal generated by the system adaptive control circuit 31.
  • the reconfiguration of the transceiver 30 is referred to the transmitter 300 and the receiver 301, and details are not described herein.
  • the frequency band information of the input signal may further include frequency band information of at least two frequency bands.
  • the bandwidth of the first frequency band is 40 MHz
  • the frequency point is 1.9 GHz
  • the bandwidth of the second frequency band is 100 MHz
  • the frequency point is 2.35 GHz.
  • the transmitter 400 includes: a system adaptive control circuit 41, a system clock circuit 42, a preprocessing circuit 43, a digital intermediate frequency processing circuit 44, and a digital to analog conversion circuit 45.
  • the configuration process of the transmitter 400 is described as follows:
  • the system adaptive control circuit 41 generates a control signal based on the band information of the input signal.
  • the control signal includes configuration information required for reconfiguration of the transmitter 400, and the configuration information includes at least one of the following: a system clock, or a digital intermediate frequency processing rate, or a digital to analog conversion sampling rate, or an analog to digital conversion sampling rate.
  • the digital intermediate frequency processing rate should be greater than 240 Msps, and the integer frequency of the LTE baseband signal rate of 30.72 Msps needs to be taken.
  • the digital intermediate frequency processing rate is set to 368.64 Msps; for the second frequency band of 100 MHz, consider the effect of eliminating the third-order distortion component and considering the influence of the second frequency band of 40 MHz, the number
  • the IF processing rate should be greater than 300 Msps, while taking an integer multiple of the LTE baseband signal rate of 30.72 Msps and leaving enough transition bands for the digital filter, thus setting the digital intermediate frequency processing rate to 368.64 Msps.
  • the digital-to-analog conversion sampling rate and the analog-to-digital conversion sampling rate should be greater than the signal frequency. Consider the integer multiple of 30.72 Msps and the transition band of the analog filter.
  • the sampling rate of the digital-to-analog conversion and the sampling rate of the analog-to-digital conversion are determined to be 2941.12 Msps. Therefore, according to these two rates, it is necessary to output two system clocks of 368.64 MHz and 2949.12 MHz.
  • the system adaptive control circuit 41 may determine the configuration information by means of table lookup or online calculation, etc., and the generated control signal may be a strobe signal or a configuration signal. These configuration information determined by the system adaptive control circuit 41 is used for adaptive control of other parts of the system.
  • the system clock circuit 42 outputs two system clocks of 368.64 MHz and 2949.12 MHz according to the control signal.
  • the pre-processing circuit 43 preprocesses the received baseband signal according to a system clock of 368.64 MHz and a control signal to generate a band signal. Specifically, as shown in FIG. 15 and FIG. 16 , the pre-processing circuit 43 includes a fifth up-conversion filtering module 431 , an eleventh spectrum shifting module 432 , a sixth up-conversion filtering module 433 , and a seventh up-conversion filtering module 434 .
  • the number of the fifth up-conversion filtering module 431 and the eleventh spectrum shifting module 432 is related to the dual-band input signal bandwidth and the baseband signal bandwidth.
  • the dual-band input signal includes a first frequency band having a bandwidth of 40 MHz and a second frequency band having a bandwidth of 100 MHz, and thus the pre-processing circuit 43 has seven fifth up-conversion filtering modules 431 and seven eleventh spectrum shifting. Module 432.
  • the two fifth up-conversion filtering modules 431 combine the two single-carrier 20 MHz zero-frequency signals into one 40 MHz zero-IF signal according to the system clock and the control signal of 368.64 MHz, specifically, The two fifth up-conversion filter modules 431 first perform up-conversion up-conversion to a sampling rate of 122.88 Msps, and then filter, the passband of the filter can be set to [-10 MHz, 10 MHz], and the stop band is set to [-50 MHz] , 50MHz], the attenuation is 80dBc.
  • the two eleventh spectrum shifting modules 432 move the two carriers to the [-10 MHz, 10 MHz] frequency point, and combine to generate a 40 MHz zero intermediate frequency signal.
  • the sixth up-conversion filtering module 433 performs up-conversion of the combined signal by 3 times up-conversion to a sampling rate of 368.64 Msps, and performs filtering, and the passband of the filter is set to [-20 MHz, 20 MHz], and the stop band is set to [-160MHz, 160MHz], the attenuation is 80dBc.
  • the five fifth up-conversion filtering modules 431 combine five single-carrier 20 MHz zero-frequency signals into one 100 MHz zero-IF signal according to the system clock and the control signal, specifically, five fifths.
  • the frequency conversion filter module 431 first performs up-conversion up-conversion to a sampling rate of 122.88 Msps, and then filters, the passband of the filter can be set to [-10 MHz, 10 MHz], and the stop band is set to [-50 MHz, 50 MHz], attenuation. It is 80dBc.
  • the five eleventh spectrum shifting modules 432 move the five single carriers to [-40MHz, -20MHz, 0, 20MHz, respectively.
  • the seventh up-conversion filtering module 434 performs up-conversion of the combined signal by 3 times up-conversion to a sampling rate of 368.64 Msps, and performs filtering, and the passband of the filter is set to [-50 MHz, 50 MHz], and the stop band is set to [-130MHz, 130MHz], the attenuation is 80dBc.
  • the pre-processing circuit 43 outputs one frequency band signal, and both have a sampling rate of 368.64 Msps for subsequent digital intermediate frequency processing.
  • the two signals may also be different sampling rates.
  • the digital intermediate frequency processing circuit 44 processes the frequency band signal generated by the preprocessing circuit 43 based on the system clock and the control signal to generate a digital intermediate frequency signal.
  • the digital intermediate frequency processing circuit 44 further includes a digital predistortion coefficient training circuit and a digital predistortion circuit, and the digital predistortion coefficient training circuit outputs the digital intermediate frequency signal and the digital predistortion circuit generated by the feedback analog to digital conversion circuit 48 according to the system clock and the control signal.
  • the digital intermediate frequency signal is trained by the digital pre-distortion coefficient to generate a digital pre-distortion coefficient; the digital pre-distortion circuit performs peak pre-distortion processing on the frequency band signal generated by the pre-processing circuit 43 according to the system clock, the control signal and the digital pre-distortion coefficient. , generating a digital intermediate frequency signal.
  • the digital intermediate frequency processing circuit 44 includes a first peak clipping module 441, a first frequency band digital predistortion circuit 442, a second peak clipping module 443, a second frequency band digital predistortion circuit 444, and a first frequency band digital predistortion coefficient training circuit. 445 and a second band digital predistortion coefficient training circuit 446.
  • the first peak clipping module 441 performs peak clipping processing on the frequency band signal output by the preprocessing circuit 43 based on the first frequency band according to the system clock and the control signal of 368.64 MHz.
  • the first band digital predistortion circuit 442 performs digital predistortion on the signal peaked by the first peak clipping module 441 according to the system clock and control signals of 368.64 MHz and the predistortion coefficients generated by the first band digital predistortion coefficient training circuit 445. Processing, generating a digital intermediate frequency signal corresponding to the first frequency band.
  • the first band digital predistortion circuit 442 is also affected by the band signal after the second peak clipping module 443 performs peak clipping processing based on the second frequency band when performing digital predistortion processing.
  • the second peak clipping module 443 performs peak clipping processing on the frequency band signal output by the preprocessing circuit 43 based on the second frequency band according to the system clock and the control signal.
  • the second band digital predistortion circuit 444 digitally pre-processes the frequency band signal subjected to the peak clipping process by the second peak clipping module 443 according to the system clock of 368.64 MHz, the control signal, and the predistortion coefficient generated by the second band digital predistortion coefficient training circuit 446.
  • Distortion processing generates a digital intermediate frequency signal corresponding to the second frequency band.
  • the second band digital predistortion circuit 444 is also subjected to the influence of the band signal after the peak clipping process performed by the first peak clipping module 441 based on the first frequency band when the digital predistortion process is performed.
  • the first frequency band digital predistortion coefficient training circuit 445 and the second frequency band digital predistortion coefficient training circuit 446 are respectively performing digital predistortion coefficients on the digital intermediate frequency signals generated by the feedback analog to digital conversion circuit 48 according to the system clock and the control signal of 368.64 MHz. Train to generate digital pre-distortion coefficients.
  • the digital-to-analog conversion circuit 45 is operative to process the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit 44 based on the system clock and control signal of 2949.12 MHz to generate an analog signal.
  • the digital-to-analog conversion circuit 45 includes: a third up-conversion filtering module 451, a fifth spectrum shifting module 452, a fourth up-conversion filtering module 453, a sixth spectrum shifting module 454, a second digital-to-analog conversion module 455, and a third Analog filtering module 456.
  • the third up-conversion filtering module 451 up-converts the digital intermediate frequency signal of the frequency band to the radio frequency processing rate according to the system clock and control signal of 2949.12 MHz, that is, 368.64 Msps upconverts to 2949.12 Msps.
  • the RF processing rate includes a digital-to-analog conversion sampling rate and an analog-to-digital conversion sampling rate.
  • the third up-conversion filtering module 451 first performs 8 times up-conversion to a sampling rate of 2941.12 Msps, and then filters.
  • the pass band of the filter is set to [-120MHz, 120MHz], and the stop band is set to [-1300MHz, 1300MHz] , the attenuation is 80dBc.
  • the fifth spectrum shifting module 452 moves the filtered signal to a frequency of 1.9 GHz.
  • the fourth up-conversion filtering module 453 up-converts the digital intermediate frequency signal of the frequency band to the radio frequency processing rate according to the system clock and control signal of 2949.12 MHz, that is, 368.64 Msps upconverts to 2949.12 Msps.
  • the fourth up-conversion filtering module 453 first performs 8 times up-conversion to a sampling rate of 2949.12 Msps, and then filters.
  • the pass band of the filter is set to [-120MHz, 120MHz], and the stop band is set to [-1300MHz, 1300MHz] , the attenuation is 80dBc.
  • the sixth spectrum shifting module 454 moves the filtered signal to a frequency of 2.35 GHz.
  • the digital-to-analog conversion circuit 45 combines the signal output by the fifth spectrum shifting module 452 based on the first frequency band and the signal output by the sixth frequency spectrum shifting module 454 based on the second frequency band, and the second digital-to-analog conversion module 455 is based on 2949.12 MHz.
  • the system clock and the control signal perform digital-to-analog conversion on the combined signals to generate an analog signal.
  • the third analog filtering module 456 filters the analog signal output by the second digital to analog conversion module 455 to filter out the clock image.
  • the passband of the filter is [1700MHz, 2500MHz]
  • the stopband of the filter is [1500MHz, 2900MHz]
  • the attenuation above 30dBc is guaranteed at the mirror.
  • the digital to analog conversion circuit 45 converts the two digital intermediate frequency signals into a dual band analog signal.
  • the analog transmitting circuit 405 performs analog processing on the dual-band analog signal generated by the digital-to-analog converting circuit 45, including amplification, filtering, and the like, and then transmits it through the circulator 404 and the antenna 403.
  • a coupler (not shown) is further included in front of the circulator 404 to feed back the analog signal output from the analog transmitting circuit 405 to the analog feedback circuit 406.
  • the feedback analog-to-digital conversion circuit 48 processes the feedback dual-band analog signal according to the system clock and control signal of 2949.12 MHz to generate a digital intermediate frequency signal.
  • the feedback analog-to-digital conversion circuit 48 includes: a third down conversion filter module 481, a seventh spectrum shift module 482, a fourth down conversion filter module 483, an eighth spectrum shift module 484, a second analog to digital conversion module 485, and a fourth analog filter. Module 486.
  • the fourth analog filtering module 486 performs analog filtering on the feedback analog signal, and has the same function as the analog filtering performed by the third analog filtering module 456, and the parameter settings are also the same, and will not be described again.
  • the second analog-to-digital conversion module 485 performs analog-to-digital conversion on the analog signal processed by the analog filtering according to a system clock and a control signal of 2949.12 MHz.
  • the seventh spectrum shifting module 482 moves the sampled digital signal on the 1.9 GHz carrier frequency to the zero frequency according to the system clock and control signal of 2949.12 MHz, and the third down conversion filtering module 481 again Down-converting to a processing rate of 368.64 Msps, specifically filtering first, and then performing 8-times decimation to generate a digital intermediate frequency signal corresponding to the frequency band.
  • the passband of the filter is [-120MHz, 120MHz], the stopband is set to [-180MHz, 180MHz], and the attenuation is 80dBc.
  • the first band predistortion coefficient training circuit 445 performs digital predistortion coefficient training on the digital intermediate frequency signal for digital predistortion processing of the band signal of the first frequency band.
  • the eighth spectrum shifting module 484 moves the sampled digital signal on the 2.35 GHz carrier frequency to the zero frequency according to the system clock and the control signal of 2949.12 MHz, and the fourth down conversion filtering module 483 again Down-converting to a processing rate of 368.64 Msps, specifically filtering first, and then performing 8-times decimation to generate a digital intermediate frequency signal corresponding to the frequency band.
  • the passband of the filter is [-150MHz, 150MHz], the stopband is set to [-180MHz, 180MHz], and the attenuation is 80dBc.
  • the second band predistortion coefficient training circuit 446 performs digital predistortion coefficient training on the digital intermediate frequency signal for digital predistortion processing of the band signal of the second frequency band.
  • the configuration of the transmitter 400 is completed in this manner.
  • the transmitter 400 adopts a direct radio frequency architecture.
  • other radio frequency architectures may be used in other embodiments of the present invention.
  • the input signal is an LTE dual-band signal, that is, in the frequency band information of the input signal, the bandwidth of the first frequency band is 40 MHz, the frequency point is 1.9 GHz, the bandwidth of the second frequency band is 100 MHz, and the frequency point is 2.35 GHz.
  • the receiver 401 includes a system adaptive control circuit 41, a system clock circuit 42, a receiving analog-to-digital conversion circuit 46, a post-processing circuit 47, an analog receiving circuit 49, an antenna 403, and a circulator 404.
  • the configuration process of the receiver 401 is described as follows:
  • the system adaptive control circuit 41 in the receiver 401 generates a control signal based on the band signal of the input signal.
  • the control signal includes configuration information required for reconfiguration of the transmitter 400, and the configuration information includes at least one of the following: a system clock, or a digital intermediate frequency processing rate, or a digital to analog conversion sampling rate, or an analog to digital conversion sampling rate.
  • the control signal generated by the system adaptive control circuit 41 includes a digital intermediate frequency processing rate of 368.64 Msps and an analog-to-digital conversion sampling rate of 2949.12 Msps for adaptive control of other parts of the system.
  • the system clock circuit 42 outputs two system clocks of 368.64 MHz and 2949.12 MHz according to the control signal.
  • the dual-band analog signal received through the antenna 403 is transmitted to the analog receiving circuit 49 via the circulator 404, and the analog receiving circuit 49 performs analog processing on the received dual-band analog signal, including filtering, amplification, and the like.
  • the receiving analog-to-digital conversion circuit 46 processes the dual-band analog signal received by the analog receiving circuit 49 according to the system clock and control signal of 2949.12 MHz to generate a digital intermediate frequency signal.
  • the receiving analog-to-digital conversion circuit 46 includes: a fifth down conversion filtering module 461, a ninth spectrum shifting module 462, a sixth down conversion filtering module 463, a tenth spectrum shifting module 464, a third analog to digital conversion circuit 465, and a fifth simulation.
  • the fifth analog filtering module 466 performs analog filtering on the dual-band analog signal received by the analog receiving circuit 49, and has the same function as the analog filtering performed by the third analog filtering module 456, and the parameter settings are also the same, and will not be described again.
  • the third analog-to-digital conversion circuit 465 performs analog-to-digital conversion on the analog signal subjected to the analog filtering processing by the fifth analog filtering module 466 according to the system clock and the control signal of 2949.12 MHz.
  • the ninth spectrum shifting module 462 moves the sampled digital signal on the 1.9 GHz carrier frequency to the zero frequency according to the system clock and the control signal of 2949.12 MHz, and the fifth down conversion filtering module 461 further downconverts the signal to 368.64 Msps.
  • the rate is specifically filtered first, and then 8-times decimation is performed to obtain a digital intermediate frequency signal corresponding to the first frequency band of 40 MHz.
  • the passband of the filter is [-20MHz, 20MHz], the stopband is set to [-180MHz, 180MHz], and the attenuation is 80dBc.
  • the tenth spectrum shifting module 464 moves the sampled digital signal on the 2.35 GHz carrier frequency to the zero frequency according to the system clock and control signal of 2949.12 MHz, and the sixth down conversion filtering module 463 further downconverts the signal to 368.64 Msps.
  • the rate specifically, is filtered first, and then 8-times decimation is performed to obtain a digital intermediate frequency signal corresponding to the second frequency band of 100 MHz.
  • the passband of the filter is [-50MHz, 50MHz], the stopband is set to [-180MHz, 180MHz], and the attenuation is 80dBc.
  • the post-processing circuit 47 is operative to process the digital intermediate frequency signal generated by the received analog-to-digital conversion circuit 46 based on the system clock and control signal of 368.64 MHz to generate a baseband signal. As shown in FIGS. 18 and 19, the post-processing circuit 47 includes a twelfth spectrum shifting module 471 and a seventh down-conversion filtering module 472. The number of the twelfth spectrum shifting module 471 and the seventh down-conversion filtering module 472 is related to the dual-band input signal bandwidth and the baseband signal bandwidth.
  • the dual-band input signal includes a first frequency band having a bandwidth of 40 MHz and a second frequency band having a bandwidth of 100 MHz, and thus the post-processing circuit 47 has seven twelfth spectrum shifting modules 471 and seven seventh down-conversion filters. Module 472.
  • the two twelfth spectrum shifting modules 471 perform signal separation on the 40 MHz digital intermediate frequency signal, that is, the frequency shifting of the 40 MHz digital intermediate frequency signals respectively, and the frequency of the moving is [-10 MHz, respectively). 10MHz].
  • the two seventh down conversion filtering modules 472 filter the two signals, filter out other carrier signals, and obtain two single carrier signals, and the two seventh down conversion filtering modules 472 respectively perform 12 on the two single carrier signals.
  • the passband of the filter is [-9.015MHz, 9.015MHz]
  • the stopband is [-10MHz, 10MHz]
  • the attenuation is 80dBc.
  • the five twelfth spectrum shifting modules 471 perform signal separation on the 100 MHz digital intermediate frequency signal, that is, the frequency shifting of the 100 MHz digital intermediate frequency signals respectively, and the frequency of the moving is [-40 MHz, -20 MHz, respectively).
  • the five seventh down-conversion filtering modules 472 filter the five signals, and filter out other carrier signals to obtain five single-carrier signals.
  • the five seventh down-conversion filtering modules 472 respectively perform 12-times extraction on the five single-carrier signals, down-converting to a baseband processing rate of 30.72 Msps, and generating a baseband signal.
  • the pass band of the filter is also [-9.015MHz, 9.015MHz], the stop band is [-10MHz, 10MHz], and the attenuation is 80dBc, thus completing the configuration of the receiver 401.
  • the transmitter 400 and the receiver 401 can be integrated into the transceiver 40.
  • the input signal is an LTE dual-band signal, wherein the bandwidth of the first frequency band is 40 MHz, the frequency point is 1.9 GHz, the bandwidth of the second frequency band is 100 MHz, and the frequency point is 2.35 GHz.
  • the system adaptive control circuit 41 generates a control signal based on the frequency band information of the input signal, wherein the control signal includes configuration information required for the transceiver 40 to reconfigure.
  • the system clock circuit 42 generates a system clock based on the control signal generated by the system adaptive control circuit 41.
  • the reconfiguration of the transceiver 40 is referred to the transmitter 400 and the receiver 401, and details are not described herein.
  • the transmitter 500 includes: a system adaptive control circuit 51, a system clock circuit 52, a pre-processing circuit 53, a digital intermediate frequency processing circuit 54, a digital-to-analog conversion circuit 55, a feedback analog-to-digital conversion circuit 58, and an antenna 503.
  • the system adaptive control circuit 51 generates a control signal based on the frequency band information of the input signal.
  • the control signal includes configuration information required for reconfiguration of the transmitter 500, and the configuration information includes at least one of the following: a system clock, or a digital intermediate frequency processing rate, or a digital to analog conversion sampling rate, or an analog to digital conversion sampling rate.
  • the digital intermediate frequency processing rate is set to 184.32 Msps
  • the digital intermediate frequency processing rate is set to 368.64 Msps
  • the digital-to-analog conversion sampling rate and analog-to-digital conversion corresponding to the two frequency bands are determined.
  • the sampling rate is set at 2941.12 Msps.
  • the system adaptive control circuit 51 generates different configuration information according to the two frequency band information, and can determine the configuration information by using a table lookup or online calculation, etc., for adaptive control of other parts of the system, and the generated control signal. It can be a strobe signal or a configuration signal.
  • the system clock circuit 52 outputs three system clocks of 184.32 MHz, 368.64 MHz, and 2949.12 MHz according to the control signal.
  • the pre-processing circuit 53 pre-processes the received baseband signal according to the system clock and the control signal to generate a frequency band signal. If the system adaptive control circuit 51 generates different configuration information according to the at least two frequency band information, the pre-processing circuit 53 is further configured to generate, according to the system clock and the control signal corresponding to any one of the at least two baseband signals. A band signal corresponding to any baseband signal. Specifically, the pre-processing circuit 53 upconverts the baseband signal to a rate of 184.32 Msps and 368.64 Msps, respectively, based on the system clock and the control signal for subsequent pre-distortion processing. As shown in FIG. 22 and FIG.
  • the pre-processing circuit 53 includes a fifth up-conversion filtering module 531, an eleventh spectrum shifting module 532, a sixth up-conversion filtering module 533, and a seventh up-conversion filtering module 534.
  • the number of the fifth up-conversion filtering module 531 and the eleventh spectrum shifting module 532 is related to the dual-band input signal bandwidth and the baseband signal bandwidth.
  • the dual-band input signal includes a first frequency band with a bandwidth of 20 MHz and a second frequency band with a bandwidth of 60 MHz, so the pre-processing circuit 53 has four fifth up-conversion filtering modules 531 and three eleventh frequency bands. Move module 532.
  • the sixth up-conversion filtering module 533 and the seventh up-conversion filtering module 534 in the pre-processing circuit 53 each have two.
  • the fifth up-conversion filtering module 531 up-converts the baseband signal based on the first frequency band to a sampling rate of 92.16 Msps and filters it, and the passband of the filter can be set to [- 10MHz, 10MHz], the stop band is set to [-35MHz, 35MHz], and the attenuation is 80dBc.
  • the sixth up-conversion filtering module 533 performs up-conversion up-conversion to a sampling rate of 184.32 Msps and performs filtering to generate a frequency band signal based on the first frequency band, and the passband of the filter can be set to [-10 MHz, 10 MHz].
  • the stop band is set to [-80MHz, 80MHz] and the attenuation is 80dBc.
  • the three fifth up-conversion filtering modules 531 up-convert the baseband signal based on the second frequency band to a sampling rate of 92.16 Msps and filter it, and the passband of the filter can be set to [-10 MHz, 10 MHz].
  • the stop band is set to [-35MHz, 35MHz] and the attenuation is 80dBc.
  • the three eleventh spectrum shifting modules 532 move the three carriers to the [-20MHz, 0, 20MHz] frequency points and combine them.
  • the sixth up-conversion filtering module 533 further double-samples the combined signal to a sampling rate of 184.32 Msps and filters the signal to generate a frequency band signal related to the second frequency band, and the passband of the filter can be set to [-30MHz, 30MHz], the stop band is set to [-60MHz, 60MHz], and the attenuation is 80dBc.
  • the pre-processing circuit 53 outputs two frequency band signals each having a sampling rate of 184.32 Msps for digital intermediate frequency processing, one of which is a frequency band signal associated with the second frequency band of 60 MHz.
  • the fifth up-conversion filtering module 531 up-converts the baseband signal based on the first frequency band to a sampling rate of 92.16 Msps and filters it, and the passband of the filter can be set to [- 10MHz, 10MHz], the stop band is set to [-35MHz, 35MHz], and the attenuation is 80dBc.
  • the seventh up-conversion filtering module 534 performs up-conversion up-conversion to a sampling rate of 368.64 Msps and performs filtering to generate a frequency band signal related to the first frequency band, and the passband of the filter can be set to [-10 MHz, 10 MHz].
  • the stop band is set to [-170MHz, 170MHz] and the attenuation is 80dBc.
  • the three fifth up-conversion filtering modules 531 up-convert the baseband signal based on the second frequency band to a sampling rate of 92.16 Msps and filter it, and the passband of the filter can be set to [-10 MHz, 10 MHz].
  • the stop band is set to [-35MHz, 35MHz] and the attenuation is 80dBc.
  • the three eleventh spectrum shifting modules 532 move the three carriers to the [-20MHz, 0, 20MHz] frequency points and combine them.
  • the seventh up-conversion filtering module 534 further up-converts the combined signal to a sampling rate of 368.64 Msps and filters the signal to generate a frequency band signal based on the second frequency band, and the passband of the filter can be set to [ -30MHz, 30MHz], the stop band is set to [-150MHz, 150MHz], and the attenuation is 80dBc.
  • the pre-processing circuit 53 outputs two frequency band signals each having a sampling rate of 368.64 Msps for digital intermediate frequency processing, one of which is a frequency band signal associated with the first frequency band of 20 MHz.
  • the digital intermediate frequency processing circuit 54 processes the frequency band signal generated by the preprocessing circuit 53 based on the system clock and the control signal to generate a digital intermediate frequency signal. It can be used for digital predistortion processing by the digital intermediate frequency processing circuit 54.
  • the digital intermediate frequency processing circuit 54 includes a digital predistortion coefficient training circuit and a digital predistortion circuit, and the digital predistortion coefficient training circuit performs digital predistortion coefficients on the digital intermediate frequency signal generated by the feedback analog to digital conversion circuit 58 according to the system clock and the control signal. Train to generate digital pre-distortion coefficients.
  • the digital predistortion circuit performs digital predistortion processing on the frequency band signal generated by the preprocessing circuit 53 according to the system clock, the control signal, and the digital predistortion coefficient to generate a digital intermediate frequency signal.
  • the digital intermediate frequency processing circuit 54 includes a first peak clipping module 541, a first frequency band digital predistortion circuit 542, a second peak clipping module 543, a second frequency band digital predistortion circuit 544, and a first frequency band digital predistortion coefficient training circuit. 545 and a second band digital predistortion coefficient training circuit 546.
  • the first peak clipping module 541 performs peak clipping processing on the two frequency band signals based on the first frequency band generated by the preprocessing circuit 53 according to the system clock and the control signal of 184.32 MHz.
  • the first band digital predistortion circuit 542 performs the two band signals that are peak-processed by the first peak clipping module 541 according to the system clock of 184.22 MHz, the control signal, and the predistortion coefficient generated by the first band digital predistortion coefficient training circuit 545.
  • Digital predistortion processing generates a digital intermediate frequency signal corresponding to the first frequency band.
  • the digital pre-distortion coefficient is a digital intermediate frequency signal and a feedback modulus corresponding to the first frequency band generated by the first-band digital pre-distortion coefficient training circuit 545 according to the system clock and the control signal of 184.32 MHz to the first-band digital pre-distortion circuit 542.
  • the digital intermediate frequency signal of the corresponding frequency band generated by the conversion circuit 58 is trained by digital predistortion coefficients.
  • the second peak clipping module 543 performs peak clipping processing on the two frequency band signals based on the second frequency band generated by the preprocessing circuit 53 according to the system clock and the control signal of 368.64 MHz.
  • the second band digital predistortion circuit 544 performs two band signals that are peak-processed by the second peak clipping module 543 according to a system clock of 368.64 MHz, a control signal, and a predistortion coefficient generated by the second band digital predistortion coefficient training circuit 546.
  • Digital predistortion processing generates a digital intermediate frequency signal corresponding to the second frequency band.
  • the digital pre-distortion coefficient is a second-band digital pre-distortion coefficient training circuit 546 is a digital intermediate frequency signal corresponding to the second frequency band and a feedback mode generated by the second-band digital pre-distortion circuit 544 according to a system clock and a control signal of 368.64 MHz.
  • the digital signal of the corresponding frequency band generated by the number conversion circuit 58 is obtained by training the digital predistortion coefficient.
  • the digital-to-analog conversion circuit 55 is configured to process the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit 54 based on the system clock and control signal of 2949.12 MHz to generate an analog signal.
  • the digital-to-analog conversion circuit 55 includes: a third up-conversion filtering module 551, a fifth spectrum shifting module 552, a fourth up-conversion filtering module 553, a sixth spectrum shifting module 554, a second digital-to-analog conversion module 555, and a third Analog filter module 556.
  • the third up-conversion filtering module 551 up-converts the digital intermediate frequency signal corresponding to the first frequency band to the radio frequency processing rate according to the system clock and control signal of 2949.12 MHz, that is, up to 294.32 Msps up to 294.32 Msps.
  • the RF processing rate includes a digital-to-analog conversion sampling rate and an analog-to-digital conversion sampling rate.
  • the third up-conversion filtering module 551 first performs 16-fold up-conversion to a sampling rate of 2949.12 Msps, and then filters.
  • the pass band of the filter is set to [-70MHz, 70MHz], and the stop band is set to [-1350MHz, 1350MHz] , the attenuation is 80dBc.
  • the fifth spectrum shifting module 552 moves the filtered signal to a frequency of 1.9 GHz.
  • the fourth up-conversion filtering module 553 up-converts the digital intermediate frequency signal corresponding to the second frequency band to the radio frequency processing rate according to the system clock and control signal of 2949.12 MHz, that is, 368.64 Msps up-converts to 2947.12 Msps.
  • the fourth up-conversion filtering module 553 first performs 8 times up-conversion to a sampling rate of 2941.12 Msps, and then filters.
  • the pass band of the filter is set to [-90MHz, 90MHz], and the stop band is set to [-1350MHz, 1350MHz] , the attenuation is 80dBc.
  • the sixth spectrum shifting module 554 moves the filtered signal to a frequency of 2.35 GHz.
  • the digital-to-analog conversion circuit 55 combines the signal output by the fifth spectrum shifting module 552 based on the first frequency band and the signal output by the sixth frequency spectrum shifting module 554 based on the second frequency band, and the second digital-to-analog conversion module 555 is based on 2949.12 MHz.
  • the system clock and the control signal perform digital-to-analog conversion on the combined signals to generate an analog signal.
  • the third analog filtering module 556 filters the analog signal generated by the second digital to analog conversion module 555 to filter out the clock image.
  • the passband of the filter is [1700MHz, 2500MHz]
  • the stopband of the filter is [1500MHz, 2900MHz]
  • the attenuation above 30dBc is guaranteed at the mirror.
  • the digital to analog conversion circuit 55 thus converts the two digital intermediate frequency signals into dual frequency analog signals.
  • the analog transmitting circuit 505 performs analog processing on the dual-band analog signal generated by the digital-to-analog converting circuit 55, including amplification, filtering, and the like, and then transmits it through the circulator 504 and the antenna 503.
  • a coupler (not shown) is further included in front of the circulator 504 to feed back the analog signal output by the analog transmitting circuit 505 to the analog feedback circuit 506.
  • the feedback analog-to-digital conversion circuit 58 processes the system clock of 2949.12 MHz and the dual-band analog signal fed back by the control signal to generate a digital intermediate frequency signal.
  • the feedback analog-to-digital conversion circuit 58 includes: a third down conversion filter module 581, a seventh spectrum shift module 582, a fourth down conversion filter module 583, an eighth spectrum shift module 584, a second analog to digital conversion module 585, and a fourth analog filter. Module 586.
  • the fourth analog filtering module 586 performs analog filtering on the feedback analog signal, and has the same function as the analog filtering performed by the third analog filtering module 556, and the parameter settings are also the same, and will not be described again.
  • the second analog-to-digital conversion module 585 performs analog-to-digital conversion on the analog signal processed by the analog filtering according to a system clock and a control signal of 2949.12 MHz. Since the digital intermediate frequency processing rates of the two frequency bands are different, the feedback analog to digital conversion circuit 58 needs to downconvert the signals of the two frequency bands to the rates of 184.32 Msps and 368.64 Msps, respectively, for subsequent digital predistortion coefficient training.
  • the seventh spectrum shifting module 582 moves the sampled digital signal on the 1.9 GHz carrier frequency to the zero frequency according to the system clock and the control signal of 2949.12 MHz, and the third down conversion filtering module 581 It is downconverted to a processing rate of 184.32 Msps, specifically filtered first, and then 16 times extracted to generate a digital intermediate frequency signal corresponding to the first frequency band.
  • the passband of the filter is [-70MHz, 70MHz], the stopband is set to [-90MHz, 90MHz], and the attenuation is 80dBc.
  • the seventh spectrum shifting module 582 also shifts the digital signal on the sampled 2.35GHz carrier frequency.
  • the first band predistortion coefficient training circuit 545 performs digital predistortion coefficient training on the two digital intermediate frequency signals and the digital intermediate frequency signal corresponding to the first frequency band generated by the first frequency band digital predistortion circuit 542 for the first frequency band signal. Digital predistortion processing.
  • the eighth spectrum shifting module 584 moves the sampled digital signal on the 1.9 GHz carrier frequency to the zero frequency according to the system clock and the control signal of 2949.12 MHz, and the fourth down conversion filtering module 583 lowers the digital signal.
  • the frequency is converted to a processing rate of 368.64 Msps, specifically filtered first, and then extracted 8 times to generate a digital intermediate frequency signal corresponding to the first frequency band.
  • the passband of the filter is [-90MHz, 90MHz], the stopband is set to [-180MHz, 180MHz], and the attenuation is 80dBc; at the same time, the eighth spectrum shifting module 584 is also sampled according to the system clock and control signal of 2949.12MHz.
  • the digital signal on the 2.35 GHz carrier frequency is moved to the zero frequency, and the fourth down conversion filtering module 583 downconverts it to the processing rate of 368.64 Msps, specifically filtering first, then performing 8 times extraction, generating and the second frequency band.
  • the passband of the filter is [-90MHz, 90MHz], the stopband is set to [-180MHz, 180MHz], and the attenuation is 80dBc.
  • the second band pre-distortion coefficient training circuit 546 performs digital pre-distortion coefficient training on the two-band digital intermediate frequency signal and the digital intermediate frequency signal corresponding to the second frequency band generated by the second-band digital pre-distortion circuit 544 for the second frequency band signal.
  • the transmitter 500 adopts a direct radio frequency architecture.
  • other radio frequency architectures may be used in other embodiments of the present invention.
  • the digital intermediate frequency processing rate of the first frequency band is reduced from the original 368.64 Msps to 184.32 Msps, and the processing rate is greatly reduced, and the implementation is simpler.
  • the present invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to the carrier frequency and bandwidth of signals of different frequency bands, so that the processing of each frequency band signal can be reduced at the lowest possible digital intermediate frequency processing rate to effectively reduce the number.
  • the IF processing rate reduces system latency, saves resources, and guarantees processing performance.
  • the receiver 501 includes a system adaptive control circuit 51, a system clock circuit 52, a reception analog-to-digital conversion circuit 56, a post-processing circuit 57, an analog receiving circuit 59, an antenna 503, and a circulator 504.
  • the reconfiguration process of receiver 501 is described as follows:
  • the system adaptive control circuit 51 Like the transmitter 500, the system adaptive control circuit 51 generates a control signal based on the band information of the input signal.
  • the control signal includes configuration information required for reconfiguration of the receiver 501, and the configuration information includes at least one of the following: a system clock, or a digital intermediate frequency processing rate, or a digital-to-analog conversion sampling rate, or an analog-to-digital conversion sampling rate.
  • the control signal generated by the system adaptive control circuit 51 includes a digital intermediate frequency processing rate of 184.32 Msps applied to the first frequency band of 20 MHz, and a digital intermediate frequency processing of 368.64 Msps applied to the second frequency band of 60 MHz.
  • the rate and the analog to digital conversion sampling rate of 2949.12 Msps are used for adaptive control of other parts of the receiver 501.
  • the system clock circuit 52 outputs three system clocks of 184.32 MHz, 368.64 MHz, and 2949.12 MHz according to the control signal.
  • the dual-band analog signal received through the antenna 503 is transmitted to the analog receiving circuit 59 via the circulator 504, and the analog receiving circuit 59 performs analog processing on the received dual-band analog signal, including filtering, amplification, and the like.
  • the receiving analog-to-digital conversion circuit 56 processes the dual-band analog signal received by the analog receiving circuit 59 based on the system clock and control signal of 2949.12 MHz to generate a digital intermediate frequency signal.
  • the receiving analog-to-digital conversion circuit 56 includes: a fifth down conversion filter module 561, a ninth spectrum shift module 562, a sixth down conversion filter module 563, a tenth spectrum shift module 564, a third analog to digital conversion circuit 565, and a fifth analog filter.
  • the fifth analog filtering module 566 performs analog filtering on the dual-band analog signal received by the analog receiving circuit 59, and has the same function as the analog filtering performed by the third analog filtering module 556, and the parameter settings are the same, and will not be described again.
  • the third analog-to-digital conversion circuit 565 performs analog-to-digital conversion on the analog signal subjected to the analog filtering processing by the fifth analog filtering module 566 according to the system clock and the control signal of 2949.12 MHz.
  • the ninth spectrum shifting module 562 moves the sampled digital signal on the 1.9 GHz carrier frequency to the zero frequency according to the system clock and control signal of 2949.12 MHz, and the fifth down-conversion filtering module 561 further down-converts the processing to the processing of 184.32 Msps.
  • the rate is specifically filtered first, and then 16 times extracted to obtain a digital intermediate frequency signal corresponding to the first frequency band of 20 MHz.
  • the pass band of the filter is [-10 MHz, 10 MHz], and the stop band is set to [-90 MHz, 90 MHz] , the attenuation is 80dBc.
  • the ninth spectrum shifting module 562 also moves the sampled digital signal on the 2.35 GHz carrier frequency to the zero frequency according to the system clock and control signal of 2949.12 MHz, and the fifth down conversion filtering module 561 further downconverts it to 368.64 Msps.
  • the processing rate is specifically filtered first, and then 8 times extraction is performed to obtain a digital intermediate frequency signal corresponding to the second frequency band of 60 MHz.
  • the pass band of the filter is [-30 MHz, 30 MHz], and the stop band is set to [-180 MHz, 180 MHz. ], the attenuation is 80dBc.
  • the receiving analog-to-digital conversion circuit 56 thus processes the dual-band analog signals received by the analog receiving circuit 59 to generate two digital intermediate frequency signals based on 20 MHz and 60 MHz, respectively.
  • the post-processing circuit 57 is operative to process the digital intermediate frequency signal generated by the received analog-to-digital conversion circuit 56 based on the system clock and the control signal to generate a baseband signal. As shown in FIGS. 25 and 26, the post-processing circuit 57 includes a seventh down-conversion filter module 571 and a twelfth spectrum shift module 572. The number of the seventh down conversion filter module 571 and the twelfth spectrum shift module 572 is related to the dual band input signal bandwidth and the baseband signal bandwidth.
  • the dual-band input signal includes a first frequency band having a bandwidth of 20 MHz and a second frequency band having a bandwidth of 60 MHz, so that the post-processing circuit 57 has four seventh down-conversion filtering modules 571 and three twelfth spectrum shifting. Module 572.
  • the seventh down conversion filtering module 571 filters the 20 MHz digital intermediate frequency signal according to the system clock and the control signal of 184.32 MHz, and the pass band of the filter is [-9.015 MHz, 9.015 MHz], and the stop band is [-10MHz, 10MHz], the attenuation is 80dBc, then the filtered signal is extracted 6 times, down-converted to the baseband processing rate of 30.72Msps, and the baseband signal is generated.
  • the three twelfth spectrum shifting modules 572 perform signal separation on the 60 MHz digital intermediate frequency signal, that is, three times of frequency shifting on the 60 MHz digital intermediate frequency signal, and the frequency of the moving is [-20 MHz, 0, respectively. , 20MHz], then filter the three signals, filter out other carrier signals, and get three single carrier signals.
  • the passband of the filter is [-9.015MHz, 9.015MHz]
  • the stopband is [-10MHz, 10MHz]
  • the attenuation is 80dBc.
  • the three seventh down-conversion filtering modules 571 respectively perform 12-times extraction on three single-carrier signals, down-convert to a baseband processing rate of 30.72 Msps, and generate a baseband signal.
  • the digital intermediate frequency processing rate of the first frequency band is reduced from the original 368.64 Msps to 184.32 Msps, and the processing rate is greatly reduced, and the implementation is simpler. It can be seen that the present invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to the carrier frequency and bandwidth of signals of different frequency bands, so that the processing of each frequency band signal can be reduced at the lowest possible digital intermediate frequency processing rate to effectively reduce the number.
  • the IF processing rate reduces system latency, saves resources, and guarantees processing performance.
  • the transmitter 500 and the receiver 501 can be integrated into the transceiver 50.
  • the input signal is an LTE dual-band signal, wherein the bandwidth of the first frequency band is 20 MHz, the frequency point is 1.9 GHz, the bandwidth of the second frequency band is 60 MHz, and the frequency point is 2.35 GHz.
  • the system adaptive control circuit 51 generates a control signal according to the frequency band information of the input signal, wherein the control signal includes configuration information required for the transceiver 50 to reconfigure.
  • the system clock circuit 52 generates a system clock based on the control signal generated by the system adaptive control circuit 51.
  • the reconfiguration of the transceiver 50 is referred to the transmitter 500 and the receiver 501, and details are not described herein.
  • FIG. 28 is a schematic flowchart diagram of a method for reconfiguring a transmitter according to a first embodiment of the present invention. As shown in FIG. 28, the reconfiguration method of the transmitter includes:
  • S10 Generate a control signal according to the frequency band information of the input signal, where the control signal includes configuration information required for transmitter reconfiguration.
  • the frequency band information of the input signal includes frequency band information of at least one frequency band, that is, the input signal may be a single-band signal or a dual-band signal or even a multi-band signal.
  • the control signal is a strobe signal or a configuration signal.
  • the configuration information required for transmitter reconfiguration includes at least one of the following: a system clock, or a digital intermediate frequency processing rate, or a digital to analog conversion sampling rate, or an analog to digital conversion sampling rate. If the frequency band information of the input signal includes frequency band information of at least two frequency bands, configuration information is respectively generated according to at least two frequency band information, wherein the digital intermediate frequency processing rates may be the same or different.
  • the input signal as an LTE dual-band signal as an example, if the input signal includes a first frequency band with a bandwidth of 40 MHz, a frequency of 1.9 GHz, a bandwidth of 100 MHz, and a second frequency band of 2.35 GHz, the first frequency band of 40 MHz is used.
  • the digital intermediate frequency processing rate can be set to 368.64 Msps, and the digital-to-analog conversion sampling rate and the analog-to-digital conversion sampling rate can be set to 2491.12 Msps; for the second frequency band of 100 MHz, the digital intermediate frequency processing rate and the digital-to-analog conversion sampling rate and analog-to-digital conversion
  • the sampling rate can be set to 368.64Msps And 2941.12Msps.
  • the digital intermediate frequency processing rate can be set to 184.32 Msps for the first frequency band of 20 MHz.
  • the digital-to-analog conversion sampling rate and the analog-to-digital conversion sampling rate can be set to 2941.12 Msps; for the second frequency band of 60 MHz, the digital intermediate frequency processing rate can be set to 368.64 Msps, and the digital-to-analog conversion sampling rate and the analog-to-digital conversion sampling rate are set to 2294.12. Msps.
  • the system clock includes the clock required for pre-processing and digital intermediate frequency processing, and the clock required for digital-to-analog conversion and analog-to-digital conversion.
  • the input signal includes a first frequency band with a bandwidth of 20 MHz, a frequency of 1.9 GHz, and a second frequency band with a bandwidth of 60 MHz and a frequency of 2.35 GHz
  • the generated system clock has three: 184.32 MHz, 368.64.
  • S12 Pre-process the received baseband signal according to the system clock and the control signal to generate a frequency band signal.
  • the preprocessing includes upconversion, filtering, and the like. If different configuration information is generated according to at least two frequency band information in S10, then in S12, any baseband is generated according to a system clock and a control signal corresponding to any one of the at least two baseband signals. The frequency band signal corresponding to the signal.
  • the frequency band signal generated by the preprocessing is mainly subjected to peak clipping or the like according to the system clock and the control signal.
  • the feedback analog signal is converted into a digital signal according to the system clock and the control signal, and down-converted into a digital intermediate frequency signal.
  • Digital predistortion processing and digital predistortion coefficient training are also available. Specifically, the analog IF signal is processed according to the system clock and the control signal, and the digital IF signal is generated; the digital IF signal is trained on the digital IF signal according to the system clock and the control signal to generate a digital predistortion coefficient; according to the system clock, The control signal and the digital pre-distortion coefficient perform digital pre-distortion processing on the frequency band signal generated in S12 to generate a digital intermediate frequency signal.
  • S14 Processing the digital intermediate frequency signal according to the system clock and the control signal to generate an analog signal.
  • the digital intermediate frequency signal is up-converted to a required digital-to-analog conversion sampling rate according to the system clock and the control signal, and then the spectrum is moved to the working frequency point of the corresponding frequency band, and then the analog signal is generated by digital-to-analog conversion and analog filtering.
  • the frequency band information of the input signal includes the frequency band information of the at least two frequency bands
  • the digital intermediate frequency signal of the corresponding frequency band is upconverted to the digital-to-analog conversion sampling rate required by the corresponding frequency band according to the system clock and the control signal, and the spectrum shift is performed.
  • signals of different frequency bands are combined to obtain a dual-band or multi-band signal, and then subjected to digital-to-analog conversion and analog filtering to generate an analog signal.
  • the digital-to-analog conversion sampling rate may be the same or different.
  • the analog signal generated after the analog filtering is subjected to analog processing such as amplification and filtering, and then transmitted through the circulator and the antenna.
  • analog processing such as amplification and filtering
  • the reconfiguration of the transmitter is completed.
  • the present invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to the carrier frequency and bandwidth of signals of different frequency bands, so that the processing of each frequency band signal is as low as possible.
  • the digital intermediate frequency processing rate is effectively reduced, the system delay is reduced, resources are saved, and processing performance is guaranteed.
  • FIG. 29 is a schematic flowchart diagram of a reconfiguration method of a receiver according to a first embodiment of the present invention. As shown in FIG. 29, the reconfiguration method of the receiver includes:
  • S20 Generate a control signal according to the frequency band information of the input signal, where the control signal includes configuration information required for receiver reconfiguration.
  • the band information of the input signal includes band information of at least one band, that is, the input signal may be a single band signal or a dual band signal or even a multi band signal.
  • the control signal is a strobe signal or a configuration signal.
  • the configuration information required for receiver reconfiguration includes at least one of the following: a system clock, or a digital intermediate frequency processing rate, or a digital to analog conversion sampling rate, or an analog to digital conversion sampling rate. If the frequency band information of the input signal includes the frequency band information of at least two frequency bands, the configuration information is separately generated based on the at least two frequency band information.
  • the digital intermediate frequency processing rate may be the same or different.
  • S21 Generate a system clock according to a control signal generated by the system adaptive control circuit.
  • the system clock includes the clock required for pre-processing and digital intermediate frequency processing and the clock required for digital-to-analog conversion.
  • the input signal includes a first frequency band with a bandwidth of 20 MHz, a frequency of 1.9 GHz, and a second frequency band with a bandwidth of 60 MHz and a frequency of 2.35 GHz
  • the generated system clock has three: 184.32 MHz, 368.64. MHz and 2941.12 MHz, of which 184.22 MHz and 368.64 MHz is used for digital intermediate frequency processing of the first frequency band of 20 MHz and the second frequency band of 60 MHz, respectively, and 2294.12 MHz is used for analog-to-digital conversion of the two frequency bands.
  • S22 Receive an analog signal. Wherein the analog signal is received by the antenna and the circulator for subsequent processing.
  • the analog signal After receiving the analog signal, the analog signal is filtered, amplified, and so on.
  • the analog signal is filtered according to the system clock and the control signal, and converted into a digital signal by a certain digital-to-analog conversion sampling rate. Then the spectrum is shifted to zero frequency, and the frequency is converted to a digital intermediate frequency. signal. If the frequency band information of the input signal includes frequency band information of at least two frequency bands, the digital signals on different carrier frequencies are moved to zero frequency, and then down-converted to digital intermediate frequency signals of the corresponding frequency bands.
  • the received analog signal is digital-to-analog converted to a digital signal at 1.9 GHz.
  • the carrier frequency and the carrier frequency of 2.35 GHz each have a corresponding frequency band signal.
  • the digital signals on the two carrier frequencies obtained by sampling are respectively moved to zero frequency and down-converted to respectively A digital intermediate frequency signal with a bandwidth of 20 MHz and a bandwidth of 60 MHz is obtained.
  • S24 The digital intermediate frequency signal is processed according to the system clock and the control signal to generate a baseband signal.
  • the frequency band information of the input signal includes the frequency band information of at least two frequency bands, it is necessary to down-convert the at least two digital intermediate frequency signals to generate a baseband signal corresponding to the frequency band.
  • the digital intermediate frequency signal is a multi-carrier signal
  • the digital intermediate frequency signal needs to be separated after performing the down-conversion processing, that is, the digital intermediate frequency signal is spectrally shifted, and then filtered to obtain a plurality of single-carrier signals, and the signal is obtained.
  • the bandwidth is the same as the bandwidth of the baseband signal.
  • the present invention can flexibly configure the system clock and the digital intermediate frequency processing rate according to the carrier frequency and bandwidth of signals of different frequency bands, so that the processing of each frequency band signal is as low as possible.
  • the digital intermediate frequency processing rate is effectively reduced, the system delay is reduced, resources are saved, and processing performance is guaranteed.
  • the present invention generates a control signal according to the frequency band information of the input signal by the system adaptive control circuit, wherein the control signal includes configuration information required for transmitter reconfiguration, and the system clock circuit generates a system clock according to the control signal;
  • the carrier frequency and bandwidth of signals of different frequency bands are flexibly configured for the system clock and digital intermediate frequency processing rate.
  • the pre-processing circuit preprocesses the received baseband signal according to the system clock and the control signal to generate a frequency band signal;
  • the digital intermediate frequency processing circuit processes the frequency band signal generated by the pre-processing circuit according to the system clock and the control signal to generate a digital intermediate frequency signal;
  • the conversion circuit processes the digital intermediate frequency signal generated by the digital intermediate frequency processing circuit according to the system clock control and the control signal to generate an analog signal;
  • the analog transmitting circuit transmits the analog signal generated by the digital-to-analog conversion circuit, so that the processing of each frequency band signal is as
  • the low digital intermediate frequency processing rate can effectively reduce the digital intermediate frequency processing rate, reduce system delay, save resources, and ensure processing performance.

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Abstract

本发明公开了一种可重配的发射机和接收机及其重配方法，包括：系统自适应控制电路根据输入信号的频带信息生成控制信号，系统时钟电路生成系统时钟；预处理电路根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号；数字中频处理电路根据系统时钟和控制信号对频带信号进行处理，生成数字中频信号；数模转换电路根据系统时钟和控制信号对数字中频信号进行处理，生成模拟信号；模拟发射电路发射模拟信号。通过上述方式，本发明能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置，使得每个频带信号的处理在尽可能低的数字中频处理速率下，可以减小系统时延，节省资源。

Description

可重配的发射机和接收机及其重配方法
【技术领域】
本发明涉及通信领域，特别是涉及一种可重配的发射机和接收机及其重配方法。
【背景技术】
随着射频技术的不断成熟和器件成本的不断下降，功率放大器、数模转换器等模拟器件向着宽带化的方向不断发展，射频拉远单元(Radio Remote Unit ，RRU)模拟部分数字化和支持超宽带、多频带和多制式将是主流的发展趋势。为了顺应这些趋势，收发机的数字中频处理功能越来越复杂，以替代部分模拟处理功能并满足超宽带、多频带和多制式的处理要求。现有的收发机中，一般是按照系统所需的最大数字中频处理速率来进行配置，以支持处理信号的带宽、频带数和制式变化。这种做法虽然简单易行，但是却存在一些问题，即无论输入信号是什么制式，带宽多宽，频带数有多少，收发机始终维持较高的数字中频处理速率，必然会造成在一些窄带或频带数少的场景下，RRU时延和功耗增加，浪费硬件资源。
【发明内容】
有鉴于此，本发明实施例提供了一种可重配的发射机和接收机及其重配方法，能够有效降低数字中频处理速率，减小系统时延，节省资源，同时能够保证处理性能。
第一方面提供一种可重配的发射机，包括：系统自适应控制电路，用于根据输入信号的频带信息生成控制信号，其中控制信号包括发射机重配所需的配置信息；系统时钟电路，用于根据系统自适应控制电路生成的控制信号生成系统时钟；预处理电路，用于根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号；数字中频处理电路，用于根据系统时钟和控制信号对预处理电路生成的频带信号进行处理，生成数字中频信号；数模转换电路，用于根据系统时钟和控制信号对数字中频处理电路生成的数字中频信号进行处理，生成模拟信号；模拟发射电路，用于发射数模转换电路生成的模拟信号。
结合第一方面的实现方式，在第一种可能的实现方式中，发射机重配所需的配置信息包括如下至少一种：
系统时钟；或，
数字中频处理速率；或，
数模转换采样率；或，
模数转换采样率。
结合第一方面的实现方式，在第二种可能的实现方式中，发射机还包括反馈模数转换电路，用于根据系统时钟和控制信号对反馈的模拟信号进行处理，生成数字中频信号。
结合第一方面的第二种可能的实现方式，在第三种可能的实现方式中，数字中频处理电路包括数字预失真系数训练电路，用于：根据系统时钟和控制信号对反馈模数转换电路生成的数字中频信号进行数字预失真系数训练，生成数字预失真系数。
结合第一方面的第三种可能的实现方式，在第四种可能的实现方式中，数字中频处理电路还包括数字预失真电路，用于：根据系统时钟、控制信号以及数字预失真系数对预处理电路生成的频带信号进行数字预失真处理，生成数字中频信号。
结合第一方面的实现方式，在第五种可能的实现方式中，若输入信号的频带信息包括至少两个频带的频带信息，则系统自适应控制电路根据至少两个频带信息，分别生成配置信息。
结合第一方面的第五种可能的实现方式，在第六种可能的实现方式中，若系统自适应控制电路根据至少两个频带信息，分别生成不同的配置信息，则预处理电路还用于：根据至少两个基带信号中的任一基带信号对应的系统时钟和控制信号，生成与任一基带信号对应的频带信号。
第二方面提供一种发射机的重配方法，包括： 根据输入信号的频带信息生成控制信号，其中控制信号包括发射机重配所需的配置信息；根据控制信号生成系统时钟；根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号；根据系统时钟和控制信号对频带信号进行处理，生成数字中频信号；根据系统时钟和控制信号对数字中频信号进行处理，生成模拟信号；发射模拟信号。
结合第二方面的实现方式，在第一种可能的实现方式中，发射机重配所需的配置信息包括如下至少一种：
系统时钟；或，
数字中频处理速率；或，
数模转换采样率；或，
模数转换采样率。
结合第二方面的实现方式，在第二种可能的实现方式中，该方法还包括：根据系统时钟和控制信号对反馈的模拟信号进行处理，生成数字中频信号。
结合第二方面的第二种可能的实现方式，在第三种可能的实现方式中，该方法还包括：根据系统时钟和控制信号对数字中频信号进行数字预失真系数训练，生成数字预失真系数。
结合第二方面的第三种可能的实现方式，在第四种可能的实现方式中，根据系统时钟和控制信号对频带信号进行处理，生成数字中频信号的步骤包括：根据系统时钟、控制信号以及数字预失真系数对频带信号进行数字预失真处理，生成数字中频信号。
结合第二方面的实现方式，在第五种可能的实现方式中，若输入信号的频带信息包括至少两个频带的频带信息，则根据输入信号的频带信息生成控制信号的步骤包括：根据至少两个频带信息，分别生成配置信息。
结合第二方面的第五种可能的实现方式，在第六种可能的实现方式中，若根据至少两个频带信息，分别生成不同的配置信息，则根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号的步骤包括：根据至少两个基带信号中的任一基带信号对应的系统时钟和控制信号，生成与任一基带信号对应的频带信号。
第三方面提供一种可重配的接收机，包括：系统自适应控制电路，用于根据输入信号的频带信息，生成控制信号，其中控制信号包括接收机重配所需的配置信息；系统时钟电路，用于根据系统自适应控制电路生成的控制信号，生成系统时钟；模拟接收电路，用于接收模拟信号；接收模数转换电路，用于根据系统时钟和控制信号对模拟接收电路接收的模拟信号进行处理，生成数字中频信号；后处理电路，用于根据系统时钟和控制信号对接收模数转换电路生成的数字中频信号进行处理，生成基带信号。
结合第三方面的实现方式，在第一种可能的实现方式中，接收机重配所需的配置信息包括如下至少一种：
系统时钟；或，
数字中频处理速率；或，
数模转换采样率；或，
模数转换采样率。
结合第三方面的实现方式，在第二种可能的实现方式中，若输入信号的频带信息包括至少两个频带的频带信息，则系统自适应控制电路根据至少两个频带信息，分别生成配置信息。
第四方面提供一种接收机的重配方法，包括：根据输入信号的频带信息生成控制信号，其中控制信号包括接收机重配所需的配置信息；根据系统自适应控制电路生成的控制信号生成系统时钟；接收模拟信号；根据系统时钟和控制信号对模拟接收电路接收的模拟信号进行处理，生成数字中频信号；根据系统时钟和控制信号对接收模数转换电路生成的数字中频信号进行处理，生成基带信号。
结合第四方面的实现方式，在第一种可能的实现方式中，接收机重配所需的配置信息包括如下至少一种：
系统时钟；或，
数字中频处理速率；或，
数模转换采样率；或，
模数转换采样率。
结合第四方面的实现方式，在第二种可能的实现方式中，若输入信号的频带信息包括至少两个频带的频带信息，则根据输入信号的频带信息生成控制信号的步骤包括：根据至少两个频带信息分别生成配置信息。
本发明通过系统自适应控制电路根据输入信号的频带信息生成控制信号，其中控制信号包括发射机重配所需的配置信息，系统时钟电路根据控制信号生成系统时钟；因此能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置。预处理电路根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号；数字中频处理电路根据系统时钟和控制信号对预处理电路生成的频带信号进行处理，生成数字中频信号；数模转换电路根据系统时钟和控制信号对数字中频处理电路生成的数字中频信号进行处理，生成模拟信号；模拟发射电路发射数模转换电路生成的模拟信号，如此使得在任意场景下，对每个频带信号的处理都在尽可能低的数字中频处理速率下，可以有效降低数字中频处理速率，减小系统时延，节省资源，同时保证处理性能。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例的发射机的结构示意图；
图2是本发明第二实施例的发射机的结构示意图；
图3是本发明第二实施例的发射机的预处理电路结构示意图；
图4是本发明第一实施例的接收机的结构示意图；
图5是本发明第二实施例的接收机的结构示意图；
图6是本发明第二实施例的接收机的后处理电路结构示意图；
图7是本发明第一实施例的收发机的结构示意图；
图8是本发明第二实施例的收发机的结构示意图；
图9是本发明第三实施例的发射机的结构示意图；
图10是本发明第三实施例的发射机的预处理电路结构示意图；
图11是本发明第三实施例的接收机的结构示意图；
图12是本发明第三实施例的接收机的后处理电路结构示意图；
图13是本发明第三实施例的收发机的结构示意图；
图14是本发明第四实施例的发射机的结构示意图；
图15是本发明第四实施例的发射机的40MHz时的预处理电路示意图；
图16是本发明第四实施例的发射机的100MHz时的预处理电路示意图；
图17是本发明第四实施例的接收机的结构示意图；
图18是本发明第四实施例的接收机的40MHz时的后处理电路示意图；
图19是本发明第四实施例的接收机的100MHz时的后处理电路示意图；
图20是本发明第四实施例的收发机的结构示意图；
图21是本发明第五实施例的发射机的结构示意图；
图22是本发明第五实施例的发射机的20MHz时的预处理电路示意图；
图23是本发明第五实施例的发射机的60MHz时的预处理电路示意图；
图24是本发明第五实施例的接收机的结构示意图；
图25是本发明第五实施例的收发机的20MHz时的后处理电路示意图；
图26是本发明第五实施例的收发机的60MHz时的后处理电路示意图；
图27是本发明第五实施例的收发机的结构示意图；
图28是本发明第一实施例的发射机的重配方法的流程示意图；
图29是本发明第一实施例的接收机的重配方法的流程示意图。
【具体实施方式】
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1是本发明第一实施例的可重配的发射机的结构示意图。如图1所示，可重配的发射机100包括：系统自适应控制电路11、系统时钟电路12、预处理电路13、数字中频处理电路14、数模转换电路15、模拟发射电路18、天线103以及环形器104。系统自适应控制电路11用于根据输入信号的频带信息生成控制信号，其中控制信号包括发射机100重配所需的配置信息。系统时钟电路12用于根据系统自适应控制电路11生成的控制信号生成系统时钟。预处理电路13用于根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号。数字中频处理电路14用于根据系统时钟和控制信号对预处理电路13生成的频带信号进行处理，生成数字中频信号。数模转换电路15用于根据系统时钟和控制信号对数字中频处理电路14生成的数字中频信号进行处理，生成模拟信号。模拟发射电路18用于发射数模转换电路15生成的模拟信号。
其中，系统时钟包括进行数字中频处理所需的时钟以及进行数模转换和模数转换所需的时钟。数模转换电路15将数字中频信号转换成模拟信号后，通过模拟发射电路18对该模拟信号进行模拟处理，包括滤波、衰减等，并经环形器104控制从天线103发射出去。
在本发明实施例中，输入信号可以为单频带信号或双频带信号甚至多频带信号，即输入信号的频带信息包括至少一个频带的频带信息，如包括单频带的频带信息，或者双频带的频带信息甚至多频带的频带信息，不同频带的频带信息对应的系统时钟和数字中频处理速率可能不相同。系统自适应控制电路11根据输入信号的频带信息生成的控制信号中，包括发射机100重配所需的与频带信息对应的系统时钟和数字中频处理速率。预处理电路12根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号，以便数字中频处理电路14进行后续的数字中频处理。如此本发明能够根据不同频带信号对系统时钟和数字中频处理速率进行灵活配置，使得在任意场景下，对每个频带信号的处理都在尽可能低的数字中频处理速率下，能够有效降低数字中频处理速率，减小系统时延，节省资源，同时能够保证处理性能。
具体地，输入信号的频带信息包括至少一个频带的频带信息。以输入信号为LTE（Long Term Evolution，长期演进）单频带信号为例，如图2所示，输入信号带宽是100MHz，频点是2.35GHz，在不对信号进行预失真处理的情况下，发射机200包括：系统自适应控制电路21、系统时钟电路22、预处理电路23、数字中频处理电路24、数模转换电路25、模拟发射电路28、天线203以及环形器204。发射机200的配置过程描述如下：
由于输入信号为100MHz的LTE信号，则数字中频处理速率应大于100Msps，取LTE基带信号速率30.72Msps的整数倍并给数字滤波器保留足够的过渡带，将数字中频处理速率定为153.6Msps；而数模转换采样率和模数转换采样率应大于信号频点，考虑30.72Msps的整数倍以及模拟滤波器的过渡带，数模转换采样率和模数转换采样率定为2611.2Msps。系统自适应控制电路21根据输入信号的频带信息确定发射机200所需的上述配置信息，并生成对应的控制信号。其中，配置信息包括如下至少一种：包括系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率，具体为数字中频处理速率153.6Msps，数模转换采样率和模数转换采样率2611.2Msps。系统自适应控制电路21可以通过查表或在线计算等方法获取上述配置信息。而控制信号可以是选通信号，或配置信号。系统时钟电路22根据控制信号输出153.6MHz和2611.2MHz两种系统时钟。
预处理电路23根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号。具体地如图3所示，预处理电路23包括：第二上变频滤波模块231和第三频谱搬移模块232。其中第二上变频滤波模块231和第三频谱搬移模块232的数量与输入信号带宽以及基带信号带宽相关。在本发明实施例中，基带信号带宽为20 MHz ，而输入信号带宽为100 MHz ，因此预处理电路23有5个第二上变频滤波模块231和5个第三频谱搬移模块232。在本发明的其他实施例中如果输入信号带宽不同 ，则预处理电路23可以有其他数量个第二上变频滤波模块231和第三频谱搬移模块232。在本发明实施例中，5个第二上变频滤波模块231根据系统时钟和控制信号分别将5个单载波LTE基带信号速率30.72Msps上变频到153.6Msps的采样率上，以确保后续合路后有足够的处理速率。其中，LTE基带信号是从室内基带处理单元(Building Base band Unit，BBU)传输过来的，为20MHz。5个第二上变频滤波模块231在将LTE基带信号进行上变频之前，先进行5倍上采样，然后进行滤波。滤波时，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-70MHz,70MHz]，衰减为80dBc。滤波完成后，5个第三频谱搬移模块232根据系统时钟和控制信号分别将5个单载波基带信号搬移到[-40MHz, -20MHz, 0, 20MHz, 40MHz]频点上，然后进行合路。合路后生成的频带信号的带宽变为100MHz。数字中频处理电路24根据系统时钟和控制信号对上述合路后的频带信号进行处理，主要是进行削峰处理，得到100MHz的数字中频信号。在本发明实施例中，削峰的方法没有限制，可以是现有技术中的任意一种，只需按照控制信号使数字中频处理电路24工作在153.6MHz的系统时钟下即可。
数模转换电路25是根据153.6MHz的系统时钟和控制信号对数字中频处理电路24生成的数字中频信号进行处理，生成模拟信号。具体地，数模转换电路25包括第一上变频滤波模块251、第一频谱搬移模块252、第一数模转换模块253以及第一模拟滤波模块254。第一上变频滤波模块251根据系统时钟和控制信号将数字中频信号上变频到射频处理速率，即153.6Msps上变频到2611.2Msps。具体地，第一上变频滤波模块251先做17倍的上采样，然后滤波。其中滤波器的通带设置成[-50MHz,50MHz]，阻带设置成[-1250MHz,1250MHz]。射频处理速率包括数模转换采样率和模数转换采样率。第一频谱搬移模块252将滤波后的信号搬移到2.35GHz的频点上。第一数模转换模块253在2611.2MHz的系统时钟下对第一频谱搬移模块252的信号进行数模转换。第一模拟滤波模块254对第一数模转换模块253输出的信号进行滤波，以滤除时钟镜像。滤波器的通带为[2300MHz,2400MHz]，而为滤除2611.2MHz和1305.6MHz处的镜像，滤波器的阻带为[2100MHz,2600MHz]，并保证在镜像处有30dBc以上的衰减。如此数模转换电路25对数字中频处理电路24生成的数字中频信号进行处理后生成了模拟信号。模拟发射电路28对数模转换电路25生成的模拟信号进行模拟处理，包括放大、滤波等，然后通过环形器203和天线204发射出去。如此完成对发射机200的配置，在本发明实施例中，发射机200采用直接射频(Direct Radio Frequency，DRF)架构，当然在本发明的其他实施例中也可以采用其他的射频架构。
在本发明实施例中，如果要对信号进行预失真处理，则发射机200还可以包括反馈模数转换电路（图未示），用于根据系统时钟和控制信号对模拟发射电路28生成的模拟信号进行处理，生成数字信号，并下变频为对应频带的数字中频信号，以便数字中频处理电路24进行数字预失真处理。相应地，数字中频处理电路24还包括数字预失真系数训练电路和数字预失真电路。数字预失真系数训练电路根据系统时钟和控制信号对反馈模数转换电路生成的数字中频信号进行数字预失真系数训练，生成数字预失真系数。数字预失真电路根据系统时钟、控制信号以及数字预失真系数对预处理电路生成的频带信号经过削峰处理后进行数字预失真处理，生成数字中频信号。
请参阅图4，图4是本发明第一实施例的可重配的接收机的结构示意图。如图4所示，可重配的接收机101包括：系统自适应控制电路11、系统时钟电路12、接收模数转换电路16、后处理电路17、模拟接收电路19、天线103以及环形器104。系统自适应控制电路11用于根据输入信号的频带信息生成控制信号，其中控制信号包括接收机101重配所需的配置信息。系统时钟电路12用于根据系统自适应控制电路11生成的控制信号生成系统时钟。模拟接收电路19用于接收模拟信号。接收模数转换电路16用于根据系统时钟和控制信号对模拟接收电路19接收的模拟信号进行处理，生成数字中频信号。后处理电路17用于根据系统时钟和控制信号对接收模数转换电路16生成的数字中频信号进行处理，生成基带信号。
其中，系统时钟包括进行模数转换所需的时钟以及进行后处理所需的时钟。接收的模拟信号是从天线103接收，并通过环形器104控制传输至模拟接收电路19，模拟接收电路19对模拟信号进行包括滤波、放大等模拟处理后传送给接收模拟转换电路16以进行进一步处理。
在本发明实施例中，输入信号可以为单频带信号或双频带信号甚至多频带信号，即输入信号的频带信息包括至少一个频带的频带信息，如包括单频带的频带信息，或者双频带的频带信息甚至多频带的频带信息，不同频带的频带信息对应的系统时钟和数字中频处理速率可能不相同。系统自适应控制电路11根据输入信号的频带信息生成的控制信号中，包括接收机101重配所需的与频带信息对应的系统时钟和数字中频处理速率。使得本发明能够根据不同频带信号对系统时钟和数字中频处理速率进行灵活配置，使得在任意场景下，对每个频带信号的处理都在尽可能低的数字中频处理速率下，能够有效降低数字中频处理速率，减小系统时延，节省资源，同时能够保证处理性能。
具体地，以输入信号为LTE单频带信号为例，如图5所示，输入信号带宽是100MHz，频点是2.35GHz，接收机201包括：系统自适应控制电路21、系统时钟电路22、接收模数转换电路26、后处理电路27、模拟接收电路29、天线203以及环形器204。接收机201的配置过程描述如下：
由于输入信号为100MHz的LTE信号，模数转换采样率应大于信号频点，考虑LTE基带信号速率30.72Msps的整数倍以及模拟滤波器的过渡带，数模转换采样率和模数转换采样率定为2611.2Msps。系统自适应控制电路21根据输入信号的频带信息确定收发机所需的上述配置信息，并生成对应的控制信号。其中，配置信息包括如下至少一种：系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率，具体为数字中频处理速率153.6Msps，模数转换采样率2611.2Msps。系统自适应控制电路21可以通过查表或在线计算等方法获取上述配置信息。而控制信号可以是选通信号，或配置信号。系统时钟电路22根据控制信号输出153.6MHz和2611.2MHz两种系统时钟。
接收机201在接收信号时，通过天线203接收的模拟信号经过环形器204传输到模拟接收电路29，模拟接收电路29对接收的模拟信号进行模拟处理，包括滤波、放大等。然后接收模数转换电路26根据系统时钟和控制信号对模拟接收电路29接收的模拟信号转换成数字信号，并进行下变频处理，生成数字中频信号。其中接收模数转换电路26包括：第一下变频滤波模块261、第二频谱搬移模块262、第一模数转换电路263以及第二模拟滤波模块264。第二模拟滤波模块264对经过模拟接收电路29处理得到的模拟信号进行模拟滤波，与第一数模转换电路25中的第一模拟滤波模块254的模拟滤波作用相同，参数设置也相同，不再赘述。第一模数转换电路263根据2611.2MHz的系统时钟和控制信号对经过模拟滤波的模拟信号进行模数转换。第二频谱搬移模块262将采样得到的2.35GHz载频上的数字信号搬移到零频上。第一下变频滤波模块261将零频上的数字信号下变频到153.6Msps的处理速率。下变频时，第一下变频滤波模块261先滤波，再做17倍抽取以得到数字中频信号，数字中频信号的带宽为100MHz，滤波器的通带为[-50MHz,50MHz]，阻带设置成[-70MHz, 70MHz]，衰减为80dBc。
后处理电路27用于根据系统时钟和控制信号对接收模数转换电路26生成的数字中频信号进行处理，生成基带信号。如图6所示，后处理电路27包括第四频谱搬移模块271和第二下变频滤波模块272。其中第四频谱搬移模块271和第二下变频滤波模块272的数量与输入信号带宽以及基带信号带宽相关。在本发明实施例中基带信号带宽为20 MHz ，而输入信号带宽为100 MHz ，因此后处理电路27有5个第四频谱搬移模块271和5个第二下变频滤波模块272。在本发明的其他实施例中如果输入信号带宽不同 ，则后处理电路27可以有其他数量个第四频谱搬移模块271和第二下变频滤波模块272。第二下变频滤波模块272对接收模数转换电路26生成的100MHz的数字中频信号进行信号分离，即5个第二下变频滤波模块272分别对该数字中频信号进行频谱搬移，搬移的频点分别为[-40MHz,-20MHz,0,20MHz,40MHz]，然后分别对这5个信号进行滤波，滤除其他载波信号，得到5个单载波信号。滤波器的通带为[-9.015MHz,9.015MHz]，阻带为[-10MHz,10MHz]，衰减为80dBc。5个第四频谱搬移模块271分别对这5个单载波信号进行5倍抽取，下变频到基带处理速率30.72Msps，得到基带信号以用于传输给BBU，如此完成接收机201的配置。
在本发明中，发射机和接收机也可以集成在一个收发机中。如图7所示，发射机100和接收机101集成为收发机10。其中，系统自适应控制电路11根据输入信号的频带信息生成控制信号，其中控制信号包括收发机10重配所需的配置信息，具体地，包括收发机10重配所需的与频带信息对应的系统时钟和数字中频处理速率。系统时钟电路12根据系统自适应控制电路11生成的控制信号生成系统时钟。系统时钟包括进行数字中频处理所需的时钟以及进行数模转换和模数转换所需的时钟。收发机10的重配参见发射机100和接收机101，具体不再赘述。输入信号带宽是100MHz，频点是2.35GHz时，在不对信号进行预失真处理的情况下，收发机20的结构如图8所示，其中，系统自适应控制电路21根据输入信号的频带信息生成控制信号，其中控制信号包括收发机20重配所需的配置信息。系统时钟电路22根据系统自适应控制电路21生成的控制信号生成系统时钟。收发机20的重配参见发射机200和接收机201，具体不再赘述。
当信号带宽变成40MHz，频点变成1.9GHz时，数字中频处理速率变为61.44MHz，数模转换采样率和模块模数转换采样率为2211.84 Msps，因此需要两种系统时钟：61.44MHz和2211.84MHz，并根据上述配置信息对发射机进行重配。如图9所示，系统自适应控制电路31根据输入信号的频带信息生成控制信号，其中控制信号包括发射机300重配所需的配置信息。系统时钟电路32根据上述配置信息生成61.44MHz和2611.2MHz两种系统时钟。预处理电路33根据61.44MHz的系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号。具体地如图10所示，预处理电路33包括第二上变频滤波模块331和第三频谱搬移模块332。其中第二上变频滤波模块331和第三频谱搬移模块332的数量与输入信号带宽以及基带信号带宽相关。在本发明实施例中，输入信号带宽40MHz，因此预处理电路27有2个第二上变频滤波模块331和2个第三频谱搬移模块332。其中2个第二上变频滤波模块331根据系统时钟和控制信号分别将2个20MHz的单载波LTE基带信号速率30.72Msps上变频到61.44Msps的采样率上，以确保后续合路后有足够的处理速率。2个第二上变频滤波模块331在将LTE基带信号进行上变频之前，先进行2倍上采样，然后进行滤波。滤波时，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-30MHz,30MHz]，衰减为80dBc。滤波完成后，2个第三频谱搬移模块332根据系统时钟和控制信号分别将2个单载波基带信号搬移到[-10MHz, 10MHz]频点上，然后进行合路。合路后生成的频带信号的带宽变为40MHz。数字中频处理电路34根据系统时钟和控制信号对上述合路后生成的频带信号进行处理，生成数字中频信号，主要是进行削峰处理，生成40MHz的数字中频信号。在本发明实施例中，削峰的方法没有限制，可以是现有技术中的任意一种，只需按照控制信号使数字中频处理电路34工作在61.44MHz的系统时钟下即可。
数模转换电路35是根据61.44MHz的系统时钟和控制信号对数字中频处理电路34生成的数字中频信号进行处理，生成模拟信号。具体地，第一数模转换电路35包括第一上变频滤波模块351、第一频谱搬移模块352、第一数模转换模块353以及第一模拟滤波模块354。其中第一上变频滤波模块351根据61.44MHz的系统时钟和控制信号将数字中频信号上变频到射频处理速率，即61.44Msps上变频到2211.84Msps。具体地，第一上变频滤波模块351先做36倍的上采样，然后滤波。滤波器的通带设置成[-20MHz,20MHz]，阻带设置成[-1050MHz,1050MHz]。射频处理速率包括数模转换采样率和模数转换采样率。第一频谱搬移模块352将滤波后的信号搬移到1.9GHz的频点上。第一数模转换模块353在2211.84MHz的系统时钟下对第一频谱搬移模块352的信号进行数模转换。第一模拟滤波模块354对第一数模转换模块353输出的信号进行滤波，以滤除时钟镜像。滤波器的通带为[1880MHz,1920MHz]，滤波器的阻带为[1600MHz,2200MHz]，并保证在镜像处有30dBc以上的衰减。如此第一数模转换电路35将数字中频信号对数字中频处理电路34生成的数字中频信号进行处理后生成了模拟信号，模拟发射电路38对数模转换电路35生成的模拟信号进行模拟处理，包括放大、滤波等，然后通过环形器304和天线303发射出去。如此完成对发射机300的配置，在本发明实施例中，发射机300采用直接射频架构，当然在本发明的其他实施例中也可以采用其他的射频架构。如此完成发射机200的配置。经过重新配置后，数字中频处理速率由原来的153.6Msps下降到61.144Msps，数模转换采样率由2611.2Msps下降到2211.84Msps，处理速率大大降低，实现更加简单。可见，本发明能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置，以使每个频带信号的处理在尽可能低的数字中频处理速率下，以有效降低数字中频处理速率，减小系统时延，节省资源，并保证处理性能。
在本发明实施例中，如果要对信号进行预失真处理，则发射机300还可以包括反馈模数转换电路（图未示），用于根据系统时钟和控制信号对模拟发射电路38生成的模拟信号进行处理，生成数字信号，并下变频为对应频带的数字中频信号，以便数字中频处理电路34进行数字预失真处理。相应地，数字中频处理电路34还包括数字预失真系数训练电路和数字预失真电路。数字预失真系数训练电路根据系统时钟和控制信号对反馈模数转换电路生成数字中频信号进行数字预失真系数训练，生成数字预失真系数。数字预失真电路根据系统时钟、控制信号以及数字预失真系数对预处理电路生成的频带信号经过削峰处理后进行数字预失真处理，生成数字中频信号。
当信号带宽变成40MHz，频点变成1.9GHz时，对接收机进行重配，模块模数转换采样率为2211.84 Msps。如图11所示，系统自适应控制电路31根据输入信号的频带信息生成控制信号，其中控制信号包括接收机301重配所需的配置信息。系统时钟电路32根据系统自适应控制电路31生成的控制信号生成生成61.44MHz和2611.2MHz两种系统时钟。
接收机301在接收信号时，通过天线303接收的模拟信号经过环形器304传输到模拟接收电路39，接收模数转换电路36根据2211.84MHz的系统时钟和控制信号对模拟接收电路39接收的模拟信号进行处理，生成数字信号，并下变频为数字中频信号。接收模数转换电路36包括：第一下变频滤波模块361、第二频谱搬移模块362、第一模数转换电路363以及第二模拟滤波模块364。第二模拟滤波模块364根据2211.84MHz的系统时钟和控制信号对模拟接收电路39接收的模拟信号进行模拟滤波，与第一数模转换电路35中的第一模拟滤波模块354的模拟滤波作用相同，参数设置也相同，不再赘述。第一模数转换电路363根据2211.84MHz的系统时钟和控制信号对经过模拟滤波的模拟信号进行模数转换。第二频谱搬移模块362根据2211.84MHz的系统时钟和控制信号将采样得到的1.9GHz载频上的数字信号搬移到零频上。第一下变频滤波模块361根据2211.84MHz的系统时钟和控制信号将零频上的数字信号下变频到61.44Msps的处理速率。下变频时，第一下变频滤波模块361先滤波，再做36倍抽取以得到带宽为40MHz的数字中频信号，滤波器的通带为[-20MHz,20MHz]，阻带设置成[-30MHz, 30MHz]，衰减为80dBc。
后处理电路37用于根据61.44MHz的系统时钟和控制信号对接收模数转换电路36生成的数字中频信号进行处理，生成基带信号。如图12所示，后处理电路37包括第四频谱搬移模块371和第二下变频滤波模块372。其中第四频谱搬移模块371和第二下变频滤波模块372的数量与输入信号带宽以及基带信号带宽相关。在本发明实施例中输入信号带宽40MHz，因此后处理电路37有2个第四频谱搬移模块371和2个第二下变频滤波模块372。第二下变频滤波模块372根据61.44MHz的系统时钟控和控制信号对接收模数转换电路36生成的40MHz的数字中频信号进行信号分离，即2个第二下变频滤波模块372分别对该数字中频信号进行频谱搬移，搬移的频点分别为[-10MHz, 10MHz]，然后分别对这2个信号进行滤波，滤除其他载波信号，得到2个单载波信号。滤波器的通带为[-9.015MHz,9.015MHz]，阻带为[-10MHz,10MHz]，衰减为80dBc。2个第四频谱搬移模块371根据61.44MHz的系统时钟和控制信号分别对这2个单载波信号进行2倍抽取，下变频到基带处理速率30.72Msps，生成基带信号以用于传输给BBU。如此完成接收机301的重新配置，经过重新配置后，模数转换采样率由2611.2Msps下降到2211.84Msps，处理速率大大降低，实现更加简单。可见，本发明能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置，以使每个频带信号的处理在尽可能低的数字中频处理速率下，以有效降低数字中频处理速率，减小系统时延，节省资源，并保证处理性能。
输入信号带宽变成40MHz，频点变成1.9GHz时，发射机300和接收机301可以集成为收发机30，如图13所示。其中，系统自适应控制电路31根据输入信号的频带信息生成控制信号，其中控制信号包括收发机30重配所需的配置信息。系统时钟电路32根据系统自适应控制电路31生成的控制信号生成系统时钟。收发机30的重配参见发射机300和接收机301，具体不再赘述。
在本发明实施例中，输入信号的频带信息还可以包括至少两个频带的频带信息。以输入信号为LTE双频带信号为例，在输入信号的频带信息中，第一频带的带宽是40MHz，频点是1.9GHz，第二频带的带宽是100MHz，频点是2.35GHz。如图14所示，在对信号进行预失真处理的情况下，发射机400包括：系统自适应控制电路41、系统时钟电路42、预处理电路43、数字中频处理电路44、数模转换电路45、反馈模数转换电路48、天线403、环形器404、模拟发射电路405以及模拟反馈电路406。发射机400的配置过程描述如下：
系统自适应控制电路41根据输入信号的频带信息生成控制信号。其中，控制信号包括发射机400重配所需的配置信息，配置信息包括如下至少一种：系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率。具体地，对于40MHz的第一频带，考虑消除其3阶失真分量并考虑100MHz的第二频带带来的影响，其数字中频处理速率应大于240Msps，同时需要取LTE基带信号速率30.72Msps的整数倍并给数字滤波器保留足够的过渡带，因而将数字中频处理速率定为368.64Msps；对于100MHz的第二频带，考虑消除其3阶失真分量并考虑40MHz的第二频带带来的影响，其数字中频处理速率应大于300Msps，同时取LTE基带信号速率30.72Msps的整数倍并给数字滤波器保留足够的过渡带，因而将数字中频处理速率也定为368.64Msps。数模转换采样率和模数转换采样率应大于信号频点，考虑30.72Msps的整数倍以及模拟滤波器的过渡带，数模转换采样率和模数转换采样率定为2949.12Msps。因此根据这两个速率，需要输出368.64MHz和2949.12MHz两种系统时钟。系统自适应控制电路41可以通过查表或在线计算等方法确定上述配置信息，产生的控制信号可以是选通信号或配置信号。系统自适应控制电路41确定的这些配置信息用于系统其它部分的自适应控制。系统时钟电路42根据控制信号输出368.64MHz和2949.12MHz两种系统时钟。
预处理电路43根据368.64MHz的系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号。具体地如图15和图16所示，预处理电路43包括：第五上变频滤波模块431、第十一频谱搬移模块432、第六上变频滤波模块433以及第七上变频滤波模块434。其中第五上变频滤波模块431和第十一频谱搬移模块432的数量与双频带输入信号带宽以及基带信号带宽相关。在本发明实施例中双频带输入信号包括带宽为40MHz的第一频带和带宽为100MHz的第二频带，因此预处理电路43有7个第五上变频滤波模块431和7个第十一频谱搬移模块432。其中，对于40MHz的第一频带，2个第五上变频滤波模块431根据368.64MHz的系统时钟和控制信号把2个单载波20MHz的零频信号合并成1个40MHz的零中频信号，具体地，2个第五上变频滤波模块431先做4倍上采样上变频到122.88Msps的采样率上，然后滤波，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-50MHz,50MHz]，衰减为80dBc。然后2个第十一频谱搬移模块432将2个载波分别搬移到[-10MHz,10MHz]频点上，进行合路生成40MHz的零中频信号。第六上变频滤波模块433将合路后的信号进行3倍上采样上变频到368.64Msps的采样率上，并进行滤波，滤波器的通带设置成[-20MHz,20MHz]，阻带设置成[-160MHz,160MHz]，衰减为80dBc。对于100MHz的第二频带，5个第五上变频滤波模块431根据系统时钟和控制信号把5个单载波20MHz的零频信号合并成1个100MHz的零中频信号，具体地，5个第五上变频滤波模块431先做4倍上采样上变频到122.88Msps的采样率上，然后滤波，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-50MHz,50MHz]，衰减为80dBc。然后5个第十一频谱搬移模块432将5个单载波分别搬移到[-40MHz,-20MHz,0,20MHz, 40MHz]频点上，进行合路生成100MHz的零中频信号。第七上变频滤波模块434将合路后的信号进行3倍上采样上变频到368.64Msps的采样率上，并进行滤波，滤波器的通带设置成[-50MHz,50MHz]，阻带设置成[-130MHz,130MHz]，衰减为80dBc。如此对应40MHz的第一频带和100MHz的第二频带，预处理电路43各输出一路频带信号，且都为368.64Msps的采样率，以便后续进行数字中频处理。当然在本发明的其他实施例中，该两路信号也可以是不同的采样率。
数字中频处理电路44根据系统时钟和控制信号对预处理电路43生成的频带信号进行处理，生成数字中频信号。数字中频处理电路44还包括数字预失真系数训练电路和数字预失真电路，数字预失真系数训练电路根据系统时钟和控制信号对反馈模数转换电路48生成的数字中频信号和数字预失真电路输出的数字中频信号进行数字预失真系数训练，生成数字预失真系数；数字预失真电路根据系统时钟、控制信号以及数字预失真系数对预处理电路43生成的频带信号经过削峰处理后进行数字预失真处理，生成数字中频信号。具体地，数字中频处理电路44包括第一削峰模块441、第一频带数字预失真电路442、第二削峰模块443、第二频带数字预失真电路444、第一频带数字预失真系数训练电路445以及第二频带数字预失真系数训练电路446。第一削峰模块441根据368.64MHz的系统时钟和控制信号对预处理电路43基于第一频带输出的频带信号进行削峰处理。第一频带数字预失真电路442根据368.64MHz的系统时钟和控制信号以及第一频带数字预失真系数训练电路445生成的预失真系数对经第一削峰模块441削峰处理的信号进行数字预失真处理，生成与第一频带对应的数字中频信号。第一频带数字预失真电路442在进行数字预失真处理时，还受到第二削峰模块443基于第二频带进行削峰处理后的频带信号的影响。同样地，第二削峰模块443根据系统时钟和控制信号对预处理电路43基于第二频带输出的频带信号进行削峰处理。第二频带数字预失真电路444根据368.64MHz的系统时钟、控制信号以及第二频带数字预失真系数训练电路446生成的预失真系数对经第二削峰模块443削峰处理的频带信号进行数字预失真处理，生成与第二频带对应的数字中频信号。第二频带数字预失真电路444在进行数字预失真处理时，还受到第一削峰模块441基于第一频带进行削峰处理后的频带信号的影响。其中第一频带数字预失真系数训练电路445和第二频带数字预失真系数训练电路446是根据368.64MHz的系统时钟和控制信号分别对反馈模数转换电路48生成的数字中频信号进行数字预失真系数训练，生成数字预失真系数。
数模转换电路45用于根据2949.12MHz的系统时钟和控制信号对数字中频处理电路44生成的数字中频信号进行处理，生成模拟信号。具体地，数模转换电路45包括：第三上变频滤波模块451、第五频谱搬移模块452、第四上变频滤波模块453、第六频谱搬移模块454、第二数模转换模块455以及第三模拟滤波模块456。对于40MHz的第一频带，第三上变频滤波模块451根据2949.12MHz的系统时钟和控制信号对该频带的数字中频信号进行上变频到射频处理速率，即368.64Msps上变频到2949.12Msps。其中射频处理速率包括数模转换采样率和模数转换采样率。具体地，第三上变频滤波模块451先做8倍的上变频到2949.12Msps的采样率上，然后滤波。滤波器的通带设置成[-120MHz,120MHz]，阻带设置成[-1300MHz,1300MHz] ，衰减为80dBc。第五频谱搬移模块452将滤波后的信号搬移到1.9GHz的频点上。对于100MHz的第二频带，第四上变频滤波模块453根据2949.12MHz的系统时钟和控制信号对该频带的数字中频信号进行上变频到射频处理速率，即368.64Msps上变频到2949.12Msps。具体地，第四上变频滤波模块453先做8倍的上变频到2949.12Msps的采样率上，然后滤波。滤波器的通带设置成[-120MHz,120MHz]，阻带设置成[-1300MHz,1300MHz] ，衰减为80dBc。第六频谱搬移模块454将滤波后的信号搬移到2.35GHz的频点上。数模转换电路45将基于第一频带的第五频谱搬移模块452输出的信号和基于第二频带的第六频谱搬移模块454输出的信号进行合路，第二数模转换模块455根据2949.12MHz的系统时钟和控制信号对合路后的信号进行数模转换，生成模拟信号。第三模拟滤波模块456对第二数模转换模块455输出的模拟信号进行滤波，以滤除时钟镜像。滤波器的通带为[1700MHz,2500MHz]，滤波器的阻带为[1500MHz,2900MHz]，并保证在镜像处有30dBc以上的衰减。如此数模转换电路45将两路数字中频信号转换成了双频带模拟信号。模拟发射电路405对数模转换电路45生成的双频带模拟信号进行模拟处理，包括放大、滤波等，然后通过环形器404和天线403发射出去。
在本发明实施例中，在环形器404的前面还包括一个耦合器（图未示），以将模拟发射电路405输出的模拟信号反馈至模拟反馈电路406。反馈模数转换电路48根据2949.12MHz的系统时钟和控制信号对反馈的双频带模拟信号进行处理，生成数字中频信号。反馈模数转换电路48包括：第三下变频滤波模块481、第七频谱搬移模块482、第四下变频滤波模块483、第八频谱搬移模块484、第二模数转换模块485以及第四模拟滤波模块486。第四模拟滤波模块486对反馈的模拟信号进行模拟滤波，与第三模拟滤波模块456进行的模拟滤波作用相同，参数设置也相同，不再赘述。第二模数转换模块485根据2949.12MHz的系统时钟和控制信号对经过模拟滤波处理的模拟信号进行模数转换。对于40MHz的第一频带，第七频谱搬移模块482根据2949.12MHz的系统时钟和控制信号将采样得到的1.9GHz载频上的数字信号搬移到零频上，第三下变频滤波模块481再将其下变频到368.64Msps的处理速率，具体地先进行滤波，再做8倍抽取，生成对应频带的数字中频信号。其中滤波器的通带为[-120MHz,120MHz]，阻带设置成[-180MHz,180MHz]，衰减为80dBc。第一频带预失真系数训练电路445对该数字中频信号进行数字预失真系数训练以用于第一频带的频带信号的数字预失真处理。对于100MHz的第二频带，第八频谱搬移模块484根据2949.12MHz的系统时钟和控制信号将采样得到的2.35GHz载频上的数字信号搬移到零频上，第四下变频滤波模块483再将其下变频到368.64Msps的处理速率，具体地先进行滤波，再做8倍抽取，生成对应频带的数字中频信号。其中滤波器的通带为[-150MHz,150MHz]，阻带设置成[-180MHz,180MHz]，衰减为80dBc。第二频带预失真系数训练电路446对该数字中频信号进行数字预失真系数训练以用于第二频带的频带信号的数字预失真处理。如此完成对发射机400的配置，在本发明实施例中，发射机400采用直接射频架构，当然在本发明的其他实施例中也可以采用其他的射频架构。
输入信号为LTE双频带信号，即在输入信号的频带信息中，第一频带的带宽是40MHz，频点是1.9GHz，第二频带的带宽是100MHz，频点是2.35GHz。如图17所示，接收机401包括：系统自适应控制电路41、系统时钟电路42、接收模数转换电路46、后处理电路47、模拟接收电路49、天线403以及环形器404。接收机401的配置过程描述如下：
与发射机400相同，接收机401中的系统自适应控制电路41根据输入信号的频带信生成控制信号。其中，控制信号包括发射机400重配所需的配置信息，配置信息包括如下至少一种：系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率。具体地，在本实施例中，系统自适应控制电路41生成的控制信号包括368.64Msps的数字中频处理速率和2949.12Msps的模数转换采样率，用于系统其它部分的自适应控制。系统时钟电路42根据控制信号输出368.64MHz和2949.12MHz两种系统时钟。
接收机401在接收信号时，通过天线403接收的双频带模拟信号经过环形器404传输到模拟接收电路49，模拟接收电路49对接收的双频带模拟信号进行模拟处理，包括滤波、放大等。接收模数转换电路46根据2949.12MHz的系统时钟和控制信号对模拟接收电路49接收的双频带模拟信号进行处理，生成数字中频信号。其中接收模数转换电路46包括：第五下变频滤波模块461、第九频谱搬移模块462、第六下变频滤波模块463、第十频谱搬移模块464、第三模数转换电路465以及第五模拟滤波模块466。第五模拟滤波模块466对模拟接收电路49接收的双频带模拟信号进行模拟滤波，与第三模拟滤波模块456进行的模拟滤波作用相同，参数设置也相同，不再赘述。第三模数转换电路465根据2949.12MHz的系统时钟和控制信号对经第五模拟滤波模块466模拟滤波处理的模拟信号进行模数转换。第九频谱搬移模块462根据2949.12MHz的系统时钟和控制信号将采样得到的1.9GHz载频上的数字信号搬移到零频上，第五下变频滤波模块461再将其下变频到368.64Msps的处理速率，具体地先进行滤波，再做8倍抽取以得到与40MHz的第一频带对应的数字中频信号。其中滤波器的通带为[-20MHz,20MHz]，阻带设置成[-180MHz,180MHz]，衰减为80dBc。第十频谱搬移模块464根据2949.12MHz的系统时钟和控制信号将采样得到的2.35GHz载频上的数字信号搬移到零频上，第六下变频滤波模块463再将其下变频到368.64Msps的处理速率，具体地先进行滤波，再做8倍抽取以得到与100MHz的第二频带对应的数字中频信号。其中滤波器的通带为[-50MHz,50MHz]，阻带设置成[-180MHz,180MHz]，衰减为80dBc。
后处理电路47用于根据368.64MHz的系统时钟和控制信号对接收模数转换电路46生成的数字中频信号进行处理，生成基带信号。如图18和图19所示，后处理电路47包括：第十二频谱搬移模块471和第七下变频滤波模块472。其中第十二频谱搬移模块471和第七下变频滤波模块472的数量与双频带输入信号带宽以及基带信号带宽相关。在本发明实施例中双频带输入信号包括带宽为40MHz的第一频带和带宽为100MHz的第二频带，因此后处理电路47有7个第十二频谱搬移模块471和7个第七下变频滤波模块472。对于40MHz的第一频带，2个第十二频谱搬移模块471对40MHz的数字中频信号进行信号分离，即对40MHz的数字中频信号分别进行频谱搬移，搬移的频点分别为[-10MHz, 10MHz]。然后2个第七下变频滤波模块472对这2个信号进行滤波，滤除其他载波信号，得到2个单载波信号，2个第七下变频滤波模块472分别对这2个单载波信号进行12倍抽取，下变频到基带处理速率30.72Msps，生成基带信号。滤波器的通带为[-9.015MHz,9.015MHz]，阻带为[-10MHz,10MHz]，衰减为80dBc。对于100MHz的第二频带，5个第十二频谱搬移模块471对100MHz的数字中频信号进行信号分离，即对100MHz的数字中频信号分别进行频谱搬移，搬移的频点分别为[-40MHz,-20MHz,0,20MHz,40MHz]。然后5个第七下变频滤波模块472对这5个信号进行滤波，滤除其他载波信号，得到5个单载波信号。5个第七下变频滤波模块472分别对这5个单载波信号进行12倍抽取，下变频到基带处理速率30.72Msps，生成基带信号。滤波器的通带同样为[-9.015MHz,9.015MHz]，阻带为[-10MHz,10MHz]，衰减为80dBc，如此完成接收机401的配置。
如图20所示，发射机400和接收机401可以集成为收发机40。输入信号为LTE双频带信号，其中，第一频带的带宽是40MHz，频点是1.9GHz，第二频带的带宽是100MHz，频点是2.35GHz。系统自适应控制电路41根据输入信号的频带信息生成控制信号，其中控制信号包括收发机40重配所需的配置信息。系统时钟电路42根据系统自适应控制电路41生成的控制信号生成系统时钟。收发机40的重配参见发射机400和接收机401，具体不再赘述。
当输入信号的第一频带的带宽变成20MHz，第二频带的带宽变成60MHz时，需要对发射机进行重新配置。如图21所示，发射机500包括：系统自适应控制电路51、系统时钟电路52、预处理电路53、数字中频处理电路54、数模转换电路55、反馈模数转换电路58、天线503、环形器504、模拟发射电路505以及模拟反馈电路506。发射机500的重新配置过程描述如下：
系统自适应控制电路51根据输入信号的频带信息生成控制信号。其中，控制信号包括发射机500重配所需的配置信息，配置信息包括如下至少一种：系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率。具体地，对于20MHz的第一频带，其数字中频处理速率定为184.32Msps，对于60MHz的第二频带，其数字中频处理速率定为368.64Msps，两频带对应的数模转换采样率和模数转换采样率定为2949.12Msps。根据这两个速率，需要输出184.32MHz、368.64MHz和2949.12MHz三种系统时钟。因此系统自适应控制电路51根据上述两个频带信息，分别生成不同的配置信息，可以通过查表或在线计算等方法确定上述配置信息，以用于系统其它部分的自适应控制，生成的控制信号可以是选通信号或配置信号。系统时钟电路52根据控制信号输出184.32MHz、368.64MHz和2949.12MHz三种系统时钟。
预处理电路53根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号。若系统自适应控制电路51根据至少两个频带信息，分别生成不同的配置信息，则预处理电路53还用于根据至少两个基带信号中的任一基带信号对应的系统时钟和控制信号，生成与任一基带信号对应的频带信号。具体地，预处理电路53根据系统时钟和控制信号把基带信号分别上变频到184.32Msps和368.64Msps的速率上，以用于后续的预失真处理。如图22和图23所示，预处理电路53包括：第五上变频滤波模块531、第十一频谱搬移模块532、第六上变频滤波模块533、第七上变频滤波模块534。其中第五上变频滤波模块531和第十一频谱搬移模块532的数量与双频带输入信号带宽以及基带信号带宽相关。在本发明实施例中，双频带输入信号包括带宽为20MHz的第一频带和带宽为60MHz的第二频带，因此预处理电路53有4个第五上变频滤波模块531和3个第十一频谱搬移模块532。由于两个频带的数字中频处理速率不同，预处理电路53中第六上变频滤波模块533和第七上变频滤波模块534各有2个。对于20MHz的第一频带，第五上变频滤波模块531把基于第一频带的基带信号做3倍上采样上变频到92.16Msps的采样率上并进行滤波，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-35MHz,35MHz]，衰减为80dBc。接着第六上变频滤波模块533做2倍上采样上变频到184.32Msps的采样率上并进行滤波，生成基于第一频带的频带信号，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-80MHz,80MHz]，衰减为80dBc。3个第五上变频滤波模块531把基于第二频带的基带信号做3倍上采样上变频到92.16Msps的采样率上并进行滤波，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-35MHz,35MHz]，衰减为80dBc。接着3个第十一频谱搬移模块532将3个载波分别搬移到[-20MHz,0,20MHz]频点上，并进行合路。第六上变频滤波模块533再对合路后的信号做2倍上采样上变频到184.32Msps的采样率上并进行滤波，生成与第二频带相关的频带信号，滤波器的通带可以设置成[-30MHz,30MHz]，阻带设置成[-60MHz,60MHz]，衰减为80dBc。如此对于20MHz的第一频带，预处理电路53输出采样率皆为184.32Msps的两路频带信号，以用于数字中频处理，其中一路是与60MHz的第二频带相关的频带信号。对于60MHz的第二频带，第五上变频滤波模块531把基于第一频带的基带信号做3倍上采样上变频到92.16Msps的采样率上并进行滤波，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-35MHz,35MHz]，衰减为80dBc。接着第七上变频滤波模块534做4倍上采样上变频到368.64Msps的采样率上并进行滤波，生成与第一频带相关的频带信号，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-170MHz,170MHz]，衰减为80dBc。3个第五上变频滤波模块531把基于第二频带的基带信号做3倍上采样上变频到92.16Msps的采样率上并进行滤波，滤波器的通带可以设置成[-10MHz,10MHz]，阻带设置成[-35MHz,35MHz]，衰减为80dBc。接着3个第十一频谱搬移模块532将3个载波分别搬移到[-20MHz,0,20MHz]频点上，并进行合路。第七上变频滤波模块534再对合路后的信号做4倍上采样上变频到368.64Msps的采样率上并进行滤波，生成基于第二频带的频带信号，滤波器的通带可以设置成[-30MHz,30MHz]，阻带设置成[-150MHz,150MHz]，衰减为80dBc。如此对于60MHz的第二频带，预处理电路53输出采样率皆为368.64Msps的两路频带信号，以用于数字中频处理，其中一路是与20MHz的第一频带相关的频带信号。
数字中频处理电路54根据系统时钟和控制信号对预处理电路53生成的频带信号进行处理，生成数字中频信号。可以用于数字中频处理电路54进行的数字预失真处理。相应地，数字中频处理电路54包括数字预失真系数训练电路和数字预失真电路，数字预失真系数训练电路根据系统时钟和控制信号对反馈模数转换电路58生成的数字中频信号进行数字预失真系数训练，生成数字预失真系数。数字预失真电路根据系统时钟、控制信号以及数字预失真系数对预处理电路53生成的频带信号进行数字预失真处理，生成数字中频信号。具体地，数字中频处理电路54包括第一削峰模块541、第一频带数字预失真电路542、第二削峰模块543、第二频带数字预失真电路544、第一频带数字预失真系数训练电路545以及第二频带数字预失真系数训练电路546。第一削峰模块541根据184.32MHz的系统时钟和控制信号对预处理电路53生成的基于第一频带的两路频带信号进行削峰处理。第一频带数字预失真电路542根据184.32MHz的系统时钟、控制信号以及第一频带数字预失真系数训练电路545生成的预失真系数对经第一削峰模块541削峰处理的两路频带信号进行数字预失真处理，生成一路与第一频带对应的数字中频信号。其中该数字预失真系数是第一频带数字预失真系数训练电路545根据184.32MHz的系统时钟和控制信号对第一频带数字预失真电路542生成的与第一频带对应的数字中频信号以及反馈模数转换电路58生成的对应频带的数字中频信号进行数字预失真系数训练得到的。第二削峰模块543根据368.64MHz的系统时钟和控制信号对预处理电路53生成的基于第二频带的两路频带信号进行削峰处理。第二频带数字预失真电路544根据368.64MHz的系统时钟、控制信号以及第二频带数字预失真系数训练电路546生成的预失真系数对经第二削峰模块543削峰处理的两路频带信号进行数字预失真处理，生成一路与第二频带对应的数字中频信号。其中该数字预失真系数是第二频带数字预失真系数训练电路546是根据368.64MHz的系统时钟和控制信号对第二频带数字预失真电路544生成的与第二频带对应的数字中频信号以及反馈模数转换电路58生成的对应频带的数字信号进行数字预失真系数训练得到的。
数模转换电路55用于根据2949.12MHz的系统时钟和控制信号对数字中频处理电路54生成的数字中频信号进行处理，生成模拟信号。具体地，数模转换电路55包括：第三上变频滤波模块551、第五频谱搬移模块552、第四上变频滤波模块553、第六频谱搬移模块554、第二数模转换模块555以及第三模拟滤波模块556。对于20MHz的第一频带，第三上变频滤波模块551根据2949.12MHz的系统时钟和控制信号将与第一频带对应的数字中频信号上变频到射频处理速率，即184.32Msps上变频到2949.12Msps。其中射频处理速率包括数模转换采样率和模数转换采样率。具体地，第三上变频滤波模块551先做16倍的上变频到2949.12Msps的采样率上，然后滤波。滤波器的通带设置成[-70MHz,70MHz]，阻带设置成[-1350MHz,1350MHz] ，衰减为80dBc。第五频谱搬移模块552将滤波后的信号搬移到1.9GHz的频点上。对于60MHz的第一频带，第四上变频滤波模块553根据2949.12MHz的系统时钟和控制信号将与第二频带对应的数字中频信号上变频到射频处理速率，即368.64Msps上变频到2949.12Msps。具体地，第四上变频滤波模块553先做8倍的上变频到2949.12Msps的采样率上，然后滤波。滤波器的通带设置成[-90MHz,90MHz]，阻带设置成[-1350MHz,1350MHz] ，衰减为80dBc。第六频谱搬移模块554将滤波后的信号搬移到2.35GHz的频点上。数模转换电路55将基于第一频带的第五频谱搬移模块552输出的信号和基于第二频带的第六频谱搬移模块554输出的信号进行合路，第二数模转换模块555根据2949.12MHz的系统时钟和控制信号对合路后的信号进行数模转换，生成模拟信号。第三模拟滤波模块556对第二数模转换模块555生成的模拟信号进行滤波，以滤除时钟镜像。滤波器的通带为[1700MHz,2500MHz]，滤波器的阻带为[1500MHz,2900MHz]，并保证在镜像处有30dBc以上的衰减。如此数模转换电路55将两路数字中频信号转换成了双频带模拟信号。模拟发射电路505对数模转换电路55生成的双频带模拟信号进行模拟处理，包括放大、滤波等，然后通过环形器504和天线503发射出去。
在本发明实施例中，在环形器504的前面还包括一个耦合器（图未示），以将模拟发射电路505输出的模拟信号反馈至模拟反馈电路506。反馈模数转换电路58根据2949.12MHz的系统时钟和控制信号反馈的双频带模拟信号进行处理，生成数字中频信号。反馈模数转换电路58包括：第三下变频滤波模块581、第七频谱搬移模块582、第四下变频滤波模块583、第八频谱搬移模块584、第二模数转换模块585以及第四模拟滤波模块586。第四模拟滤波模块586对反馈的模拟信号进行模拟滤波，与第三模拟滤波模块556进行的模拟滤波作用相同，参数设置也相同，不再赘述。第二模数转换模块585根据2949.12MHz的系统时钟和控制信号将经过模拟滤波处理的模拟信号进行模数转换。由于两个频带的数字中频处理速率不同，反馈模数转换电路58需要把两个频带的信号分别下变频到184.32Msps和368.64Msps的速率上，以用于后续的数字预失真系数训练。具体地，对于20MHz的第一频带，第七频谱搬移模块582根据2949.12MHz的系统时钟和控制信号将采样得到的1.9GHz载频上的数字信号搬移到零频上，第三下变频滤波模块581将其下变频到184.32Msps的处理速率，具体地先进行滤波，再做16倍抽取，生成与第一频带对应的数字中频信号。其中滤波器的通带为[-70MHz,70MHz]，阻带设置成[-90MHz,90MHz]，衰减为80dBc；同时第七频谱搬移模块582还将采样得到的2.35GHz载频上的数字信号搬移到零频上，下变频到184.32Msps的处理速率，具体地先进行滤波，再做16倍抽取，生成与第二频带相关的数字中频信号，滤波器的通带为[-70MHz,70MHz]，阻带设置成[-90MHz,90MHz]，衰减为80dBc。第一频带预失真系数训练电路545对上述两路数字中频信号以及第一频带数字预失真电路542生成的与第一频带对应的数字中频信号进行数字预失真系数训练以用于第一频带信号的数字预失真处理。对于60MHz的第二频带，第八频谱搬移模块584根据2949.12MHz的系统时钟和控制信号将采样得到的1.9GHz载频上的数字信号搬移到零频上，第四下变频滤波模块583将其下变频到368.64Msps的处理速率，具体地先进行滤波，再做8倍抽取，生成与第一频带对应的数字中频信号。其中滤波器的通带为[-90MHz,90MHz]，阻带设置成[-180MHz,180MHz]，衰减为80dBc；同时第八频谱搬移模块584还根据2949.12MHz的系统时钟和控制信号将采样得到的2.35GHz载频上的数字信号搬移到零频上，第四下变频滤波模块583再将其下变频到368.64Msps的处理速率，具体地先进行滤波，再做8倍抽取，生成与第二频带对应的数字中频信号。其中滤波器的通带为[-90MHz,90MHz]，阻带设置成[-180MHz,180MHz]，衰减为80dBc。第二频带预失真系数训练电路546对上述两路数字中频信号以及第二频带数字预失真电路544生成的与第二频带对应的数字中频信号进行数字预失真系数训练以用于第二频带信号的数字预失真处理。如此完成对发射机500的配置，在本发明实施例中，发射机500采用直接射频架构，当然在本发明的其他实施例中也可以采用其他的射频架构。如此完成发射机500的重新配置，经过重新配置后，第一频带的数字中频处理速率由原来的368.64Msps下降到184.32Msps，处理速率大大降低，实现更加简单。可见，本发明能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置，以使每个频带信号的处理在尽可能低的数字中频处理速率下，以有效降低数字中频处理速率，减小系统时延，节省资源，并保证处理性能。
当输入信号的第一频带的带宽变成20MHz，第二频带的带宽变成60MHz时，对接收机进行重新配置，两频带的模数转换采样率定为2949.12Msps。如图24所示，接收机501包括：系统自适应控制电路51、系统时钟电路52、接收模数转换电路56、后处理电路57、模拟接收电路59、天线503以及环形器504。接收机501的重新配置过程描述如下：
与发射机500相同，系统自适应控制电路51根据输入信号的频带信息生成控制信号。其中，控制信号包括接收机501重配所需的配置信息，配置信息包括如下至少一种：系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率。具体地，在本实施例中，系统自适应控制电路51生成的控制信号包括应用于20MHz的第一频带的184.32Msps的数字中频处理速率、应用于60MHz的第二频带的368.64Msps的数字中频处理速率以及2949.12Msps的模数转换采样率，用于接收机501其它部分的自适应控制。系统时钟电路52根据控制信号输出184.32MHz、368.64MHz和2949.12MHz三种系统时钟。
接收机501在接收信号时，通过天线503接收的双频带模拟信号经过环形器504传输到模拟接收电路59，模拟接收电路59对接收的双频带模拟信号进行模拟处理，包括滤波、放大等。接收模数转换电路56根据2949.12MHz的系统时钟和控制信号对模拟接收电路59接收的双频带模拟信号进行处理，生成数字中频信号。接收模数转换电路56包括：第五下变频滤波模块561、第九频谱搬移模块562、第六下变频滤波模块563、第十频谱搬移模块564、第三模数转换电路565以及第五模拟滤波模块566。第五模拟滤波模块566对模拟接收电路59接收的双频带模拟信号进行模拟滤波，与第三模拟滤波模块556进行的模拟滤波作用相同，参数设置也相同，不再赘述。第三模数转换电路565根据2949.12MHz的系统时钟和控制信号对经第五模拟滤波模块566模拟滤波处理的模拟信号进行模数转换。第九频谱搬移模块562根据2949.12MHz的系统时钟和控制信号将采样得到的1.9GHz载频上的数字信号搬移到零频上，第五下变频滤波模块561再将其下变频到184.32Msps的处理速率，具体地先进行滤波，再做16倍抽取以得到与20MHz的第一频带对应的数字中频信号，滤波器的通带为[-10MHz,10MHz]，阻带设置成[-90MHz,90MHz]，衰减为80dBc。第九频谱搬移模块562还根据2949.12MHz的系统时钟和控制信号将采样得到的2.35GHz载频上的数字信号搬移到零频上，第五下变频滤波模块561再将其下变频到368.64Msps的处理速率，具体地先进行滤波，再做8倍抽取以得到与60MHz的第二频带对应的数字中频信号，滤波器的通带为[-30MHz,30MHz]，阻带设置成[-180MHz,180MHz]，衰减为80dBc。如此接收模数转换电路56对模拟接收电路59接收的双频带模拟信号进行处理后生成两路分别基于20MHz和60MHz的数字中频信号。
后处理电路57用于根据系统时钟和控制信号对接收模数转换电路56生成的数字中频信号进行处理，生成基带信号。如图25和图26所示，后处理电路57包括：第七下变频滤波模块571、第十二频谱搬移模块572。其中第七下变频滤波模块571和第十二频谱搬移模块572的数量与双频带输入信号带宽以及基带信号带宽相关。在本发明实施例中双频带输入信号包括带宽为20MHz的第一频带和带宽为60MHz的第二频带，因此后处理电路57有4个第七下变频滤波模块571和3个第十二频谱搬移模块572。对于20MHz的第一频带，第七下变频滤波模块571根据184.32MHz的系统时钟和控制信号对20MHz的数字中频信号进行滤波，滤波器的通带为[-9.015MHz,9.015MHz]，阻带为[-10MHz,10MHz]，衰减为80dBc，然后对滤波得到的信号进行6倍抽取，下变频到基带处理速率30.72Msps，生成基带信号。对于60MHz的第二频带，3个第十二频谱搬移模块572对60MHz的数字中频信号进行信号分离，即对60MHz的数字中频信号进行3次频谱搬移，搬移的频点分别为[-20MHz,0,20MHz]，然后对这3个信号进行滤波，滤除其他载波信号，得到3个单载波信号。滤波器的通带为[-9.015MHz,9.015MHz]，阻带为[-10MHz,10MHz]，衰减为80dBc。3个第七下变频滤波模块571分别对3个单载波信号进行12倍抽取，下变频到基带处理速率30.72Msps，生成基带信号。如此完成接收机501的重新配置，经过重新配置后，第一频带的数字中频处理速率由原来的368.64Msps下降到184.32Msps，处理速率大大降低，实现更加简单。可见，本发明能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置，以使每个频带信号的处理在尽可能低的数字中频处理速率下，以有效降低数字中频处理速率，减小系统时延，节省资源，并保证处理性能。
如图27所示，发射机500和接收机501可以集成为收发机50。输入信号为LTE双频带信号，其中，第一频带的带宽是20MHz，频点是1.9GHz，第二频带的带宽是60MHz，频点是2.35GHz。其中，系统自适应控制电路51根据输入信号的频带信息生成控制信号，其中控制信号包括收发机50重配所需的配置信息。系统时钟电路52根据系统自适应控制电路51生成的控制信号生成系统时钟。收发机50的重配参见发射机500和接收机501，具体不再赘述。
请参阅图28，图28是本发明第一实施例的发射机的重配方法的流程示意图。如图28所示，发射机的重配方法包括：
S10：根据输入信号的频带信息生成控制信号，其中控制信号包括发射机重配所需的配置信息。
在本发明实施例中，输入信号的频带信息包括至少一个频带的频带信息，即输入信号可以为单频带信号或双频带信号甚至多频带信号。控制信号为选通信号，或配置信号。发射机重配所需的配置信息包括如下至少一种：系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率。如果输入信号的频带信息包括至少两个频带的频带信息，则根据至少两个频带信息，分别生成配置信息，其中数字中频处理速率可以相同，或者不相同。以输入信号为LTE双频带信号为例，如果输入信号包括带宽为40MHz，频点为1.9GHz的第一频带和带宽为100MHz，频点为2.35GHz的第二频带，则对于40MHz的第一频带，数字中频处理速率可以定为368.64Msps，而数模转换采样率和模数转换采样率可以定为2949.12Msps；对于100MHz的第二频带，数字中频处理速率和数模转换采样率和模数转换采样率可以分别定为368.64Msps 和2949.12Msps。如果输入信号包括带宽为20MHz，频点为1.9GHz的第一频带和带宽为60MHz，频点为2.35GHz的第二频带，则对于20MHz的第一频带，数字中频处理速率可以定为184.32Msps，而数模转换采样率和模数转换采样率可以定为2949.12Msps；对于60MHz的第二频带，数字中频处理速率可以定为368.64Msps，而数模转换采样率和模数转换采样率定为2949.12Msps。
S11: 根据控制信号生成系统时钟。
其中，系统时钟包括进行预处理和数字中频处理所需的时钟以及进行数模转换和模数转换所需的时钟。例如，若输入信号包括带宽为20MHz，频点为1.9GHz的第一频带和带宽为60MHz，频点为2.35GHz的第二频带，则所生成的系统时钟有三个：184.32MHz、368.64 MHz以及2949.12 MHz，其中，184.32MHz和368.64 MHz分别用于20MHz的第一频带和60MHz的第二频带的数字中频处理，2949.12 MHz用于两频带的数模转换和模数转换。
S12: 根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号。
其中预处理包括上变频、滤波等处理。若在S10中根据至少两个频带信息，分别生成不同的配置信息，则在S12中，根据至少两个基带信号中的任一基带信号对应的系统时钟和控制信号，生成与所述任一基带信号对应的频带信号。
S13: 根据系统时钟和控制信号对预处理生成的频带信号进行处理，生成数字中频信号。
在S13中，主要是根据系统时钟和控制信号对预处理生成的频带信号进行削峰等处理。
若对信号进行预失真处理，则在S13中，根据系统时钟和控制信号分别将反馈的模拟信号转换成数字信号，并下变频为数字中频信号。并且还可以进行数字预失真处理和数字预失真系数训练。具体地，根据系统时钟和控制信号对反馈的模拟信号进行处理，生成的数字中频信号；根据系统时钟和控制信号对数字中频信号进行数字预失真系数训练，生成数字预失真系数；根据系统时钟、控制信号以及数字预失真系数对S12中生成的频带信号进行数字预失真处理，生成数字中频信号。
S14: 根据系统时钟和控制信号对数字中频信号进行处理，生成模拟信号。
在S14中，根据系统时钟和控制信号将数字中频信号上变频到所需的数模转换采样率上，然后频谱搬移到对应频带的工作频点，再经数模转换和模拟滤波后生成模拟信号。其中若输入信号的频带信息包括至少两个频带的频带信息，则根据系统时钟和控制信号分别将对应频带的数字中频信号上变频到对应频带所需的数模转换采样率上，并进行频谱搬移，然后将不同频带的信号进行合路以得到双频带或多频带信号，再经数模转换和模拟滤波后生成模拟信号。对于不同频带的信号，其数模转换采样率可以相同，或不相同。
S15：发射模拟信号。
经过模拟滤波后生成的模拟信号经过如放大、滤波等模拟处理后经环形器和天线发射出去。如此即完成了对发射机的重配，可见本发明能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置，以使每个频带信号的处理在尽可能低的数字中频处理速率下，以有效降低数字中频处理速率，减小系统时延，节省资源，并保证处理性能。
请参阅图29，图29是本发明第一实施例的接收机的重配方法的流程示意图。如图29所示，接收机的重配方法包括：
S20：根据输入信号的频带信息生成控制信号，其中控制信号包括接收机重配所需的配置信息。
输入信号的频带信息包括至少一个频带的频带信息，即输入信号可以为单频带信号或双频带信号甚至多频带信号。控制信号为选通信号，或配置信号。接收机重配所需的配置信息包括如下至少一种：系统时钟、或数字中频处理速率、或数模转换采样率、或模数转换采样率。如果输入信号的频带信息包括至少两个频带的频带信息，则根据至少两个频带信息，分别生成配置信息。其中数字中频处理速率可以相同，或者不相同。
S21：根据系统自适应控制电路生成的控制信号生成系统时钟。
其中，系统时钟包括进行预处理和数字中频处理所需的时钟以及进行数模转换所需的时钟。例如，若输入信号包括带宽为20MHz，频点为1.9GHz的第一频带和带宽为60MHz，频点为2.35GHz的第二频带，则所生成的系统时钟有三个：184.32MHz、368.64 MHz以及2949.12 MHz，其中，184.32MHz和368.64 MHz分别用于20MHz的第一频带和60MHz的第二频带的数字中频处理，2949.12 MHz用于两频带的模数转换。
S22：接收模拟信号。其中，通过天线和环形器接收模拟信号以用于后续的处理。
S23：根据系统时钟和控制信号对接收的模拟信号进行处理，生成数字中频信号。
接收的模拟信号经滤波、放大等模拟处理后，根据系统时钟和控制信号进行模拟滤波，并以一定的数模转换采样率转换成数字信号，然后频谱搬移到零频上，下变频为数字中频信号。若输入信号的频带信息包括至少两个频带的频带信息，则将不同载频上的数字信号搬移到零频上，再下变频为对应频带的数字中频信号。例如，如果输入信号包括带宽为20MHz，频点为1.9GHz的第一频带和带宽为60MHz，频点为2.35GHz的第二频带，则接收的模拟信号数模转换成数字信号后，在1.9GHz的载频上和2.35GHz的载频上各有一个对应频带的信号，在进行频谱搬移时，分别将采样得到的这两个载频上的数字信号搬移到零频上并进行下变频以分别得到带宽为20MHz和带宽为60MHz的数字中频信号。
S24: 根据系统时钟和控制信号对数字中频信号进行处理，生成基带信号。
在S24中，若输入信号的频带信息包括至少两个频带的频带信息，则需要将至少两个数字中频信号进行下变频处理，生成对应频带的基带信号。
若数字中频信号为多载波信号，则在进行下变频处理之前，需要对该数字中频信号进行信号分离，即对该数字中频信号进行频谱搬移，然后滤波，以得到多个单载波信号，且信号带宽与基带信号的带宽相同。如此即完成了对接收机的重配，可见本发明能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置，以使每个频带信号的处理在尽可能低的数字中频处理速率下，以有效降低数字中频处理速率，减小系统时延，节省资源，并保证处理性能。
综上所述，本发明通过系统自适应控制电路根据输入信号的频带信息生成控制信号，其中控制信号包括发射机重配所需的配置信息，系统时钟电路根据控制信号生成系统时钟；如此能够根据不同频带信号的载频和带宽等对系统时钟和数字中频处理速率进行灵活配置。预处理电路根据系统时钟和控制信号对接收的基带信号进行预处理，生成频带信号；数字中频处理电路根据系统时钟和控制信号对预处理电路生成的频带信号进行处理，生成数字中频信号；数模转换电路根据系统时钟控和控制信号对数字中频处理电路生成的数字中频信号进行处理，生成模拟信号；模拟发射电路发射数模转换电路生成的模拟信号，如此使得每个频带信号的处理在尽可能低的数字中频处理速率下，可以有效降低数字中频处理速率，减小系统时延，节省资源，同时保证处理性能。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种可重配的发射机，其特征在于，所述发射机包括：
    系统自适应控制电路，用于根据输入信号的频带信息生成控制信号，其中所述控制信号包括所述发射机重配所需的配置信息；
    系统时钟电路，用于根据所述系统自适应控制电路生成的所述控制信号生成系统时钟；
    预处理电路，用于根据所述系统时钟和所述控制信号对接收的基带信号进行预处理，生成频带信号；
    数字中频处理电路，用于根据所述系统时钟和所述控制信号对所述预处理电路生成的所述频带信号进行处理，生成数字中频信号；
    数模转换电路，用于根据所述系统时钟和所述控制信号对所述数字中频处理电路生成的所述数字中频信号进行处理，生成模拟信号；
    模拟发射电路，用于发射所述数模转换电路生成的所述模拟信号。
  2. 根据权利要求1所述的发射机，其特征在于，所述发射机重配所需的配置信息包括如下至少一种：
    系统时钟；或，
    数字中频处理速率；或，
    数模转换采样率；或，
    模数转换采样率。
  3. 根据权利要求1所述的发射机，其特征在于所述发射机还包括反馈模数转换电路，用于根据所述系统时钟和所述控制信号对反馈的模拟信号进行处理，生成数字中频信号。
  4. 根据权利要求3所述的发射机，其特征在于，所述数字中频处理电路包括数字预失真系数训练电路，用于：
    根据所述系统时钟和所述控制信号对所述反馈模数转换电路生成的所述数字中频信号进行数字预失真系数训练，生成数字预失真系数。
  5. 根据权利要求4所述的发射机，其特征在于，所述数字中频处理电路还包括数字预失真电路，用于：
    根据所述系统时钟、所述控制信号以及所述数字预失真系数对所述预处理电路生成的频带信号进行数字预失真处理，生成数字中频信号。
  6. 根据权利要求1所述的发射机，其特征在于，若所述输入信号的频带信息包括至少两个频带的频带信息，则所述系统自适应控制电路根据所述至少两个频带信息，分别生成配置信息。
  7. 根据权利要求 6所述的发射机，其特征在于，若所述系统自适应控制电路根据所述至少两个频带信息，分别生成不同的配置信息，则所述预处理电路还用于：
    根据所述至少两个基带信号中的任一基带信号对应的系统时钟和控制信号，生成与所述任一基带信号对应的频带信号。
  8. 一种发射机的重配方法，其特征在于，所述方法包括：
    根据输入信号的频带信息生成控制信号，其中所述控制信号包括所述发射机重配所需的配置信息；
    根据所述控制信号生成系统时钟；
    根据所述系统时钟和所述控制信号对接收的基带信号进行预处理，生成频带信号；
    根据所述系统时钟和所述控制信号对预处理生成的所述频带信号进行处理，生成数字中频信号；
    根据所述系统时钟和所述控制信号对所述数字中频信号进行处理，生成模拟信号；
    发射所述模拟信号。
  9. 根据权利要求8所述的方法，其特征在于，所述发射机重配所需的配置信息包括如下至少一种：
    系统时钟；或，
    数字中频处理速率；或，
    数模转换采样率；或，
    模数转换采样率。
  10. 根据权利要求8所述的方法，其特征在于，所述方法还包括：根据所述系统时钟和所述控制信号对反馈的模拟信号进行处理，生成数字中频信号。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：根据所述系统时钟和所述控制信号对所述数字中频信号进行数字预失真系数训练，生成数字预失真系数。
  12. 根据权利要求11所述的方法，其特征在于，所述根据所述系统时钟和所述控制信号对所述频带信号进行处理，生成数字中频信号的步骤包括：根据所述系统时钟、所述控制信号以及所述数字预失真系数对所述频带信号进行数字预失真处理，生成数字中频信号。
  13. 根据权利要求8所述的方法，其特征在于，若所述输入信号的频带信息包括至少两个频带的频带信息，则所述根据输入信号的频带信息生成控制信号的步骤包括：根据所述至少两个频带信息，分别生成配置信息。
  14. 根据权利要求13所述的方法，其特征在于，若根据所述至少两个频带信息，分别生成不同的配置信息，则所述根据所述系统时钟和所述控制信号对接收的基带信号进行预处理，生成频带信号的步骤包括：根据所述至少两个基带信号中的任一基带信号对应的系统时钟和控制信号，生成与所述任一基带信号对应的频带信号。
  15. 一种可重配的接收机，其特征在于，所述接收机包括：
    系统自适应控制电路，用于根据输入信号的频带信息，生成控制信号，其中所述控制信号包括所述接收机重配所需的配置信息；
    系统时钟电路，用于根据所述系统自适应控制电路生成的所述控制信号，生成系统时钟；
    模拟接收电路，用于接收模拟信号；
    接收模数转换电路，用于根据所述系统时钟和所述控制信号对所述模拟接收电路接收的所述模拟信号进行处理，生成数字中频信号；
    后处理电路，用于根据所述系统时钟和所述控制信号对所述接收模数转换电路生成的所述数字中频信号进行处理，生成所述基带信号。
  16. 根据权利要求15所述的接收机，其特征在于，所述接收机重配所需的配置信息包括如下至少一种：
    系统时钟；或，
    数字中频处理速率；或，
    数模转换采样率；或，
    模数转换采样率。
  17. 根据权利要求15所述的接收机，其特征在于，若所述输入信号的频带信息包括至少两个频带的频带信息，则所述系统自适应控制电路根据所述至少两个频带信息，分别生成配置信息。
  18. 一种接收机的重配方法，其特征在于，所述方法包括：
    根据输入信号的频带信息生成控制信号，其中所述控制信号包括所述接收机重配所需的配置信息；
    根据所述系统自适应控制电路生成的所述控制信号生成系统时钟；
    接收模拟信号；
    根据所述系统时钟和所述控制信号对所述模拟信号进行处理，生成数字中频信号；
    根据所述系统时钟和所述控制信号对所述数字中频信号进行处理，生成所述基带信号。
  19. 根据权利要求18所述的方法，其特征在于，所述接收机重配所需的配置信息包括如下至少一种：
    系统时钟；或，
    数字中频处理速率；或，
    数模转换采样率；或，
    模数转换采样率。
  20. 根据权利要求18所述的方法，其特征在于，若所述输入信号的频带信息包括至少两个频带的频带信息，则所述根据输入信号的频带信息生成控制信号的步骤包括：根据所述至少两个频带信息分别生成配置信息。
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