WO2021104169A1 - 适用于5g的零中频的硬件平台系统和射频拉远单元 - Google Patents

适用于5g的零中频的硬件平台系统和射频拉远单元 Download PDF

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WO2021104169A1
WO2021104169A1 PCT/CN2020/130474 CN2020130474W WO2021104169A1 WO 2021104169 A1 WO2021104169 A1 WO 2021104169A1 CN 2020130474 W CN2020130474 W CN 2020130474W WO 2021104169 A1 WO2021104169 A1 WO 2021104169A1
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radio frequency
radio
transceiver
hardware platform
platform system
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PCT/CN2020/130474
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English (en)
French (fr)
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陈高强
徐锡强
吴涛
胡鸿飞
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三维通信股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

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  • This application relates to the field of communication technology, and in particular to a zero-IF hardware platform system and a remote radio unit suitable for 5G.
  • 5G network equipment Compared with traditional network equipment, 5G network equipment has wider bandwidth and higher frequency band, and the requirements for high-speed, accuracy and stability of network transmission are also increasing.
  • the modulation and demodulation technology of the physical layer in the traditional wireless communication system is increasingly unable to meet today's needs.
  • Traditional wireless devices have low integration.
  • traditional superheterodyne receivers are widely used transceiver structures. The superheterodyne system needs to modulate the signal to the intermediate frequency first, and the signal is processed by up-conversion to obtain the radio frequency signal.
  • the power amplifier is located at the end of the radio frequency transmission link.
  • the main structure of the RF power amplifier is a transistor.
  • the performance of the power amplifier mainly depends on the characteristics of the semiconductor material of the transistor. Due to the characteristics of these semiconductor materials, the RF power amplifier has inherent memory effects and nonlinear characteristics. In order to improve the working efficiency of the radio frequency power amplifier and minimize the distortion interference caused by the non-linear characteristics of the memory of the power amplifier, it is necessary to linearize the power amplifier.
  • Digital pre-distortion Digital Pre-Distortion, referred to as DPD
  • DPD Digital Pre-Distortion
  • the digital predistortion technology requires the feedback path to sample the output of the power amplifier to obtain the feedback path signal.
  • the spectrum expansion caused by the nonlinearity of the power amplifier makes the bandwidth of the feedback signal several times the original bandwidth.
  • the traditional superheterodyne system currently cannot meet the RF bandwidth requirements of 100MHz and above, and the feedback path bandwidth requirements of 400MHz or above that are required by the application of digital predistortion technology on the RF bandwidth.
  • the traditional superheterodyne system because the superheterodyne receiver is susceptible to frequency-domain image interference, a complex filter device is required. Therefore, the traditional superheterodyne system requires high frequency selectivity, which makes different systems, The hardware platforms of different frequency bands need to adapt the corresponding filter components, which makes the hardware platforms unable to be universal. At the same time, the increase of these filter components has also led to low integration and increased power consumption of the superheterodyne system.
  • a zero-IF hardware platform system includes: a baseband processor, a radio transceiver, a radio frequency transceiver link module, and a feedback module.
  • the baseband processor is coupled to the radio transceiver, the radio frequency receiving end and the radio frequency transmitting end of the radio transceiver are respectively coupled to the radio frequency transceiver link module, and the feedback module is coupled to the radio frequency transceiver chain Between the circuit module and the feedback receiving end of the radio transceiver.
  • the baseband processor supports digital predistortion processing of signals no less than 450MHz; the receiving bandwidth of the radio transceiver is no less than 200MHz, the transmission bandwidth is no less than 450MHz, and the The feedback bandwidth of the radio transceiver is not less than 450MHz.
  • the zero-IF hardware platform system further includes: an eCPRI interface, and the eCPRI interface is coupled with the baseband processor.
  • the zero-IF hardware platform system further includes: a clock module, the clock module is respectively coupled with the baseband processor and the radio transceiver, wherein,
  • the baseband processor is further configured to recover a clock signal from the eCPRI interface
  • the clock module is configured to generate a working clock signal with the same phase as the clock signal recovered from the eCPRI interface, and provide the working clock signal to the baseband processor and the radio transceiver.
  • the clock module includes: a two-stage phase-locked loop unit, the two-stage phase-locked loop unit includes a voltage-controlled oscillator, and the voltage-controlled oscillator is used to divide the frequency of the working clock signal It is a plurality of clock signals, which are respectively provided to the baseband processor and the radio transceiver.
  • the radio transceiver includes N pairs of radio frequency receiving ends and radio frequency transmitting ends, and a feedback receiving end, and the number of the radio frequency transceiver link module and the feedback module is M; wherein , Each of the radio frequency transceiver link modules is coupled to a pair of the radio frequency receiving end and the radio frequency transmitting end of the radio transceiver, and each of the feedback modules is coupled to the feedback receiver of the radio transceiver Between the terminal and one of the RF transceiver link modules, N ⁇ M ⁇ 1, and N and M are integers.
  • the number of the radio transceiver is one or more.
  • the radio frequency transceiver link module includes: a radio frequency receiving link, a radio frequency sending link, and a duplex filter, wherein both the radio frequency receiving link and the radio frequency sending link pass through the The duplex filter is coupled with the antenna; the radio frequency receiving link includes a low-noise amplifying module, and the radio frequency transmitting link includes a power amplifying module.
  • the baseband processor includes: ZYNQ series chips; the radio transceiver includes at least one of the following: ADRV9009 series chips, AFE768x series chips.
  • a remote radio frequency unit includes a multiple-input multiple-output antenna system and the aforementioned zero-IF hardware platform system.
  • a zero-IF hardware platform system including a baseband processor, a radio transceiver, a radio frequency transceiver link module and a feedback module is adopted.
  • the baseband processor is coupled with the radio transceiver, and the radio frequency receiver of the radio transceiver
  • the radio frequency transmitting end is coupled with the radio frequency transceiver link module
  • the feedback module is coupled between the radio frequency transceiver link module and the feedback receiving end of the radio transceiver, which solves the problem of the traditional superheterodyne system hardware platform with large volume and power.
  • the problem of high consumption and the inability of different standards and different frequency bands to be universal reduces the size and power consumption of the hardware platform system, and can be universally used in different standards and different frequency bands.
  • Fig. 1 is a schematic structural diagram of a hardware platform system according to an embodiment of the present application.
  • Fig. 2 is a first structural diagram of a hardware platform system according to a preferred embodiment of the present application.
  • Fig. 3 is a second structural diagram of the hardware platform system of the preferred embodiment of the present application.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access Wireless
  • FDMA Frequency Division Multiple access
  • OFDMA Orthogonal Frequency-Division Multiple Access
  • SC-FDMA Single carrier FDMA
  • General Packet Radio Service General Packet Radio Service
  • LTE Long Term Evolution
  • NR 5G New Radio
  • the hardware platform system provided in this embodiment can be integrated in a base station, a radio remote unit (RRU for short), or any other network element equipment that needs to perform radio frequency transceiving.
  • the base station in this document may be a device that communicates with a wireless terminal through one or more sectors on the air interface in an access network.
  • the base station can be used to convert the received air frame and Internet Protocol (IP) packets to each other, as a router between the wireless terminal and the rest of the access network, where the rest of the access network can include IP The internet.
  • IP Internet Protocol
  • the base station can also coordinate the attribute management of the air interface.
  • the base station can be a base station (Base Transceiver Station, referred to as BTS) in GSM or CDMA, a base station (NodeB) in WCDMA, or an evolved base station (evolutional NodeB, referred to as eNB or e -NodeB), it may also be a generation NodeB (gNB for short) in 5G NR, which is not limited in this application.
  • BTS Base Transceiver Station
  • NodeB base station
  • eNB evolved base station
  • gNB generation NodeB
  • a hardware platform system suitable for 5G is provided.
  • Fig. 1 is a schematic structural diagram of a hardware platform system of an embodiment of the present application.
  • the hardware platform system includes: a baseband processor 10, a radio transceiver 20, a radio frequency transceiver link module 30, and a feedback module 40.
  • the baseband processor 10 is coupled to the radio transceiver 20.
  • the radio frequency receiving end and the radio frequency transmitting end of the radio transceiver 20 are respectively coupled to the radio frequency transceiver link module 30, and the feedback module 40 is coupled to the radio frequency transceiver link module 30 and the radio. Between the feedback receiving ends of the transceiver 20.
  • the zero-intermediate frequency (ZIF) hardware platform system of this embodiment directly modulates the baseband signal obtained by the baseband processor 10 to the radio frequency, and does not perform the two-step process of the super-heterodyne device.
  • the sub-spectrum shift and filtering process improves the integration of the system.
  • the use of the integrated chip of the baseband processor 10 and the radio transceiver 20 further mentions the integration level of the system, so that the transceiver can be made small, while reducing the cost and system power consumption.
  • the zero-IF hardware platform system does not require the consideration of suppressing the image frequency like the superheterodyne system, it reduces the difficulty of designing the system; it does not require complex filter components, which reduces the system’s high frequency selectivity requirements, and makes the hardware platform It can be universally applied to hardware platforms of different standards and different frequency bands, which also improves integration and reduces cost and power consumption.
  • the baseband processor 10 preferably supports digital predistortion processing of signals not lower than 450MHz; the receiving bandwidth of the radio transceiver 20 (Transceiver) is not Below 200MHz, the transmission bandwidth is not less than 450MHz, and the feedback bandwidth of the radio transceiver 20 is not less than 450MHz.
  • the hardware platform system using the above-mentioned baseband processor 10 and the radio transceiver 20 can meet the needs of the 5G frequency band, and because the above-mentioned hardware platform system has low frequency selectivity requirements, the specific frequency bands of the above-mentioned hardware platform system can be flexibly configured Into any bandwidth below 200MHz, such as 5MHz ⁇ 10MHz ⁇ 15MHz ⁇ 20MHz ⁇ 60MHz ⁇ 100MH ⁇ 200MHz.
  • the above hardware platform system can be applied to the power amplification system based on the large bandwidth DPD technology in the 5G frequency band, such as the 5G frequency optical fiber repeater or other 5G frequency remote radio units, and supports 100MHz or 160MHz, etc.
  • Power amplifier system with flexible bandwidth and configurable. For example, you can configure the parameters of the radio transceiver 20 according to the system requirements, so that the system can be configured to support the 5G frequency band of China Mobile, the 5G frequency band of China Unicom, the 5G frequency band of China Telecom, and the 5G frequency bands of 6GHz and below in other Japanese and European countries. system.
  • the baseband processor 10 preferably adopts a Field Programmable Gate Array (Field Programmable Gate Array, FPGA for short) chip.
  • the performance requirements for the FPGA chip include: supporting digital predistortion technology, especially supporting the digital predistortion technology 7.0 intellectual property (IP) core, so that the baseband processor 10 supports digital predistortion processing of signals not lower than 450MHz.
  • the baseband processor 10 includes, but is not limited to, the ZYNQ series of chips from Xilinx. Among them, the ZYNQ series of platform chips integrate two ARM Cotex A9 processors and programmable logic
  • the radio transceiver 20 is mainly used to implement the mixing, sampling, demodulation, modulation, data serial-to-parallel conversion, and Quasi-Monte Carlo (QMC) processing of radio frequency signals.
  • LDL Local Oscillator Leakage
  • the radio transceiver 20 adopts a chip that supports multi-channel radio frequency reception and multi-channel radio frequency transmission and has a feedback channel, such as the ADRV9009 series chip of Analog Devices (AD for short).
  • the configurable frequency band of this series of chips is 75MHz ⁇ 6GHz, with two radio frequency receiving, two radio frequency sending and one feedback channel.
  • the receiving bandwidth is not less than 200MHz
  • the transmission bandwidth is not less than 450MHz
  • the feedback channel bandwidth is not less than 450MHz.
  • the feedback module 40 in this embodiment is used to obtain output power information from the power amplifier module, and provide the output power information to the baseband processor 10 for DPD technology processing.
  • the output power information includes but is not limited to: output power size, output waveform shape and other parameters.
  • the feedback module 40 obtains the output power information from the power amplifier module in the radio frequency transceiver link module 30, it feeds the information back to the feedback channel of the radio transceiver 20, and performs frequency mixing through the radio transceiver 20.
  • A/D conversion, etc. extract the radio frequency signal into a baseband signal, and send it to the baseband processor 10 through the serial interface between the radio transceiver 20 and the baseband processor 10.
  • the baseband processor 10 uses an algorithm to preprocess the signal. Distortion processing to improve the Adjacent Channel Power Ratio (ACPR) performance of the downlink output signal.
  • ACPR Adjacent Channel Power Ratio
  • Fig. 2 is a structural schematic diagram 1 of the hardware platform system of the preferred embodiment of the present application.
  • the zero-IF hardware platform system also includes: Evolution Common Public Radio Interface (evolution Common Public Radio) Interface, referred to as eCPRI for short) 50, the eCPRI interface 50 is coupled with the baseband processor 10.
  • eCPRI interface 50 is used to receive and return baseband signals.
  • the eCPRI interface 50 can flexibly adapt to a base station with a standard eCPRI interface 50 and connect with the optical interface of the base station to realize interactive communication with the base station.
  • the baseband processor 10 supports multiple optical path interfaces, and each optical path interface is coupled to an eCPRI interface 50.
  • each optical path interface is coupled to an eCPRI interface 50.
  • the baseband processor 10 is coupled with two eCPRI interfaces 50, one eCPRI interface 50 can be used to support the uplink port, and one eCPRI interface 50 can be used to support the downlink port, thereby realizing chain networking.
  • the chain networking can be expanded to a 5G system platform including 6 hardware platform systems of this embodiment at most.
  • the zero-IF hardware platform system further includes: a clock module 60, which is respectively coupled with the baseband processor 10 and the radio transceiver 20, wherein the baseband processor 10, It is also used to recover the clock signal from the eCPRI interface 50; the clock module 60 is used to generate a working clock signal with the same phase as the clock signal recovered from the eCPRI interface 50, and to provide the working clock signal to the baseband processor 10 and the radio transceiver for dual purposes Machine 20.
  • a clock module 60 which is respectively coupled with the baseband processor 10 and the radio transceiver 20, wherein the baseband processor 10, It is also used to recover the clock signal from the eCPRI interface 50; the clock module 60 is used to generate a working clock signal with the same phase as the clock signal recovered from the eCPRI interface 50, and to provide the working clock signal to the baseband processor 10 and the radio transceiver for dual purposes Machine 20.
  • the baseband processor 10 recovers a clock signal from the baseband signal received from the eCPRI interface 50 as the input clock of the clock module 60, and then the clock module 60 generates the same phase as the clock signal recovered from the eCPRI interface 50
  • the clock module 60 provides the working clock signal to the baseband processor 10 and the radio transceiver 20, which realizes the recovery of the clock from the upper-level clock for the hardware platform system to use, and reaches the local clock The effect of synchronizing with the upper-level clock.
  • the clock module 60 includes: a two-stage phase-locked loop unit, the two-stage phase-locked loop unit includes a voltage-controlled oscillator, and the voltage-controlled oscillator is used to divide the working clock signal into multiple
  • the clock signal is provided to the baseband processor 10 and the radio transceiver 20 respectively.
  • the clock signal recovered by the baseband processor 10 from the eCPRI interface 50 is used as the input clock, and the working clock signal with the same phase as the recovered clock signal is obtained by phase-locking through the two-stage phase-locked loop unit, and then through the voltage-controlled oscillation
  • the Voltage-Controlled Oscillator (VCO) divides the clock signal and supplies it to the baseband processor 10 and the radio transceiver 20, so as to realize the synchronization of the baseband processor 10 and the radio transceiver 20 with the upper-level clock .
  • clock module 60 is not limited to the above-mentioned clock module 60 with a two-stage phase-locked loop unit, and other clock modules 60 that can achieve the same or similar effects are also applicable to this embodiment.
  • the radio transceiver 20 includes N pairs of radio frequency receiving ends and radio frequency transmitting ends, and feedback receiving ends.
  • the number of the radio frequency transceiver link module 30 and the feedback module 40 is M;
  • the radio frequency transceiver link module 30 is coupled to one of the radio frequency receiving end and the radio frequency transmitting end of the radio transceiver 20, and each feedback module 40 is coupled to the feedback receiving end of the radio transceiver 20 and one of the radio frequency transceiver chains.
  • N ⁇ M ⁇ 1, and N and M are both integers.
  • the chip has two pairs of radio frequency receiving ends and radio frequency transmitting ends, and can support the simultaneous connection of two radio frequency transceiver link modules 30 and two feedback modules 40 at most. It can be seen that the use of the ADRV9009 chip with 2 radio frequency receivers, 2 radio frequency transmitters and 1 feedback receiver can realize multiple input and multiple output (2T2R, also called 2 ⁇ 2) that supports two transmissions and two receptions ( Multiple Input Multiple Output (referred to as MIMO) antenna system.
  • 2T2R also called 2 ⁇ 2 ⁇ 2
  • MIMO Multiple Input Multiple Output
  • the number of the radio transceiver 20 may be one or more.
  • FIG. 3 is the second structural diagram of the hardware platform system of the preferred embodiment of the present application. As shown in FIG. 3, in this embodiment, the number of radio transceivers 20 is two. Still taking the radio transceiver 20 as the ADRV9009 chip as an example, to realize the support of a multi-MIMO antenna system with four transmissions and four receptions (4T4R, also known as 4 ⁇ 4), a hardware platform with two ADRV9009 chips is adopted. System, and configure a radio frequency transceiver link module 30, a feedback module 40 and an antenna on each pair of transceiver channels. By analogy, with the method provided in this embodiment, support for more antenna systems for transmission and reception can also be achieved, and a high degree of device integration can be ensured.
  • the radio frequency transceiver link module 30 includes: a radio frequency receiving link, a radio frequency sending link, and a duplex filter 33, wherein the radio frequency receiving link and the radio frequency sending link pass The duplex filter is coupled with the antenna.
  • the radio frequency receiving link includes a low-noise amplifier module 31, and the radio frequency transmitting link includes a power amplifier module 32.
  • the duplex filter 33 is preferably composed of a cavity duplexer and a cavity filter module.
  • the frequency band module in the power amplifier module, the duplex filter, and the antenna connected to the hardware platform system can all be flexibly configured according to the frequency band and power requirements of different operators.
  • the power amplifying modules in this embodiment also use power amplifying modules that support a 450MHz bandwidth and an adjustable output power of up to 46dBm.
  • Each power amplifying module can support 5G frequency bands of different formats and different frequency bands below 6GHz.
  • the power amplifier module provided in this embodiment may be integrated in at least one chip, for example, an application-specific integrated circuit (ASIC for short), or may be composed of at least one discrete device; or It is a chip system that includes at least one chip and at least one discrete device. This embodiment does not limit the specific implementation form of the power amplifier module.
  • ASIC application-specific integrated circuit
  • the hardware platform system further includes a local network port module 70, and the local network port module 70 is used to connect with the network management system to implement remote parameter configuration of the hardware platform system.
  • the hardware platform system also includes a storage module 80, which is used to store configuration information.
  • the hardware platform system further includes a power supply module 90, which is mainly used to supply power to the baseband processor 10, the radio transceiver 20, and the power amplifier module. It should be noted that in a hardware platform system that uses multiple radio transceivers 20 to implement support for a multiple MIMO antenna system, the carrying capacity of the power supply module 90 needs to be appropriately increased as required.
  • the power supply module 90 of this embodiment converts 220V (or -48V) power into 12V and 30V through an AC/DC (or DC/DC) module, and passes through the baseband processing board in the The DC/DC module and the Low Dropout Regulator (LDO) chip are converted into the working voltage required by each chip or module in the board to achieve stable power supply.
  • DC/DC Low Dropout Regulator
  • a remote radio unit is also provided.
  • the remote radio unit includes a MIMO antenna system and the aforementioned zero-IF hardware platform system.
  • the highly integrated transceiver chip solution of this embodiment is used to combine traditional discrete ADCs, DACs, and mixers.
  • Discrete devices such as single-chip solutions are used instead, which greatly reduces the layout area and power consumption, and is very suitable for 5G array antennas with multiple input multiple output (massive Multiple Input Multiple Output, referred to as massive MIMO) application scenarios.
  • massive MIMO massive MIMO
  • the radio frequency bandwidth and DPD bandwidth are greatly improved, thereby meeting the requirement of 5G large bandwidth.
  • Adopting the zero-IF solution of this embodiment does not require special frequency filter components, so that 5G mobile communication requirements of different frequency bands and different standards can be flexibly supported.
  • the disclosed system, device, or method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be It can be combined or integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the foregoing processor may include a central processing unit (CPU), or a specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
  • the above-mentioned storage medium can be used for mass storage of data or instructions.
  • the memory may include a hard disk drive (Hard Disk Drive, referred to as HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape or Universal Serial Bus (Universal Bus, referred to as USB) drive or two A combination of one or more of these.
  • the storage may include removable or non-removable (or fixed) media.
  • the memory can be internal or external to the data processing device.
  • the memory is a non-volatile solid state memory.
  • the memory includes read-only memory (ROM).
  • ROM read-only memory
  • the ROM can be mask-programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically rewritable ROM (EAROM) or flash memory or A combination of two or more of these.

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Abstract

本申请涉及一种适用于5G的零中频的硬件平台系统和射频拉远单元。其中，该硬件平台系统包括基带处理器、无线电收发两用机、射频收发链路模块和反馈模块，其中，基带处理器与无线电收发两用机耦合，无线电收发两用机的射频接收端和射频发送端分别与射频收发链路模块耦合，反馈模块耦合在射频收发链路模块和无线电收发两用机的反馈接收端之间。通过本申请，解决了传统的超外差系统的硬件平台体积大、功耗高且不同制式和不同频段无法通用的问题，降低了硬件平台系统的体积、功耗，并且能够通用于不同制式和不同频段。

Description

适用于5G的零中频的硬件平台系统和射频拉远单元
相关申请
本申请要求2019年11月29日申请的，申请号为201911198787.6，发明名称为“一种适用于5G的零中频的硬件平台系统和射频拉远单元”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，特别是涉及一种适用于5G的零中频的硬件平台系统和射频拉远单元。
背景技术
随着社会的发展、行业的进步以及用户对移动互联网络需求的日益增长，全球各大运营商开始对5G网络进行建设。相比传统的网络设备，5G网络设备带宽更宽、频段更高，对网络传输的高速性、准确性和稳定性要求也越来越高。而传统的无线通信系统中的物理层的调制解调技术越来越无法满足如今的需求。传统的无线设备集成度低，例如传统的超外差接收机就是目前应用十分广泛的收发机结构，超外差系统需要将信号首先调制到中频，将信号通过上变频处理得到射频信号，为了实现上述的功能，在超外差系统中需要采用分立的模/数转换器(Analog-to-Digital Converter，简称为ADC)、数/模转换器(Digital-to-Analog Converter，简称为DAC)、mixer等中射频硬件，造成了发射/接收系统电路复杂、器件多，同时也带来了功耗大和成本高的问题。上述问题在阵列天线多输入多输出(massive Multiple Input Multiple Output，简称为massive MIMO)系统中尤为突出。
功率放大器作为通信系统的重要部分，位于射频发送链路的最末端。射频功率放大器的主要结构是晶体管，功放的性能主要取决于晶体管的半导体材料的特性，由于这些半导体材料的自身特性，造成了射频功放存在固有的记忆效应和非线性特性。为了提高射频功放的工作效率，同时尽量降低功放有记忆非线性特性带来的失真干扰，需要对功放进行线性化处理。
数字预失真(Digital Pre-Distortion，简称为DPD)技术是一种受到广泛研究和应用的功放线性化技术。而数字预失真技术需要反馈通路将功放输出进行采样，得到反馈通路信号，由于功放非线性造成的频谱扩展，使得反馈信号的带宽是原带宽的数倍。然而传统的超外差 系统目前尚无法满足100MHz及以上的射频带宽需求，以及在该射频带宽上应用数字预失真技术需求的400MHz以上的反馈通路带宽的需求。
此外，传统的超外差系统中，由于超外差接收机容易受到频域镜像干扰，从而需要结构复杂的滤波器件，因此传统的超外差系统对频率选择性要求高，这使得不同制式、不同频段的硬件平台需要适配对应的滤波器件，从而导致了硬件平台无法通用。同时，这些滤波器件的增加也导致了超外差系统的集成度不高、功耗增大。
发明内容
根据本申请的各种实施例，提供一种零中频的硬件平台系统，所述零中频的硬件平台系统包括：基带处理器、无线电收发两用机、射频收发链路模块和反馈模块，所述基带处理器与所述无线电收发两用机耦合，所述无线电收发两用机的射频接收端和射频发送端分别与所述射频收发链路模块耦合，所述反馈模块耦合在所述射频收发链路模块和所述无线电收发两用机的反馈接收端之间。
在其中一些实施例中，所述基带处理器支持不低于450MHz的信号的数字预失真处理；所述无线电收发两用机的接收带宽不低于200MHz，发送带宽不低于450MHz，且所述无线电收发两用机的反馈带宽不低于450MHz。
在其中一些实施例中，所述零中频的硬件平台系统还包括：eCPRI接口，所述eCPRI接口与所述基带处理器耦合。
在其中一些实施例中，所述零中频的硬件平台系统还包括：时钟模块，所述时钟模块分别与所述基带处理器和所述无线电收发两用机耦合，其中，
所述基带处理器，还用于从所述eCPRI接口恢复时钟信号；
所述时钟模块，用于生成与从所述eCPRI接口恢复的时钟信号同相位的工作时钟信号，并将所述工作时钟信号提供给所述基带处理器和所述无线电收发两用机。
在其中一些实施例中，所述时钟模块包括：二级锁相环单元，所述二级锁相环单元包括压控振荡器，所述压控振荡器用于将所述工作时钟信号分频为多个时钟信号，并分别提供给所述基带处理器和所述无线电收发两用机。
在其中一些实施例中，所述无线电收发两用机包括N对射频接收端和射频发射端，以及反馈接收端，所述射频收发链路模块和所述反馈模块的数量均为M个；其中，每个所述射频收发链路模块耦合至所述无线电收发两用机的其中一对射频接收端和射频发送端，每个所述反馈模块均耦合在所述无线电收发两用机的反馈接收端和其中一个射频收发链路模块之间，N≥M≥1，且N、M均为整数。
在其中一些实施例中，所述无线电收发两用机的数量为一个或多个。
在其中一些实施例中，所述射频收发链路模块包括：射频接收链路、射频发送链路、双工滤波器，其中，所述射频接收链路、所述射频发送链路均通过所述双工滤波器与天线耦合；所述射频接收链路包括低噪放大模块，所述射频发送链路包括功率放大模块。
在其中一些实施例中，所述基带处理器包括：ZYNQ系列芯片；所述无线电收发两用机包括以下至少之一：ADRV9009系列芯片、AFE768x系列芯片。
根据本申请的各种实施例，还提供一种射频拉远单元，所述射频拉远单元包括多输入多输出天线系统和上述的零中频的硬件平台系统。
上述零中频的硬件平台系统和射频拉远单元具有以下优点：
采用包括基带处理器、无线电收发两用机、射频收发链路模块和反馈模块的零中频的硬件平台系统，其中，基带处理器与无线电收发两用机耦合，无线电收发两用机的射频接收端和射频发送端分别与射频收发链路模块耦合，反馈模块耦合在射频收发链路模块和无线电收发两用机的反馈接收端之间，解决了传统的超外差系统的硬件平台体积大、功耗高且不同制式和不同频段无法通用的问题，降低了硬件平台系统的体积、功耗，并且能够通用于不同制式和不同频段。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是本申请实施例的硬件平台系统的结构示意图。
图2是本申请优选实施例的硬件平台系统的结构示意图一。
图3是本申请优选实施例的硬件平台系统的结构示意图二。
具体实施方式
为了便于理解本申请，为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请，附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的 具体实施例的限制。
显而易见地，下面描述中的附图仅仅是本申请的一些示例或实施例，对于本领域的普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图将本申请应用于其他类似情景。此外，还可以理解的是，虽然这种开发过程中所作出的努力可能是复杂并且冗长的，然而对于与本申请公开的内容相关的本领域的普通技术人员而言，在本申请揭露的技术内容的基础上进行的一些设计，制造或者生产等变更只是常规的技术手段，不应当理解为本申请公开的内容不充分。
在本申请中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域普通技术人员显式地和隐式地理解的是，本申请所描述的实施例在不冲突的情况下，可以与其它实施例相结合。
除非另作定义，本申请所涉及的技术术语或者科学术语应当为本申请所属技术领域内具有一般技能的人士所理解的通常意义。本申请所涉及的“一”、“一个”、“一种”、“该”等类似词语并不表示数量限制，可表示单数或复数。本申请所涉及的术语“包括”、“包含”、“具有”以及它们任何变形，意图在于覆盖不排他的包含；例如包含了一系列步骤或模块(单元)的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可以还包括没有列出的步骤或单元，或可以还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。本申请所涉及的“连接”、“相连”、“耦接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电气的连接，不管是直接的还是间接的。本申请所涉及的“多个”、“各个”、“不同”是指两个或两个以上。“和/或”描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。本申请所涉及的术语“第一”、“第二”等仅仅是区别类似的对象，不代表针对对象的特定排序。
本文中描述的各种技术可用于各种无线通信系统，例如2G、3G、4G、5G通信系统以及下一代通信系统，又例如全球移动通信系统(Global System for Mobile communications，简称为GSM)，码分多址(Code Division Multiple Access，简称为CDMA)系统，时分多址(Time Division Multiple Access，简称为TDMA)系统，宽带码分多址(Wideband Code Division Multiple Access Wireless，简称为WCDMA)，频分多址(Frequency Division Multiple Addressing，简称为FDMA)系统，正交频分多址(Orthogonal Frequency-Division Multiple Access，简称为OFDMA)系统，单载波FDMA(SC-FDMA)系统，通用分组无线业务(General Packet Radio Service，简称为GPRS)系统，长期演进(Long Term Evolution，简称为LTE)系统，5G新 空口(New Radio，简称为NR)系统以及其他此类通信系统。
本实施例提供的硬件平台系统可集成在基站、射频拉远单元(Radio Remote Unit，简称为RRU)或者其他任意需要进行射频收发的网元设备中。本文中的基站可以是接入网中在空中接口上通过一个或多个扇区与无线终端通信的设备。基站可用于将收到的空中帧与网际协议(Internet Protocol，简称为IP)分组进行相互转换，作为无线终端与接入网的其余部分之间的路由器，其中接入网的其余部分可包括IP网络。基站还可协调对空中接口的属性管理。例如，基站可以是GSM或CDMA中的基站(Base Transceiver Station，简称为BTS)，也可以是WCDMA中的基站(NodeB)，还可以是LTE中的演进型基站(evolutional NodeB，简称为eNB或e-NodeB)，还可以是5G NR中的(generation NodeB，简称为gNB)，本申请并不限定。
在本实施例中提供了一种适用于5G的硬件平台系统。图1是本申请实施例的硬件平台系统的结构示意图，如图1所示，该硬件平台系统包括：基带处理器10、无线电收发两用机20、射频收发链路模块30和反馈模块40，基带处理器10与无线电收发两用机20耦合，无线电收发两用机20的射频接收端和射频发送端分别与射频收发链路模块30耦合，反馈模块40耦合在射频收发链路模块30和无线电收发两用机20的反馈接收端之间。
相对于超外差系统而言，本实施例的零中频(Zero Intermediate Frequency，简称为ZIF)的硬件平台系统直接将基带处理器10得到的基带信号调制到射频，不进行超外差设备的两次频谱搬移和滤波过程，提高了系统的集成度。此外，采用基带处理器10和无线电收发两用机20集成芯片，进一步提到了系统的集成度，从而可以将收发机做得很小，同时降低成本和系统功耗。另外，由于零中频的硬件平台系统不需要超外差系统那样的抑制镜像频率的考虑，降低了设计系统的难度；无需结构复杂的滤波器件，降低了系统对频率选择性要求高，使得硬件平台能够通用于不同制式、不同频段的硬件平台，同样也提高了集成度、降低了成本和功耗。
为了满足5G频段对硬件平台系统的需求，在本实施例中，优选地，基带处理器10支持不低于450MHz的信号的数字预失真处理；无线电收发两用机20(Transceiver)的接收带宽不低于200MHz，发送带宽不低于450MHz，且无线电收发两用机20的反馈带宽不低于450MHz。采用上述的基带处理器10和无线电收发两用机20的硬件平台系统能够满足5G频段的需求，并且，由于上述硬件平台系统对频率选择性要求低，上述的硬件平台系统的具体频段可以灵活配置成5MHz\10MHz\15MHz\20MHz\60MHz\100MH\200MHz等低于200MHz的任意带宽。
采用上述的硬件平台系统，可以应用于5G频段中基于大带宽的DPD技术的功率放 大系统中，例如5G频段的光纤直放站或者其他的5G频段的射频拉远单元，并且支持100MHz或160MHz等带宽灵活可配的功率放大系统。例如可以根据系统需求对无线电收发两用机20进行参数配置，从而将系统配置为支持中国移动5G频段、中国联通5G频段、中国电信5G频段，以及其他日欧美国家的6GHz及以下的5G频段的系统。
在本实施例中，基带处理器10优选采用现场可编程门阵列(Field Programmable Gate Array，简称为FPGA)芯片。对于该FPGA芯片的性能要求包括：支持数字预失真技术，尤其是支持数字预失真技术7.0知识产权(IP)核，以使得基带处理器10支持不低于450MHz的信号的数字预失真处理。基带处理器10包括但不限于赛灵思(Xilinx)公司的ZYNQ系列芯片。其中，ZYNQ系列的平台芯片集成有两个ARM Cotex A9处理器和可编程逻辑
(Programmable Logic，简称为PL)处理模块。
在本实施例中，无线电收发两用机20主要用于实现射频信号的混频、采样、解调、调制、数据串并转化以及准蒙特卡罗(Quasi-Monte Carlo，简称为QMC)处理、本振泄露(Local Oscillator Leakage，简称为LOL)追踪(Tracking)等功能。无线电收发两用机20采用支持多路射频接收、多路射频发送，并具有反馈通道的芯片，例如亚诺德半导体(Analog Devices，简称为AD)公司的ADRV9009系列芯片。该系列芯片的可配置频段为75MHz～6GHz，具有两路射频接收、两路射频发送和一路反馈通道，接收带宽不低于200MHz，发送带宽不低于450MHz，反馈通道带宽不低于450MHz。
在本实施例中的反馈模块40用于从功率放大模块上获取输出功率信息，并将输出功率信息提供给基带处理器10进行DPD技术处理。其中，输出功率信息包括但不限于：输出功率大小、输出波形形状等参数。反馈模块40从射频收发链路模块30中的功率放大模块中获取到输出功率信息后，将这些信息反馈到无线电收发两用机20的反馈通道，并通过无线电收发两用机20进行混频、A/D转换等将射频信号提取为基带信号，并经过无线电收发两用机20和基带处理器10之间的串行接口发送给基带处理器10，由基带处理器10采用算法对信号进行预失真处理，从而提高下行输出信号的邻信道功率比(Adjacent Channel Power Ratio，简称为ACPR)性能。
图2是本申请优选实施例的硬件平台系统的结构示意图一，如图2所示，在其中一些实施例中，零中频的硬件平台系统还包括：演进的通用公共无线电接口(evolution Common Public Radio Interface，简称为eCPRI)50，eCPRI接口50与基带处理器10耦合。在上述方式中，eCPRI接口50用于接收和回传基带信号，通过eCPRI接口50可以灵活适配拥有标准的eCPRI接口50的基站，并与基站的光接口对接，以实现与基站的交互通信。
较优地，在上述实施例中的硬件平台系统中，基带处理器10支持多个光路接口，每 个光路接口与一个eCPRI接口50耦合。在基带处理器10耦合了两个eCPRI接口50的情况下，可以使用一个eCPRI接口50支持上链口，一个eCPRI接口50支持下链口，从而实现链型组网。链型组网最多可以扩展得到包括6台本实施例的硬件平台系统的5G系统平台。
继续参考图2，在其中一些实施例中，零中频的硬件平台系统还包括：时钟模块60，时钟模块60分别与基带处理器10和无线电收发两用机20耦合，其中，基带处理器10，还用于从eCPRI接口50恢复时钟信号；时钟模块60，用于生成与从eCPRI接口50恢复的时钟信号同相位的工作时钟信号，并将工作时钟信号提供给基带处理器10和无线电收发两用机20。在本实施例中，基带处理器10在从eCPRI接口50接收到的基带信号中恢复出时钟信号作为时钟模块60的输入时钟，然后由时钟模块60生成与从eCPRI接口50恢复的时钟信号同相位的工作时钟信号，并由时钟模块60将工作时钟信号提供给基带处理器10和无线电收发两用机20，实现了从上一级的时钟中恢复出时钟给硬件平台系统使用，达到了本地时钟同步于上一级时钟的效果。
较优地，在其中一些实施例中，时钟模块60包括：二级锁相环单元，二级锁相环单元包括压控振荡器，压控振荡器用于将工作时钟信号分频为多个时钟信号，并将时钟信号分别提供给基带处理器10和无线电收发两用机20。在本实施例中，基带处理器10从eCPRI接口50恢复的时钟信号作为输入时钟，通过二级锁相环单元锁相得到与恢复的时钟信号同相位的工作时钟信号，然后再通过压控振荡器(Voltage-Controlled Oscillator，简称为VCO)分频出时钟信号提供给基带处理器10和无线电收发两用机20，从而实现基带处理器10和无线电收发两用机20与上一级时钟的同步。
当然，需要说明的是，时钟模块60并不限于上述具有二级锁相环单元的时钟模块60，其他能够实现相同或者相似效果的时钟模块60也适用于本实施例。
在其中一些实施例中，无线电收发两用机20包括N对射频接收端和射频发射端，以及反馈接收端，射频收发链路模块30和反馈模块40的数量均为M个；其中，每个射频收发链路模块30耦合至无线电收发两用机20的其中一对射频接收端和射频发送端，每个反馈模块40均耦合在无线电收发两用机20的反馈接收端和其中一个射频收发链路模块30之间，N≥M≥1，且N、M均为整数。
以无线电收发两用机20为ADRV9009芯片为例，该芯片具有两对射频接收端和射频发射端，最大可以支持同时连接两个射频收发链路模块30和两个反馈模块40。由此可见，采用具有2个射频接收端、2个射频发送端和1个反馈接收端的ADRV9009芯片可以实现支持两路发送两路接收(2T2R，也称为2×2)的多输入多输出(Multiple Input Multiple Output，简称为MIMO)天线系统。
无线电收发两用机20的数量可以为一个或者多个。图3是本申请优选实施例的硬件平台系统的结构示意图二，如图3所示，在本实施例中，无线电收发两用机20的数量为两个。仍以无线电收发两用机20为ADRV9009芯片为例，要实现对四路发送四路接收(4T4R，也称为4×4)的多MIMO天线系统的支持，采用具有两个ADRV9009芯片的硬件平台系统，并在每对收发通道上配置射频收发链路模块30、反馈模块40和天线。以此类推，采用本实施例提供的方式，还可以实现对更多路发送和接收的天线系统的支持，并且能够保证高度的器件集成程度。
参考图2和图3，在本实施例中，射频收发链路模块30包括：射频接收链路、射频发送链路、双工滤波器33，其中，射频接收链路、射频发送链路均通过双工滤波器与天线耦合。其中，射频接收链路包括低噪放大模块31，射频发送链路包括功率放大模块32。其中的双工滤波器33优选地由腔体双工器和腔体滤波模块组成。
在本实施例中，功率放大模块中的频段模块、以及双工滤波器、硬件平台系统连接的天线均可以根据不同运营商对频段、功率的需求灵活配置。本实施例的功率放大模块也都采用支持450MHz带宽，输出功率最大46dBm可调的功率放大模块，每个功率放大模块均可以支持6GHz以下的不同制式和不同频段的5G频段。
可选的，本实施例所提供的功率放大模块，可以集成在至少一个芯片中，例如，专用集成电路(Application-Specific Integrated Circuit，简称为ASIC)，也可以由至少一个分立器件构成；也可以是一个芯片系统，该芯片系统中包含至少一个芯片和至少一个分立器件。本实施例对功率放大模块的具体实现形式不做限定。
在其中一些实施例中，硬件平台系统还包括本地网口模块70，该本地网口模块70用于与网络管理系统连接，以实现远程对硬件平台系统的参数配置。硬件平台系统还包括存储模块80，该存储模块80用于保存配置信息。
在其中一些实施例中，硬件平台系统还包括电源模块90，该电源模块90主要用于为基带处理器10、无线电收发两用机20以及功率放大模块供电。需要说明的是，在采用多个无线电收发两用机20实现对多MIMO天线系统支持的硬件平台系统中，电源模块90的带载能力需要根据需要适当提高。
作为一种可选地实现方式，本实施例的电源模块90经过AC/DC(或者DC/DC)模块，将220V(或者-48V)的电源转换为12V和30V，并通过基带处理板内的DC/DC模块和低压差线性稳压器(Low Dropout Regulator，简称为LDO)芯片转换成板内各芯片或者模块所需要的工作电压，实现稳定供电。
在本实施例中还提供了一种射频拉远单元，该射频拉远单元包括MIMO天线系统和 上述的零中频的硬件平台系统。
综上所述，通过本申请实施例提供的零中频的硬件平台系统和射频拉远单元，采用本实施例的高集成度的收发芯片方案，将传统分立的ADC、DAC、混合器(mixer)等分立器件采用单芯片方案代替，大大缩减了布板面积和功耗，非常适合5G中阵列天线多输入多输出(massive Multiple Input Multiple Output，简称为massive MIMO)的应用场景。采用本实施例的零中频硬件方案，大大提升了射频带宽和DPD带宽，从而满足了5G大带宽的需求。采用本实施例的零中频方案，不需要特殊频率滤波器件，从而可灵活支持不同频段、不同制式的5G移动通信需求。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置或方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的相合或直接相合或通信连接可以是通过一些接口、装置或单元的间接相合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元末实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。上述的理器可以包括中央处理器(CPU)，或者特定集成电路(Application Specific Integrated Circuit，简称为ASIC)，或者可以被配置成实施本申请实施例的一个或多个集成电路。上述的存储介质可以用于数据或指令的大容量存储器。举例来说而非限制，存储器可包括硬盘驱动器(Hard Disk Drive，简称为HDD)、软盘驱动器、闪存、光盘、磁光盘、磁带或通用串行总线(Universal Serial Bus，简称为USB)驱动器或者两个或更多个以上这些的组合。在合适的情况下，存储器可包括可移除或不可移除(或固定)的介质。 在合适的情况下，存储器可在数据处理装置的内部或外部。在特定实施例中，存储器是非易失性固态存储器。在特定实施例中，存储器包括只读存储器(ROM)。在合适的情况下，该ROM可以是掩模编程的ROM、可编程ROM(PROM)、可擦除PROM(EPROM)、电可擦除PROM(EEPROM)、电可改写ROM(EAROM)或闪存或者两个或更多个以上这些的组合。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种零中频的硬件平台系统，其特征在于，所述零中频的硬件平台系统包括：基带处理器、无线电收发两用机、射频收发链路模块和反馈模块，所述基带处理器与所述无线电收发两用机耦合，所述无线电收发两用机的射频接收端和射频发送端分别与所述射频收发链路模块耦合，所述反馈模块耦合在所述射频收发链路模块和所述无线电收发两用机的反馈接收端之间。
  2. 根据权利要求1所述的零中频的硬件平台系统，其特征在于，所述基带处理器支持不低于450MHz的信号的数字预失真处理；所述无线电收发两用机的接收带宽不低于200MHz，发送带宽不低于450MHz，且所述无线电收发两用机的反馈带宽不低于450MHz。
  3. 根据权利要求1所述的零中频的硬件平台系统，其特征在于，所述零中频的硬件平台系统还包括：eCPRI接口，所述eCPRI接口与所述基带处理器耦合。
  4. 根据权利要求3所述的零中频的硬件平台系统，其特征在于，所述零中频的硬件平台系统还包括：时钟模块，所述时钟模块分别与所述基带处理器和所述无线电收发两用机耦合，其中，
    所述基带处理器，还用于从所述eCPRI接口恢复时钟信号；
    所述时钟模块，用于生成与从所述eCPRI接口恢复的时钟信号同相位的工作时钟信号，并将所述工作时钟信号提供给所述基带处理器和所述无线电收发两用机。
  5. 根据权利要求4所述的零中频的硬件平台系统，其特征在于，所述时钟模块包括：二级锁相环单元，所述二级锁相环单元包括压控振荡器，所述压控振荡器用于将所述工作时钟信号分频为多个时钟信号，并分别提供给所述基带处理器和所述无线电收发两用机。
  6. 根据权利要求1所述的零中频的硬件平台系统，其特征在于，所述无线电收发两用机包括N对射频接收端和射频发射端，以及反馈接收端，所述射频收发链路模块和所述反馈模块的数量均为M个；其中，每个所述射频收发链路模块耦合至所述无线电收发两用机的其中一对射频接收端和射频发送端，每个所述反馈模块均耦合在所述无线电收发两用机的反馈接收端和其中一个射频收发链路模块之间，N≥M≥1，且N、M均为整数。
  7. 根据权利要求1所述的零中频的硬件平台系统，其特征在于，所述无线电收发两用机的数量为一个或多个。
  8. 根据权利要求1所述的零中频的硬件平台系统，其特征在于，所述射频收发链路模块包括：射频接收链路、射频发送链路、双工滤波器，其中，所述射频接收链路、所述射频发送链路均通过所述双工滤波器与天线耦合；所述射频接收链路包括低噪放大模块，所述射频发送链路包括功率放大模块。
  9. 根据权利要求1至8中任一项所述的零中频的硬件平台系统，其特征在于，所述基带处理器包括：ZYNQ系列芯片；所述无线电收发两用机包括以下之一：ADRV9009系列芯片、AFE768x系列芯片。
  10. 一种射频拉远单元，其特征在于，所述射频拉远单元包括多输入多输出天线系统和权利要求1至9中任一项所述的零中频的硬件平台系统。
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