WO2015180349A1 - Substrat d'affichage flexible et son procédé de préparation, et dispositif d'affichage flexible - Google Patents

Substrat d'affichage flexible et son procédé de préparation, et dispositif d'affichage flexible Download PDF

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Publication number
WO2015180349A1
WO2015180349A1 PCT/CN2014/087866 CN2014087866W WO2015180349A1 WO 2015180349 A1 WO2015180349 A1 WO 2015180349A1 CN 2014087866 W CN2014087866 W CN 2014087866W WO 2015180349 A1 WO2015180349 A1 WO 2015180349A1
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gate
layer
flexible display
substrate
gate line
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PCT/CN2014/087866
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English (en)
Chinese (zh)
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王东方
陈海晶
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京东方科技集团股份有限公司
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Publication of WO2015180349A1 publication Critical patent/WO2015180349A1/fr

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

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  • Embodiments of the present invention relate to a flexible display substrate, a method of fabricating the same, and a flexible display device.
  • flexible displays mainly include: electronic paper (flexible electrophoretic display), flexible organic light-emitting diode (OLED), and flexible LCD.
  • the preparation method generally comprises: forming a flexible substrate on the carrier substrate, forming a thin film transistor (TFT) on the flexible substrate, and a corresponding electrode layer, and then peeling the carrier substrate from the flexible substrate.
  • TFT thin film transistor
  • At least one embodiment of the present invention provides a flexible display substrate, a method of fabricating the same, and a flexible display device, which can reduce the influence of the flexible substrate on the performance of the TFT during deformation and peeling.
  • At least one embodiment of the present invention provides a flexible display substrate including: a flexible substrate, a gate metal layer disposed on the flexible substrate, a gate insulating layer, a semiconductor active layer, a source/drain metal layer, a conductive connection structure, and At least one electrode layer; the gate metal layer includes a gate, a gate line, and the gate and the gate line are disconnected; the conductive connection structure is electrically connected to the gate and the gate line, respectively .
  • At least one embodiment of the present invention provides a flexible display device including the above flexible display substrate.
  • At least one embodiment of the present invention provides a method of fabricating a flexible display substrate, comprising: forming a flexible substrate on a carrier substrate; forming a gate metal layer, a gate insulating layer, and a half on the flexible substrate a conductor active layer, a source/drain metal layer, and at least one electrode layer; peeling off the carrier substrate and the flexible substrate in contact with the carrier substrate to form the flexible display substrate; the gate metal layer includes a gate, a gate line, and the gate and the gate line are disconnected; the gate and the gate line are electrically connected by a conductive connection structure.
  • FIG. 1 is a top plan view of a flexible display substrate according to an embodiment of the invention.
  • FIG. 2 is a cross-sectional view of the flexible display substrate of FIG. 1 taken along the line AA;
  • FIG. 3 is a cross-sectional view of the flexible display substrate shown in FIG. 1 taken along the line AA;
  • FIG. 4 is a schematic top plan view of a flexible display substrate according to another embodiment of the present invention.
  • Figure 5 is a cross-sectional view of the flexible display substrate of Figure 4 taken along the line AA;
  • FIG. 6 is a schematic top plan view of a flexible display substrate according to another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a flexible display substrate including an etch barrier layer according to still another embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a flexible display substrate including a first buffer layer and a second buffer layer according to still another embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a process of forming a flexible substrate on a carrier substrate according to an embodiment of the invention.
  • FIG. 10 and FIG. 11 are schematic diagrams showing processes of forming a gate metal layer, an insulating layer, a semiconductor active layer, a source/drain metal layer, and at least one electrode layer of FIG. 9;
  • FIG. 12 is a schematic view showing the process of forming an etch barrier layer of FIG. 11;
  • FIG. 13 is a schematic view showing the process of forming the first buffer layer and the second buffer layer in FIG.
  • the inventors have found that in the process of preparing a flexible display, since the thermal expansion coefficient of the flexible substrate is high, the deformation is large, which causes the generated stress to act on the thin film transistor, thereby affecting the performance of the thin film transistor. Moreover, when the flexible substrate is peeled off from the carrier substrate, the degree of shrinkage of the flexible substrate is high, and the adverse effect on the performance of the TFT is also easily aggravated.
  • the flexible display substrate 01 includes a flexible substrate 10, a gate metal layer disposed on the flexible substrate 10, a gate insulating layer 30 (not shown in FIGS. 1 and 4), and a semiconductor.
  • the gate metal layer includes a gate 201 and a gate line 202, and the gate 201 and the gate line 202 are disconnected without being directly connected; in this case, the flexible display substrate 01 further includes a conductive connection Structure 504, the conductive connection structure 504 is electrically connected to the gate 201 and the gate line 202, respectively.
  • the source/drain metal layer may include a source 501, a drain 502, and a data line 503.
  • the gate electrode 201, the gate insulating layer 30, the semiconductor active layer 40, the source electrode 501, and the drain electrode 502 constitute a thin film transistor.
  • the gate insulating layer 30 in the thin film transistor refers only to a portion of the gate insulating layer 30 located in the thin film transistor region.
  • the material of the flexible substrate 10 may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate. At least one of them.
  • the at least one electrode layer when the flexible display substrate is an array substrate of a liquid crystal display (LCD), the at least one electrode layer includes a pixel electrode 601.
  • the pixel electrode 601 is electrically connected to the drain 502.
  • the at least one electrode layer may further include a common electrode 602 (as shown in FIG. 3).
  • the pixel electrode 601 and the common electrode 602 are spaced apart from each other, and are strip electrodes; for advanced super-dimensional field conversion type (Advanced-super Dimensional Switching, ADS) array substrate, as shown in FIG. 3, the pixel electrode 601 and the common electrode 602 are disposed in different layers, for example, the upper electrode is a strip electrode, and the lower electrode is a plate. Electrode.
  • the at least one electrode layer includes an anode 603 and a cathode 604 (not shown in FIG. 4). Mark out).
  • the flexible display substrate 01 further includes an organic material functional layer 605 (not labeled in FIG. 4) disposed between the anode 603 and the cathode 604.
  • the organic material functional layer 605 includes at least an electron transport layer, a light emitting layer, and a hole transport layer.
  • the organic material functional layer may further include a cathode 604 disposed thereon. An electron injecting layer between the electron transporting layers, and a hole injecting layer between the anode 603 and the hole transporting layer.
  • an encapsulation layer for encapsulating the organic material must also be formed on the flexible display substrate 01 to form a flexible display device;
  • the encapsulation layer may be a flexible package substrate, It may be a layer of sealing film, which is not limited herein.
  • each sub-pixel unit includes two thin film transistors, one thin film transistor is called a switching thin film transistor, and the other thin film transistor is called a driving thin film transistor; the gate 201 of the switching thin film transistor and the gate line 202 pass through the
  • the conductive connection structure 504 is electrically connected, the source 501 of the switching thin film transistor is electrically connected to the data line 503, and the drain 502 of the switching thin film transistor is electrically connected to the gate 201 of the driving thin film transistor, the source of the driving thin film transistor
  • the pole 501 is electrically connected to the data line 503, and the drain 502 of the driving thin film transistor is electrically connected to the anode 603.
  • the sub-pixel unit of the OLED is not limited to the above-described configuration including two thin film transistors, and may be other types, which are not limited herein.
  • the conductive connection structure 504 for electrically connecting the gate 201 and the gate line 202 is bound to be the gate 201 and The gate lines 202 are different layers. Otherwise, when the gate electrodes 201 and the gate lines 202 are formed, the two may be directly connected or integrally formed.
  • the conductive connection structure 504 may be located under the gate metal layer or above the gate metal layer. Of course, considering the number of patterning processes, it may be formed together with other electrodes, which is not limited herein. Set according to the actual situation.
  • the conductive connection structure 504 is electrically connected to the gate electrode 201 and the gate line 202, the conductive connection structure 504 can not be electrically connected thereto regardless of whether the conductive connection structure 504 is in the same layer as the other electrodes.
  • the embodiment of the present invention does not limit the specific shape of the conductive connection structure 504 to connect the gate 201 and the gate line 202 without being electrically connected to other electrodes.
  • connection manner is, for example, a via connection.
  • the thin film transistor may be an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, a metal oxide thin film transistor, or an organic thin film transistor, which is not limited herein.
  • the thin film transistor may be of a bottom gate type or a top gate type.
  • the materials of the anode 603 and the cathode 604 are not limited.
  • the OLED flexible display substrate can be classified into a single-sided light-emitting type flexible display substrate and a double-sided light-emitting type flexible display substrate; when the anode 603 and the cathode 604 are When the material of one of the electrodes is an opaque material, the flexible display substrate is a single-sided light-emitting type; when the materials of the anode 603 and the cathode 604 are both transparent materials, the flexible display substrate is a double-sided light-emitting type.
  • the single-sided light-emitting type flexible display substrate can be further classified into an upper light-emitting type and a lower light-emitting type depending on the materials of the anode 603 and the cathode 604. Specifically, when the anode 603 is disposed adjacent to the flexible substrate 10, the cathode 604 is disposed away from the flexible substrate 10, and the material of the anode 603 is a transparent conductive material, and the material of the cathode 604 is an opaque conductive material.
  • the OLED Since light is emitted from the anode 603 and then through the side of the flexible substrate 10, the OLED may be referred to as a lower emission type; when the material of the anode 603 is an opaque conductive material, the material of the cathode 604 is transparent or translucent conductive. In the case of the material, since the light is emitted from the cathode 604 and then through the encapsulation layer disposed opposite to the flexible substrate 10, the OLED may be referred to as an upper emission type.
  • At least one embodiment of the present invention provides a flexible display substrate 01 comprising: a flexible substrate 10, a gate metal layer disposed on the flexible substrate 10, a gate insulating layer 30, a semiconductor active layer 40, and a source/drain metal layer And at least one electrode layer.
  • the gate metal layer includes a gate 201 and a gate line 202, and the gate 201 and the gate line 202 are disconnected; the flexible display substrate 01 further includes a conductive connection structure 504, and the conductive connection structure 504 respectively The gate 201 and the gate line 202 are electrically connected.
  • the semiconductor active layer 40, the source 501 and the drain 502 of the thin film transistor are both patterned, the area thereof is relatively small, and therefore, when the flexible substrate 10 is deformed and peeled off from the carrier substrate, the influence on the pattern layer is compared. small.
  • the gate line 202 is deformed relative to the known technique, causing the gate 201 directly connected to the gate line 202 to be deformed, thereby causing a gate insulating layer to the thin film transistor.
  • the adverse effect of 30, at least one embodiment of the present invention by disposing the gate electrode 201 and the gate line 202 of the gate metal layer, can avoid the gate insulating layer of the gate electrode 201 or even the thin film transistor when the gate line 202 is deformed. The influence of 30, thereby reducing the impact on the performance of the thin film transistor, and improving the reliability of the thin film transistor.
  • the conductive connection structure 504 is disposed in the same layer as the source 501 and the drain 502. For example, the conductive connection structure 504 passes through the via hole and the gate 201 and the gate respectively. Line 202 is connected.
  • the gate 201 and the gate line 202 can be electrically connected through the conductive connection structure 504 to electrically connect the gate 201 and the gate line 202, and the number of patterning processes can be avoided. Increase.
  • the source 501, the drain 502, and the data line 503 located in the same layer are not in contact with the conductive connection structure 504.
  • the gate insulating layer 30 includes the cover a first insulation pattern 301 of the gate line 202 and a second insulation pattern 302 covering the gate 201, the first insulation pattern 301 being disconnected from the second insulation pattern 302.
  • the first insulation pattern 301 is disposed only at an intersection of the gate line 202 and the data line 503, for example; the second insulation pattern 302 is only disposed to cover the gate 201. Thin film transistor region.
  • the deformation of the flexible substrate 10 can be reduced and
  • the influence of the flexible substrate on the gate insulating layer of the thin film transistor when it is peeled off from the carrier substrate can further reduce the influence on the performance of the thin film transistor and improve the reliability of the thin film transistor.
  • the semiconductor active layer 40 is a metal oxide semiconductor active layer.
  • the material of the metal oxide semiconductor active layer may be: zinc oxynitride (ZnON), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or indium zinc oxide (InZnO), or zinc. Tin oxide (ZnSnO) and the like.
  • an etch stop layer 70 can be formed over the metal oxide semiconductor active layer.
  • a first buffer layer 801 is provided on the upper surface of the flexible substrate 10 for reinforcing the first buffer layer 801 and the flexible substrate 10, and the first buffer layer 801 and The adhesion between the pattern layers above the first buffer layer can solve the problem of roughness, and can also avoid cracking or falling off of the film layer disposed on the flexible substrate 10.
  • a second buffer layer 802 may be disposed on the lower surface of the flexible substrate 10, that is, the second buffer layer 802 is disposed between the flexible substrate 10 and the carrier substrate, so that the flexibility may be The deformation of the substrate 10 and its peeling from the carrier substrate further alleviate the effect on the thin film transistor pattern layer.
  • At least one embodiment of the present invention also provides a flexible display device comprising any of the flexible display substrates 01 described above.
  • the flexible display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a display, a notebook computer, a digital photo frame, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a display, a notebook computer, a digital photo frame, and the like.
  • At least one embodiment of the present invention also provides a method of fabricating a flexible display substrate, the method comprising the following steps.
  • Step S10 as shown in FIG. 9, a flexible substrate 10 is formed on the carrier substrate 90.
  • the carrier substrate 90 may be a glass substrate, or may be a substrate made of a metal having good thermal conductivity such as an iron plate or a steel plate.
  • the material of the flexible substrate 10 may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate. At least one of them.
  • Step S11 as shown in FIG. 1, FIG. 4, FIG. 6, FIG. 10 and FIG. 11, a gate metal layer, a gate insulating layer 30 (not shown in FIGS. 1 and 4), and a semiconductor are formed on the flexible substrate 10.
  • the gate metal layer includes a gate 201, a gate line 202, and the gate 201 and the gate line 202 are disconnected; the gate 201 and the gate line 202 are electrically connected by a conductive connection structure 504.
  • the source/drain metal layer includes a source 501, a drain 502, and a data line 503 (none of which are not identified in FIGS. 10 and 11).
  • the gate electrode 201, the gate insulating layer 30, the semiconductor active layer 40, the source electrode 501, and the drain electrode 502 constitute a thin film transistor.
  • the gate insulating layer 30 in the thin film transistor refers only to a portion of the gate insulating layer 30 located in the thin film transistor region (for example, as shown in FIG. 6).
  • the at least one electrode layer when the flexible display substrate is an array substrate of an LCD, the at least one electrode layer includes a pixel electrode 601, and the pixel electrode 601 is electrically connected to the drain 502.
  • the at least one electrode layer may further include a common electrode 602 (not identified in FIG. 10).
  • the at least one electrode layer includes an anode 603 and a cathode 604.
  • the flexible display substrate 01 may further include an organic material functional layer 605 formed between the anode 603 and the cathode 604.
  • the organic material functional layer 605 includes at least an electron transport layer, a light emitting layer, and a hole transport layer.
  • the organic material functional layer may further include forming At the cathode 604 An electron injection layer between the electron transport layer and a hole injection layer between the anode 603 and the hole transport layer.
  • an encapsulation layer for encapsulating the organic material must also be formed on the flexible display substrate 01; the encapsulation layer may be a flexible package substrate or a sealing film. It is not limited here.
  • One sub-pixel unit of the OLED may include two thin film transistors: one thin film transistor is called a switching thin film transistor, and the other thin film transistor is called a driving thin film transistor; the gate 201 of the switching thin film transistor is connected to the gate line 202 through the conductive connection
  • the structure 504 is electrically connected, the source 501 of the switching thin film transistor is electrically connected to the data line 503, the drain 502 of the switching thin film transistor is electrically connected to the gate 201 of the driving thin film transistor, and the source 501 of the driving thin film transistor
  • the data line 503 is electrically connected, and the drain 502 of the driving thin film transistor is electrically connected to the anode 603.
  • the structure of the sub-pixel unit is not limited to include the above two thin film transistors, and may be other types, which are not limited herein.
  • the conductive connection structure 504 for electrically connecting the gate electrode 201 and the gate line 202 is bound to be opposite to the gate electrode.
  • 201 and the gate line 202 are different layers, otherwise, when the gate electrode 201 and the gate line 202 are formed, the two may be connected.
  • the conductive connection structure 504 may be formed under the gate metal layer or may be formed on the gate metal layer. Of course, the number of times of the patterning process may be formed together with other electrodes, which is not limited herein.
  • the conductive connection structure 504 is electrically connected to the gate electrode 201 and the gate line 202, the conductive connection structure 504 can not be electrically connected thereto regardless of whether the conductive connection structure 504 is in the same layer as the other electrodes.
  • the embodiment of the present invention does not limit the specific shape of the conductive connection structure 504 to connect the gate 201 and the gate line 202 without being electrically connected to other electrodes.
  • connection manner is, for example, a via connection.
  • FIG. 11 only schematically illustrates the structural relationship of one of the thin film transistors, and the anode 603, the cathode 604, and the organic material functional layer 605, only for the case where the flexible display substrate is an OLED. Be explained.
  • the embodiment of the present invention does not limit the material of the semiconductor active layer 40, which may Or amorphous silicon, or low temperature polycrystalline silicon, or metal oxide, organic or the like, that is, the thin film transistor may be an amorphous silicon thin film transistor, or a low temperature polysilicon thin film transistor, or a metal oxide thin film transistor, or an organic thin film Transistors, etc.
  • the embodiment of the present invention does not limit the formation order of the gate 201 and the gate insulating layer 30, and may form the gate 201 first, and then form the gate insulating layer 30, that is, the thin film transistor is a bottom gate type at this time;
  • the gate insulating layer 30 may be formed first, and then the gate electrode 201 may be formed, that is, the thin film transistor is a top gate type.
  • Step S12 peeling off the carrier substrate 90 and the flexible substrate 10 in contact with the carrier substrate to form the flexible display substrate 01.
  • the carrier substrate 90 and the flexible substrate 10 in direct contact with the carrier substrate may be peeled off by laser irradiation.
  • the carrier substrate 90 is a substrate made of a metal having good thermal conductivity
  • the carrier substrate 90 may be heated by heating, thereby the carrier substrate 90 and the flexible substrate in direct contact with the carrier substrate. 10 peeling.
  • it can also be other methods, and will not be described here.
  • At least one embodiment of the present invention provides a method of fabricating a flexible display substrate, comprising: forming a flexible substrate 10 on a carrier substrate 90; forming a gate metal layer, a gate insulating layer 30, and a semiconductor active layer on the flexible substrate 10. 40.
  • a source/drain metal layer and at least one electrode layer; and the carrier substrate 90 and the flexible substrate in contact with the carrier substrate are peeled off to form the flexible display substrate 01.
  • the gate metal layer includes a gate 201, a gate line 202, and the gate 201 and the gate line 202 are disconnected; the gate 201 and the gate line 202 are electrically connected by a conductive connection structure 504.
  • the semiconductor active layer 40, the source 501 and the drain 502 of the thin film transistor are both patterned, the area thereof is relatively small, and therefore, when the flexible substrate 10 is deformed and peeled off from the carrier substrate, the above-mentioned pattern layer is adversely affected. smaller.
  • the gate line 202 is deformed relative to the known technique, causing the gate 201 directly connected to the gate line 202 to be deformed, thereby causing gate isolation of the thin film transistor.
  • the effect of the layer 30, at least one embodiment of the present invention, by disposing the gate electrode 201 and the gate line 202 of the gate metal layer, can avoid the gate insulating layer of the gate electrode 201 or even the thin film transistor when the gate line 202 is deformed.
  • the adverse effects of 30, thereby reducing the adverse effects on the performance of the thin film transistor, and improving the reliability of the thin film transistor.
  • the source and drain are formed.
  • the method further includes forming vias on the gate 201 and the gate line 202 that expose the gate 201 and the gate line 202.
  • the conductive connection structure 504 is formed by the same patterning process as the source 501 and the drain 502, and the conductive connection structure 504 passes through the via and the gate 201. Connected to the gate line 202. The conductive connection structure 504 is not in contact with the source 501, the drain 502, and the data line 503.
  • the conductive connection structure 504 is formed by the same patterning process as the source 501 and the drain 502 data line 503. In this way, the gate 201 and the gate line 202 can be electrically connected through the conductive connection structure 504 to electrically connect the gate 201 and the gate line 202, and the number of patterning processes can be avoided. Increase.
  • forming the gate insulating layer 30 includes: forming a first insulating pattern 301 covering the gate line 202 and a second insulating pattern 302 covering the gate 201 The first insulation pattern 301 is disconnected from the second insulation pattern 302.
  • the first insulation pattern 301 is formed only at an intersection area of the gate line 202 and the data line 503, for example; the second insulation pattern 302 is formed only to cover the gate 201. Thin film transistor region.
  • the deformation of the flexible substrate 10 can be reduced, compared to the gate insulating layer on the substrate on which the gate electrode 201 and the gate line 202 are formed in the prior art. And the influence on the gate insulating layer of the thin film transistor when it is peeled off from the carrier substrate, so that the influence on the performance of the thin film transistor can be further reduced, and the reliability of the thin film transistor can be improved.
  • the semiconductor active layer 40 is a metal oxide semiconductor active layer.
  • the material of the metal oxide semiconductor active layer may be: zinc oxynitride (ZnON), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or indium zinc oxide (InZnO), Or zinc tin oxide (ZnSnO) and the like.
  • the method may further include: oxidizing the metal An etch stop layer 70 is formed over the active layer 40 of the semiconductor.
  • the method may further include: forming a first buffer layer 801 on a surface of the flexible substrate 10 away from the side of the carrier substrate 90; A second buffer layer 802 is formed on a surface of the substrate 10 adjacent to the side of the carrier substrate 90.
  • the first buffer layer 801 is for enhancing the adhesion between the first buffer layer 801 and the flexible substrate 10, and the first buffer layer 801 and the pattern layer located above the first buffer layer, which can solve The problem of roughness can also avoid cracking or peeling of the film layer formed on the flexible substrate 10.
  • the second buffer layer 802 is used to further alleviate the influence on the thin film transistor pattern layer when the flexible substrate 10 is deformed and peeled off from the carrier substrate 90.

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Abstract

La présente invention concerne un substrat d'affichage flexible (01) et son procédé de préparation, et un dispositif d'affichage flexible. Le substrat d'affichage flexible (01) comprend une base flexible (10) et une couche métallique de grille, une couche isolante de grille (30), une couche active à semi-conducteur (40), une couche métallique source-drain, une structure de connexion conductrice (504) et au moins une couche d'électrode qui sont disposées sur la base flexible (10), la couche métallique de grille comprenant une électrode de grille (201) et une ligne de grille (202), et l'électrode de grille (201) étant déconnectée de la ligne de grille (202) ; et la structure de connexion conductrice (504) étant électriquement connectée à l'électrode de grille (201) et à la ligne de grille (202) respectivement. Le substrat d'affichage flexible (01) et le procédé de préparation associé peuvent réduire l'influence d'une base flexible sur les performances de TFT dans les procédés de déformation et de décapage.
PCT/CN2014/087866 2014-05-26 2014-09-30 Substrat d'affichage flexible et son procédé de préparation, et dispositif d'affichage flexible WO2015180349A1 (fr)

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Families Citing this family (5)

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CN104022124B (zh) * 2014-05-26 2017-06-27 京东方科技集团股份有限公司 一种柔性显示基板及其制备方法、柔性显示装置
CN105845701A (zh) * 2015-01-16 2016-08-10 昆山工研院新型平板显示技术中心有限公司 一种柔性显示装置及其制作方法
CN107706156A (zh) * 2017-11-13 2018-02-16 京东方科技集团股份有限公司 一种柔性显示基板及其制备方法、柔性显示装置
CN109597258A (zh) * 2018-11-19 2019-04-09 南京华日触控显示科技有限公司 一种邦定去邦定工艺制作的膜结构胆甾相液晶显示屏
CN109830504A (zh) * 2019-01-08 2019-05-31 云谷(固安)科技有限公司 可拉伸显示结构及其制造方法以及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060255338A1 (en) * 2005-05-16 2006-11-16 Jeong Jae K Thin film transistor and the manufacturing method thereof
KR20090058995A (ko) * 2007-12-05 2009-06-10 엘지디스플레이 주식회사 전기영동표시소자에 적용한 유기박막트랜지스터 및 그제조방법
CN102842674A (zh) * 2011-06-20 2012-12-26 索尼公司 半导体元件、其制造方法、显示装置和电子装置
CN102956672A (zh) * 2011-08-18 2013-03-06 乐金显示有限公司 显示装置及其制造方法
CN103700322A (zh) * 2013-12-27 2014-04-02 京东方科技集团股份有限公司 阵列基板及显示装置
CN104022124A (zh) * 2014-05-26 2014-09-03 京东方科技集团股份有限公司 一种柔性显示基板及其制备方法、柔性显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100709719B1 (ko) * 2004-09-13 2007-04-19 삼성전자주식회사 플라스틱 기판을 이용한 플렉서블 표시 장치 및 그 제조방법
KR101198218B1 (ko) * 2006-06-19 2012-11-07 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조 방법
KR20080019398A (ko) * 2006-08-28 2008-03-04 삼성전자주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN102487043A (zh) * 2010-12-03 2012-06-06 京东方科技集团股份有限公司 阵列基板及其制造方法和电子纸显示器
CN102819158B (zh) * 2012-08-10 2015-08-12 北京京东方光电科技有限公司 一种显示面板
CN203850299U (zh) * 2014-05-26 2014-09-24 京东方科技集团股份有限公司 一种柔性显示基板及柔性显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060255338A1 (en) * 2005-05-16 2006-11-16 Jeong Jae K Thin film transistor and the manufacturing method thereof
KR20090058995A (ko) * 2007-12-05 2009-06-10 엘지디스플레이 주식회사 전기영동표시소자에 적용한 유기박막트랜지스터 및 그제조방법
CN102842674A (zh) * 2011-06-20 2012-12-26 索尼公司 半导体元件、其制造方法、显示装置和电子装置
CN102956672A (zh) * 2011-08-18 2013-03-06 乐金显示有限公司 显示装置及其制造方法
CN103700322A (zh) * 2013-12-27 2014-04-02 京东方科技集团股份有限公司 阵列基板及显示装置
CN104022124A (zh) * 2014-05-26 2014-09-03 京东方科技集团股份有限公司 一种柔性显示基板及其制备方法、柔性显示装置

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