WO2015174020A1 - Memory system, memory peripheral circuit, and memory control method - Google Patents

Memory system, memory peripheral circuit, and memory control method Download PDF

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WO2015174020A1
WO2015174020A1 PCT/JP2015/002164 JP2015002164W WO2015174020A1 WO 2015174020 A1 WO2015174020 A1 WO 2015174020A1 JP 2015002164 W JP2015002164 W JP 2015002164W WO 2015174020 A1 WO2015174020 A1 WO 2015174020A1
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memory
circuit
area
data
writing
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French (fr)
Japanese (ja)
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伸吾 麻生
佐鳥　謙一
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ソニー株式会社
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers

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  • the present disclosure relates to a memory system, a memory peripheral circuit, and a memory control method.
  • SoC System-on-a-chip
  • volatile memory mainly SRAM (Static Random Access Memory)
  • DRAM Dynamic Random Access Memory
  • EEPROM Electrical Erasable Programmable ROM
  • embedded NVM NonVolatile Memory
  • volatile memory can be written and read at high speed, and has a rewrite life of 10 12 times.
  • the non-volatile memory can retain information even after the power is cut off, but has a shorter rewrite life than a volatile memory and a slower writing / reading speed. Since SoC requires both applications, it has both volatile and non-volatile memory in the system. Conventionally, it is necessary to provide a memory peripheral circuit for each of the volatile memory and the nonvolatile memory, and there is a problem in that the circuit area is increased.
  • a memory spin-injection memory or STT (Spin Transfer Transfer Torque) -RAM
  • STT Spin Transfer Transfer Torque
  • the STT-RAM can be miniaturized, a current value required for writing is reduced, and has characteristics suitable for high density.
  • the data retention period As a characteristic of the STT-RAM, when data is written at the same speed as the SRAM, the data retention period is remarkably shortened and the non-volatile characteristic is lost. On the other hand, if a sufficient writing time is set, the data retention period can be set to 10 years, for example.
  • the present disclosure includes a memory cell and a memory peripheral circuit, In this memory system, the memory cell is divided into a first area where high-speed writing is performed and a second area where the data retention period is long.
  • the present disclosure has an address circuit, a data write circuit, a sense amplifier, and a programmable timing generation circuit, This is a memory peripheral circuit configured to set the length of a period in which writing is activated by a programmable timing generation circuit.
  • the present disclosure divides a memory cell into a first region where high-speed writing is performed and a second region where a data retention period is long, This is a memory control method for setting a division position by configuration data.
  • high-speed access memory and non-volatile memory are realized by using a plurality of memories such as SRAM and ROM or SRAM and embedded NVM. be able to. Therefore, the area of the memory can be reduced.
  • memories such as SRAM and ROM or SRAM and embedded NVM.
  • FIG. 1 is a block diagram of an embodiment of the present disclosure.
  • 6 is a timing chart used for describing a writing process for an area used as a volatile memory according to an embodiment of the present disclosure.
  • 6 is a timing chart used for explaining a writing process for an area used as a nonvolatile memory in an embodiment of the present disclosure.
  • 6 is a timing chart used for describing a reading process according to an embodiment of the present disclosure. It is a basic diagram which shows an example of a configuration table.
  • FIG. 6 is a block diagram used to explain the advantages of the present disclosure.
  • the memory cell array 1 is, for example, an STT-RAM.
  • a memory peripheral circuit is integrated on one semiconductor chip for the memory cell array 1.
  • Memory cells are formed at the intersections of word lines and bit lines, and a memory cell array 1 is constituted by a large number of memory cells arranged in a matrix.
  • the storage element of the STT-RAM records information by reversing the direction of magnetization of the storage layer of the storage element by spin injection, as described in Patent Document 1 or Patent Document 2 described above. is there.
  • the memory layer is made of a magnetic material such as a ferromagnetic layer, and holds information by the magnetization state (magnetization direction) of the magnetic material.
  • Write data is supplied to the bit line decoder and write circuit 3 through the data input / output circuit 2.
  • the data input / output circuit 2 has a data buffer function.
  • the address is supplied to the address decoder 5 through the address input circuit 4.
  • a word line address and a bit line address are output from the address decoder 5.
  • the word line address is supplied to the word line decoder and driver 6, and the bit line address is supplied to the bit line decoder and write circuit 3.
  • a word line drive signal for the memory cell array 1 is output from the word line decoder / driver 6, and a bit line drive signal for the memory cell array 1 is output from the bit line decoder / write circuit 3. Reading / writing of the memory cells in the row selected by the word line is selectively performed using the bit line.
  • a read address is input to the address input circuit 4, a word line at the time of reading is selected from the address decoder 5, and a change in the voltage of the bit line is determined by the bit line decoder and the sense amplifier 7. Is determined by Read data is taken out through the data input / output circuit 2.
  • the memory cell array 1 is divided into a first region 1A in which high-speed writing is performed and a second region 1B having a long data holding period.
  • the first region 1A has a data retention period shorter than that of the second region 1B.
  • the first area 1A is used as a volatile memory
  • the second area 1B is used as a nonvolatile memory.
  • the division position is represented by a word line address.
  • ⁇ Data representing the set division position is called configuration (or configuration data).
  • the configuration is stored, for example, at a predetermined address of the memory cell array 1, and is read from the memory cell array 1 when the power is turned on.
  • the configuration is written in advance at a predetermined address of the memory cell array 1 when the memory system is manufactured. Alternatively, it may be data set and written by the user after manufacturing.
  • configuration data from the configuration circuit 8 is supplied to the address decoder 5, and an address corresponding to the configuration output from the address decoder 5 is supplied to the programmable timing generation circuit 9.
  • the programmable timing generation circuit 9 generates a timing reference. For example, the time width for activating writing is defined by the configuration.
  • the period for activating the writing is short, and the data is stored in the region 1B having a long data holding period used as a nonvolatile memory. Is written, the period for activating the writing is long. Note that the period in which reading is activated is the same in the region 1A and the region B.
  • FIG. 2 is a timing chart of the write operation for the area 1A. From the top, clock CLK, address ADRS, data DATA, write enable, read enable, write pulse, and read pulse are shown. For the write operation, the write enable is active (high level) and the read enable is inactive (low level). Further, no read pulse is generated.
  • FIG. 3 is a timing chart of the write operation for the region 1B. From the top, clock CLK, address ADRS, data DATA, write enable, read enable, write pulse, and read pulse are shown. For the write operation, the write enable is active (high level) and the read enable is inactive (low level). Further, no read pulse is generated.
  • the write pulse In writing to the region 1A, the write pulse needs to have a width of a certain period or more. As an example, the write pulse has a width of 5 cycles of the clock CLK. Therefore, the address (A1, A2,%) And the data (D1, D2,%) Are held for a period of five clock cycles.
  • the reading process is performed at the timing shown in the timing chart shown in FIG.
  • the clock CLK, address ADRS, data DATA, write enable, read enable, write pulse, and read pulse are shown in order from the top of FIG.
  • the write enable is inactive (low level) and the read enable is active (high level). Further, no write pulse is generated.
  • the reading process may be performed in a short period in both the regions 1A and 1B. For example, data can be read out in one cycle of the clock.
  • the configuration is stored in the memory cell array 1 in a table format.
  • An example of a configuration in the case where the memory cell array 1 is divided into three regions is shown in FIG. 5A.
  • the configuration is defined by a last address and parameters.
  • the minimum last address, for example, 100 represents a configuration from address 0 to address 100.
  • the next last address is 200.
  • This last address represents a configuration from the next address (for example, address 101) of the previous configuration to the last address 200.
  • the next address is 300.
  • This last address represents the configuration from the next address (for example, address 201) to the last address 300 of the previous configuration.
  • Parameters are specified as shown in FIG. 5B.
  • Parameter 1 means a write pulse width of 10 nsec
  • parameter 2 means a write pulse width of 100 nsec
  • parameter 3 means a write pulse width of 10 ⁇ sec.
  • the nonvolatile memory can have a long data holding period.
  • a volatile memory for example, SRAM
  • a nonvolatile memory for example, mask ROM or flash memory
  • a memory peripheral circuit including a data input / output circuit 22, a bit line decoder and write circuit 23, an address input circuit 24, a word line decoder and driver 26, and a bit line decoder and sense amplifier 27 is provided. Is provided.
  • the address input circuit 24 includes an address decoder.
  • a similar memory peripheral circuit is provided in association with the memory cell 31 of the mask ROM or flash memory. That is, a data input / output circuit 32, a bit line decoder and write circuit 33, an address input circuit 34, a word line decoder and driver 36, and a bit line decoder and sense amplifier 37 are provided. These memory cells 31 and memory peripheral circuits are integrated on one semiconductor chip.
  • the memory cell array 1 is divided into a region 1A (SRAM) and a region 1B (mask ROM or flash memory), and thus the configuration is used.
  • SRAM semiconductor RAM
  • region 1B mask ROM or flash memory
  • the circuit 8 is required, other peripheral circuits can be shared. Therefore, the area of the memory can be reduced as compared with the conventional configuration. Thereby, the cost reduction of SoC is realizable.
  • the balance between the volatile memory and the nonvolatile memory can be individually set for each product, it is possible to deal with a plurality of applications with a single SoC.
  • this indication can also take the following structures.
  • a memory cell and a memory peripheral circuit A memory system that divides the memory cell into a first area in which high-speed writing is performed and a second area having a long data retention period.
  • the memory system according to (1) wherein the first area has a data retention period shorter than that of the second area.
  • the memory peripheral circuit includes an address decoder, a data write circuit, a sense amplifier, and a programmable timing generation circuit, The memory system according to (1) or (2), wherein a length of a period in which writing is activated is set by the programmable timing generation circuit.
  • a length of a period for activating the writing is defined by configuration data.
  • a memory peripheral circuit configured to set a length of a period in which writing is activated by the programmable timing generation circuit.
  • the memory cell is divided into a first area where high-speed writing is performed and a second area where the data retention period is long, A memory control method for setting a division position by configuration data.

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  • Computer Hardware Design (AREA)
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Abstract

Provided is a memory system having memory cells and memory peripheral circuits, with the memory cells being divided into a first region in which high-speed writing is performed and a second region having a long data retention period. The memory peripheral circuits include an address circuit, a data writing circuit, a sense amp, and a programmable timing generation circuit, with the length of the writing activation period being set by the programmable timing generation circuit. Also provided is a memory control method whereby memory cells are divided into a first region in which high-speed writing is performed and a second region having a long data retention period, with the division period being set by means of configuration data.

Description

メモリシステム、メモリ周辺回路およびメモリ制御方法Memory system, memory peripheral circuit, and memory control method
　本開示は、メモリシステム、メモリ周辺回路およびメモリ制御方法に関する。 The present disclosure relates to a memory system, a memory peripheral circuit, and a memory control method.
　１つの半導体チップ上に回路全体を集積化したＳｏＣ(System-on-a-chip)においては、例えば揮発性メモリ（主にＳＲＡＭ(Static Random Access Memory) ／ＤＲＡＭ(Dynamic Random Access Memory)）と不揮発性メモリ（ＥＥＰＲＯＭ(Electrical Erasable Programmable ＲＯＭ）／エンベデッドＮＶＭ(NonVolatile Memory)）とを有する。これらのメモリを使用してＳｏＣのプログラムがロードされ、実行される。 In SoC (System-on-a-chip) in which the entire circuit is integrated on one semiconductor chip, for example, volatile memory (mainly SRAM (Static Random Access Memory)) / DRAM (Dynamic Random Access Memory) and non-volatile Memory (EEPROM (Electrical Erasable Programmable ROM) / embedded NVM (NonVolatile Memory)). SoC programs are loaded and executed using these memories.
　通常、揮発性メモリは、高速に書き込み、読み出しを行うことができ、書き換え寿命も１０の１２乗回ほど持つ。しかしながら、高容量化が難しいという欠点を持つ。一方、不揮発性メモリは、電源が遮断された後でも情報を保持することができるが、書き換え寿命が揮発性メモリより少なく、書き込み、読み出し速度も遅い。ＳｏＣは、両方の用途を必要とするので、揮発性メモリと不揮発性メモリとをシステム内に有している。従来では、揮発性メモリと不揮発性メモリとのそれぞれに対してメモリ周辺回路を設ける必要があり、回路面積の増大を招く問題があった。 Normally, volatile memory can be written and read at high speed, and has a rewrite life of 10 12 times. However, there is a drawback that it is difficult to increase the capacity. On the other hand, the non-volatile memory can retain information even after the power is cut off, but has a shorter rewrite life than a volatile memory and a slower writing / reading speed. Since SoC requires both applications, it has both volatile and non-volatile memory in the system. Conventionally, it is necessary to provide a memory peripheral circuit for each of the volatile memory and the nonvolatile memory, and there is a problem in that the circuit area is increased.
　例えば下記の特許文献１および特許文献２に記載されているように、ＳＲＡＭ並の高速アクセスを可能とし、不揮発性の特性を有するメモリ（スピン注入メモリ或いはＳＴＴ(Spin Transfer Torque)－ＲＡＭと称される）が開発されつつある。ＳＴＴ－ＲＡＭのメモリセルでは、電子のスピンによって生じる磁気モーメントを利用して磁性体の磁化の方向を変えるものである。ＳＴＴ－ＲＡＭは、微細化することができ、書き込みに必要な電流値が小さくなり、高密度化に適した特性を有する。 For example, as described in Patent Document 1 and Patent Document 2 below, a memory (spin-injection memory or STT (Spin Transfer Transfer Torque) -RAM) that enables high-speed access similar to SRAM and has non-volatile characteristics. Are being developed. In the memory cell of the STT-RAM, the direction of magnetization of the magnetic material is changed using a magnetic moment generated by electron spin. The STT-RAM can be miniaturized, a current value required for writing is reduced, and has characteristics suitable for high density.
特開２００８－２２７３８８号公報JP 2008-227388 A 特開２０１２－５９８７９号公報JP 2012-59879 A
　ＳＴＴ－ＲＡＭの特性として、ＳＲＡＭ並の速度で書き込みを行うと、データ保持期間が著しく短くなり、不揮発性の特性が失われる。一方、十分な書き込み時間を設定すると、データ保持期間を例えば１０年とすることができる。 As a characteristic of the STT-RAM, when data is written at the same speed as the SRAM, the data retention period is remarkably shortened and the non-volatile characteristic is lost. On the other hand, if a sufficient writing time is set, the data retention period can be set to 10 years, for example.
　したがって、本開示は、かかる特性を利用して回路面積の増大を防止することができるメモリシステム、メモリ周辺回路およびメモリ制御方法の提供を目的とする。 Therefore, it is an object of the present disclosure to provide a memory system, a memory peripheral circuit, and a memory control method that can prevent an increase in circuit area using such characteristics.
　本開示は、メモリセルとメモリ周辺回路とを有し、
　メモリセルが高速書き込みがなされる第１の領域と、データ保持期間が長い第２の領域とに分割される
　メモリシステムである。
　本開示は、アドレス回路と、データ書き込み回路と、センスアンプと、プログラマブルタイミング生成回路とを有し、
　プログラマブルタイミング生成回路によって書き込みを活性化する期間の長さを設定するようになされるメモリ周辺回路である。
　本開示は、メモリセルを高速書き込みがなされる第１の領域と、データ保持期間が長い第２の領域とに分割し、
　分割位置をコンフィギュレーションデータによって設定するメモリ制御方法である。 The present disclosure includes a memory cell and a memory peripheral circuit,
In this memory system, the memory cell is divided into a first area where high-speed writing is performed and a second area where the data retention period is long.
The present disclosure has an address circuit, a data write circuit, a sense amplifier, and a programmable timing generation circuit,
This is a memory peripheral circuit configured to set the length of a period in which writing is activated by a programmable timing generation circuit.
The present disclosure divides a memory cell into a first region where high-speed writing is performed and a second region where a data retention period is long,
This is a memory control method for setting a division position by configuration data.
　少なくとも一つの実施形態によれば、ＳＲＡＭとＲＯＭ、またはＳＲＡＭとエンベデッドＮＶＭのように、複数のメモリを使用して高速アクセスメモリと不揮発性メモリとを実現しているのを単一メモリで実現することができる。したがって、メモリの面積を小さくすることができる。なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であっても良い。 According to at least one embodiment, high-speed access memory and non-volatile memory are realized by using a plurality of memories such as SRAM and ROM or SRAM and embedded NVM. be able to. Therefore, the area of the memory can be reduced. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
本開示の一実施の形態のブロック図である。1 is a block diagram of an embodiment of the present disclosure. 本開示の一実施の形態における揮発性メモリとして使用する領域に対する書き込み処理の説明に使用するタイミングチャートである。6 is a timing chart used for describing a writing process for an area used as a volatile memory according to an embodiment of the present disclosure. 本開示の一実施の形態における不揮発性メモリメモリとして使用する領域に対する書き込み処理の説明に使用するタイミングチャートである。6 is a timing chart used for explaining a writing process for an area used as a nonvolatile memory in an embodiment of the present disclosure. 本開示の一実施の形態における読み出し処理の説明に使用するタイミングチャートである。6 is a timing chart used for describing a reading process according to an embodiment of the present disclosure. コンフィギュレーションテーブルの一例を示す略線図である。It is a basic diagram which shows an example of a configuration table. 本開示の利点の説明に使用するブロック図である。FIG. 6 is a block diagram used to explain the advantages of the present disclosure.
　以下に説明する実施の形態は、本開示の好適な具体例であり、技術的に好ましい種々の限定が付されている。しかしながら、本開示の範囲は、以下の説明において、特に本開示を限定する旨の記載がない限り、これらの実施の形態に限定されないものとする。
　なお、本開示の説明は、下記の順序にしたがってなされる。
＜１．第１の実施の形態＞
＜２．変形例＞ The embodiment described below is a preferable specific example of the present disclosure, and various technically preferable limitations are given. However, the scope of the present disclosure is not limited to these embodiments unless otherwise specified in the following description.
In addition, description of this indication is made | formed according to the following order.
<1. First Embodiment>
<2. Modification>
＜第１の実施の形態＞
　図１を参照して本開示の第１の実施の形態によるメモリシステムについて説明する。メモリセルアレイ１は、例えばＳＴＴ－ＲＡＭである。メモリセルアレイ１に対してメモリ周辺回路が１つの半導体チップ上に集積化されている。メモリセルがワード線およびビット線の交叉位置に形成され、マトリクス状に配置される多数のメモリセルによってメモリセルアレイ１が構成される。 <First Embodiment>
A memory system according to a first embodiment of the present disclosure will be described with reference to FIG. The memory cell array 1 is, for example, an STT-RAM. A memory peripheral circuit is integrated on one semiconductor chip for the memory cell array 1. Memory cells are formed at the intersections of word lines and bit lines, and a memory cell array 1 is constituted by a large number of memory cells arranged in a matrix.
　ＳＴＴ－ＲＡＭの記憶素子は、上述した特許文献１または特許文献２に記載されているように、スピン注入により、記憶素子の記憶層の磁化の向きを反転させて、情報の記録を行うものである。記憶層は、強磁性層等の磁性体により構成され、情報を磁性体の磁化状態（磁化の向き）により保持するものである。 The storage element of the STT-RAM records information by reversing the direction of magnetization of the storage layer of the storage element by spin injection, as described in Patent Document 1 or Patent Document 2 described above. is there. The memory layer is made of a magnetic material such as a ferromagnetic layer, and holds information by the magnetization state (magnetization direction) of the magnetic material.
　ライトデータがデータ入出力回路２を通じてビット線デコーダおよび書き込み回路３に供給される。データ入出力回路２は、データバッファの機能を有する。アドレスがアドレス入力回路４を通じてアドレスデコーダ５に供給される。アドレスデコーダ５からワード線アドレスおよびビット線アドレスが出力される。 Write data is supplied to the bit line decoder and write circuit 3 through the data input / output circuit 2. The data input / output circuit 2 has a data buffer function. The address is supplied to the address decoder 5 through the address input circuit 4. A word line address and a bit line address are output from the address decoder 5.
　ワード線アドレスがワード線デコーダおよびドライバ６に供給され、ビット線アドレスがビット線デコーダおよび書き込み回路３に供給される。ワード線デコーダおよびドライバ６からメモリセルアレイ１のワード線の駆動信号が出力され、ビット線デコーダおよび書き込み回路３からメモリセルアレイ１のビット線の駆動信号が出力される。ワード線によって選択された行のメモリセルのリード／ライトがビット線を使用して選択的に行われる。 The word line address is supplied to the word line decoder and driver 6, and the bit line address is supplied to the bit line decoder and write circuit 3. A word line drive signal for the memory cell array 1 is output from the word line decoder / driver 6, and a bit line drive signal for the memory cell array 1 is output from the bit line decoder / write circuit 3. Reading / writing of the memory cells in the row selected by the word line is selectively performed using the bit line.
　メモリセルアレイ１からのデータの読み出し時には、アドレス入力回路４に対して読み出しアドレスが入力され、アドレスデコーダ５から読み出し時のワード線が選択され、ビット線の電圧の変化がビット線デコーダおよびセンスアンプ７によって判別される。読み出しデータがデータ入出力回路２を通じて取り出される。 When reading data from the memory cell array 1, a read address is input to the address input circuit 4, a word line at the time of reading is selected from the address decoder 5, and a change in the voltage of the bit line is determined by the bit line decoder and the sense amplifier 7. Is determined by Read data is taken out through the data input / output circuit 2.
　図１において、破線で示すように、メモリセルアレイ１が高速書き込みがなされる第１の領域１Ａと、データ保持期間が長い第２の領域１Ｂとに分割される。第１の領域１Ａは、データ保持期間が第２の領域１Ｂに比して短いものとされる。具体的には、第１の領域１Ａが揮発性メモリとして使用され、第２の領域１Ｂが不揮発性メモリとして使用される。分割位置は、ワード線アドレスによって表される。 In FIG. 1, as indicated by a broken line, the memory cell array 1 is divided into a first region 1A in which high-speed writing is performed and a second region 1B having a long data holding period. The first region 1A has a data retention period shorter than that of the second region 1B. Specifically, the first area 1A is used as a volatile memory, and the second area 1B is used as a nonvolatile memory. The division position is represented by a word line address.
　設定される分割位置を表すデータをコンフィギュレーション（またはコンフィギュレーションデータ）と称する。コンフィギュレーションは、例えばメモリセルアレイ１の所定のアドレスに記憶されており、電源オン時等にメモリセルアレイ１から読み出される。コンフィギュレーションは、メモリシステムの製造時に予めメモリセルアレイ１の所定のアドレスに書き込むようになされる。或いは、製造後にユーザ自身が設定して書き込んだデータでも良い。 ∙ Data representing the set division position is called configuration (or configuration data). The configuration is stored, for example, at a predetermined address of the memory cell array 1, and is read from the memory cell array 1 when the power is turned on. The configuration is written in advance at a predetermined address of the memory cell array 1 when the memory system is manufactured. Alternatively, it may be data set and written by the user after manufacturing.
　図１に示すように、コンフィギュレーション回路８からのコンフィギュレーションデータがアドレスデコーダ５に供給され、アドレスデコーダ５から出力されるコンフィギュレーションと対応するアドレスがプログラマブルタイミング生成回路９に供給される。プログラマブルタイミング生成回路９は、タイミング基準を発生するもので、例えば書き込みを活性化する時間の幅がコンフィギュレーションによって規定されたものとされる。 As shown in FIG. 1, configuration data from the configuration circuit 8 is supplied to the address decoder 5, and an address corresponding to the configuration output from the address decoder 5 is supplied to the programmable timing generation circuit 9. The programmable timing generation circuit 9 generates a timing reference. For example, the time width for activating writing is defined by the configuration.
　揮発性メモリとして使用されるデータ保持期間が短い領域１Ａにデータを書き込む場合には、書き込みを活性化する期間が短いものとされ、不揮発性メモリとして使用されるデータ保持期間が長い領域１Ｂにデータを書き込む場合には、書き込みを活性化する期間が長いものとされる。なお、読み出しが活性化される期間は、領域１Ａと領域Ｂとで等しいものとされている。 When data is written to the region 1A having a short data holding period used as a volatile memory, the period for activating the writing is short, and the data is stored in the region 1B having a long data holding period used as a nonvolatile memory. Is written, the period for activating the writing is long. Note that the period in which reading is activated is the same in the region 1A and the region B.
　図２は、領域１Ａに対する書き込み動作のタイミングチャートである。上から順にクロックＣＬＫ、アドレスＡＤＲＳ、データＤＡＴＡ、ライトイネーブル、リードイネーブル、ライトパルス、リードパルスが示されている。書き込み動作のために、ライトイネーブルがアクティブ（ハイレベル）とされ、リードイネーブルが非アクティブ（ローレベル）とされている。さらに、リードパルスが発生しない。 FIG. 2 is a timing chart of the write operation for the area 1A. From the top, clock CLK, address ADRS, data DATA, write enable, read enable, write pulse, and read pulse are shown. For the write operation, the write enable is active (high level) and the read enable is inactive (low level). Further, no read pulse is generated.
　領域１Ａに対する書き込みにおいて、ライトパルスが短くて良いので、クロックＣＬＫの１サイクル毎にアドレス（Ａ１，Ａ２，・・・）とデータ（Ｄ１，Ｄ２，・・・）とを入力するようになされる。 In writing to the area 1A, since the write pulse may be short, an address (A1, A2,...) And data (D1, D2,...) Are input every cycle of the clock CLK. .
　図３は、領域１Ｂに対する書き込み動作のタイミングチャートである。上から順にクロックＣＬＫ、アドレスＡＤＲＳ、データＤＡＴＡ、ライトイネーブル、リードイネーブル、ライトパルス、リードパルスが示されている。書き込み動作のために、ライトイネーブルがアクティブ（ハイレベル）とされ、リードイネーブルが非アクティブ（ローレベル）とされている。さらに、リードパルスが発生しない。 FIG. 3 is a timing chart of the write operation for the region 1B. From the top, clock CLK, address ADRS, data DATA, write enable, read enable, write pulse, and read pulse are shown. For the write operation, the write enable is active (high level) and the read enable is inactive (low level). Further, no read pulse is generated.
　領域１Ａに対する書き込みにおいて、ライトパルスがある一定期間以上の幅を有することが必要とされる。一例として、クロックＣＬＫの５サイクルの幅をライトパルスが有する。したがって、クロックの５サイクルの期間、アドレス（Ａ１，Ａ２，・・・）とデータ（Ｄ１，Ｄ２，・・・）とが保持されている。 In writing to the region 1A, the write pulse needs to have a width of a certain period or more. As an example, the write pulse has a width of 5 cycles of the clock CLK. Therefore, the address (A1, A2,...) And the data (D1, D2,...) Are held for a period of five clock cycles.
　読み出し時には、図４に示すタイミングチャートで示すようなタイミングで読み出し処理がなされる。図４の上から順にクロックＣＬＫ、アドレスＡＤＲＳ、データＤＡＴＡ、ライトイネーブル、リードイネーブル、ライトパルス、リードパルスが示されている。読み出し動作のために、ライトイネーブルが非アクティブ（ローレベル）とされ、リードイネーブルがアクティブ（ハイレベル）とされている。さらに、ライトパルスが発生しない。読み出し処理は、領域１Ａおよび１Ｂの両者とも、短い期間で行えば良い。例えばクロックの１サイクルでデータの読み出しが可能とされる。 At the time of reading, the reading process is performed at the timing shown in the timing chart shown in FIG. The clock CLK, address ADRS, data DATA, write enable, read enable, write pulse, and read pulse are shown in order from the top of FIG. For the read operation, the write enable is inactive (low level) and the read enable is active (high level). Further, no write pulse is generated. The reading process may be performed in a short period in both the regions 1A and 1B. For example, data can be read out in one cycle of the clock.
　コンフィギュレーションは、テーブル形式でメモリセルアレイ１に格納されている。メモリセルアレイ１を３個の領域に分割する場合のコンフィギュレーションの一例を図５Ａに示す。図５Ａに示すように、コンフィギュレーションは、ラストアドレスとパラメータとによって定義される。最小のラストアドレス例えば１００は、アドレス０～アドレス１００までのコンフィギュレーションを表す。次のラストアドレスが２００とされている。このラストアドレスは、一つ前のコンフィギュレーションの次のアドレス（例えばアドレス１０１）からラストアドレス２００までのコンフィギュレーションを表している。さらに次のアドレスが３００とされている。このラストアドレスは、一つ前のコンフィギュレーションの次のアドレス（例えばアドレス２０１）からラストアドレス３００までのコンフィギュレーションを表している。 The configuration is stored in the memory cell array 1 in a table format. An example of a configuration in the case where the memory cell array 1 is divided into three regions is shown in FIG. 5A. As shown in FIG. 5A, the configuration is defined by a last address and parameters. The minimum last address, for example, 100 represents a configuration from address 0 to address 100. The next last address is 200. This last address represents a configuration from the next address (for example, address 101) of the previous configuration to the last address 200. Further, the next address is 300. This last address represents the configuration from the next address (for example, address 201) to the last address 300 of the previous configuration.
　パラメータが図５Ｂに示すように規定されている。パラメータ１は、書き込みパルスの幅が１０nsecを意味し、パラメータ２は、書き込みパルスの幅が１００nsecを意味し、パラメータ３は、書き込みパルスの幅が１０μsecを意味する。例えば書き込みパルスの幅が１００μsecとされると、不揮発性メモリとして長いデータ保持期間を持つことができる。 Parameters are specified as shown in FIG. 5B. Parameter 1 means a write pulse width of 10 nsec, parameter 2 means a write pulse width of 100 nsec, and parameter 3 means a write pulse width of 10 μsec. For example, when the width of the write pulse is 100 μsec, the nonvolatile memory can have a long data holding period.
　上述した本開示の一実施の形態によれば、実現に必要なメモリの面積を小さくすることができる。従来では、図６Ａに示すように、揮発性メモリ（例えばＳＲＡＭ）と不揮発性メモリ（例えばマスクＲＯＭまたはフラッシュメモリ）を必要とする場合に、別々のチップ上に構成していた。 According to the embodiment of the present disclosure described above, it is possible to reduce the area of the memory necessary for realization. Conventionally, as shown in FIG. 6A, when a volatile memory (for example, SRAM) and a nonvolatile memory (for example, mask ROM or flash memory) are required, they are configured on separate chips.
　ＳＲＡＭのメモリセル２１と関連して、データ入出力回路２２、ビット線デコーダおよび書き込み回路２３、アドレス入力回路２４、ワード線デコーダおよびドライバ２６、並びにビット線デコーダおよびセンスアンプ２７を含むメモリ周辺回路が設けられている。アドレス入力回路２４にアドレスデコーダが含まれている。これらのメモリセル２１およびメモリ周辺回路が一つの半導体チップ上に集積化される。 In connection with the SRAM memory cell 21, a memory peripheral circuit including a data input / output circuit 22, a bit line decoder and write circuit 23, an address input circuit 24, a word line decoder and driver 26, and a bit line decoder and sense amplifier 27 is provided. Is provided. The address input circuit 24 includes an address decoder. These memory cells 21 and memory peripheral circuits are integrated on one semiconductor chip.
　マスクＲＯＭまたはフラッシュメモリのメモリセル３１と関連して、同様のメモリ周辺回路が設けられている。すなわち、データ入出力回路３２、ビット線デコーダおよび書き込み回路３３、アドレス入力回路３４、ワード線デコーダおよびドライバ３６、並びにビット線デコーダおよびセンスアンプ３７が設けられている。これらのメモリセル３１およびメモリ周辺回路が一つの半導体チップ上に集積化される。 A similar memory peripheral circuit is provided in association with the memory cell 31 of the mask ROM or flash memory. That is, a data input / output circuit 32, a bit line decoder and write circuit 33, an address input circuit 34, a word line decoder and driver 36, and a bit line decoder and sense amplifier 37 are provided. These memory cells 31 and memory peripheral circuits are integrated on one semiconductor chip.
　図６Ａに示すように、メモリセル２１とメモリセル３１のそれぞれに対して重複してメモリ周辺回路を持つことが必要となり、メモリの面積が大きくなり、また、冗長なものとなる。これに対して、図６Ｂに示すように、本開示の一実施の形態では、メモリセルアレイ１を領域１Ａ（ＳＲＡＭ）と領域１Ｂ（マスクＲＯＭまたはフラッシュメモリ）に分割して使用するので、コンフィギュレーション回路８を必要とするが、他の周辺回路を共用することができる。したがって、メモリの面積を従来の構成と比較して小さいものとできる。これによって、ＳｏＣのコストダウンを実現することができる。さらに、製品毎に揮発性メモリと不揮発性メモリとのバランスを個別に設定することかできるので、単一のＳｏＣで複数のアプリケーションに対応することができる。 As shown in FIG. 6A, it is necessary to overlap the memory peripheral circuit with respect to each of the memory cell 21 and the memory cell 31, which increases the area of the memory and makes it redundant. On the other hand, as shown in FIG. 6B, in the embodiment of the present disclosure, the memory cell array 1 is divided into a region 1A (SRAM) and a region 1B (mask ROM or flash memory), and thus the configuration is used. Although the circuit 8 is required, other peripheral circuits can be shared. Therefore, the area of the memory can be reduced as compared with the conventional configuration. Thereby, the cost reduction of SoC is realizable. Furthermore, since the balance between the volatile memory and the nonvolatile memory can be individually set for each product, it is possible to deal with a plurality of applications with a single SoC.
＜２．変形例＞
　以上、本開示の実施形態について具体的に説明したが、上述の各実施形態に限定されるものではなく、本開示の技術的思想に基づく各種の変形が可能である。例えば、上述の実施形態において挙げた構成、方法、工程、形状、材料および数値などはあくまでも例に過ぎず、必要に応じてこれと異なる構成、方法、工程、形状、材料および数値などを用いてもよい。 <2. Modification>
As mentioned above, although embodiment of this indication was described concretely, it is not limited to each above-mentioned embodiment, and various modification based on the technical idea of this indication is possible. For example, the configurations, methods, processes, shapes, materials, numerical values, and the like given in the above-described embodiments are merely examples, and different configurations, methods, processes, shapes, materials, numerical values, and the like are used as necessary. Also good.
　なお、本開示は、以下のような構成も取ることができる。
（１）
　メモリセルとメモリ周辺回路とを有し、
　前記メモリセルを高速書き込みがなされる第１の領域と、データ保持期間が長い第２の領域とに分割する
　メモリシステム。
（２）
　前記第１の領域は、データ保持期間が前記第２の領域に比して短い（１）に記載のメモリシステム。
（３）
　前記第１の領域が揮発性メモリとして使用され、前記第２の領域が不揮発性メモリとして使用される（１）または（２）に記載のメモリシステム。
（４）
　前記メモリ周辺回路は、アドレスデコーダと、データ書き込み回路と、センスアンプと、プログラマブルタイミング生成回路とを有し、
　前記プログラマブルタイミング生成回路によって書き込みを活性化する期間の長さを設定するようになされる（１）または（２）に記載のメモリシステム。
（５）
　前記書き込みを活性化する期間の長さは、コンフィギュレーションデータによって規定される（４）に記載のメモリシステム。
（６）
　アドレス回路と、データ書き込み回路と、センスアンプと、プログラマブルタイミング生成回路とを有し、
　前記プログラマブルタイミング生成回路によって書き込みを活性化する期間の長さを設定するようになされるメモリ周辺回路。
（７）
　メモリセルを高速書き込みがなされる第１の領域と、データ保持期間が長い第２の領域とに分割し、
　分割位置をコンフィギュレーションデータによって設定するメモリ制御方法。 In addition, this indication can also take the following structures.
(1)
A memory cell and a memory peripheral circuit;
A memory system that divides the memory cell into a first area in which high-speed writing is performed and a second area having a long data retention period.
(2)
The memory system according to (1), wherein the first area has a data retention period shorter than that of the second area.
(3)
The memory system according to (1) or (2), wherein the first area is used as a volatile memory and the second area is used as a nonvolatile memory.
(4)
The memory peripheral circuit includes an address decoder, a data write circuit, a sense amplifier, and a programmable timing generation circuit,
The memory system according to (1) or (2), wherein a length of a period in which writing is activated is set by the programmable timing generation circuit.
(5)
The memory system according to (4), wherein a length of a period for activating the writing is defined by configuration data.
(6)
An address circuit, a data write circuit, a sense amplifier, and a programmable timing generation circuit;
A memory peripheral circuit configured to set a length of a period in which writing is activated by the programmable timing generation circuit.
(7)
The memory cell is divided into a first area where high-speed writing is performed and a second area where the data retention period is long,
A memory control method for setting a division position by configuration data.
１・・・メモリセルアレイ
２・・・データ入出力回路
３・・・ビット線デコーダおよび書き込み回路
４・・・アドレス入力回路
５・・・アドレスデコーダ
６・・・ワード線デコーダおよびドライバ
７・・・ビット線デコーダおよびセンスアンプ
８・・・コンフィギュレーション回路 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Data input / output circuit 3 ... Bit line decoder and write circuit 4 ... Address input circuit 5 ... Address decoder 6 ... Word line decoder and driver 7 ... Bit line decoder and sense amplifier 8... Configuration circuit

Claims (7)

  1. 　メモリセルとメモリ周辺回路とを有し、
    　前記メモリセルを高速書き込みがなされる第１の領域と、データ保持期間が長い第２の領域とに分割する
    　メモリシステム。     A memory cell and a memory peripheral circuit;
    A memory system that divides the memory cell into a first area in which high-speed writing is performed and a second area having a long data retention period.
  2. 　前記第１の領域は、データ保持期間が前記第２の領域に比して短い請求項１に記載のメモリシステム。 The memory system according to claim 1, wherein the first area has a shorter data retention period than the second area.
  3. 　前記第１の領域が揮発性メモリとして使用され、前記第２の領域が不揮発性メモリとして使用される請求項１または２に記載のメモリシステム。 The memory system according to claim 1 or 2, wherein the first area is used as a volatile memory and the second area is used as a nonvolatile memory.
  4. 　前記メモリ周辺回路は、アドレスデコーダと、データ書き込み回路と、センスアンプと、プログラマブルタイミング生成回路とを有し、
    　前記プログラマブルタイミング生成回路によって書き込みを活性化する期間の長さを設定するようになされる請求項１または２に記載のメモリシステム。     The memory peripheral circuit includes an address decoder, a data write circuit, a sense amplifier, and a programmable timing generation circuit,
    The memory system according to claim 1, wherein a length of a period for activating writing is set by the programmable timing generation circuit.
  5. 　前記書き込みを活性化する期間の長さは、コンフィギュレーションデータによって規定される請求項４に記載のメモリシステム。 5. The memory system according to claim 4, wherein a length of a period for activating the writing is defined by configuration data.
  6. 　アドレス回路と、データ書き込み回路と、センスアンプと、プログラマブルタイミング生成回路とを有し、
    　前記プログラマブルタイミング生成回路によって書き込みを活性化する期間の長さを設定するようになされるメモリ周辺回路。     An address circuit, a data write circuit, a sense amplifier, and a programmable timing generation circuit;
    A memory peripheral circuit configured to set a length of a period in which writing is activated by the programmable timing generation circuit.
  7. 　メモリセルを高速書き込みがなされる第１の領域と、データ保持期間が長い第２の領域とに分割し、
    　分割位置をコンフィギュレーションデータによって設定するメモリ制御方法。     The memory cell is divided into a first area where high-speed writing is performed and a second area where the data retention period is long,
    A memory control method for setting a division position by configuration data.
PCT/JP2015/002164 2014-05-13 2015-04-21 Memory system, memory peripheral circuit, and memory control method WO2015174020A1 (en)

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