WO2015161890A1 - Configurations d'horloge adaptative et procédés d'étalonnage associé - Google Patents

Configurations d'horloge adaptative et procédés d'étalonnage associé Download PDF

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Publication number
WO2015161890A1
WO2015161890A1 PCT/EP2014/058457 EP2014058457W WO2015161890A1 WO 2015161890 A1 WO2015161890 A1 WO 2015161890A1 EP 2014058457 W EP2014058457 W EP 2014058457W WO 2015161890 A1 WO2015161890 A1 WO 2015161890A1
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Prior art keywords
clock
frequency
circuit
signal
source
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PCT/EP2014/058457
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English (en)
Inventor
Jordi Cortadella
Luciano Lavagno
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Universitat Politècnica De Catalunya
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Priority to PCT/EP2014/058457 priority Critical patent/WO2015161890A1/fr
Publication of WO2015161890A1 publication Critical patent/WO2015161890A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Definitions

  • the present disclosure relates to electronics and more specifically to adaptive clocking schemes.
  • a typical synchronous circuit operates with a periodic clock signal that synchronizes all sequential elements of the circuit. For a correct operation, the period of the clock signal must be longer than the worst-case internal propagation delays between the sequential elements triggered by the clock signal.
  • a circuit may have multiple clock signals, possibly working at different frequencies, which synchronize different parts of the circuit.
  • Clock signals are produced by clock generators.
  • the most common scheme for a clock generator is a phase-locked loop (PLL) that generates a periodic output signal from an input reference signal produced by a crystal oscillator.
  • PLL phase-locked loop
  • One of the desirable properties of a clock signal is to have a stable frequency with very small variations so that the frequency can be closely adjusted to the worst-case propagation delays of the circuit.
  • the variation of the clock frequency is called jitter. The larger the jitter, the longer the clock period must be to cover all possible variations of the clock period.
  • the clock period must also cover the delay variations produced by different sources, such as process, voltage, temperature and aging.
  • the clock period that could be used for an ideal circuit with no variability must be lengthened with various guard-band margins to account for the worst-case delay generated by all the sources of variability.
  • Process variations are static and their impact on the delay of the circuit can be measured after fabrication.
  • the margins required to cover process variability can be defined individually for each circuit according to the delay measurements. This approach is called binning and contributes to improving performance or reducing power when the actual process variability is less than the estimated worst case.
  • Dynamic variations can be classified into slow and fast.
  • temperature and aging are sources of slow variability.
  • Voltage is typically a source of fast variability, since voltage droops may occur with frequencies close to the frequency of the clock signal.
  • CPR critical path replica
  • Another mechanism is the use of critical path replica (CPR) configurations with extra guard-band delays to alert when a timing error is about to occur.
  • Critical path replica configurations reflect delay characteristics of critical paths under e.g. process, voltage, temperature changes or other variability parameters.
  • a timing error in the CPR indicates that the delay of the real critical paths is approaching the clock period. This information may be used to modify the clock period and avoid timing errors.
  • the mechanism can be implemented using multiple CPRs with different sensitivity to different variability parameters.
  • the present disclosure provides adaptive clocking configurations with delay monitoring and clock generation to reduce the margins required for the clock period to cover slow and fast variability of logic circuits. Additionally, the present disclosure also includes a method of calibrating the proposed clocking configurations in such a way that timing correctness is guaranteed for the logic circuit.
  • Timing correctness is defined as the ability to (1 ) function without violating setup and hold times for any sequential element, and to (2) deliver a pre-specified level performance under all operating conditions, when the performance measurement period is long enough and a pre-specified average voltage is supplied during that period.
  • the adaptive clocking scheme proposed herein may monitor the static and dynamic variability of a logic circuit and generate a clock signal that dynamically adapts to the timing of the critical paths in the circuit.
  • the clocking scheme may only contain digital components and generate a clock signal with a variable frequency that can be instantaneously adapted to the dynamic variations of the logic circuit, such as voltage droops, temperature and aging.
  • the time margins required for the circuit may be smaller when running with variable frequency.
  • the average frequency of the clock signal may be higher than the one generated with fixed frequency (e.g., by a PLL) running the circuit at the same voltage. Alternatively, the circuit can run at the same average frequency with a lower voltage.
  • the present invention allows the clocking scheme to use various clock generators and be calibrated by software, hardware or both.
  • a calibration method to guarantee the timing correctness of the circuit is also presented.
  • the method can be applied after fabrication by defining the parameters of the control used to adjust the frequency of the clock signal.
  • the method can be supported by static timing analysis tools used in the conventional design flows.
  • a clocking device for generating at least one clock signal at one or more outputs.
  • the device comprises at least a first clock source for generating a clock signal having an adaptive clock frequency at an output, at least one multiplexer having at least a first input coupled to the output of the at least first clock source and at least a second input configured to be coupled to the output of at least a second clock source having a fixed clock frequency.
  • the device further comprises a controller coupled at least to said at least first clock source, and to said at least one multiplexer.
  • the controller is configured to generate the at least one clock signal by selecting between at least a first and a second clock value from said at least first and second clock sources, respectively.
  • the controller may select between a fixed clock frequency and an adaptive clock frequency. For example, if there is a requirement for a synchronous mode of operation, then the controller may select a clock source with a fixed frequency. On the other hand, if, e.g. an application indicates that an asynchronous mode is allowable then the controller may select a clock source with an adaptive frequency. This flexibility allows the device to operate between two modes, a rigid mode and an adaptive mode, depending on whether the fixed frequency clock source or the adaptive frequency clock source is used for clocking the logic circuit.
  • the controller may also be connected to any other device (e.g. a voltage regulator) that may determine any non-functional parameter of the circuit, such as performance, power, etc.).
  • the controller may be implemented fully in hardware or may have some programmable components, e.g., may comprise a microprocessor with an external program that can be uploaded into the controller.
  • the clocking device may further comprise the at least second clock source. This may be desirable when, e.g., it is more convenient to replace an existing fixed frequency clocking source with the proposed clocking device than to connect the existing frequency clocking source to the multiplexer input of the proposed clocking device.
  • the clocking device may further comprise one or more digital monitors.
  • the controller may then be configured to generate the at least one clock signal based on information received from said one or more digital monitors.
  • the controller circuit may read information from the digital monitors and calibrate the controlled logic circuits to ensure the desired level of performance, power, energy consumption, speed etc.
  • the controller may be further configured to adjust the frequency of the first clock source based on said information received from said one or more digital monitors. Therefore, the same controller may calculate the optimum clock frequency for a given state of the logic circuit based on the information received by the digital monitors, adjust the frequency of the adaptive clock source and provide the adapted clock signal to the logic circuit.
  • the at least first clock source may comprise a ring oscillator.
  • a ring oscillator may be used as a clock generator that instantaneously reacts to delay fluctuations produced by fast variability, i.e., by fast voltage droops that cannot be compensated by other means (e.g. by changing the frequency of the fixed clock source), or that would require excessively expensive on-chip decoupling capacitors.
  • fast variability i.e., by fast voltage droops that cannot be compensated by other means (e.g. by changing the frequency of the fixed clock source), or that would require excessively expensive on-chip decoupling capacitors.
  • a significant part of the margins required for fast variability may be reduced because the clock generator, i.e. the ring oscillator, is highly sensitive to the voltage variations of the circuit.
  • the at least second clock source may comprise a PLL.
  • a conventional PLL or a quartz oscillator or any other traditional clock generation mechanism, which can be used to operate the circuit in a conventional synchronous mode may be used as a fixed frequency clock source.
  • the digital monitors may be time-to-digital converters (TDCs).
  • TDCs time-to-digital converters
  • the time-to-digital converters may be used to measure the delay of the circuit.
  • the information obtained from the TDCs may be used to adjust the frequency of the clock to the operating conditions of the circuit and alert about potential future timing violations.
  • the functionality of the TDCs may not interfere with the functionality of the logic circuit.
  • the TDCs may be connected to one of the outputs of the clock generator that can select the same clock source with adaptive frequency as the one selected for the logic circuit.
  • the TDCs may be calibrated before fabrication.
  • the calibration method may be based on static timing analysis of the delays of the TDCs and the critical paths of the logic circuit using conventional commands for setup/hold constraints and similar on- chip variability factors and margins as the ones used for clock schemes with fixed frequency.
  • the calibration of each TDC may be defined similarly for all dies and may be applied either during the design of the circuit (e.g., by hardwiring the calibration signals) or after fabrication (e.g., by laser trimming) or during the initialization of the circuit by a program executed by the control circuit. Any calibration methods supported by conventional static timing analysis tools and using similar margins and derating factors as the ones used for timing signoff may be used for the calibration.
  • the TDCs may be calibrated while the circuit is operating, i.e. during runtime.
  • the calibration method may be based on a process that measures the frequency of the adaptive clock source, e.g. the ring oscillator, with different configurations and the delay of the TDCs for different calibrations.
  • This process may be executed by the controller by selecting the adaptive clock source for the TDCs and a different clock source, e.g. a PLL, for the logic circuit. Based on the measurements obtained during this process, the control circuit calibrates the TDCs.
  • This method can be executed periodically to adapt the calibration to parameters that slowly change during the life of the circuit (e.g., due to aging). In other implementations both calibration methods may be performed, one during the initialization of the circuit and the other periodically along the life of the circuit.
  • each of the one or more digital monitors e.g.
  • the TDCs may comprise a programmable delay circuit coupled to an edge detection circuit.
  • the programmable delay circuit may comprise an input and an output and a plurality of delay circuits. Each of the plurality of delay circuits may be configured to generate a delay to the programmable delay circuit.
  • the plurality of delay circuits may be coupled in a multiplexed configuration so that the output of the programmable delay circuit is selectably a delay output of any of the delay circuits or a multiplexed combination of delays.
  • any other type of programmable delay circuits may be used without departing from the scope of embodiments disclosed herein.
  • the edge detector may comprise a plurality of tapped delays, arranged in a chain configuration, and a plurality of flip-flop circuits.
  • the edge detector may be configured to receive an input signal and propagate it across the chain of tapped delays and each flip-flop may be configured to store the signal from an output of the corresponding tapped delay.
  • some of the flip-flops may capture the previous value of the input signal whereas some others may capture the next value.
  • other implementations of edge detectors may be possible with the capacity to measure the propagation delay of a timing path and obtain information about the actual variability of the circuit.
  • the clocking device may further comprise a plurality of multiplexers.
  • Each multiplexer may have a plurality of clock source inputs for receiving the outputs of each clock source of the plurality of clock sources, and a control input for receiving a corresponding clock selection signal, respectively.
  • Each multiplexer may be configured to provide a clock signal based on the corresponding clock selection signal.
  • the multiplexer may be constantly receiving a plurality of clock signals from fixed or adaptive clock sources but only allow one signal at its output. Thus, the controller may select the clock signal simply by controlling the multiplexer.
  • the clocking device may further comprise at least one synchronizing circuit, configured to receive a control signal at a first input, the clock signal at a second input and generate a clock activation signal at an output.
  • the synchronizing circuit may comprise a synchronizer having a sequence of flip-flops triggered by the clock signal and generating the clock activation signal.
  • the device may further comprise a clock gating circuit, having a first input coupled to the clock signal and a second input coupled to the output of the synchronizer. This allows for the controller to enable or disable the clock and avoid any spurious behavior of the clock.
  • a digital circuit is disclosed.
  • the digital circuit may comprise a clocking device for generating at least one clock signal at one or more outputs according to embodiments disclosed herein and a logic circuit.
  • the logic circuit may have at least a first input coupled to the output of the clocking device for receiving said at least one clock signal.
  • the one or more digital monitors of the clocking device may be distributed in the logic circuit to measure directly the delay of one or more replica paths and thereby indirectly the delay of one or more critical paths. By monitoring the delay at various paths in the logic circuit it is possible to measure delays caused by fast dynamic variability in the logic circuit.
  • the device may be configured to calculate the frequency of said at least one clock signal based on a function, e.g. the maximum, of the delays measured by the one or more digital monitors.
  • the device may be further configured to set the period of the first clock source based on said calculation.
  • the digital circuit may further comprise a power management unit.
  • the power management unit may be configured to regulate the power supply so that the frequency of the clock is a function of the frequency of a reference clock.
  • the frequency of the clock may be set equal to the frequency of the reference clock or a multiple of the frequency of the reference clock.
  • the frequency of the adaptive clock may be a function of the supply voltage.
  • the frequency may be regulated by a feedback loop that controls a voltage regulator of the power supply and stabilizes it to a value determined by the reference clock that may be external.
  • the power management unit may be configured to power the controller, the clock sources and the TDCs and the controller may be configured to generate a control signal to regulate the power supply of the power management unit.
  • At least one of the clocking devices and the logic circuit is an integrated circuit.
  • the margins can be defined individually for each die of the integrated circuit, by software, hardware or both, by calibrating the delay monitors and the adaptive clock source.
  • a method of calibrating an adaptive frequency clock source comprises setting a clock signal for a logic circuit equal to a first clock signal; receiving information from one or more digital monitors monitoring delays in paths of the logic circuit; calculating a desired clock frequency in response to the received information; setting a clock frequency at a second clock source, said second clock source configured to generate a second clock signal with an adaptive frequency, equal to the calculated clock frequency; setting the clock signal for the logic circuit equal to the second clock signal.
  • the controller may calibrate the adaptive clock at runtime based on the measurements obtained from the digital monitors, e.g. the TDCs, during the operation of the circuit.
  • the controller may adapt the frequency of the clock to the delays of the TDCs, by reducing the frequency when the delays measured in the TDCs are too long or by increasing the frequency when the delays are too short.
  • the controller may receive a reference clock frequency and regulate a power supply of the logic circuit until the clock frequency at the second clock source is a function of the reference clock frequency;
  • said receiving information from one or more digital monitors may comprise receiving information from a plurality of digital monitors distributed in the logic circuit to monitor critical paths of the logic circuit.
  • the method may be implemented by electronic means or a combination of electronic and computer means.
  • the method (or a part of it) may be implemented by logic gates in combination with computer programs.
  • a computing device may comprise a memory and a processor.
  • the memory may store computer program instructions executable by the processor. Said instructions may comprise functionality to execute a method of calibrating an adaptive frequency clock source according to embodiments disclosed herein.
  • a computer program product is disclosed.
  • the computer product may comprise comprising instructions to provoke that a computing device implements a method of calibrating an adaptive frequency clock source according to embodiments disclosed herein.
  • the computer program product may be embodied on a storage medium (for example, a CD-ROM, a DVD, a USB drive, on a computer memory or on a read-only memory) or carried on a carrier signal (for example, on an electrical or optical carrier signal).
  • the computer program may be in the form of source code, object code, a code intermediate source and object code such as in partially compiled form, or in any other form suitable for use in the implementation of the processes according to the invention.
  • the carrier may be any entity or device capable of carrying the computer program.
  • the carrier may comprise a storage medium, such as a ROM, for example a CD ROM or a semiconductor ROM, or a magnetic recording medium, for example a floppy disc or hard disk.
  • a storage medium such as a ROM, for example a CD ROM or a semiconductor ROM, or a magnetic recording medium, for example a floppy disc or hard disk.
  • the carrier may be a transmissible carrier such as an electrical or optical signal, which may be conveyed via electrical or optical cable or by radio or other means.
  • the carrier may be constituted by such cable or other device or means.
  • the carrier may be an integrated circuit in which the computer program is embedded, the integrated circuit being adapted for performing, or for use in the performance of, the relevant methods.
  • the proposed solutions provide a number of benefits for logic circuit designers. They may provide significant savings in power if the voltage supply is regulated so that the adaptive clock generator is adjusted according to a reference clock frequency. They may provide performance benefits if the adaptive clock generator is operated at maximum allowed frequency that guarantees timing correctness without violating variability margins. Furthermore, the technics are not intrusive as the adaptive clocking circuits need not interfere with the logic circuit. Additionally, they provide zero risk as the clocking mechanism may always switch to the fixed clocking source when recalibration of the adaptive clocking source is required or when the digital monitors appear to provide erroneous or untrustworthy information or simply when the adaptive clock source may fail. Therefore, no changes are required in the design flow meaning that no extra delays may be anticipated in tapeout. As the margins may be dynamically tuned at runtime, there is no need for calibrating the clocking mechanism before tapeout, although this may also be possible.
  • Figure 1 illustrates a block diagram of a digital circuit according to an embodiment
  • Figure 2 depicts an implementation of a programmable delay
  • Figure 3 depicts an example of an implementation of an edge detector
  • FIG. 4 depicts an example implementation of a Time-to- Digital Converter (TDC);
  • TDC Time-to- Digital Converter
  • Figure 5 shows an example of a clocking device using a ring oscillator
  • Figure 6 is an example timing diagram for the clocking device of Fig. 5
  • Figure 7 shows another example of a clocking device with two output clocks
  • Figure 8 depicts an example digital circuit configuration according to an example
  • Figure 9 depicts an example digital circuit configuration according to another embodiment for power management using the adaptive clocking scheme
  • Figure 10 illustrates a static calibration method according to an example
  • Figure 1 1 illustrates the delay and margins calculated for the calibration of a TDC
  • Figure 12 illustrates graphically how the regions may be determined for one TDC
  • Figure 13 is a flow diagram of a method of calibrating an adaptive frequency clock source.
  • FIG. 1 illustrates a block diagram of a digital circuit according to an embodiment.
  • the digital circuit 10 comprises a clocking device 20, a logic circuit 60 and a fixed frequency clock source 70.
  • the clocking device 20 comprises an adaptive clock source 30, a controller 40 and a multiplexer 50.
  • a first input of the multiplexer 50 is coupled to an output of the adaptive clock source 30 to receive a clock signal having an adaptive frequency.
  • a second input of the multiplexer may be coupled to the fixed clock source 70 for receiving a clock signal having a fixed frequency.
  • the multiplexer further comprises a control input coupled to an output of the controller 40 for receiving a signal for selecting between the clock signal of the adaptive clock source 30 and the clock signal of the fixed clock source 70.
  • the controller 40 is also coupled to the adaptive clock source 30 for setting the frequency of the clock signal of the adaptive clock source 30.
  • the controller 40 may also be coupled to the logic circuit.
  • Figure 2 depicts an implementation of a programmable delay.
  • Programmable delay 100 comprises different delays dO-dn that can be selected by multiplexers m1 -mn. Every combination of values for the selection signals s1 to sn of the multiplexers ml to mn results in a different delay.
  • the programmable delay 100 may also have a fixed delay (dO) independent from the selection signals. Each delay may be composed by a chain of gates, as shown in an example in Fig. 2a, with different sensitivities to the environment conditions.
  • the values of the delays d1 -dn can be defined in such a way that a large spectrum of different total delays can be constructed.
  • a set of delays is used such that d(i+1 ) is approximately 2 * d(i) providing 2 n uniformly distributed different values for the total delay.
  • Figure 3 depicts an example of an implementation of an edge detector.
  • the edge detector 200 receives an input signal that is propagated across a chain of tapped delays 205-1 to 205-i.
  • a set of flip-flops 210-1 to 210-i store the signals from the outputs of the tapped delays 205-1 to 205-i, respectively.
  • TDC 300 combines a programmable delay, such as the programmable delay 100 of Fig. 2, with an edge detector, such as the edge detector 200 of Fig. 3.
  • a programmable delay such as the programmable delay 100 of Fig. 2
  • an edge detector such as the edge detector 200 of Fig. 3.
  • the flip-flop 305 at the input of the programmable delay 100 is used to launch an edge that is propagated along the programmable delay 100 and the edge detector 200.
  • An enable signal may be used to trigger the TDC 300 periodically and not necessarily at every clock cycle.
  • a clock edge is generated at the launching flip-flop 305 and another clock edge is generated one cycle later, with the help of Flip Flop 310, at the edge detector to capture the propagation of the edge.
  • the enable signal may be activated more or less frequently in order to save power or cover different possible aging behaviors. The effect of aging on the delay of gates may depend, for example, on how frequently they switch.
  • the outputs of the edge detector 200 may be in metastability shortly after the values have been captured.
  • a strategy to avoid spurious behaviors produced by metastability is to read the outputs of the edge detector a few cycles after having been captured, thus guaranteeing an acceptable Mean Time Between Failures (MTBF). With this strategy, there may be no need to use synchronizers.
  • MTBF Mean Time Between Failures
  • FIG. 5 shows an example of a clock generator using a ring oscillator.
  • the clock generator 400 permits several clock sources, e.g., one generated by a PLL 405 (PLL), or by any other fixed frequency mechanism, such as e.g. a quartz-based oscillator, and another (R.O) generated by a ring oscillator 410 (or any other adaptive frequency mechanism).
  • PLL PLL 405
  • R.O radio frequency generator
  • a multiplexer 415 may be coupled to the outputs of the multiple clock sources 405, 410 and be controlled by a Select Clock signal.
  • the example clock generator of Fig. 4 may have a first mode of operation using the PLL-based clock and a second mode of operation using the ring oscillator based clock.
  • the clock period may be determined by conventional methods used in circuit design, either considering the worst-case delays estimated by static timing analysis or the ones estimated after binning.
  • the ring oscillator 410 is constructed with a programmable delay 100. Any configuration of the programmable delay 100, determined by the signals "Frequency", must construct a ring with an odd number of inverting gates.
  • the ring oscillator may have a control signal (Stop) to stop its activity e.g. for power saving.
  • the output of the programmable delay is coupled together with the Stop signal to a NAND gate to perform this function.
  • Stop signal to a NAND gate
  • the clock generator 400 also comprises a synchronizer 420 with an enable signal as a first input (Enable Clock).
  • the synchronizer 420 includes a sequence of flip-flops 425-1 to 425-i, triggered by the clock generated after the multiplexer (Clkmux). In the implementation of Fig. 5, the inverted signal generated after the multiplexer is used to trigger the flip flops.
  • the "Enable Clock" signal needs to be able to activate and de-activate the clock without generating any glitches or spurious transitions. Any change on the configuration of the clock generator requires a preceding disabling of the clock.
  • the clock may be enabled again.
  • the output of synchronizer 420 (S) and the output of multiplexer 415 (Clkmux) are coupled to a clock gating circuit 425.
  • the clock gating circuit comprises an AND gate to perform the function of clock enabling.
  • other implementations are also possible.
  • Figure 6 is an example timing diagram for the clocking device of Fig. 5. It illustrates (i) the signal at the output of the adaptive clock source (R.O.), (ii) the signal at the output of the fixed clock source (PLL), (iii) the clock enable signal that controls the synchronizer (Enable Clock), (iv) the signal at the output of the synchronizer (S) and before the clock gating circuit, (v), the clock select signal that controls the multiplexer (Select Clock), (vi) the output of the multiplexer (Clkmux), and, (vii) the clock signal (Clock). All signals may assume a high (enable) or a low (disable) value at any given moment.
  • the Enable Clock signal is high, the S signal is high and the Select Clock signal is low.
  • the clock signal is then equal to the PLL signal.
  • an instruction to switch from the fixed clock source signal (PLL) to the adaptive clock signal (R.O.) is received.
  • the Enable Clock signal is set to low which triggers the synchronizer.
  • the S signal is switched to low by the synchronizer and the Clock signal is disabled (set to low).
  • the S signal remains low, while the Clkmux signal is stabilizing.
  • the clock signal is still disabled and any glitches that might have been caused by the yet unstable Clkmux signal are avoided in the Clock signal.
  • the Clkmux signal may be considered stable enough and the synchronizer sets the S signal high which re- enables the Clock signal.
  • the Clock signal is now the R.O. signal during the period P6, after the moment t5.
  • FIG. 7 shows another example of a clock generator with two output clocks.
  • the clock generator 500 allows for the selection between different clocks for different components of the system.
  • having different clock outputs would allow the use of the PLL 505 for the main circuit while the ring oscillator 510 might be used to calibrate the TDCs.
  • the PLL 505 and the ring oscillator 510 are both coupled to two multiplexers 515A and 515B, each being independently controlled by control signals Select Clock 1 and Select Clock 2, respectively.
  • the output of multiplexers 515A and 515B may be accordingly controlled by synchronizers 520A and 520B, respectively, in a similar manner as discussed with reference to Fig. 5.
  • Gating circuits 525A and 525B are used to enable the two clock signals Clock 1 and Clock 2, respectively.
  • the flexibility of using the same or different clocks may increase the degree of parallelism between the operation of the main circuit and the control of the adaptive clocking scheme.
  • two clock sources are used in the implementation of Fig. 7, one skilled in the art may appreciate that any number of clock sources may be used, coupled to a corresponding number of multiplexers to generate a corresponding number of clock signals.
  • FIG 8 depicts an example circuit configuration according to an example.
  • the circuit 760 at the top of the figure is the logic circuit that implements the main functionality of the system 700.
  • the circuit 760 may be designed using conventional flows with or without depending on any information about the components of embodiments of adaptive clock generation disclosed herein. In particular, it may have been designed down to the layout level without considering the embodiments of adaptive clock generation disclosed herein, or its layout may be generated while including any components of the adaptive clock generation embodiments.
  • the clocks of the system may be generated by a clock generator such as the the clock generator 500 described with reference to Figure 7.
  • a set of TDCs, such as the TDCs 300, may be included to measure the delays of several paths.
  • a control system 750 may be used to calibrate the TDCs 300 and adjust them according to the critical paths of the circuit 760. This calibration may be done before tapeout, after fabrication (before or after packaging) or at runtime. In case it is done at runtime, it may be done each time the system is powered up, or it may be done several times during the operation of the circuit. For example, it may adapt progressively to aging, or it may change the margins in case the circuit is running at a very high temperature.
  • the clock source for the circuit 760 can be alternated between a PLL and a ring oscillator.
  • the TDCs 300 may be clocked with the same ring oscillator and their timing analysis can be done jointly with the main circuit.
  • the circuit 760 and the TDCs 300 may be both clocked with the ring oscillator. In this mode of operation the frequency of the ring oscillator will be able to be adjusted according to the delays of the TDCs.
  • the control circuit 750 may read the outputs of the TDCs 300 periodically to obtain information about the timing of the critical paths of the circuit. Based on this information, the control circuit 750 may decide to modify the configuration of the clock generator 500 either by calibrating the ring oscillator with a new frequency, or by selecting another clock source (e.g., the PLL) or by stopping the clock generator 500. This can be helpful, for example, when due to other operating conditions (e.g. excessive temperature) the delay tracking between the ring oscillator and the circuit would not lead to reliable operation, or when failures due to the ring oscillator are detected by a self-checking circuitry.
  • another clock source e.g., the PLL
  • the control circuit 750 may be designed in various ways, e.g., as a simple finite- state machine fully implemented in hardware or as a complex microprocessor with advanced algorithms that can be programmed by software. The preferred implementations are those that allow the calibration of the circuit during runtime either with software of with programmable logic.
  • the control circuit 750 may adjust the delay of the ring oscillator to follow as closely as possible the delay of the paths in the TDC, and hence the delay of the longest paths of the circuit.
  • Figure 9 depicts an example circuit configuration according to another embodiment for power management using the adaptive clocking scheme.
  • the circuit configuration 900 may use information obtained by the control unit 950 to regulate the power supply by means of a power management unit 910.
  • the frequency generated by the adaptive clock can be measured and compared with the frequency of a reference clock.
  • the frequency of the system will change accordingly in such a way that voltage and power will be adjusted to achieve a target clock frequency.
  • a possible mode of operation for the clock generator 500 generating three clock signals could be as follows: the control circuit 950 may always be clocked with a PLL (e.g. Clk3), the TDCs 930 may always be clocked with a ring oscillator (e.g. Clk2) and the logic circuit 960 may alternate between the clock generated by the PLL and the ring oscillator, depending on the operation mode of the system (rigid or adaptive clock).
  • a PLL e.g. Clk3
  • the TDCs 930 may always be clocked with a ring oscillator (e.g. Clk2)
  • the logic circuit 960 may alternate between the clock generated by the PLL and the ring oscillator, depending on the operation mode of the system (rigid or adaptive clock).
  • the adaptive clocking scheme may allow the use of a conventional design flow for synchronous circuits.
  • the presence of one (or more, for each clock domain) clock input in the clocking scheme may be used to simulate, synthesize, analyze, verify and test the circuit in a similar way as it is done for a synchronous circuit.
  • the period determined by the timing analysis using the external clock input may be the one used when the physical circuit is clocked with the PLL (or with any other traditional fixed frequency clocking mechanism).
  • the adaptive clocking scheme also allows the operation of the circuit in adaptive mode, in which the variable frequency clocking mechanism, e.g. the ring oscillator described herein, generates the clock.
  • the control circuit may then be responsible for calibrating the TDCs and the ring oscillator to ensure timing correctness of the circuit, while static timing analysis may ensure that the control circuit shall always, under any operating or aging conditions, be able to do so.
  • Figure 10 illustrates a static calibration method according to an example. The method is based on a multi-corner analysis of the critical paths of the circuit and the TDCs. The figure depicts the analysis for one of the corners of the library.
  • the critical path 1010 in the figure represents a worst-case propagation delay for the setup constraints of the circuit. The only important parameter for the analysis is the propagation delay of a critical path, regardless of which critical path is associated to that delay.
  • derating factors may be used to account for the on-chip variability between competing paths, e.g., launching and capturing paths in setup constraints.
  • launching paths may be derated with factors greater than or equal to one
  • capturing paths may be derated with factors smaller than or equal to one.
  • some extra safety margins may be used in the analysis to account for other unknown or hard to determine factors that could make the analysis too optimistic (e.g., inaccuracy of the analysis tools, aging, etc.).
  • the worst propagation delay in the timing analysis method described herein can be calculated with the same derating factors and margins used for a conventional timing analysis with a traditional fixed frequency clock.
  • This information may be used now to calibrate the TDCs and parameterize the method to determine the frequency of the ring oscillator.
  • a possible calibration method for one TDC is next described. The method may be applied to all TDCs of the circuit.
  • the TDCs are representative paths of the critical paths of the circuit, i.e. they must always be longer than any critical path of the circuit and should (for best performance and power) be as close as possible to the critical paths, for the entire lifetime of the circuit. For this reason, the analysis must take into account the on-chip variability that may differentiate the delays of the TDCs with regard to the delays of the critical paths.
  • derating factors must be used to account for the potential variability that may affect timing in the opposite direction as it affects the critical paths. For example, the analysis can be done by applying launching path derating factors paths for the critical paths (as it is normally done) and capturing path derating factors for the TDCs, e.g. 1 .05 for launching paths and 0.95 for capturing paths.
  • Figure 1 1 illustrates the delay and margins calculated for the calibration of a TDC.
  • the delay of a TDC must be longer than the worst-case delay of the circuit plus some margin associated to on-chip variability. Additionally, an extra margin must be added to protect the critical paths from the dynamic regulation of the ring oscillator.
  • the plot illustrated at the bottom of Figure 1 1 depicts a piecewise representation of the different clock periods that can be obtained by different configurations of the ring oscillator.
  • the biggest delay step ( ⁇ ) in the clock period must be added to the margins of the TDC so that it can alert about a possible timing violation in the critical path when the clock period is reduced by one step.
  • the TDCs have to be calibrated so that the arrival of the edge falls in some region interval that can be measured by the edge detector. This can be achieved by analyzing the slack, with regard to the period P, of all inputs of the flip-flops of the edge detector for each possible configuration of the programmable delay. Those flip-flop inputs with positive slack represent delays shorter than the clock period (first region), whereas those flip-flop inputs with negative slack represent delays longer than the clock period (second region). The preferred configuration will be the one that makes the separation of these two regions fall in the middle of the edge detector. In the example of Fig.
  • the edge detector comprises nine flip flops
  • the positive slack includes the first four flip flops while the negative slack includes the remaining five flip flops.
  • the edge detector will capture the arrival of the edge and the location of the flip-flops associated to the change of value will be identified.
  • the arrival within the first region (positive slacks) will be an indication that the period is too short
  • the arrival within the second region (negative slacks) will be an indication that the period is long enough for timing correctness, as will be described more in detail with reference to Fig. 10 below. Since the circuit may be operating at different environmental conditions, the regions must be conservatively defined to cover all possible corners of operation.
  • Figure 12 illustrates graphically how the regions may be determined for one TDC. Every row represents the result of static timing analysis performed at every corner of interest (as chosen by the circuit designer based on the usual reliability and yield criteria). To be conservative, the regions may be defined statically in such a way that the information obtained from the TDC shall be safe for any operating condition of interest. For this reason, the largest first region 1200A must be considered for the dynamic analysis of the circuit behavior. In Fig. 12, the first regions are indicated by the hatched boxes and the second regions are indicated by the dark boxes.
  • a hysteresis region 1200B can be defined to stabilize the configuration of the adaptive clock.
  • This region can be defined by identifying a small set of flip-flops in the second region, next to the border of the largest first region 1200C. This small intermediate region will be the target region for the control circuit when trying to calibrate the ring oscillator and achieve the optimum performance.
  • the calibration of the programmable delays and the definition of the three regions must be done individually for each TDC, but it can be done before fabrication (fully statically), once after fabrication (to reduce the process-related margins) or periodically (to reduce the aging-related margins).
  • the control of the adaptive clocking system will dynamically make decisions about the calibration of the ring oscillator based on the information obtained from the TDCs while the circuit is operating.
  • a safe strategy for guaranteeing timing correctness is to ensure that none of the edges of the multiple TDCs distributed within the circuit may be captured in the first region 1200C. In case this happens, the ring oscillators must be recalibrated to increase the clock period and move the edges away from the first region 1200C. Alternatively, when all the edges are in the second region 1200A, the control might decide to decrease the clock period to move the edges towards the hysteresis region 1200B. Multiple methods may be devised to dynamically decide the best calibration of the ring oscillator based on the information obtained from the TDCs. Also, different margins may be applied to the timing analysis to account for the inaccuracy of the ring oscillator tracking the voltage drops or for the discretization of the possible frequency values generated by the different configurations of the ring oscillator.
  • the TDCs and the ring oscillator can also be dynamically calibrated at runtime, either at the initiation of the operation of the circuit or periodically.
  • the dynamic calibration can be done without stopping the main operation of the circuit. For example, this is possible by configuring the clock generator in a mode in which the circuit is clocked with the PLL while the TDCs are calibrated and clocked using the ring oscillator. Since the TDCs and the ring oscillator are not interacting with the circuit, their calibration will not interfere with the operation of the circuit.
  • Information about the different clock periods that can be generated by the ring oscillator can be obtained by exercising all configurations and measuring the frequency using, for example, a mechanism based on the comparison of the frequency with a reference clock may be used.
  • Information about the delay of the TDCs can be obtained by exercising all the configurations with a specific configuration of the ring oscillator and reading the values from the edge detector.
  • a software program could calibrate the TDCs, possibly adding some extra safety margins.
  • the calibration can be customized differently for each die according to the variability parameters.
  • the calibration can also be changed dynamically as the circuit devices degrade due to aging.
  • Figure 13 is a flow diagram of a method of calibrating an adaptive frequency clock source.
  • a clock signal for a logic circuit is set equal to a clock signal of a first clock source.
  • the first clock source may be configured to generate a first clock signal with a fixed frequency.
  • the first clock source may be a PLL. Therefore the logic circuit is running in synchronous mode.
  • the clock frequency may, therefore, account for the worst-case variability scenario and would, thus, be relatively slow, compared to what the logic circuit might tolerate as an average clock frequency.
  • information from one or more digital monitors monitoring delays in paths of the logic circuit is received. This information may provide variability indications from across the logic circuit.
  • a desired clock frequency in response to the received information may be calculated.
  • This desired frequency may be higher than the frequency of the first clock source and at the same time guarantee timing correctness by accounting for all present slow and fast variability factors in the logic circuit. Therefore, the frequency calibration would not be a "just-in-case” calibration based on worst-case timing scenarios but, rather, a "just-in-time” calibration that avoids timing violations based on delay information from digital monitors.
  • a clock frequency at a second clock source is set equal to the desired clock frequency.
  • the second clock may be an adaptive clocking source and may be configured to generate a second clock signal with a frequency equal to the calculated clock frequency.
  • step 1350 the clock signal for the logic circuit is set equal to the clock signal from the second clock source.
  • the calibration method described with reference to Fig. 13 may allow for the logic circuit to be initiated with a worst- case scenario and, during a first period of runtime, adapt its clock frequency based on the information received from the monitors.

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Abstract

La présente invention concerne des configurations d'horloge adaptative destinées à la surveillance de la variabilité statique et dynamique d'un circuit et à la génération d'un signal d'horloge qui s'adapte dynamiquement à la synchronisation des chemins critiques dans le circuit. Des dispositifs d'horloge donnés à titre d'exemple génèrent au moins un signal d'horloge au niveau d'une ou plusieurs sorties. Les dispositifs d'horloge donnés à titre d'exemple comprennent au moins une première source d'horloge présentant une fréquence d'horloge adaptative, au moins un multiplexeur présentant au moins une première entrée couplée à la sortie d'au moins la première source d'horloge et au moins une seconde entrée configurée pour être couplée à la sortie d'au moins la seconde source d'horloge présentant une fréquence d'horloge fixe. Un dispositif de commande est couplé à ladite première source d'horloge, audit multiplexeur et auxdits moniteurs numériques et est configuré pour générer le ou les signaux d'horloge par sélection entre au moins une première et une seconde valeur d'horloge à partir desdites première et seconde sources d'horloge, respectivement. La présente invention concerne également des procédés destinés à l'étalonnage desdits dispositifs d'horloge.
PCT/EP2014/058457 2014-04-25 2014-04-25 Configurations d'horloge adaptative et procédés d'étalonnage associé WO2015161890A1 (fr)

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US9413344B2 (en) * 2014-09-08 2016-08-09 Qualcomm Incorporated Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems
FR3050341A1 (fr) * 2016-04-18 2017-10-20 St Microelectronics Crolles 2 Sas Procede et dispositif de surveillance d'un chemin critique d'un circuit integre
WO2017222620A1 (fr) * 2016-06-24 2017-12-28 Qualcomm Incorporated Générateur d'horloge de suivi de tension d'alimentation dans des systèmes de distribution d'horloge adaptative
US9984732B2 (en) 2016-04-19 2018-05-29 Samsung Electronics Co., Ltd. Voltage monitor for generating delay codes
WO2019213654A1 (fr) * 2018-05-04 2019-11-07 Texas Instruments Incorporated Circuit de convertisseur temps-numérique
US10491222B2 (en) 2018-03-13 2019-11-26 Texas Instruments Incorporated Switch between input reference clocks of different frequencies in a phase locked loop (PLL) without phase impact
US10498344B2 (en) 2018-03-09 2019-12-03 Texas Instruments Incorporated Phase cancellation in a phase-locked loop
US10505555B2 (en) 2018-03-13 2019-12-10 Texas Instruments Incorporated Crystal oscillator offset trim in a phase-locked loop
US10505554B2 (en) 2018-05-14 2019-12-10 Texas Instruments Incorporated Digital phase-locked loop
US10516401B2 (en) 2018-03-09 2019-12-24 Texas Instruments Incorporated Wobble reduction in an integer mode digital phase locked loop
US10516402B2 (en) 2018-03-09 2019-12-24 Texas Instruments Incorporated Corrupted clock detection circuit for a phase-locked loop
US10686456B2 (en) 2018-03-09 2020-06-16 Texas Instruments Incorporated Cycle slip detection and correction in phase-locked loop
WO2020249922A1 (fr) * 2019-06-14 2020-12-17 Arm Limited Techniques de régulation de performance
CN113325918A (zh) * 2021-06-15 2021-08-31 展讯通信（上海）有限公司 时钟管理电路、芯片及电子设备
US11249530B1 (en) 2020-11-25 2022-02-15 Qualcomm Incorporated Adaptive voltage controller
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KR20240008469A (ko) * 2022-07-12 2024-01-19 (주)피델릭스 신호 전송 시간의 변화로 배선의 열화를 감시하는 열화 감시 회로 및 이를 포함하는 반도체 메모리 장치

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Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9413344B2 (en) * 2014-09-08 2016-08-09 Qualcomm Incorporated Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems
US10451670B2 (en) 2016-04-18 2019-10-22 Stmicroelectronics (Crolles 2) Sas Method and device for monitoring a critical path of an integrated circuit
FR3050341A1 (fr) * 2016-04-18 2017-10-20 St Microelectronics Crolles 2 Sas Procede et dispositif de surveillance d'un chemin critique d'un circuit integre
US9984732B2 (en) 2016-04-19 2018-05-29 Samsung Electronics Co., Ltd. Voltage monitor for generating delay codes
CN109314507A (zh) * 2016-06-24 2019-02-05 高通股份有限公司 自适应时钟分布系统中的供应电压跟踪时钟产生器
WO2017222620A1 (fr) * 2016-06-24 2017-12-28 Qualcomm Incorporated Générateur d'horloge de suivi de tension d'alimentation dans des systèmes de distribution d'horloge adaptative
US10686456B2 (en) 2018-03-09 2020-06-16 Texas Instruments Incorporated Cycle slip detection and correction in phase-locked loop
US10498344B2 (en) 2018-03-09 2019-12-03 Texas Instruments Incorporated Phase cancellation in a phase-locked loop
US10868550B2 (en) 2018-03-09 2020-12-15 Texas Instruments Incorporated Cycle slip detection and correction in phase-locked loop
US10727846B2 (en) 2018-03-09 2020-07-28 Texas Instruments Incorporated Phase cancellation in a phase-locked loop
US10516401B2 (en) 2018-03-09 2019-12-24 Texas Instruments Incorporated Wobble reduction in an integer mode digital phase locked loop
US10516402B2 (en) 2018-03-09 2019-12-24 Texas Instruments Incorporated Corrupted clock detection circuit for a phase-locked loop
US10491222B2 (en) 2018-03-13 2019-11-26 Texas Instruments Incorporated Switch between input reference clocks of different frequencies in a phase locked loop (PLL) without phase impact
US10505555B2 (en) 2018-03-13 2019-12-10 Texas Instruments Incorporated Crystal oscillator offset trim in a phase-locked loop
WO2019213654A1 (fr) * 2018-05-04 2019-11-07 Texas Instruments Incorporated Circuit de convertisseur temps-numérique
US10691074B2 (en) 2018-05-04 2020-06-23 Texas Instruments Incorporated Time-to-digital converter circuit
US10496041B2 (en) 2018-05-04 2019-12-03 Texas Instruments Incorporated Time-to-digital converter circuit
US10505554B2 (en) 2018-05-14 2019-12-10 Texas Instruments Incorporated Digital phase-locked loop
WO2020249922A1 (fr) * 2019-06-14 2020-12-17 Arm Limited Techniques de régulation de performance
US10886847B1 (en) 2019-06-14 2021-01-05 Arm Limited Performance regulation techniques
US11249530B1 (en) 2020-11-25 2022-02-15 Qualcomm Incorporated Adaptive voltage controller
CN113325918A (zh) * 2021-06-15 2021-08-31 展讯通信（上海）有限公司 时钟管理电路、芯片及电子设备
WO2024011410A1 (fr) * 2022-07-12 2024-01-18 Telefonaktiebolaget Lm Ericsson (Publ) Procédé et dispositif de réseau de synchronisation d'horloge de ptp
KR20240008469A (ko) * 2022-07-12 2024-01-19 (주)피델릭스 신호 전송 시간의 변화로 배선의 열화를 감시하는 열화 감시 회로 및 이를 포함하는 반도체 메모리 장치
KR102634456B1 (ko) 2022-07-12 2024-02-06 주식회사 피델릭스 신호 전송 시간의 변화로 배선의 열화를 감시하는 열화 감시 회로 및 이를 포함하는 반도체 메모리 장치

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