WO2015152373A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2015152373A1
WO2015152373A1 PCT/JP2015/060473 JP2015060473W WO2015152373A1 WO 2015152373 A1 WO2015152373 A1 WO 2015152373A1 JP 2015060473 W JP2015060473 W JP 2015060473W WO 2015152373 A1 WO2015152373 A1 WO 2015152373A1
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WO
WIPO (PCT)
Prior art keywords
sealing resin
electrode
terminal
semiconductor device
semiconductor element
Prior art date
Application number
PCT/JP2015/060473
Other languages
French (fr)
Japanese (ja)
Inventor
啓行 原田
畑中 康道
藤野 純司
武敏 鹿野
吉松 直樹
正行 眞舩
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2016512001A priority Critical patent/JP6045749B2/en
Publication of WO2015152373A1 publication Critical patent/WO2015152373A1/en

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    • HELECTRICITY
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Definitions

  • the present invention relates to a semiconductor device, and more particularly to a technique for improving the reliability of bonding wiring used in a semiconductor device.
  • the sealing resin and the case terminal block (and the electrode terminal) are peeled off due to the stress caused by the curing shrinkage of the resin and the stress caused by the difference in the coefficient of linear expansion between the members, the peeling extends to the portion of the electrode terminal. If vibration or heat cycle is applied to the semiconductor element in this state, the wiring may be broken. Thus, peeling of the sealing resin significantly reduces the reliability of the semiconductor device.
  • the present invention has been made in view of the above problems. By suppressing the peeling of the resin that occurs between the sealing resin and the electrode terminal, the disconnection of the wiring due to the expansion and contraction of the sealing resin that occurs in the heat cycle is prevented, and a highly reliable semiconductor device is obtained. With the goal.
  • the semiconductor device includes an insulating substrate having a first electrode pattern formed on the first main surface and a second electrode pattern formed on the second main surface, and a first of the insulating substrate.
  • a base plate bonded to the electrode pattern; a semiconductor element having a front electrode and a back electrode; a semiconductor element having the back electrode bonded to the second electrode pattern of the insulating substrate; and a terminal portion having a recess.
  • a resin case member an electrode terminal fixed to the case member and having a wiring connection portion exposed from the bottom surface of the depression, a bonding wiring for connecting the wiring connection portion of the electrode terminal and the front side electrode of the semiconductor element,
  • the inside of the case member is filled with an insulating substrate, a semiconductor element, and a sealing resin member that seals the bonding wiring, and a recess formed in the terminal portion is provided with an entrance for the bonding wiring, enter Is one that is oriented and open system inside.
  • the semiconductor device of the present invention it is possible to suppress the peeling of the sealing resin member from the electrode terminal, to extend the connection life of the bonding wiring, and to obtain a highly reliable semiconductor device.
  • FIG. 4A is a front view showing a first structure of the terminal portion according to Embodiment 1 of the present invention.
  • FIG. 4B is a side view showing the first structure of the terminal portion according to Embodiment 1 of the present invention.
  • the semiconductor device of this embodiment is a semiconductor power module widely used for home appliances, industrial use, automobile use, train use, and the like.
  • FIG. 1 is a sectional view showing a basic structure of a semiconductor device according to the first embodiment of the present invention.
  • the semiconductor device 100 includes a sealing resin member 1, a semiconductor element 2a, a semiconductor element 2b, an electrode terminal 4, a bonding wiring 6, a case member 7, a semiconductor element substrate 11, a bonding material 12, a base plate 13, an adhesive 14, and the like.
  • the semiconductor element 2a and the semiconductor element 2b are fixed to the semiconductor element substrate 11 with a bonding material 12 such as solder.
  • the base plate 13 is fixed to the semiconductor element substrate 11 with a bonding material 12 such as solder.
  • the case member 7 is fixed by a base plate 13 and a silicone adhesive 14.
  • the base plate 13 serves as a bottom plate, and the base plate 13 and the case member 7 form a casing.
  • the case member 7 is required not to be thermally deformed in the operating temperature range and to maintain insulation. For this reason, a resin having a high softening point such as PPS (Poly Phenylene Sulfide) resin is used for the case member 7.
  • PPS Poly Phenylene Sulfide
  • the case member 7 has a terminal portion 3 to which the electrode terminal 4 is fixed.
  • the semiconductor element 2 a and the semiconductor element 2 b are connected to the electrode terminal 4 of the terminal portion 3 by the bonding wiring 6.
  • the electrode terminal 4 is insert-molded in the case member 7 and connected to an external device.
  • the electrode terminal 4 is usually made of copper.
  • the epoxy resin is used as the sealing resin member 1, it is not limited to this, and any resin having a desired elastic modulus and heat resistance can be suitably used.
  • a silicone resin, a urethane resin, a polyimide resin, a polyamide resin, a polyamideimide resin, an acrylic resin, or the like may be used for the sealing resin member 1 as long as the material has both insulating properties and adhesiveness.
  • FIG. 2 is a top view showing the structure of the semiconductor device 100 according to the first embodiment of the present invention.
  • the semiconductor element 2a is a power semiconductor element represented by a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) that controls a large current.
  • the semiconductor element 2b is a reflux diode provided in parallel with the power semiconductor element.
  • Bonding wiring 6 for electrical connection with the electrode terminal 4 is connected to the semiconductor elements 2a and 2b. One end of the bonding wiring 6 is connected to the terminal portion 3.
  • the number is not limited to this, and a necessary number can be provided depending on the current density of the semiconductor element.
  • the bonding wiring 6 can be bonded by fusion bonding or ultrasonic bonding to a metal piece such as copper or tin, but is not particularly limited as long as it is a method capable of supplying necessary current and voltage to the semiconductor element.
  • the electrode terminal 4 may be connected to the second electrode pattern 9 via the bonding wiring 6.
  • the semiconductor element 2a and the semiconductor element 2b in addition to those formed of silicon (Si), those formed of a wide band gap semiconductor having a band gap larger than that of silicon can be suitably used.
  • the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride-based material, and diamond.
  • FIG. 3 is a side view showing a state in which the semiconductor element 2a and the semiconductor element 2b are joined to the semiconductor element substrate 11.
  • FIG. 1 the front side electrode 2o and the back side electrode 2u are formed in the surface and the back surface, respectively.
  • a front side electrode 2o and a back side electrode 2u are formed on the front surface and the back surface, respectively.
  • the semiconductor element substrate 11 includes a first electrode pattern 8, a second electrode pattern 9, and an insulating substrate 10.
  • the back electrode 2u of the semiconductor element 2a is bonded to the second electrode pattern 9 of the semiconductor element substrate 11 with a bonding material 12 such as solder (see FIG. 1).
  • the back side electrode 2u of the semiconductor element 2b is bonded to the second electrode pattern 9 of the semiconductor element substrate 11 with a bonding material 12 such as solder (see FIG. 1).
  • a base plate 13 is bonded to the first electrode pattern 8 of the semiconductor element substrate 11 with a bonding material 12 such as solder (see FIG. 1).
  • a first electrode pattern 8 is formed on the first main surface 10a on the lower side of the insulating substrate 10, leaving a first blank portion 11a on the outer periphery.
  • a second electrode pattern 9 is formed on the second main surface 10b on the upper side of the insulating substrate 10 leaving a second blank portion 11b on the outer periphery.
  • the semiconductor element substrate 11 refers to a substrate in which a first electrode pattern 8 and a second electrode pattern 9 are provided on an insulating substrate 10 made of ceramic (Al2O3, SiO2, AlN, BN, Si3N4, etc.). Copper, aluminum or the like is used for the first electrode pattern 8 and the second electrode pattern 9.
  • the insulating substrate 10 is required to have heat dissipation and insulating properties, and is not limited to ceramic, but is insulating such as a cured resin in which ceramic powder is dispersed or a cured resin in which a ceramic plate is embedded. A substrate may be used.
  • the first electrode pattern 8 is formed on the back surface of the insulating substrate 10 (or the semiconductor element substrate 11).
  • the second electrode pattern 9 is formed on the surface of the insulating substrate 10 (or the semiconductor element substrate 11).
  • the ceramic powder used for the insulating substrate 10 is Al2O3, SiO2, AlN, BN, Si3N4 or the like, but is not limited thereto, and diamond, SiC, B2O3, or the like may be used. Further, resin powder such as silicone resin and acrylic resin may be used. The powder shape is often spherical, but is not limited thereto, and a crushed shape, a granular shape, a flake shape, an aggregate shape, or the like may be used. The filling amount of the powder is not limited as long as the necessary heat dissipation and insulation are obtained. As the resin used for the insulating substrate 10, an epoxy resin is usually used. The resin used for the insulating substrate 10 is not limited to this, and a polyimide resin, a silicone resin, an acrylic resin, or the like may be used as long as the material has both insulating properties and adhesiveness.
  • the electrode terminal 4, the first electrode pattern 8, the second electrode pattern 9, and the base plate 13 are usually made of copper, but are not limited thereto, and are not particularly limited as long as they have necessary heat dissipation characteristics.
  • aluminum or iron may be used, or a composite material of these may be used.
  • a composite material such as copper / invar / copper may be used, and an alloy such as SiCAl or CuMo may be used.
  • the surface is usually plated with nickel.
  • the present invention is not limited to this, and may be plated with gold or tin as long as it has a structure capable of supplying necessary current and voltage to the semiconductor element.
  • At least a part of the electrode terminal 4, the first electrode pattern 8, and the second electrode pattern 9 may be provided with minute irregularities on the surface in order to improve the adhesion to the resin, and an adhesion improver such as a primer treatment. May be provided.
  • an adhesion improver such as a primer treatment.
  • a silane coupling agent, a polyimide resin, an epoxy resin, or the like is used, but it is not particularly limited as long as it improves the adhesion between the electrode member of the semiconductor element substrate and the sealing resin.
  • FIG. 4A is a front view showing the terminal portion 3 of the case member 7, and FIG. 4B is a side view showing the terminal portion 3 of the case member 7.
  • the terminal portion 3 is formed of the same material as the case member 7 and is integrated with the case member 7.
  • the recess 3a of the terminal portion 3 has an entrance 3b, a back surface 3o, a top surface 3t, a bottom surface 31, a side surface 3p, and a side surface 3q.
  • the top surface 3t of the recess 3a or the upper surface 3u of the terminal portion 3 is open.
  • the wiring connection portion 4a of the electrode terminal 4 is exposed from the bottom surface 3l of the recess 3a.
  • the junction point (wiring connection portion 4a) of the electrode terminal 4 is arranged at a position lower than the top surface 3t of the recess 3a (or the upper surface 3u of the terminal portion 3).
  • the wiring connection portion 4a has a structure surrounded by the back surface 3o, the side surface 3p, and the side surface 3q.
  • the bonding wiring 6 connects the wiring connection portion 4a of the electrode terminal 4 and the front side electrode 2o of the semiconductor element (2a, 2b).
  • the recess 3a has the same width from the entrance 3b to the back surface 3o.
  • the entrance 3 b of the bonding wiring 6 is provided in the recess 3 a of the terminal portion 3.
  • FIG. 5 is a perspective view of the terminal portion.
  • An entrance 3 b provided in the recess 3 a of the terminal portion 3 faces the inside of the semiconductor device 100.
  • the recess 3a is open at the entrance 3b and closed at the back.
  • the bonding wiring 6 is bonded to the upper surface (or exposed surface) of the wiring connection portion 4a by a bonding apparatus. When wire bonding is performed, the bonding wiring 6 enters the recess 3a from the entrance 3b.
  • the bonding wiring 6 uses a wire body having a circular cross section made of aluminum or gold, but is not limited to this, and for example, a copper plate having a rectangular cross section may be used.
  • the recess 3a of the terminal portion 3 is not particularly limited as long as it has a space sufficient for bonding the bonding wiring 6, but has a size capable of cutting the bonding wiring 6 using a wire cutting tool attached to the bonding apparatus. It is preferable.
  • the wiring connection portion 4a of the electrode terminal 4 is sealed with an epoxy resin or the like after the bonding wiring 6 is joined.
  • the first bonding of the bonding wiring 6 is performed at the wiring connection portion 4 a of the electrode terminal 4.
  • the bonding wiring 6 can be connected.
  • the semiconductor element 2 may be damaged.
  • a third bond is further performed from the semiconductor element 2 to the second electrode pattern 9.
  • the electrode terminal 4 is insert-molded in the case member 7, but can be fixed to the recess 3a with an adhesive or the like.
  • the recess 3 a may have a tapered structure (a shape in which a cross-sectional area decreases toward the semiconductor element 2). That is, the width may become wider as it goes from the entrance of the recess 3a to the inner surface. Since the terminal portion 3 made of the case member 7 has a taper shape, the sealing resin member 1 in which thermal stress is generated at the time of heat cycle or power cycle is formed on the wiring connection portion 4a surrounded by the terminal portion 3 on three sides. Thermal stress applied to the interface with the upper part is reduced. Since peeling between the electrode terminal 4 and the sealing resin member 1 is suppressed, a highly reliable semiconductor device 100 can be obtained.
  • the terminal portion according to this embodiment has an opening structure in which a depression is surrounded on three sides.
  • the case member of the opening has an acute-angle shape, but is not limited to the acute-angle shape, and is preferably a fillet shape such as a skirt, that is, a round shape. Since the opening structure has a rounded shape, even when the sealing resin member 1 is peeled off, it is possible to suppress the opening from being a starting point of cracks in the sealing resin member 1, and a more reliable semiconductor. Device 100 can be obtained.
  • a shear stress is generated at the interface between the terminal portion 3 and the sealing resin member 1. Since the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 depends on the linear continuous distance of the contact interface between the upper surface 3 u and the sealing resin member 1, this contact interface is linearly continuous. By reducing the distance, the shear stress can be reduced.
  • the wiring connection portion 4 a of the electrode terminal 4 is disposed at a position lower than the upper surface 3 u of the terminal portion 3 integrated with the case member 7. Since the wiring connection portion 4a and the terminal portion 3 do not exist on the same plane, the linear continuous distance between the upper surface 3u and the sealing resin member 1 can be cut off. Thereby, the shear stress due to the curing shrinkage of the sealing resin generated at the contact interface between the terminal portion 3 and the sealing resin member 1 is reduced, and the peeling between the wiring connection portion 4a and the sealing resin member 1 can be suppressed. it can.
  • the terminal part 3 made of the same material as the case member 7 has a hollow structure (recess 3a).
  • the bonding area between the sealing resin member 1 and the terminal portion 3 is increased in the vicinity of the bonding wiring bonded to the wiring connection portion 4 a of the electrode terminal 4.
  • the connection life of the bonding wiring 6 can be extended by extending the peeling extension distance to the terminal part 3, and a highly reliable semiconductor device can be obtained. it can.
  • the three sides surrounding the depression 3a of the terminal portion 3 may be subjected to a treatment for improving the adhesion with the sealing resin member 1 such as surface roughening, coating, and coupling.
  • the step (height of the terminal portion 3) from the wiring connection portion 4a of the electrode terminal 4 to the upper surface 3u of the terminal portion 3 may be 1 mm or more.
  • the level difference of the terminal portion 3 is 1 mm or less, the adhesion area between the sealing resin member 1 and the terminal portion 3 is not sufficient, so that the peeling suppression effect is not sufficient.
  • the wiring connection portion 4a of the electrode terminal 4 to which the bonding wiring is bonded is lower than the upper surface 3u of the terminal portion 3 made of the same material as the case member 7. Buried in position.
  • the bonding wiring 6 has a structure in which three sides are surrounded by a recess 3 a of the terminal portion 3 made of the same material as that of the case member 7, and shear stress generated by curing shrinkage of the sealing resin member 1 is reduced.
  • the bonding wiring 6 is electrically connected from the electrode terminal 4 to the semiconductor element 2 and the semiconductor element substrate 11.
  • the load on the bonding portion of the bonding wiring is increased due to the expansion, contraction, and vibration of the sealing resin member 1 due to the heat cycle. It ’s all over.
  • the disconnection of the bonding wiring 6 can be suppressed and the highly reliable semiconductor device 100 can be obtained.
  • the present invention can provide a remarkable effect when applied to a semiconductor element operating at 150 ° C. or higher, not only in the first embodiment but also in other embodiments.
  • FIG. 7 is a side view showing a terminal portion according to Embodiment 2 of the present invention.
  • FIG. 8 is a perspective view showing a terminal portion according to Embodiment 2 of the present invention.
  • the wiring connection part 4a of the electrode terminal 4 has a structure where four sides were surrounded by the case member 7.
  • FIG. 1 For the sealing resin member 1, in order to avoid peeling from the insulating substrate 10 (or the semiconductor element substrate 11), a resin that matches the linear expansion coefficient and elastic modulus of these members is selected. The adhesiveness with the case member 7 is often lowered, and the bonding wiring 6 is disconnected as the sealing resin member 1 is peeled off.
  • the recess 3 a is filled with a resin material having high adhesive strength with the terminal portion 3 and the case member 7.
  • the adhesiveness with the case member 7 is high on the wiring connection portion 4 a having the structure surrounded on the four sides by the case member 7, and the linear expansion coefficient is close to the linear expansion coefficient of the case member 7.
  • the sealing resin member 15 (second sealing resin member) is sealed.
  • the sealing resin member 1 ensures adhesion between the semiconductor element 2 and the semiconductor element substrate 11 and the bonding wiring 6.
  • the sealing resin member 15 covers the wiring connection portion 4 a of the electrode terminal 4 and ensures adhesion with the case member 7. As a result, the semiconductor device 100 with higher reliability can be obtained.
  • the epoxy resin is used as the sealing resin member 15, it is not limited thereto, and any resin having a desired linear expansion coefficient and elastic modulus can be used.
  • a silicone resin, a urethane resin, a polyimide resin, a polyamide resin, a polyamideimide resin, an acrylic resin, or the like may be used as long as the material has both insulating properties and adhesiveness.
  • the recess 3a of the terminal portion 3 is not particularly limited as long as it has a space sufficient for bonding the bonding wiring 6, but has a size capable of cutting the bonding wiring 6 using a wire cutting tool attached to the bonding apparatus. It is preferable.
  • the recess 3 a of the terminal portion 3 does not have a size capable of cutting the bonding wiring 6 with a wire cutting tool, the first bonding of the bonding wiring 6 is performed at the wiring connection portion 4 a of the electrode terminal 4.
  • the bonding wiring 6 can be connected.
  • the semiconductor element 2 may be damaged.
  • second bonding may be performed on the semiconductor element 2. Thereafter, third bonding is further performed from the semiconductor element 2 to the second electrode pattern 9, and the bonding wiring is cut by the second electrode pattern 9, whereby the highly reliable semiconductor device 100 can be obtained.
  • the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 depends on the linear continuous distance of the contact interface between the upper surface 3 u and the sealing resin member 1. By reducing the linear continuous distance of the contact interface, the shear stress is reduced.
  • the wiring connection portion 4a is arranged at a position lower than the upper surface 3u of the terminal portion 3 constituted by the case member 7, and the wiring connection portion 4a of the electrode terminal 4 is in the recess 3a. Buried.
  • the linear continuous distance between the upper surface 3u and the sealing resin member 1 can be cut off. Thereby, the shear stress due to the curing shrinkage of the sealing resin generated at the contact interface between the terminal portion 3 and the sealing resin member 1 is reduced, and the peeling between the wiring connection portion 4a and the sealing resin member 1 can be suppressed. it can.
  • the adhesion area between the sealing resin member 1 and the case member 7 in the vicinity of the wiring connection portion 4a is increased.
  • peeling of the sealing resin member 1 is suppressed, and the extension distance of the electrode terminal 4 to the wiring connection portion 4a can be extended.
  • the terminal portion 3 made of the case member 7 having a low adhesive strength with the sealing resin member 1 is peeled off from the sealing resin member 1, the connection life of the bonding wiring 6 is extended, and a highly reliable semiconductor device 100 is obtained. be able to.
  • the four sides surrounded by the case member 7 may be subjected to a treatment for improving adhesiveness with the sealing resin member 1 such as surface roughening, coating, and coupling.
  • the wiring connection portion 4a to which the bonding wiring is bonded is disposed at a lower position than the upper surface 3u of the terminal portion 3 integrated with the case member 7. Yes.
  • the wiring connection part 4 a of the electrode terminal 4 has a structure in which four sides are surrounded by a recess 3 a of the terminal part 3 made of the case member 7. Thereby, the shear stress generated by the curing shrinkage of the sealing resin member 1 is reduced.
  • the adhesion area between the terminal part 3 and the sealing resin member 1 in the vicinity of the wiring connection part 4a of the electrode terminal 4 is increased, so that the adhesion between the wiring connection part 4a and the terminal part 3 and the sealing resin member 1 is increased. Will improve.
  • the sealing resin has a structure in which the four sides are surrounded by the terminal portion 3, thereby partially sealing the second sealing resin having high adhesiveness with the case member 7.
  • adhesion to the case member 7 can be improved.
  • Electrical connection from the electrode terminal 4 to the semiconductor element 2 and the semiconductor element substrate 11 is performed by the bonding wiring 6.
  • the bonding wiring 6 is subjected to disconnection due to an increase in load on the bonding part due to expansion, contraction, and vibration of the sealing resin member 1 accompanying the heat cycle. .
  • the disconnection of the bonding wiring 6 can be suppressed, and the highly reliable semiconductor device 100 can be obtained.
  • Embodiment 3 the structure of the terminal portion integrated with the case member 7 is different from that of the first embodiment of the present invention.
  • the first embodiment has a structure in which the wiring connection portion 4 a of the electrode terminal 4 is surrounded by the terminal portion 3 including the case member 7 on three sides.
  • the wiring connection portion 4 a of the electrode terminal 4 protrudes from the terminal portion 3 formed of the case member 7.
  • the terminal portion 3 is formed with a step 3d protruding from the periphery.
  • the wiring connection portion 4 a of the electrode terminal 4 to which the bonding wiring 6 is joined is disposed at a position higher than the upper surface 3 u of the terminal portion 3.
  • the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 will be described. Since the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 depends on the linear continuous distance of the contact interface between the upper surface 3 u and the sealing resin member 1, this contact interface is linearly continuous. By reducing the distance, the shear stress can be reduced.
  • the wiring connection portion 4a of the electrode terminal 4 is disposed at a position higher than the upper surface 3u of the terminal portion 3 constituted by the case member 7, and the wiring connection portion of the electrode terminal 4 is provided. 4 a protrudes from the step 3 d formed in the terminal portion 3.
  • the wiring connection portion 4a is arranged so as to avoid the same plane as the terminal portion 3, the interface distance between the electrode terminal 4 and the sealing resin member 1 can be separated, and the electrode terminal 4 and the sealing resin member 1 The shear stress due to the curing shrinkage of the sealing resin member 1 generated at the interface is reduced. By suppressing the peeling between the electrode terminal 4 and the sealing resin member 1, the disconnection of the bonding wiring 6 can be suppressed, and the highly reliable semiconductor device 100 can be obtained.
  • the wiring connection portion 4a to which the bonding wiring 6 is bonded is disposed at a position higher than the upper surface 3u of the terminal portion 3 constituted by the case member 7. Yes.
  • the shear stress generated by the curing shrinkage of the sealing resin member 1 is reduced.
  • a protruding step 3d is formed on the terminal portion 3, and the bonding area between the terminal portion 3 made of the case member 7 and the sealing resin member 1 is increased, whereby the terminal portion 3 made of the electrode terminal 4 and the case member 7 is formed.
  • the sealing resin member 1 can be improved in adhesion.
  • the electrical connection from the electrode terminal 4 to the semiconductor element 2 and the semiconductor element substrate 11 is performed by bonding wiring.
  • FIG. 11 shows the structure of the semiconductor device according to the fourth embodiment of the present invention.
  • the electrode terminal 4 and the wiring connection portion 4 a are sealed to cover the semiconductor element 2 a, the semiconductor element 2 b, the electrode terminal 4, the bonding wiring 6, and the semiconductor element substrate 11 included in the case member 7. It is sealed by the resin member 1.
  • the sealing resin member 1 includes a semiconductor element 2 a, a semiconductor element 2 b, an electrode terminal 4, a bonding wiring 6, a first sealing resin member 1 a that covers the semiconductor element substrate 11, and a case member 7.
  • the electrode portion 4 is surrounded by three sides of the terminal portion 3 and the second sealing resin member 1b covering the wiring connection portion 4a.
  • the second sealing resin member 1b one having a lower elastic modulus than that of the first sealing resin member 1a is used.
  • the stress generated when the second sealing resin member covers the electrode terminal 4 and the wiring connection portion 4a surrounded on the three sides by the terminal portion 3 formed of the case member 7 of the present embodiment will be described.
  • the various members constituting the semiconductor device are warped due to the difference in linear expansion coefficient, and shear stress is generated at the interface between the wiring connection portion 4a and the sealing resin.
  • the linear expansion coefficient of the first sealing resin member is made as low as possible, and the semiconductor element substrate 11 and the semiconductor element It is effective to approach a linear expansion coefficient of 2.
  • the electrode terminal 4 made of a metal member has a linear expansion coefficient away from the case member 7 and the sealing resin member made of a resin material, so that the interface between the terminal portion 3 and the sealing resin member 1 As a result, the shearing stress generated in the electrode increases and the electrode terminal 4 and the sealing resin member 1 are peeled off, and the bonding wiring 6 is disconnected.
  • the electrode terminal 4 and the wiring surrounded by the terminal portion 3 including the case member 7 on the three sides Since the shear stress generated at the interface between the electrode terminal 4 and the sealing resin member depends on the linear expansion coefficient and the elastic modulus of the sealing resin, the electrode terminal 4 and the wiring surrounded by the terminal portion 3 including the case member 7 on the three sides.
  • the elastic modulus of the second sealing resin member covering the connection portion 4a By reducing the elastic modulus of the second sealing resin member covering the connection portion 4a, the shear stress generated at the interface between the wiring connection portion 4a and the sealing resin is reduced, and the connection between the wiring connection portion 4a and the sealing resin is reduced. Peeling can be suppressed. Further, when the adhesive force between the second sealing resin member and the first sealing resin member is low, even if a large warp occurs in the semiconductor device, the first sealing resin is exceeded when a certain stress is exceeded.
  • the adhesive strength between the second sealing resin member and the first sealing resin member that seals the insulating substrate is set to 5 Mpa or less.
  • a silicone-based release material may be applied to the surface on which the second sealing resin member is exposed, and the entire surface may be sealed with the first sealing resin member.
  • the semiconductor device (module) for the evaluation test was manufactured using various materials and sealing resin.
  • a semiconductor element 2 and a semiconductor element substrate (made of ceramics) 11 were attached to a copper metal plate via a solder bonding material.
  • a case member produced by insert molding was attached to this metal plate with an adhesive.
  • the terminal portion was formed on the upper side of the case member.
  • This work in process was sealed with a liquid sealing resin made of an epoxy resin having a linear expansion coefficient of 20, and a sample for evaluation was produced by heating at 150 ° C. for 2 hours. Various heat cycle tests were performed on the sample for evaluation.
  • a plurality of evaluation samples corresponding to Examples 1 to 4 and the comparative example were prototyped.
  • the height difference between the wiring connection portion 4a and the terminal portion 3 is set to 3 mm.
  • the prototype semiconductor device was put in a thermostat capable of temperature control and subjected to a heat cycle test. The temperature of the thermostat was adjusted, and each of a plurality of evaluation samples was evaluated.
  • the heat cycle test was carried out under two conditions by changing the temperature of the thermostat at high temperature.
  • the first condition of the heat cycle test is that the evaluation sample is held at ⁇ 40 ° C. for 30 minutes and then held at 125 ° C. for 30 minutes as one cycle, and this cycle is repeated 500 times.
  • the second condition of the heat cycle test is that the evaluation sample is held at ⁇ 40 for 30 minutes and then held at 150 ° C. for 30 minutes as one cycle, and this cycle is repeated 500 times.
  • FIG. 14 shows the results of a heat cycle test performed on the evaluation samples corresponding to Embodiments 1 to 4 and the comparative example. In various evaluations, three semiconductor devices were evaluated. In the figure, in the continuity test conducted after 500 cycles of the heat cycle test, the items that passed all three units are indicated as ⁇ , the items that passed one or two units are indicated as ⁇ , and the items that did not pass are indicated as ⁇ . It is described.
  • the evaluation result of the evaluation sample corresponding to the comparative example will be described.
  • a heat cycle test was performed using a semiconductor device having an electrode terminal structure in which there is no difference in height between the wiring connection portion 4 a and the terminal portion 3.
  • conduction failure occurred after 50 cycles.
  • conduction failure occurred after 100 cycles. That is, in the evaluation sample corresponding to the comparative example, the semiconductor device stopped operating under the first condition and the second condition.
  • the evaluation result of the evaluation sample corresponding to the first embodiment will be described.
  • the heat cycle test was performed with a semiconductor device having an electrode terminal structure in which the wiring connection portion 4a of the electrode terminal 4 is lower than the terminal portion.
  • the test evaluation under the first condition ⁇ 40 ° C. to 125 ° C.
  • the test evaluation under the second condition ⁇ 40 ° C. to 150 ° C.
  • the evaluation result of the evaluation sample corresponding to the second embodiment will be described.
  • the semiconductor device in which the wiring connection part 4a of the electrode terminal 4 has an electrode terminal structure lower than the terminal part, and a sealing resin different from the resin for sealing the semiconductor element substrate is partially sealed on the electrode terminal The heat cycle test was carried out. Even in the test evaluation under the first condition ( ⁇ 40 ° C. to 125 ° C.), it was found that no conduction failure occurred after 500 cycles and the semiconductor device operated normally. Also in the test evaluation under the second condition ( ⁇ 40 ° C. to 150 ° C.), it was found that no conduction failure occurred after 500 cycles and the semiconductor device operated normally.
  • the evaluation result of the evaluation sample corresponding to the fourth embodiment will be described.
  • a semiconductor device having an electrode terminal structure in which the wiring connection portion 4a of the electrode terminal 4 is lower than the terminal portion is used.
  • a sealing resin having a lower elastic modulus than that of the first sealing resin member for sealing the semiconductor element substrate is used for the second sealing resin member.
  • the second sealing resin whose elastic modulus was lowered by knitting a rubber material was partially sealed on the electrode terminal and semi-cured at 100 ° C./1 hr. Thereafter, a silicone release material was applied to the surface where the second sealing resin was exposed, and the entire surface was sealed with the first sealing resin.
  • a heat cycle test was conducted on the semiconductor device created under the above conditions.
  • the power semiconductor element When SiC is used for the semiconductor element, the power semiconductor element is operated at a higher temperature than that of Si in order to take advantage of its characteristics. In a power module equipped with a SiC device, higher reliability is required as a semiconductor element. Therefore, the merit of the present invention for realizing a highly reliable power module becomes more effective.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The purpose of the present invention is to obtain a highly reliable semiconductor device in which a bonding wire is prevented from breaking. A semiconductor device is provided with: an insulating substrate having a first principal surface on which a first electrode pattern is formed, and a second principal surface on which a second electrode pattern is formed; a base plate joined to the first electrode pattern of the insulating substrate; a semiconductor element having a front-side electrode and a back-side electrode, the back-side electrode being joined to the second electrode pattern of the insulating substrate; a resinous case member having a terminal portion in which a recess is formed; an electrode terminal secured to the case member and having a wire connecting portion exposed from the bottom surface of the recess; a bonding wire connecting the wire connecting portion of the electrode terminal and the front-side electrode of the semiconductor element; and a sealing resin member filled into the case member to seal the insulating substrate, the semiconductor element, and the bonding wire. In the recess formed in the terminal portion, an inlet for the bonding wire is provided, and the inlet faces the inside of the device and is opened.

Description

半導体装置Semiconductor device
 この発明は、半導体装置に関し、特に、半導体装置に使用されているボンディング配線の信頼性を向上させる技術に関するものである。 The present invention relates to a semiconductor device, and more particularly to a technique for improving the reliability of bonding wiring used in a semiconductor device.
 産業機器、電機鉄道、自動車などの発達に伴い、これらに使用される半導体素子の使用温度が高くなっている。高温でも安定して動作する半導体素子の開発は近年精力的に行われており、半導体素子における小型化、高耐圧化および高電流密度化が進展している。特に、SiC、GaNなどのワイドバンドギャップ半導体は、Si半導体よりもバンドギャップが大きいため、半導体装置における高耐圧化、小型化、高電流密度化、高動作温度化などに貢献すると期待されている。このような特徴を持つ半導体素子を装置化するためには、封止樹脂の剥離、配線の劣化、接合材のクラック発生などを抑え、半導体素子が150℃以上の高温で動作する場合にも、半導体装置の安定な動作を確保する必要がある(例えば特許文献1~4)。 With the development of industrial equipment, electric railways, automobiles, etc., the operating temperature of semiconductor elements used for these has increased. In recent years, development of semiconductor elements that stably operate even at high temperatures has been energetically performed, and miniaturization, high breakdown voltage, and high current density have been progressing in semiconductor elements. In particular, wide bandgap semiconductors such as SiC and GaN have a larger bandgap than Si semiconductors, so they are expected to contribute to higher breakdown voltage, smaller size, higher current density, higher operating temperature, etc. in semiconductor devices. . In order to deviceize a semiconductor element having such characteristics, peeling of the sealing resin, deterioration of the wiring, cracking of the bonding material is suppressed, and even when the semiconductor element operates at a high temperature of 150 ° C. or higher, It is necessary to ensure a stable operation of the semiconductor device (for example, Patent Documents 1 to 4).
 半導体装置において半導体素子を樹脂で封止する方法として、ケース端子台および電極端子(電極端子)を高弾性なエポキシ樹脂で部分的に封止し、配線の信頼性を向上させる提案がなされている。エポキシ樹脂で封止された電極端子を含む回路面は全面がさらにゲル化物であるシリコーン樹脂で封止される(例えば特許文献1)。また、アルミワイヤの線径と封止するエポキシ樹脂の平均線膨張係数を調整することにより、半導体素子に接合されたアルミワイヤの接続寿命を向上させる提案もなされている(例えば特許文献2)。 As a method of sealing a semiconductor element with a resin in a semiconductor device, a case has been proposed in which a case terminal block and an electrode terminal (electrode terminal) are partially sealed with a highly elastic epoxy resin to improve wiring reliability. . The entire circuit surface including the electrode terminals sealed with the epoxy resin is further sealed with a silicone resin that is a gelled material (for example, Patent Document 1). There has also been a proposal for improving the connection life of an aluminum wire joined to a semiconductor element by adjusting the wire diameter of the aluminum wire and the average linear expansion coefficient of the epoxy resin to be sealed (for example, Patent Document 2).
特開平10-50897号公報Japanese Patent Laid-Open No. 10-50897 特開2008-270455号公報JP 2008-270455 A 特開2011-14739号公報JP 2011-14739 A 特開2003-142635号公報Japanese Patent Laid-Open No. 2003-142635
 封止樹脂とケース端子台(および電極端子)が、樹脂の硬化収縮に伴う応力や部材間の線膨張率の差に起因する応力により剥離すると、電極端子の部位にまで剥離が伸展する。この状態で半導体素子に振動やヒートサイクルが加わると、配線に断線が生じることが懸念される。このように、封止樹脂の剥離は半導体装置の信頼性を著しく低下させる。 When the sealing resin and the case terminal block (and the electrode terminal) are peeled off due to the stress caused by the curing shrinkage of the resin and the stress caused by the difference in the coefficient of linear expansion between the members, the peeling extends to the portion of the electrode terminal. If vibration or heat cycle is applied to the semiconductor element in this state, the wiring may be broken. Thus, peeling of the sealing resin significantly reduces the reliability of the semiconductor device.
 本発明は上記のような課題を鑑みてなされたものである。封止樹脂と電極端子との間に発生する樹脂の剥離を抑制することで、ヒートサイクルで生じる封止樹脂の膨張と収縮に伴う配線の断線を阻止し、信頼性の高い半導体装置を得ることを目的とする。 The present invention has been made in view of the above problems. By suppressing the peeling of the resin that occurs between the sealing resin and the electrode terminal, the disconnection of the wiring due to the expansion and contraction of the sealing resin that occurs in the heat cycle is prevented, and a highly reliable semiconductor device is obtained. With the goal.
 本発明に係る半導体装置は、第一主面には第一電極パターンが形成されており、第二主面には第二電極パターンが形成されている絶縁性基板と、絶縁性基板の第一電極パターンに接合されているベース板と、表側電極と裏側電極を有し、絶縁性基板の第二電極パターンに裏側電極が接合されている半導体素子と、窪みが形成されている端子部を有する樹脂製のケース部材と、ケース部材に固定されていて、配線接続部が窪みの底面から露呈している電極端子と、電極端子の配線接続部と半導体素子の表側電極を接続するボンディング配線と、ケース部材の内側に充填され、絶縁性基板と半導体素子とボンディング配線を封止する封止樹脂部材と、を備え、端子部に形成されている窪みにはボンディング配線の入り口が設けられていて、入り口は装置内側を向きかつ開放されているものである。 The semiconductor device according to the present invention includes an insulating substrate having a first electrode pattern formed on the first main surface and a second electrode pattern formed on the second main surface, and a first of the insulating substrate. A base plate bonded to the electrode pattern; a semiconductor element having a front electrode and a back electrode; a semiconductor element having the back electrode bonded to the second electrode pattern of the insulating substrate; and a terminal portion having a recess. A resin case member, an electrode terminal fixed to the case member and having a wiring connection portion exposed from the bottom surface of the depression, a bonding wiring for connecting the wiring connection portion of the electrode terminal and the front side electrode of the semiconductor element, The inside of the case member is filled with an insulating substrate, a semiconductor element, and a sealing resin member that seals the bonding wiring, and a recess formed in the terminal portion is provided with an entrance for the bonding wiring, enter Is one that is oriented and open system inside.
 本発明の半導体装置によれば、封止樹脂部材の電極端子からの剥離を抑制することができるとともに、ボンディング配線の接続寿命を延ばすことができ、信頼性の高い半導体装置を得ることができる。 According to the semiconductor device of the present invention, it is possible to suppress the peeling of the sealing resin member from the electrode terminal, to extend the connection life of the bonding wiring, and to obtain a highly reliable semiconductor device.
本発明の実施の形態に係る半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device which concerns on embodiment of this invention. 半導体素子基板に半導体素子が接合された状態を表す側面図である。It is a side view showing the state where the semiconductor element was joined to the semiconductor element substrate. 図4Aは本発明の実施の形態1に係る端子部の第1の構造を示す正面図である。図4Bは本発明の実施の形態1に係る端子部の第1の構造を示す側面図である。FIG. 4A is a front view showing a first structure of the terminal portion according to Embodiment 1 of the present invention. FIG. 4B is a side view showing the first structure of the terminal portion according to Embodiment 1 of the present invention. 本発明の実施の形態1に係る端子部の第1の構造を示す斜視図である。It is a perspective view which shows the 1st structure of the terminal part which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る端子部の第2の構造を示す説明図である。It is explanatory drawing which shows the 2nd structure of the terminal part which concerns on Embodiment 1 of this invention. 本発明の実施の形態2に係る端子部の構造を示す側面図である。It is a side view which shows the structure of the terminal part which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る端子部の構造を示す斜視図である。It is a perspective view which shows the structure of the terminal part which concerns on Embodiment 2 of this invention. 本発明の実施の形態3に係る端子部の構造を示す説明図である。It is explanatory drawing which shows the structure of the terminal part which concerns on Embodiment 3 of this invention. 本発明の実施の形態3に係る端子部の構造を示す斜視図である。It is a perspective view which shows the structure of the terminal part which concerns on Embodiment 3 of this invention. 本発明の実施の形態4に係る半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 4 of this invention. 比較例に係る端子部の構造を示す説明図である。It is explanatory drawing which shows the structure of the terminal part which concerns on a comparative example. 比較例に係る端子部の構造を示す斜視図である。It is a perspective view which shows the structure of the terminal part which concerns on a comparative example. ヒートサイクル試験の結果を表す図である。It is a figure showing the result of a heat cycle test.
 以下に本発明にかかる半導体装置の実施の形態を図面に基づいて詳細に説明する。なお、本発明は以下の記述に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜変更可能である。図において、同一符号が付与されている構成要素は、同一の、または、相当する構成要素を表している。本実施の形態の半導体装置は、家電用、産業用、自動車用、電車用などに広く用いられる半導体パワーモジュールである。 Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the figure, the components given the same reference numerals represent the same or corresponding components. The semiconductor device of this embodiment is a semiconductor power module widely used for home appliances, industrial use, automobile use, train use, and the like.
実施の形態1.
 最初に本発明の実施の形態に係る半導体装置の全体構成について説明する。図1は本発明の実施の形態1による半導体装置の基本構造を示す断面図である。半導体装置100は、封止樹脂部材1、半導体素子2a、半導体素子2b、電極端子4、ボンディング配線6、ケース部材7、半導体素子基板11、接合材12、ベース板13、接着剤14などから構成されている。半導体素子2aおよび半導体素子2bは、半導体素子基板11にはんだなどの接合材12で固着されている。ベース板13は半導体素子基板11にはんだなどの接合材12で固着されている。ケース部材7はベース板13とシリコーン製の接着剤14によって固定されている。ベース板13が底板となり、ベース板13とケース部材7とで筐体を成している。ケース部材7は、使用温度領域内で熱変形を起こさず、しかも、絶縁性を維持することが求められている。このため、ケース部材7には、PPS(Poly Phenylene Sulfide)樹脂などの、軟化点が高い樹脂が使用されている。
Embodiment 1 FIG.
First, the overall configuration of the semiconductor device according to the embodiment of the present invention will be described. FIG. 1 is a sectional view showing a basic structure of a semiconductor device according to the first embodiment of the present invention. The semiconductor device 100 includes a sealing resin member 1, a semiconductor element 2a, a semiconductor element 2b, an electrode terminal 4, a bonding wiring 6, a case member 7, a semiconductor element substrate 11, a bonding material 12, a base plate 13, an adhesive 14, and the like. Has been. The semiconductor element 2a and the semiconductor element 2b are fixed to the semiconductor element substrate 11 with a bonding material 12 such as solder. The base plate 13 is fixed to the semiconductor element substrate 11 with a bonding material 12 such as solder. The case member 7 is fixed by a base plate 13 and a silicone adhesive 14. The base plate 13 serves as a bottom plate, and the base plate 13 and the case member 7 form a casing. The case member 7 is required not to be thermally deformed in the operating temperature range and to maintain insulation. For this reason, a resin having a high softening point such as PPS (Poly Phenylene Sulfide) resin is used for the case member 7.
 ケース部材7は電極端子4が固定される端子部3を有する。半導体素子2aおよび半導体素子2bは、ボンディング配線6によって端子部3の電極端子4と接続されている。電極端子4はケース部材7にインサートモールドされていて、外部機器と接続される。電極端子4は、通常銅を用いる。封止樹脂部材1としては、エポキシ樹脂を用いているが、これに限定するものではなく、所望の弾性率と耐熱性を有している樹脂であれば好適に用いることが出来る。例えば、封止樹脂部材1にシリコーン樹脂、ウレタン樹脂、ポリイミド樹脂、ポリアミド樹脂、ポリアミドイミド樹脂、アクリル樹脂等を用いても良く、絶縁性と接着性を兼ね備えた材料であれば構わない。 The case member 7 has a terminal portion 3 to which the electrode terminal 4 is fixed. The semiconductor element 2 a and the semiconductor element 2 b are connected to the electrode terminal 4 of the terminal portion 3 by the bonding wiring 6. The electrode terminal 4 is insert-molded in the case member 7 and connected to an external device. The electrode terminal 4 is usually made of copper. Although the epoxy resin is used as the sealing resin member 1, it is not limited to this, and any resin having a desired elastic modulus and heat resistance can be suitably used. For example, a silicone resin, a urethane resin, a polyimide resin, a polyamide resin, a polyamideimide resin, an acrylic resin, or the like may be used for the sealing resin member 1 as long as the material has both insulating properties and adhesiveness.
 図2は、本発明の実施の形態1による半導体装置100の構造を示す上面図である。ここで、半導体素子2aは大電流を制御するMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)に代表される電力用半導体素子である。半導体素子2bは電力用半導体素子に並列に設けられた還流用のダイオードである。半導体素子2aと半導体素子2bには電極端子4と電気接続するためのボンディング配線6が接続されている。ボンディング配線6の一端は端子部3に接続されている。図では、半導体素子2aに2本の配線しか施されていないが、これに限定するものではなく、半導体素子の電流密度などにより、必要な本数を設けることができる。ボンディング配線6の接合には、銅や錫などの金属片に対する、溶融接合あるいは超音波接合を用いることができるが、必要な電流と電圧を半導体素子に供給できる方法であれば特に限定されない。電極端子4は、ボンディング配線6を介して、第二電極パターン9と接続されていてもよい。 FIG. 2 is a top view showing the structure of the semiconductor device 100 according to the first embodiment of the present invention. Here, the semiconductor element 2a is a power semiconductor element represented by a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) that controls a large current. The semiconductor element 2b is a reflux diode provided in parallel with the power semiconductor element. Bonding wiring 6 for electrical connection with the electrode terminal 4 is connected to the semiconductor elements 2a and 2b. One end of the bonding wiring 6 is connected to the terminal portion 3. In the figure, only two wirings are provided in the semiconductor element 2a. However, the number is not limited to this, and a necessary number can be provided depending on the current density of the semiconductor element. The bonding wiring 6 can be bonded by fusion bonding or ultrasonic bonding to a metal piece such as copper or tin, but is not particularly limited as long as it is a method capable of supplying necessary current and voltage to the semiconductor element. The electrode terminal 4 may be connected to the second electrode pattern 9 via the bonding wiring 6.
 半導体素子2aと半導体素子2bは、珪素(Si)によって形成したものの他、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成したものも好適に使用することができる。ワイドバンドギャップ半導体としては、炭化珪素(SiC)、窒化ガリウム系材料またはダイヤモンドなどがある。ワイドバンドギャップ半導体を用いた場合、許容電流密度が高く、電力損失も低いため、電力半導体素子を用いた装置の小型化が可能となる。 As the semiconductor element 2a and the semiconductor element 2b, in addition to those formed of silicon (Si), those formed of a wide band gap semiconductor having a band gap larger than that of silicon can be suitably used. Examples of the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride-based material, and diamond. When a wide bandgap semiconductor is used, the allowable current density is high and the power loss is low, so that a device using a power semiconductor element can be downsized.
 図3は半導体素子基板11に半導体素子2aと半導体素子2bが接合された状態を表す側面図である。半導体素子2aは、表側電極2oと裏側電極2uが、それぞれ、表面と裏面に、形成されている。同様に、半導体素子2bは、表側電極2oと裏側電極2uが、それぞれ、表面と裏面に、形成されている。半導体素子基板11は、第一電極パターン8と第二電極パターン9と絶縁性基板10からなる。半導体素子2aの裏側電極2uは、半導体素子基板11の第二電極パターン9にはんだ等の接合材12で接合されている(図1参照)。同様に、半導体素子2bの裏側電極2uは、半導体素子基板11の第二電極パターン9にはんだ等の接合材12で接合されている(図1参照)。半導体素子基板11の第一電極パターン8にはベース板13がはんだ等の接合材12で接合される(図1参照)。絶縁性基板10の下側の第一主面10aには外周に第一余白部11aを残して第一電極パターン8が形成されている。絶縁性基板10の上側の第二主面10bには外周に第二余白部11bを残して第二電極パターン9が形成されている。 FIG. 3 is a side view showing a state in which the semiconductor element 2a and the semiconductor element 2b are joined to the semiconductor element substrate 11. FIG. As for the semiconductor element 2a, the front side electrode 2o and the back side electrode 2u are formed in the surface and the back surface, respectively. Similarly, in the semiconductor element 2b, a front side electrode 2o and a back side electrode 2u are formed on the front surface and the back surface, respectively. The semiconductor element substrate 11 includes a first electrode pattern 8, a second electrode pattern 9, and an insulating substrate 10. The back electrode 2u of the semiconductor element 2a is bonded to the second electrode pattern 9 of the semiconductor element substrate 11 with a bonding material 12 such as solder (see FIG. 1). Similarly, the back side electrode 2u of the semiconductor element 2b is bonded to the second electrode pattern 9 of the semiconductor element substrate 11 with a bonding material 12 such as solder (see FIG. 1). A base plate 13 is bonded to the first electrode pattern 8 of the semiconductor element substrate 11 with a bonding material 12 such as solder (see FIG. 1). A first electrode pattern 8 is formed on the first main surface 10a on the lower side of the insulating substrate 10, leaving a first blank portion 11a on the outer periphery. A second electrode pattern 9 is formed on the second main surface 10b on the upper side of the insulating substrate 10 leaving a second blank portion 11b on the outer periphery.
 半導体素子基板11は、セラミック(Al2O3、SiO2、AlN、BN、Si3N4など)からなる絶縁性基板10に第一電極パターン8および第二電極パターン9を設けてあるものを指す。第一電極パターン8および第二電極パターン9には銅、アルミなどが用いられる。絶縁性基板10は、放熱性と絶縁性を備えていることが必要であり、セラミックに限らず、セラミック粉を分散させた樹脂硬化物、あるいはセラミック板を埋め込んだ樹脂硬化物のような絶縁性基板でも良い。第一電極パターン8は絶縁性基板10(または半導体素子基板11)の裏面に形成されている。第二電極パターン9は絶縁性基板10(または半導体素子基板11)の表面に形成されている。 The semiconductor element substrate 11 refers to a substrate in which a first electrode pattern 8 and a second electrode pattern 9 are provided on an insulating substrate 10 made of ceramic (Al2O3, SiO2, AlN, BN, Si3N4, etc.). Copper, aluminum or the like is used for the first electrode pattern 8 and the second electrode pattern 9. The insulating substrate 10 is required to have heat dissipation and insulating properties, and is not limited to ceramic, but is insulating such as a cured resin in which ceramic powder is dispersed or a cured resin in which a ceramic plate is embedded. A substrate may be used. The first electrode pattern 8 is formed on the back surface of the insulating substrate 10 (or the semiconductor element substrate 11). The second electrode pattern 9 is formed on the surface of the insulating substrate 10 (or the semiconductor element substrate 11).
 絶縁性基板10に使用するセラミック粉は、Al2O3、SiO2、AlN、BN、Si3N4などが用いられるが、これに限定するものではなく、ダイヤモンド、SiC、B2O3、などを用いても良い。また、シリコーン樹脂やアクリル樹脂などの樹脂製の粉を用いても良い。粉形状は、球状を用いることが多いが、これに限定するものではなく、破砕状、粒状、リン片状、凝集体形状などを用いても良い。粉体の充填量は、必要な放熱性と絶縁性が得られる量が充填されていれば良い。絶縁性基板10に使用する樹脂は、通常、エポキシ樹脂が用いられる。絶縁性基板10に用いる樹脂は、これに限定するものではなく、ポリイミド樹脂、シリコーン樹脂、アクリル樹脂などを用いても良く、絶縁性と接着性を兼ね備えた材料であれば構わない。 The ceramic powder used for the insulating substrate 10 is Al2O3, SiO2, AlN, BN, Si3N4 or the like, but is not limited thereto, and diamond, SiC, B2O3, or the like may be used. Further, resin powder such as silicone resin and acrylic resin may be used. The powder shape is often spherical, but is not limited thereto, and a crushed shape, a granular shape, a flake shape, an aggregate shape, or the like may be used. The filling amount of the powder is not limited as long as the necessary heat dissipation and insulation are obtained. As the resin used for the insulating substrate 10, an epoxy resin is usually used. The resin used for the insulating substrate 10 is not limited to this, and a polyimide resin, a silicone resin, an acrylic resin, or the like may be used as long as the material has both insulating properties and adhesiveness.
 電極端子4、第一電極パターン8、第二電極パターン9およびベース板13は、通常銅を用いるが、これに限定するものではなく、必要な放熱特性を有するものであれば特に限定はされない。例えばアルミや鉄を用いても良く、これらを複合した材料を用いても良い。また、銅/インバー/銅などの複合材料を用いても良く、SiCAl、CuMoなどの合金を用いても良い。表面には、通常、ニッケルメッキを行うが、これに限定するものではなく、金や錫メッキを行っても良く、必要な電流と電圧を半導体素子に供給できる構造であれば構わない。電極端子4、第一電極パターン8、第二電極パターン9の少なくとも一部は、樹脂との密着性を向上させるため表面に微小な凹凸を設けても良く、またプライマー処理等の密着性向上剤を設けても良い。密着性向上剤は、シランカップリング剤、ポリイミド樹脂、エポキシ樹脂等が用いられるが、半導体素子基板の電極部材と封止樹脂との密着性を向上させるものであれば特に限定されない。 The electrode terminal 4, the first electrode pattern 8, the second electrode pattern 9, and the base plate 13 are usually made of copper, but are not limited thereto, and are not particularly limited as long as they have necessary heat dissipation characteristics. For example, aluminum or iron may be used, or a composite material of these may be used. Further, a composite material such as copper / invar / copper may be used, and an alloy such as SiCAl or CuMo may be used. The surface is usually plated with nickel. However, the present invention is not limited to this, and may be plated with gold or tin as long as it has a structure capable of supplying necessary current and voltage to the semiconductor element. At least a part of the electrode terminal 4, the first electrode pattern 8, and the second electrode pattern 9 may be provided with minute irregularities on the surface in order to improve the adhesion to the resin, and an adhesion improver such as a primer treatment. May be provided. As the adhesion improver, a silane coupling agent, a polyimide resin, an epoxy resin, or the like is used, but it is not particularly limited as long as it improves the adhesion between the electrode member of the semiconductor element substrate and the sealing resin.
 図4Aはケース部材7の端子部3を表す正面図、図4Bはケース部材7の端子部3を表す側面図である。端子部3はケース部材7と同じ材料で形成されていて、ケース部材7と一体化している。端子部3の窪み3aは入り口3b、奥面3o、天面3t、底面3l、側面3pおよび側面3qを有する。窪み3aの天面3tまたは端子部3の上面3uは開放されている。窪み3aの底面3lからは電極端子4の配線接続部4aが露呈している。実施の形態1の半導体装置100では、窪み3aの天面3t(または端子部3の上面3u)よりも電極端子4の接合点(配線接続部4a)が低い位置に配置されている。配線接続部4aは奥面3o、側面3pおよび側面3qに取り囲まれた構造を有している。ボンディング配線6は電極端子4の配線接続部4aと半導体素子(2a、2b)の表側電極2oを接続している。窪み3aは、入り口3bから奥面3oまで、幅が同じである。ボンディング配線6の入り口3bは端子部3の窪み3aに設けられている。 4A is a front view showing the terminal portion 3 of the case member 7, and FIG. 4B is a side view showing the terminal portion 3 of the case member 7. The terminal portion 3 is formed of the same material as the case member 7 and is integrated with the case member 7. The recess 3a of the terminal portion 3 has an entrance 3b, a back surface 3o, a top surface 3t, a bottom surface 31, a side surface 3p, and a side surface 3q. The top surface 3t of the recess 3a or the upper surface 3u of the terminal portion 3 is open. The wiring connection portion 4a of the electrode terminal 4 is exposed from the bottom surface 3l of the recess 3a. In the semiconductor device 100 of the first embodiment, the junction point (wiring connection portion 4a) of the electrode terminal 4 is arranged at a position lower than the top surface 3t of the recess 3a (or the upper surface 3u of the terminal portion 3). The wiring connection portion 4a has a structure surrounded by the back surface 3o, the side surface 3p, and the side surface 3q. The bonding wiring 6 connects the wiring connection portion 4a of the electrode terminal 4 and the front side electrode 2o of the semiconductor element (2a, 2b). The recess 3a has the same width from the entrance 3b to the back surface 3o. The entrance 3 b of the bonding wiring 6 is provided in the recess 3 a of the terminal portion 3.
 図5は端子部の斜視図である。端子部3の窪み3aに設けられている入り口3bは、半導体装置100の装置内側を向いている。窪み3aは、入り口3bが開放されていて、奥は閉じている。ボンディング配線6は配線接続部4aの上面(または露出面)にボンディング装置により接合される。ワイヤボンディングを行う際、ボンディング配線6は入り口3bから窪み3aに進入する。ボンディング配線6は、アルミまたは金でできた断面が円形の線体を用いているが、これに限定するものではなく、例えば断面が方形の銅板を帯状にしたものを用いても良い。端子部3の窪み3aは、ボンディング配線6を接合するに足る空間を有すれば特に限定するものではないが、ボンディング装置に付属のワイヤ切断ツールを用い、ボンディング配線6を切断できる大きさを有することが好ましい。電極端子4の配線接続部4aは、ボンディング配線6が接合された後、エポキシ樹脂などで封止される。 FIG. 5 is a perspective view of the terminal portion. An entrance 3 b provided in the recess 3 a of the terminal portion 3 faces the inside of the semiconductor device 100. The recess 3a is open at the entrance 3b and closed at the back. The bonding wiring 6 is bonded to the upper surface (or exposed surface) of the wiring connection portion 4a by a bonding apparatus. When wire bonding is performed, the bonding wiring 6 enters the recess 3a from the entrance 3b. The bonding wiring 6 uses a wire body having a circular cross section made of aluminum or gold, but is not limited to this, and for example, a copper plate having a rectangular cross section may be used. The recess 3a of the terminal portion 3 is not particularly limited as long as it has a space sufficient for bonding the bonding wiring 6, but has a size capable of cutting the bonding wiring 6 using a wire cutting tool attached to the bonding apparatus. It is preferable. The wiring connection portion 4a of the electrode terminal 4 is sealed with an epoxy resin or the like after the bonding wiring 6 is joined.
 端子部3の窪み3aがワイヤ切断ツールによりボンディング配線6を切断できる大きさを有さない場合には、ボンディング配線6のファーストボンドを電極端子4の配線接続部4aで実施する。セカンドボンドを第二電極パターン9の上面及び半導体素子2の上面で実施することにより、ボンディング配線6を接続することできる。ただし、セカンドボンドを半導体素子2の上面で実施し、ワイヤ切断ツールによりボンディング配線6を切断する際には半導体素子2の損傷が懸念される。半導体素子2と配線接続部4aとをボンディング配線6により接合する場合、セカンドボンドを半導体素子2に実施した後、さらに半導体素子2から第二電極パターン9へサードボンドを実施する。この後、第二電極パターン9でボンディング配線6を切断することで信頼性の高い半導体装置100を得ることができる。なお、図では電極端子4はケース部材7にインサート成形されているが、窪み3aに接着材等で固定することも出来る。 When the recess 3 a of the terminal portion 3 does not have a size capable of cutting the bonding wiring 6 with the wire cutting tool, the first bonding of the bonding wiring 6 is performed at the wiring connection portion 4 a of the electrode terminal 4. By performing the second bond on the upper surface of the second electrode pattern 9 and the upper surface of the semiconductor element 2, the bonding wiring 6 can be connected. However, when the second bond is performed on the upper surface of the semiconductor element 2 and the bonding wiring 6 is cut with a wire cutting tool, the semiconductor element 2 may be damaged. When the semiconductor element 2 and the wiring connection portion 4 a are bonded by the bonding wiring 6, after the second bond is performed on the semiconductor element 2, a third bond is further performed from the semiconductor element 2 to the second electrode pattern 9. Thereafter, by cutting the bonding wiring 6 with the second electrode pattern 9, the highly reliable semiconductor device 100 can be obtained. In the figure, the electrode terminal 4 is insert-molded in the case member 7, but can be fixed to the recess 3a with an adhesive or the like.
 なお、実施の形態1に係る端子部3の構造はこれに限定されるものではない。図6に示すように窪み3aが、テーパー形状(半導体素子2に向かって断面積が小さくなる形状)の構造を有していてもよい。すなわち窪み3aの入り口から奥面に向かうほど、幅が広くなっていてもよい。ケース部材7からなる端子部3がテーパー形状を有することで、ヒートサイクル時またはパワーサイクル時に熱応力が発生する封止樹脂部材1は、端子部3に3辺を囲まれた配線接続部4aの上部との界面にかかる熱応力が低減される。電極端子4と封止樹脂部材1との剥離が抑制されるので、信頼性の高い半導体装置100を得ることができる。 In addition, the structure of the terminal part 3 which concerns on Embodiment 1 is not limited to this. As shown in FIG. 6, the recess 3 a may have a tapered structure (a shape in which a cross-sectional area decreases toward the semiconductor element 2). That is, the width may become wider as it goes from the entrance of the recess 3a to the inner surface. Since the terminal portion 3 made of the case member 7 has a taper shape, the sealing resin member 1 in which thermal stress is generated at the time of heat cycle or power cycle is formed on the wiring connection portion 4a surrounded by the terminal portion 3 on three sides. Thermal stress applied to the interface with the upper part is reduced. Since peeling between the electrode terminal 4 and the sealing resin member 1 is suppressed, a highly reliable semiconductor device 100 can be obtained.
 本実施の形態による端子部は窪みが三辺を取り囲まれた開口構造を有している。開口部のケース部材は鋭角形状であるが、鋭角形状に限定するものではなく、裾野のようなフィレット形状すなわち丸みを有した形状であることが好ましい。開口構造が丸みを有した形状を持つことで、封止樹脂部材1が剥離した際においても、開口部が封止樹脂部材1のクラックの起点となることを抑制でき、より信頼性の高い半導体装置100を得ることができる。 The terminal portion according to this embodiment has an opening structure in which a depression is surrounded on three sides. The case member of the opening has an acute-angle shape, but is not limited to the acute-angle shape, and is preferably a fillet shape such as a skirt, that is, a round shape. Since the opening structure has a rounded shape, even when the sealing resin member 1 is peeled off, it is possible to suppress the opening from being a starting point of cracks in the sealing resin member 1, and a more reliable semiconductor. Device 100 can be obtained.
 次に本実施の形態の効果について説明する。端子部3と封止樹脂部材1との界面にはせん断応力が発生する。端子部3と封止樹脂部材1との界面に発生するせん断応力は、上面3uと封止樹脂部材1との接触界面の直線的な連続距離に依存するため、この接触界面の直線的な連続距離を小さくすることでせん断応力を低減することができる。本実施の形態の半導体装置100によれば、電極端子4の配線接続部4aはケース部材7と一体化された端子部3の上面3uより低い位置に配置されている。配線接続部4aと端子部3は同一平面状に存在しないため、上面3uと封止樹脂部材1との直線的な連続距離を断ち切ることができる。これにより、端子部3と封止樹脂部材1との接触界面に生じる封止樹脂の硬化収縮起因のせん断応力は低減し、配線接続部4aと封止樹脂部材1との剥離を抑制することができる。 Next, the effect of this embodiment will be described. A shear stress is generated at the interface between the terminal portion 3 and the sealing resin member 1. Since the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 depends on the linear continuous distance of the contact interface between the upper surface 3 u and the sealing resin member 1, this contact interface is linearly continuous. By reducing the distance, the shear stress can be reduced. According to the semiconductor device 100 of the present embodiment, the wiring connection portion 4 a of the electrode terminal 4 is disposed at a position lower than the upper surface 3 u of the terminal portion 3 integrated with the case member 7. Since the wiring connection portion 4a and the terminal portion 3 do not exist on the same plane, the linear continuous distance between the upper surface 3u and the sealing resin member 1 can be cut off. Thereby, the shear stress due to the curing shrinkage of the sealing resin generated at the contact interface between the terminal portion 3 and the sealing resin member 1 is reduced, and the peeling between the wiring connection portion 4a and the sealing resin member 1 can be suppressed. it can.
 ケース部材7と同一材料からなる端子部3は空洞構造(窪み3a)を有する。電極端子4の配線接続部4aに接合されたボンディング配線の近傍において封止樹脂部材1と端子部3との接着面積が増加している。端子部3と封止樹脂部材1が剥離した際に端子部3までの剥離の伸展距離を伸ばすことで、ボンディング配線6の接続寿命を延ばすことができ、信頼性の高い半導体装置を得ることができる。端子部3の窪み3aを囲む三辺は表面粗化、コーティング、カップリングなどの封止樹脂部材1との接着性を向上させるための処理が施されていてもよい。電極端子4の配線接続部4aから端子部3の上面3uまでの段差(端子部3の高さ)としては、1mm以上あれば良い。端子部3の段差が1mm以下では、封止樹脂部材1と端子部3との接着面積が十分でないため剥離抑制効果は十分でない。 The terminal part 3 made of the same material as the case member 7 has a hollow structure (recess 3a). The bonding area between the sealing resin member 1 and the terminal portion 3 is increased in the vicinity of the bonding wiring bonded to the wiring connection portion 4 a of the electrode terminal 4. When the terminal part 3 and the sealing resin member 1 are peeled off, the connection life of the bonding wiring 6 can be extended by extending the peeling extension distance to the terminal part 3, and a highly reliable semiconductor device can be obtained. it can. The three sides surrounding the depression 3a of the terminal portion 3 may be subjected to a treatment for improving the adhesion with the sealing resin member 1 such as surface roughening, coating, and coupling. The step (height of the terminal portion 3) from the wiring connection portion 4a of the electrode terminal 4 to the upper surface 3u of the terminal portion 3 may be 1 mm or more. When the level difference of the terminal portion 3 is 1 mm or less, the adhesion area between the sealing resin member 1 and the terminal portion 3 is not sufficient, so that the peeling suppression effect is not sufficient.
 以上のように、本実施の形態の半導体装置100によれば、ケース部材7と同一材料からなる端子部3の上面3uよりも、ボンディング配線が接合された電極端子4の配線接続部4aは低い位置に埋設されている。ボンディング配線6はケース部材7と同一材料からなる端子部3の窪み3aに三辺を取り囲まれた構造を有しており、封止樹脂部材1の硬化収縮により生じるせん断応力が低減する。配線接続部4aの近傍における端子部3と封止樹脂部材1との接着面積を増加させることで、電極端子4および端子部3と封止樹脂部材1との接着性が向上する。 As described above, according to the semiconductor device 100 of the present embodiment, the wiring connection portion 4a of the electrode terminal 4 to which the bonding wiring is bonded is lower than the upper surface 3u of the terminal portion 3 made of the same material as the case member 7. Buried in position. The bonding wiring 6 has a structure in which three sides are surrounded by a recess 3 a of the terminal portion 3 made of the same material as that of the case member 7, and shear stress generated by curing shrinkage of the sealing resin member 1 is reduced. By increasing the adhesion area between the terminal part 3 and the sealing resin member 1 in the vicinity of the wiring connection part 4a, the adhesiveness between the electrode terminal 4 and the terminal part 3 and the sealing resin member 1 is improved.
 ボンディング配線6は電極端子4から半導体素子2および半導体素子基板11へ電気接続する。ボンディング配線6の近傍の電極端子4と封止樹脂部材1とが剥離すると、ヒートサイクルにともなう封止樹脂部材1の膨張と収縮や振動により、ボンディング配線の接合部への負荷が高くなり断線にいたる。上述のように電極端子4と封止樹脂部材1との剥離を抑制することで、ボンディング配線6の断線を抑制し、信頼性の高い半導体装置100を得ることができる。本発明は、本実施の形態1のみならず他の実施の形態においても、150℃以上で動作する半導体素子に適用すると顕著な効果が得られる。 The bonding wiring 6 is electrically connected from the electrode terminal 4 to the semiconductor element 2 and the semiconductor element substrate 11. When the electrode terminal 4 in the vicinity of the bonding wiring 6 and the sealing resin member 1 are separated, the load on the bonding portion of the bonding wiring is increased due to the expansion, contraction, and vibration of the sealing resin member 1 due to the heat cycle. It ’s all over. By suppressing the peeling between the electrode terminal 4 and the sealing resin member 1 as described above, the disconnection of the bonding wiring 6 can be suppressed and the highly reliable semiconductor device 100 can be obtained. The present invention can provide a remarkable effect when applied to a semiconductor element operating at 150 ° C. or higher, not only in the first embodiment but also in other embodiments.
実施の形態2.
 本発明の実施の形態2では、本発明の実施の形態1と比較して、ケース部材7と一体化している端子部の構造が異なっている。実施の形態1は電極端子4の配線接続部4aが窪み3aに三辺を取り囲まれた構造であるが、実施の形態2では電極端子4の配線接続部4aが端子部3の窪み3aに四辺を囲まれた構造を有している。図7は、本発明の実施の形態2に係る端子部を示す側面図である。図8は、本発明の実施の形態2に係る端子部を示す斜視図である。
Embodiment 2. FIG.
In the second embodiment of the present invention, the structure of the terminal portion integrated with the case member 7 is different from that of the first embodiment of the present invention. The first embodiment has a structure in which the wiring connection portion 4a of the electrode terminal 4 is surrounded by the recess 3a on three sides, but in the second embodiment, the wiring connection portion 4a of the electrode terminal 4 has four sides on the recess 3a of the terminal portion 3. It has a structure surrounded by. FIG. 7 is a side view showing a terminal portion according to Embodiment 2 of the present invention. FIG. 8 is a perspective view showing a terminal portion according to Embodiment 2 of the present invention.
 実施の形態2に係る端子部3では、窪み3aには入り口に敷居3cが設けられている。このため、本実施の形態では、電極端子4の配線接続部4aは、四辺をケース部材7に囲まれた構造を持つ。封止樹脂部材1は、絶縁性基板10(あるいは半導体素子基板11)との剥離を避けるために、これら部材の線膨張率と弾性率にあわせた樹脂が選択されている。ケース部材7との接着性が低くなることが多く、封止樹脂部材1の剥離にともないボンディング配線6の断線が生じる。本実施の形態では、窪み3aに、端子部3およびケース部材7と接着強度が高い樹脂材料が充填されている。 In the terminal part 3 according to the second embodiment, a sill 3c is provided at the entrance to the recess 3a. For this reason, in this Embodiment, the wiring connection part 4a of the electrode terminal 4 has a structure where four sides were surrounded by the case member 7. FIG. For the sealing resin member 1, in order to avoid peeling from the insulating substrate 10 (or the semiconductor element substrate 11), a resin that matches the linear expansion coefficient and elastic modulus of these members is selected. The adhesiveness with the case member 7 is often lowered, and the bonding wiring 6 is disconnected as the sealing resin member 1 is peeled off. In the present embodiment, the recess 3 a is filled with a resin material having high adhesive strength with the terminal portion 3 and the case member 7.
 本実施の形態では、四辺をケース部材7に囲まれた構造を持つ配線接続部4aの上に、ケース部材7との接着性が高く、ケース部材7の線膨張率と近い線膨張率をもつ封止樹脂部材15(第2の封止樹脂部材)が封止されている。封止樹脂部材1は、半導体素子2および半導体素子基板11とボンディング配線6との接着性を確保する。封止樹脂部材15は、電極端子4の配線接続部4aを被覆しており、ケース部材7との接着性を確保する。その結果、さらに信頼性の高い半導体装置100を得ることができる。 In the present embodiment, the adhesiveness with the case member 7 is high on the wiring connection portion 4 a having the structure surrounded on the four sides by the case member 7, and the linear expansion coefficient is close to the linear expansion coefficient of the case member 7. The sealing resin member 15 (second sealing resin member) is sealed. The sealing resin member 1 ensures adhesion between the semiconductor element 2 and the semiconductor element substrate 11 and the bonding wiring 6. The sealing resin member 15 covers the wiring connection portion 4 a of the electrode terminal 4 and ensures adhesion with the case member 7. As a result, the semiconductor device 100 with higher reliability can be obtained.
 封止樹脂部材15としては、エポキシ樹脂を用いているが、これに限定するものではなく、所望の線膨張率と弾性率を有している樹脂であれば用いることが出来る。例えばエポキシ樹脂の他に、シリコーン樹脂、ウレタン樹脂、ポリイミド樹脂、ポリアミド樹脂、ポリアミドイミド樹脂、アクリル樹脂等を用いても良く、絶縁性と接着性を兼ね備えた材料であれば構わない。 Although the epoxy resin is used as the sealing resin member 15, it is not limited thereto, and any resin having a desired linear expansion coefficient and elastic modulus can be used. For example, in addition to an epoxy resin, a silicone resin, a urethane resin, a polyimide resin, a polyamide resin, a polyamideimide resin, an acrylic resin, or the like may be used as long as the material has both insulating properties and adhesiveness.
 端子部3の窪み3aは、ボンディング配線6を接合するに足る空間を有すれば特に限定するものではないが、ボンディング装置に付属のワイヤ切断ツールを用い、ボンディング配線6を切断できる大きさを有することが好ましい。端子部3の窪み3aがワイヤ切断ツールによりボンディング配線6を切断できる大きさを有さない場合には、ボンディング配線6のファーストボンドを電極端子4の配線接続部4aで実施する。セカンドボンドを第二電極パターン9及び半導体素子2の上面で実施することにより、ボンディング配線6を接続することできる。ただし、セカンドボンドを半導体素子2の上面で実施し、ワイヤ切断ツールによりボンディング配線6を切断する際には半導体素子2の損傷が懸念される。半導体素子2と配線接続部4aとをボンディング配線により接合する場合、セカンドボンドを半導体素子2に実施するとよい。その後、さらに半導体素子2から第二電極パターン9へサードボンドを実施し、第二電極パターン9でボンディング配線を切断することで信頼性の高い半導体装置100を得ることができる。 The recess 3a of the terminal portion 3 is not particularly limited as long as it has a space sufficient for bonding the bonding wiring 6, but has a size capable of cutting the bonding wiring 6 using a wire cutting tool attached to the bonding apparatus. It is preferable. When the recess 3 a of the terminal portion 3 does not have a size capable of cutting the bonding wiring 6 with a wire cutting tool, the first bonding of the bonding wiring 6 is performed at the wiring connection portion 4 a of the electrode terminal 4. By performing the second bond on the second electrode pattern 9 and the upper surface of the semiconductor element 2, the bonding wiring 6 can be connected. However, when the second bond is performed on the upper surface of the semiconductor element 2 and the bonding wiring 6 is cut with a wire cutting tool, the semiconductor element 2 may be damaged. When the semiconductor element 2 and the wiring connection portion 4a are bonded by bonding wiring, second bonding may be performed on the semiconductor element 2. Thereafter, third bonding is further performed from the semiconductor element 2 to the second electrode pattern 9, and the bonding wiring is cut by the second electrode pattern 9, whereby the highly reliable semiconductor device 100 can be obtained.
 次に本実施の形態の端子部3と封止樹脂部材1との界面に発生するせん断応力について説明する。端子部3と封止樹脂部材1との界面に発生するせん断応力は、上面3uと封止樹脂部材1との接触界面の直線的な連続距離に依存する。この接触界面の直線的な連続距離を小さくすることでせん断応力は低減する。本実施の形態の半導体装置によれば、配線接続部4aがケース部材7で構成された端子部3の上面3uより低い位置に配置されていて、電極端子4の配線接続部4aが窪み3aに埋設されている。配線接続部4aと端子部3は同一平面状に存在しないため、上面3uと封止樹脂部材1との直線的な連続距離を断ち切ることができる。これにより、端子部3と封止樹脂部材1との接触界面に生じる封止樹脂の硬化収縮起因のせん断応力は低減し、配線接続部4aと封止樹脂部材1との剥離を抑制することができる。 Next, the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 according to the present embodiment will be described. The shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 depends on the linear continuous distance of the contact interface between the upper surface 3 u and the sealing resin member 1. By reducing the linear continuous distance of the contact interface, the shear stress is reduced. According to the semiconductor device of the present embodiment, the wiring connection portion 4a is arranged at a position lower than the upper surface 3u of the terminal portion 3 constituted by the case member 7, and the wiring connection portion 4a of the electrode terminal 4 is in the recess 3a. Buried. Since the wiring connection portion 4a and the terminal portion 3 do not exist on the same plane, the linear continuous distance between the upper surface 3u and the sealing resin member 1 can be cut off. Thereby, the shear stress due to the curing shrinkage of the sealing resin generated at the contact interface between the terminal portion 3 and the sealing resin member 1 is reduced, and the peeling between the wiring connection portion 4a and the sealing resin member 1 can be suppressed. it can.
 本実施の形態では電極端子4の四辺をケース部材で囲むことによって、封止樹脂部材1と配線接続部4aの近傍のケース部材7との接着面積が増加している。電極端子4の配線接続部4aの近傍においては封止樹脂部材1の剥離が抑制され、電極端子4の配線接続部4aまでの伸展距離を伸ばすことができる。封止樹脂部材1との接着強度が低いケース部材7からなる端子部3が封止樹脂部材1と剥離した際には、ボンディング配線6の接続寿命が延び、信頼性の高い半導体装置100を得ることができる。また、ケース部材7に囲まれた四辺は表面粗化、コーティング、カップリングなどの封止樹脂部材1との接着性を向上させるための処理が施されていてもよい。 In this embodiment, by enclosing the four sides of the electrode terminal 4 with a case member, the adhesion area between the sealing resin member 1 and the case member 7 in the vicinity of the wiring connection portion 4a is increased. In the vicinity of the wiring connection portion 4a of the electrode terminal 4, peeling of the sealing resin member 1 is suppressed, and the extension distance of the electrode terminal 4 to the wiring connection portion 4a can be extended. When the terminal portion 3 made of the case member 7 having a low adhesive strength with the sealing resin member 1 is peeled off from the sealing resin member 1, the connection life of the bonding wiring 6 is extended, and a highly reliable semiconductor device 100 is obtained. be able to. Further, the four sides surrounded by the case member 7 may be subjected to a treatment for improving adhesiveness with the sealing resin member 1 such as surface roughening, coating, and coupling.
 以上のように、本実施の形態の半導体装置100によれば、ケース部材7と一体化された端子部3の上面3uより、ボンディング配線が接合された配線接続部4aが低い位置に配置されている。電極端子4の配線接続部4aはケース部材7からなる端子部3の窪み3aに四辺を取り囲まれた構造を有している。このことにより、封止樹脂部材1の硬化収縮により生じるせん断応力が低減する。電極端子4の配線接続部4aの近傍における端子部3と封止樹脂部材1との接着面積が増加していることで、配線接続部4aおよび端子部3と封止樹脂部材1との接着性が向上する。 As described above, according to the semiconductor device 100 of the present embodiment, the wiring connection portion 4a to which the bonding wiring is bonded is disposed at a lower position than the upper surface 3u of the terminal portion 3 integrated with the case member 7. Yes. The wiring connection part 4 a of the electrode terminal 4 has a structure in which four sides are surrounded by a recess 3 a of the terminal part 3 made of the case member 7. Thereby, the shear stress generated by the curing shrinkage of the sealing resin member 1 is reduced. The adhesion area between the terminal part 3 and the sealing resin member 1 in the vicinity of the wiring connection part 4a of the electrode terminal 4 is increased, so that the adhesion between the wiring connection part 4a and the terminal part 3 and the sealing resin member 1 is increased. Will improve.
 本実施の形態によれば、封止樹脂が端子部3に四辺を取り囲まれた構造を有することで、ケース部材7との接着性が高い第2の封止樹脂を部分的に封止することができ、ケース部材7との接着性を高めることができる。電極端子4から半導体素子2および半導体素子基板11への電気接続はボンディング配線6が担っている。近傍の配線接続部4aと封止樹脂部材1とが剥離すると、ボンディング配線6は、ヒートサイクルにともなう封止樹脂部材1の膨張と収縮や振動により、接合部への負荷が高くなり断線にいたる。上述のように端子部3と封止樹脂部材1との剥離を抑制することで、ボンディング配線6の断線を抑制し、信頼性の高い半導体装置100を得ることができる。 According to the present embodiment, the sealing resin has a structure in which the four sides are surrounded by the terminal portion 3, thereby partially sealing the second sealing resin having high adhesiveness with the case member 7. Thus, adhesion to the case member 7 can be improved. Electrical connection from the electrode terminal 4 to the semiconductor element 2 and the semiconductor element substrate 11 is performed by the bonding wiring 6. When the wiring connection part 4a and the sealing resin member 1 in the vicinity are peeled off, the bonding wiring 6 is subjected to disconnection due to an increase in load on the bonding part due to expansion, contraction, and vibration of the sealing resin member 1 accompanying the heat cycle. . By suppressing the peeling between the terminal portion 3 and the sealing resin member 1 as described above, the disconnection of the bonding wiring 6 can be suppressed, and the highly reliable semiconductor device 100 can be obtained.
実施の形態3. 
 本発明の実施の形態3では、本発明の実施の形態1と比較して、ケース部材7と一体化している端子部の構造が異なっている。実施の形態1は、電極端子4の配線接続部4aがケース部材7から成る端子部3に三辺を取り囲まれた構造である。実施の形態3では図9と図10に示すような、電極端子4の配線接続部4aがケース部材7から成る端子部3から突出した構造を有している。端子部3には周囲から突出した段3dが形成されている。ボンディング配線6が接合される電極端子4の配線接続部4aは、端子部3の上面3uより高い位置に配置されている。
Embodiment 3 FIG.
In the third embodiment of the present invention, the structure of the terminal portion integrated with the case member 7 is different from that of the first embodiment of the present invention. The first embodiment has a structure in which the wiring connection portion 4 a of the electrode terminal 4 is surrounded by the terminal portion 3 including the case member 7 on three sides. In the third embodiment, as shown in FIGS. 9 and 10, the wiring connection portion 4 a of the electrode terminal 4 protrudes from the terminal portion 3 formed of the case member 7. The terminal portion 3 is formed with a step 3d protruding from the periphery. The wiring connection portion 4 a of the electrode terminal 4 to which the bonding wiring 6 is joined is disposed at a position higher than the upper surface 3 u of the terminal portion 3.
 次に本実施の形態の端子部3と封止樹脂部材1との界面に発生するせん断応力について説明する。端子部3と封止樹脂部材1との界面に発生するせん断応力は、上面3uと封止樹脂部材1との接触界面の直線的な連続距離に依存するため、この接触界面の直線的な連続距離を小さくすることでせん断応力を低減することができる。本実施の形態の半導体装置100によれば、電極端子4の配線接続部4aはケース部材7で構成された端子部3の上面3uより高い位置に配置されていて、電極端子4の配線接続部4aが端子部3に形成された段3dより突出している。配線接続部4aが端子部3と同一平面上を避けて配置されているため、電極端子4と封止樹脂部材1との界面距離を区切ることができ、電極端子4と封止樹脂部材1との界面に生じる封止樹脂部材1の硬化収縮起因のせん断応力が減少する。電極端子4と封止樹脂部材1との剥離を抑制することで、ボンディング配線6の断線を抑制し、信頼性の高い半導体装置100を得ることができる。 Next, the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 according to the present embodiment will be described. Since the shear stress generated at the interface between the terminal portion 3 and the sealing resin member 1 depends on the linear continuous distance of the contact interface between the upper surface 3 u and the sealing resin member 1, this contact interface is linearly continuous. By reducing the distance, the shear stress can be reduced. According to the semiconductor device 100 of the present embodiment, the wiring connection portion 4a of the electrode terminal 4 is disposed at a position higher than the upper surface 3u of the terminal portion 3 constituted by the case member 7, and the wiring connection portion of the electrode terminal 4 is provided. 4 a protrudes from the step 3 d formed in the terminal portion 3. Since the wiring connection portion 4a is arranged so as to avoid the same plane as the terminal portion 3, the interface distance between the electrode terminal 4 and the sealing resin member 1 can be separated, and the electrode terminal 4 and the sealing resin member 1 The shear stress due to the curing shrinkage of the sealing resin member 1 generated at the interface is reduced. By suppressing the peeling between the electrode terminal 4 and the sealing resin member 1, the disconnection of the bonding wiring 6 can be suppressed, and the highly reliable semiconductor device 100 can be obtained.
 以上のように、本実施の形態の半導体装置100によれば、ボンディング配線6が接合された配線接続部4aは、ケース部材7で構成された端子部3の上面3uより高い位置に配置されている。その結果、封止樹脂部材1の硬化収縮により生じるせん断応力が減少する。端子部3に突出した段3dを形成し、ケース部材7からなる端子部3と封止樹脂部材1との接着面積が増加していることで、電極端子4およびケース部材7からなる端子部3と封止樹脂部材1との接着性を向上させることができる。電極端子4から半導体素子2および半導体素子基板11への電気接続はボンディング配線が担っている。ボンディング配線6の近傍の配線接続部4aと封止樹脂部材1とが剥離すると、ヒートサイクルにともなう封止樹脂部材1の膨張と収縮や振動により、ボンディング配線6の接合部への負荷が高くなり断線にいたる。上述のように端子部3と封止樹脂部材1との剥離を抑制することで、ボンディング配線の断線を抑制し、信頼性の高い半導体装置100を得ることができる。 As described above, according to the semiconductor device 100 of the present embodiment, the wiring connection portion 4a to which the bonding wiring 6 is bonded is disposed at a position higher than the upper surface 3u of the terminal portion 3 constituted by the case member 7. Yes. As a result, the shear stress generated by the curing shrinkage of the sealing resin member 1 is reduced. A protruding step 3d is formed on the terminal portion 3, and the bonding area between the terminal portion 3 made of the case member 7 and the sealing resin member 1 is increased, whereby the terminal portion 3 made of the electrode terminal 4 and the case member 7 is formed. And the sealing resin member 1 can be improved in adhesion. The electrical connection from the electrode terminal 4 to the semiconductor element 2 and the semiconductor element substrate 11 is performed by bonding wiring. When the wiring connection portion 4a in the vicinity of the bonding wiring 6 and the sealing resin member 1 are separated, the load on the bonding portion of the bonding wiring 6 is increased due to expansion, contraction, and vibration of the sealing resin member 1 due to the heat cycle. It leads to disconnection. By suppressing the separation between the terminal portion 3 and the sealing resin member 1 as described above, the disconnection of the bonding wiring can be suppressed and the highly reliable semiconductor device 100 can be obtained.
実施の形態4.
 本発明の実施の形態4に係る半導体装置の構造を図11に示す。実施の形態1および2における、電極端子4および配線接続部4aは、ケース部材7の内部に含まれる半導体素子2a、半導体素子2b、電極端子4、ボンディング配線6、半導体素子基板11を覆う封止樹脂部材1により、封止されている。本実施の形態では、封止樹脂部材1を、半導体素子2a、半導体素子2b、電極端子4、ボンディング配線6、半導体素子基板11を覆う第1の封止樹脂部材1aと、ケース部材7から成る端子部3に三辺を取り囲まれた電極端子4および配線接続部4aを覆う第2の封止樹脂部材1bとで構成している。第2の封止樹脂部材1bには、第1の封止樹脂部材1aよりも低弾性率のものを使用する。
Embodiment 4 FIG.
FIG. 11 shows the structure of the semiconductor device according to the fourth embodiment of the present invention. In the first and second embodiments, the electrode terminal 4 and the wiring connection portion 4 a are sealed to cover the semiconductor element 2 a, the semiconductor element 2 b, the electrode terminal 4, the bonding wiring 6, and the semiconductor element substrate 11 included in the case member 7. It is sealed by the resin member 1. In the present embodiment, the sealing resin member 1 includes a semiconductor element 2 a, a semiconductor element 2 b, an electrode terminal 4, a bonding wiring 6, a first sealing resin member 1 a that covers the semiconductor element substrate 11, and a case member 7. The electrode portion 4 is surrounded by three sides of the terminal portion 3 and the second sealing resin member 1b covering the wiring connection portion 4a. As the second sealing resin member 1b, one having a lower elastic modulus than that of the first sealing resin member 1a is used.
 次に本実施の形態のケース部材7から成る端子部3に三辺を取り囲まれた電極端子4および配線接続部4aを、第2の封止樹脂部材が覆う際に発生する応力について説明する。半導体装置が高温になると、半導体装置を構成する各種部材には、線膨張率の違いにより反りが生じるとともに、配線接続部4aと封止樹脂との界面にせん断応力が生じる。半導体装置の高温動作化に伴い、半導体素子基板11および半導体素子2との剥離を抑制するためには、第1の封止樹脂部材の線膨張率をなるべく低くし、半導体素子基板11および半導体素子2の線膨張率に近づけることが有効である。しかし、金属部材で構成される電極端子4は、樹脂材料で構成されるケース部材7および封止樹脂部材と、線膨張率が離れているため、端子部3と封止樹脂部材1との界面に発生するせん断応力が増加し、電極端子4と封止樹脂部材1との剥離が進行し、ボンディング配線6の断線を促すこととなる。 Next, the stress generated when the second sealing resin member covers the electrode terminal 4 and the wiring connection portion 4a surrounded on the three sides by the terminal portion 3 formed of the case member 7 of the present embodiment will be described. When the temperature of the semiconductor device becomes high, the various members constituting the semiconductor device are warped due to the difference in linear expansion coefficient, and shear stress is generated at the interface between the wiring connection portion 4a and the sealing resin. In order to suppress the separation between the semiconductor element substrate 11 and the semiconductor element 2 as the semiconductor device is operated at a high temperature, the linear expansion coefficient of the first sealing resin member is made as low as possible, and the semiconductor element substrate 11 and the semiconductor element It is effective to approach a linear expansion coefficient of 2. However, the electrode terminal 4 made of a metal member has a linear expansion coefficient away from the case member 7 and the sealing resin member made of a resin material, so that the interface between the terminal portion 3 and the sealing resin member 1 As a result, the shearing stress generated in the electrode increases and the electrode terminal 4 and the sealing resin member 1 are peeled off, and the bonding wiring 6 is disconnected.
 電極端子4と封止樹脂部材界面に生じるせん断応力は、封止樹脂の線膨張率および弾性率に依存するため、ケース部材7から成る端子部3に三辺を取り囲まれた電極端子4および配線接続部4aを覆う第2の封止樹脂部材の弾性率を低下させることにより、配線接続部4aと封止樹脂との界面に生じるせん断応力を低減させ、配線接続部4aと封止樹脂との剥離を抑制することができる。また、第2の封止樹脂部材と第1の封止樹脂部材との接着力が低い場合、半導体装置に大きな反りが生じたとしても、一定の応力を越えた場合に第1の封止樹脂部材1aと第2の封止樹脂部材1bとの界面で剥離が生じるため、端子部と封止樹脂とのせん断応力を低減することができる。このとき、第2の封止樹脂部材と絶縁性基板を封止する第1の封止樹脂部材との接着強度が5Mpa以下となるようにする。さらに、接着力の低減には、例えば、第2の封止樹脂部材が露呈している面へシリコーン系離型材を塗布し、第1の封止樹脂部材で全面を封止すればよい。このように端子部3と封止樹脂部材1との剥離を抑制することで、ボンディング配線の断線を抑制し、信頼性の高い半導体装置100を得ることができる。 Since the shear stress generated at the interface between the electrode terminal 4 and the sealing resin member depends on the linear expansion coefficient and the elastic modulus of the sealing resin, the electrode terminal 4 and the wiring surrounded by the terminal portion 3 including the case member 7 on the three sides. By reducing the elastic modulus of the second sealing resin member covering the connection portion 4a, the shear stress generated at the interface between the wiring connection portion 4a and the sealing resin is reduced, and the connection between the wiring connection portion 4a and the sealing resin is reduced. Peeling can be suppressed. Further, when the adhesive force between the second sealing resin member and the first sealing resin member is low, even if a large warp occurs in the semiconductor device, the first sealing resin is exceeded when a certain stress is exceeded. Since peeling occurs at the interface between the member 1a and the second sealing resin member 1b, the shear stress between the terminal portion and the sealing resin can be reduced. At this time, the adhesive strength between the second sealing resin member and the first sealing resin member that seals the insulating substrate is set to 5 Mpa or less. Furthermore, in order to reduce the adhesive force, for example, a silicone-based release material may be applied to the surface on which the second sealing resin member is exposed, and the entire surface may be sealed with the first sealing resin member. Thus, by suppressing peeling between the terminal portion 3 and the sealing resin member 1, disconnection of the bonding wiring can be suppressed, and the highly reliable semiconductor device 100 can be obtained.
実施例1~4と比較例との対比.
 以下、本発明の効果を実施例1~4と比較例とを対比させて説明する。先ず、比較例に関わる端子部の構造を図12と図13に基づいて説明する。比較例では配線接続部4aと端子部3に高低差が設けられていない。すなわちこの電極端子構造では電極端子4の配線接続部4aと端子部3の上面3uが同一平面上に存在している。電極端子4は端子部3にインサートモールドされている。
Comparison between Examples 1 to 4 and Comparative Example.
The effects of the present invention will be described below by comparing Examples 1 to 4 with Comparative Examples. First, the structure of the terminal part regarding a comparative example is demonstrated based on FIG. 12 and FIG. In the comparative example, there is no difference in height between the wiring connection portion 4 a and the terminal portion 3. That is, in this electrode terminal structure, the wiring connection portion 4a of the electrode terminal 4 and the upper surface 3u of the terminal portion 3 exist on the same plane. The electrode terminal 4 is insert-molded in the terminal portion 3.
 評価試験用の半導体装置(モジュール)は、種々の材料と封止樹脂を用いて作製した。銅の金属板には、半導体素子2と半導体素子基板(セラミックス製)11をはんだ接合材を介して取り付けた。この金属板に、インサート成型により作製されたケース部材を接着剤により取り付けた。端子部はケース部材の上側に形成した。この仕掛品を線膨張係数が20であるエポキシ樹脂からなる液状封止樹脂を用いて封止し、150℃で2時間加熱をすることで評価用サンプルを作製した。この評価用サンプルに対し、各種のヒートサイクル試験を実行した。 The semiconductor device (module) for the evaluation test was manufactured using various materials and sealing resin. A semiconductor element 2 and a semiconductor element substrate (made of ceramics) 11 were attached to a copper metal plate via a solder bonding material. A case member produced by insert molding was attached to this metal plate with an adhesive. The terminal portion was formed on the upper side of the case member. This work in process was sealed with a liquid sealing resin made of an epoxy resin having a linear expansion coefficient of 20, and a sample for evaluation was produced by heating at 150 ° C. for 2 hours. Various heat cycle tests were performed on the sample for evaluation.
 実施例1~4および比較例に対応する評価用サンプルは複数個試作した。実施の形態1~4に対応する評価用サンプルでは、配線接続部4aと端子部3との高低差は3mmに設定してある。試作した半導体装置は全体を温度制御が可能な恒温曹に入れ、ヒートサイクル試験に供した。恒温曹の温度を調整し、複数の評価用サンプルのそれぞれを評価した。ヒートサイクル試験は高温時の恒温曹の温度を変えて2種類の条件で実施した。ヒートサイクル試験の第一条件は、評価用サンプルを-40℃で30分間保持し、その後125℃で30分間保持することを1サイクルとし、このサイクルを500回繰り返す。ヒートサイクル試験の第二条件は、評価用サンプルを-40で30分間保持し、その後150℃で30分間保持することを1サイクルとし、このサイクルを500回繰り返す。 A plurality of evaluation samples corresponding to Examples 1 to 4 and the comparative example were prototyped. In the samples for evaluation corresponding to the first to fourth embodiments, the height difference between the wiring connection portion 4a and the terminal portion 3 is set to 3 mm. The prototype semiconductor device was put in a thermostat capable of temperature control and subjected to a heat cycle test. The temperature of the thermostat was adjusted, and each of a plurality of evaluation samples was evaluated. The heat cycle test was carried out under two conditions by changing the temperature of the thermostat at high temperature. The first condition of the heat cycle test is that the evaluation sample is held at −40 ° C. for 30 minutes and then held at 125 ° C. for 30 minutes as one cycle, and this cycle is repeated 500 times. The second condition of the heat cycle test is that the evaluation sample is held at −40 for 30 minutes and then held at 150 ° C. for 30 minutes as one cycle, and this cycle is repeated 500 times.
 ヒートサイクル試験では、50サイクル毎に導通試験を実施した。故障が発見された場合には、超音波探傷装置による非破壊での剥離観察と、樹脂溶解剤にて封止樹脂を溶解した後の目視観察により、不具合の主原因を調査した。図14に、実施の形態1~4と比較例に対応する評価用サンプルにヒートサイクル試験を行った結果を示す。各種評価では3台の半導体装置を評価した。図では、ヒートサイクル試験の500サイクル後に行った導通試験において、3台全て合格した項目を○と記載し、1台もしくは2台合格した項目を△とし、合格にいたるものがなかった項目を×と記載している。 In the heat cycle test, a continuity test was performed every 50 cycles. When a failure was discovered, the main cause of the failure was investigated by non-destructive peeling observation with an ultrasonic flaw detector and visual observation after the sealing resin was dissolved with a resin dissolving agent. FIG. 14 shows the results of a heat cycle test performed on the evaluation samples corresponding to Embodiments 1 to 4 and the comparative example. In various evaluations, three semiconductor devices were evaluated. In the figure, in the continuity test conducted after 500 cycles of the heat cycle test, the items that passed all three units are indicated as ◯, the items that passed one or two units are indicated as △, and the items that did not pass are indicated as ×. It is described.
 先ず、比較例に対応する評価用サンプルの評価結果から説明する。ここでは配線接続部4aと端子部3とに高低差を設けない電極端子構造の半導体装置でヒートサイクル試験を実施した。第一条件(-40℃~125℃)の試験評価では、50サイクル後に導通不良が生じた。また、第二条件(-40℃~150℃)の試験評価では、100サイクル後に導通不良が生じた。すなわち、比較例に対応する評価用サンプルでは、第一条件および第二条件において、半導体装置が動作しなくなった。 First, the evaluation result of the evaluation sample corresponding to the comparative example will be described. Here, a heat cycle test was performed using a semiconductor device having an electrode terminal structure in which there is no difference in height between the wiring connection portion 4 a and the terminal portion 3. In the test evaluation under the first condition (−40 ° C. to 125 ° C.), conduction failure occurred after 50 cycles. Further, in the test evaluation under the second condition (−40 ° C. to 150 ° C.), conduction failure occurred after 100 cycles. That is, in the evaluation sample corresponding to the comparative example, the semiconductor device stopped operating under the first condition and the second condition.
 次に、実施の形態1に対応する評価用サンプルの評価結果について説明する。ここでは電極端子4の配線接続部4aが端子部よりも低い電極端子構造の半導体装置でヒートサイクル試験を実施した。第一条件(-40℃~125℃)の試験評価では、500サイクル後にも導通不良が生じず、半導体装置が正常に動作することがわかった。また、第二条件(-40℃~150℃)の試験評価においても、500サイクル後には導通不良が生じず、半導体装置が正常に動作することがわかった。 Next, the evaluation result of the evaluation sample corresponding to the first embodiment will be described. Here, the heat cycle test was performed with a semiconductor device having an electrode terminal structure in which the wiring connection portion 4a of the electrode terminal 4 is lower than the terminal portion. In the test evaluation under the first condition (−40 ° C. to 125 ° C.), it was found that no conduction failure occurred even after 500 cycles, and the semiconductor device operated normally. Also in the test evaluation under the second condition (−40 ° C. to 150 ° C.), it was found that no conduction failure occurred after 500 cycles and the semiconductor device operated normally.
 次に、実施の形態2に対応する評価用サンプルの評価結果について説明する。ここでは、電極端子4の配線接続部4aが端子部よりも低い電極端子構造を持ち、半導体素子基板を封止する樹脂とは異なる封止樹脂を電極端子上に部分的に封止した半導体装置でヒートサイクル試験を実施した。第一条件(-40℃~125℃)の試験評価でも、500サイクル後で導通不良が生じず、半導体装置が正常に動作することがわかった。また、第二条件(-40℃~150℃)の試験評価においても、500サイクル後には導通不良が生じず、半導体装置が正常に動作することがわかった。 Next, the evaluation result of the evaluation sample corresponding to the second embodiment will be described. Here, the semiconductor device in which the wiring connection part 4a of the electrode terminal 4 has an electrode terminal structure lower than the terminal part, and a sealing resin different from the resin for sealing the semiconductor element substrate is partially sealed on the electrode terminal The heat cycle test was carried out. Even in the test evaluation under the first condition (−40 ° C. to 125 ° C.), it was found that no conduction failure occurred after 500 cycles and the semiconductor device operated normally. Also in the test evaluation under the second condition (−40 ° C. to 150 ° C.), it was found that no conduction failure occurred after 500 cycles and the semiconductor device operated normally.
 さらに、実施の形態3に対応する評価用サンプルの評価結果について説明する。ここでは電極端子4の配線接続部4aが端子部よりも高い電極端子構造の半導体装置でヒートサイクル試験を実施した。第一条件(-40℃~125℃)の試験評価では、500サイクル後にも導通不良が生じず、半導体装置が正常に動作することがわかった。しかし、第二条件(-40℃~150℃)の試験評価においては、一部の半導体装置で400サイクル後に導通不良が生じており、半導体装置が動作しなくなることがわかった。 Furthermore, the evaluation result of the evaluation sample corresponding to the third embodiment will be described. Here, a heat cycle test was performed using a semiconductor device having an electrode terminal structure in which the wiring connection portion 4a of the electrode terminal 4 is higher than the terminal portion. In the test evaluation under the first condition (−40 ° C. to 125 ° C.), it was found that no conduction failure occurred even after 500 cycles, and the semiconductor device operated normally. However, in the test evaluation under the second condition (−40 ° C. to 150 ° C.), it was found that some semiconductor devices had poor conduction after 400 cycles, and the semiconductor devices stopped operating.
 さらに、実施の形態4に対応する評価用サンプルの評価結果について説明する。ここでは電極端子4の配線接続部4aが端子部よりも低い電極端子構造を持つ半導体装置を用いた。第2の封止樹脂部材には、半導体素子基板を封止する第1の封止樹脂部材よりも弾性率の低い封止樹脂を用いる。先ず、ゴム材料を編成することで弾性率を低下させた第2の封止樹脂を電極端子上に部分的に封止し、100℃/1hrで半硬化させた。その後、第2の封止樹脂が露呈している面へシリコーン系離型材を塗布し、第1の封止樹脂で全面を封止した。以上の条件で作成した半導体装置でヒートサイクル試験を実施した。第一条件(-40℃~125℃)の試験評価でも、500サイクル後で導通不良が生じず、半導体装置が正常に動作することがわかった。また、第二条件(-40℃~150℃)の試験評価においても、500サイクル後には導通不良が生じず、半導体装置が正常に動作することがわかった。 Furthermore, the evaluation result of the evaluation sample corresponding to the fourth embodiment will be described. Here, a semiconductor device having an electrode terminal structure in which the wiring connection portion 4a of the electrode terminal 4 is lower than the terminal portion is used. For the second sealing resin member, a sealing resin having a lower elastic modulus than that of the first sealing resin member for sealing the semiconductor element substrate is used. First, the second sealing resin whose elastic modulus was lowered by knitting a rubber material was partially sealed on the electrode terminal and semi-cured at 100 ° C./1 hr. Thereafter, a silicone release material was applied to the surface where the second sealing resin was exposed, and the entire surface was sealed with the first sealing resin. A heat cycle test was conducted on the semiconductor device created under the above conditions. Even in the test evaluation under the first condition (−40 ° C. to 125 ° C.), it was found that no conduction failure occurred after 500 cycles and the semiconductor device operated normally. Also in the test evaluation under the second condition (−40 ° C. to 150 ° C.), it was found that no conduction failure occurred after 500 cycles and the semiconductor device operated normally.
 これらの結果より、配線接続部4aと端子部に高低差を設けることによって、ヒートサイクルによる封止樹脂の膨張と収縮においても断線を生じない信頼性の高い半導体装置を作製できることが示された。また、電極端子の配線接続部4aは端子部よりも高く設定するよりも低く設定するほうが、より信頼性の高い半導体装置を作製できることが判明した。 From these results, it was shown that by providing a height difference between the wiring connection portion 4a and the terminal portion, a highly reliable semiconductor device that does not break even when the sealing resin expands and contracts due to heat cycle can be manufactured. It has also been found that a semiconductor device with higher reliability can be manufactured by setting the wiring connection portion 4a of the electrode terminal lower than setting it higher than the terminal portion.
 半導体素子にSiCを用いた場合、電力半導体素子はその特徴を生かすべくSiの時と比較してより高温で動作させることになる。SiCデバイスを搭載するパワーモジュールにおいては、半導体素子としてより高い信頼性が求められるため、高信頼のパワーモジュールを実現するという本発明のメリットはより効果的なものとなる。 When SiC is used for the semiconductor element, the power semiconductor element is operated at a higher temperature than that of Si in order to take advantage of its characteristics. In a power module equipped with a SiC device, higher reliability is required as a semiconductor element. Therefore, the merit of the present invention for realizing a highly reliable power module becomes more effective.
 なお、本発明は、その発明の範囲内において、実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。 In the present invention, it is possible to freely combine the embodiments within the scope of the invention, and to appropriately modify and omit each embodiment.
1 封止樹脂部材、2 半導体素子、2a 半導体素子、2b 半導体素子、2o 表側電極、2u 裏側電極、3 端子部、3a 窪み、3b 入り口、3c 敷居、3d 段、3l 底面、3o 奥面、3p 側面、3q 側面、3t 天面、3u 上面、4 電極端子、4a 配線接続部、6 ボンディング配線、7 ケース部材、8 第一電極パターン、9 第二電極パターン、10 絶縁性基板、10a 第一主面、10b 第二主面、11 半導体素子基板、11a 第一余白部、11b 第二余白部、12 接合材、13 ベース板、14 接着剤、15 封止樹脂部材、100 半導体装置。
 
DESCRIPTION OF SYMBOLS 1 Sealing resin member, 2 semiconductor element, 2a semiconductor element, 2b semiconductor element, 2o front side electrode, 2u back side electrode, 3 terminal part, 3a hollow, 3b entrance, 3c threshold, 3d step, 3l bottom face, 3o back face, 3p Side surface, 3q side surface, 3t top surface, 3u top surface, 4 electrode terminal, 4a wiring connection part, 6 bonding wiring, 7 case member, 8 first electrode pattern, 9 second electrode pattern, 10 insulating substrate, 10a first main Surface, 10b Second main surface, 11 Semiconductor element substrate, 11a First margin, 11b Second margin, 12 Bonding material, 13 Base plate, 14 Adhesive, 15 Sealing resin member, 100 Semiconductor device.

Claims (13)

  1.  第一主面には第一電極パターンが形成されており、第二主面には第二電極パターンが形成されている絶縁性基板と、
    前記絶縁性基板の第一電極パターンに接合されているベース板と、
    表側電極と裏側電極を有し、前記絶縁性基板の第二電極パターンに前記裏側電極が接合されている半導体素子と、
    窪みが形成されている端子部を有する樹脂製のケース部材と、
    前記ケース部材に固定されていて、配線接続部が前記窪みの底面から露呈している電極端子と、
    前記電極端子の配線接続部と前記半導体素子の表側電極を接続するボンディング配線と、
    前記ケース部材の内側に充填され、前記絶縁性基板と前記半導体素子と前記ボンディング配線を封止する封止樹脂部材と、を備え、
    前記端子部に形成されている窪みには前記ボンディング配線の入り口が設けられていて、前記入り口は装置内側を向きかつ開放されている半導体装置。
    An insulating substrate having a first electrode pattern formed on the first main surface and a second electrode pattern formed on the second main surface;
    A base plate bonded to the first electrode pattern of the insulating substrate;
    A semiconductor element having a front side electrode and a back side electrode, wherein the back side electrode is bonded to the second electrode pattern of the insulating substrate;
    A resin case member having a terminal portion in which a depression is formed;
    An electrode terminal that is fixed to the case member and the wiring connection part is exposed from the bottom surface of the depression;
    Bonding wiring for connecting the wiring connection portion of the electrode terminal and the front side electrode of the semiconductor element;
    A sealing resin member that is filled inside the case member and seals the insulating substrate, the semiconductor element, and the bonding wiring;
    A semiconductor device in which an entrance for the bonding wiring is provided in a recess formed in the terminal portion, and the entrance faces the inside of the device and is open.
  2.  前記端子部に形成されている窪みは、前記入り口から奥面まで、幅が同じであることを特徴とする請求項1に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the depression formed in the terminal portion has the same width from the entrance to the back surface.
  3.  前記端子部に形成されている窪みは、前記入り口から奥面に向かうほど、幅が広くなっていることを特徴とする請求項1に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the recess formed in the terminal portion becomes wider as it goes from the entrance to the back surface.
  4.  前記端子部に形成されている窪みは、前記入り口に敷居が設けられていることを特徴とする請求項1に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the depression formed in the terminal portion is provided with a threshold at the entrance.
  5.  前記端子部に形成されている窪みは、前記電極端子の配線接続部を被覆する樹脂が充填されていることを特徴とする請求項4に記載の半導体装置。 5. The semiconductor device according to claim 4, wherein the depression formed in the terminal portion is filled with a resin covering the wiring connection portion of the electrode terminal.
  6.  前記封止樹脂部材は、前記絶縁性基板を封止する第1の封止樹脂部材と、前記電極端子の配線接続部を被覆する第2の封止樹脂部材を含み、
     前記第1の封止樹脂部材と前記第2の封止樹脂部材は、異なる材料からなることを特徴とする請求項1に記載の半導体装置。  
    The sealing resin member includes a first sealing resin member that seals the insulating substrate, and a second sealing resin member that covers a wiring connection portion of the electrode terminal,
    The semiconductor device according to claim 1, wherein the first sealing resin member and the second sealing resin member are made of different materials.
  7.  前記第2の封止樹脂部材は、前記第1の封止樹脂部材よりも弾性率が低いことを特徴とする請求項6に記載の半導体装置。 The semiconductor device according to claim 6, wherein the second sealing resin member has an elastic modulus lower than that of the first sealing resin member.
  8.  前記第2の封止樹脂部材と前記第1の封止樹脂部材との接着強度は、5Mpa以下であることを特徴とする請求項6に記載の半導体装置。 The semiconductor device according to claim 6, wherein an adhesive strength between the second sealing resin member and the first sealing resin member is 5 Mpa or less.
  9.  第一主面には第一電極パターンが形成されており、第二主面には第二電極パターンが形成されている絶縁性基板と、
    前記絶縁性基板の第一電極パターンに接合されているベース板と、
    表側電極と裏側電極を有し、前記絶縁性基板の第二電極パターンに前記裏側電極が接合されている半導体素子と、
    周囲から突出した段が形成されている端子部を有する樹脂製のケース部材と、
    前記ケース部材に固定されていて、配線接続部が前記端子部に形成されている段から露呈している電極端子と、
    前記電極端子の配線接続部と前記半導体素子の表側電極を接続するボンディング配線と、
    前記ケース部材の内側に充填され、前記絶縁性基板と前記半導体素子と前記ボンディング配線を封止する封止樹脂部材と、を備えている半導体装置。
    An insulating substrate having a first electrode pattern formed on the first main surface and a second electrode pattern formed on the second main surface;
    A base plate bonded to the first electrode pattern of the insulating substrate;
    A semiconductor element having a front side electrode and a back side electrode, wherein the back side electrode is bonded to the second electrode pattern of the insulating substrate;
    A resin case member having a terminal portion formed with a step protruding from the periphery;
    An electrode terminal fixed to the case member and exposed from the step where the wiring connection portion is formed in the terminal portion;
    Bonding wiring for connecting the wiring connection portion of the electrode terminal and the front side electrode of the semiconductor element;
    A semiconductor device comprising: a sealing resin member filled inside the case member and sealing the insulating substrate, the semiconductor element, and the bonding wiring.
  10.  前記半導体素子の少なくとも一部がワイドバンドギャップ半導体により形成されていることを特徴とする請求項1から9のいずれか1項に記載の半導体装置。 10. The semiconductor device according to claim 1, wherein at least a part of the semiconductor element is formed of a wide band gap semiconductor.
  11.  前記ワイドバンドギャップ半導体は、炭化珪素,窒化ガリウム系材料,ダイヤモンドのいずれかの半導体であることを特徴とする請求項10に記載の半導体装置。 11. The semiconductor device according to claim 10, wherein the wide band gap semiconductor is one of silicon carbide, a gallium nitride-based material, and diamond.
  12.  第一主面には第一電極パターンが形成されており、第二主面には第二電極パターンが形成されている絶縁性基板と、
    前記絶縁性基板の第一電極パターンに接合されているベース板と、
    表側電極と裏側電極を有し、前記絶縁性基板の第二電極パターンに前記裏側電極が接合されている半導体素子と、
    周囲に対して段差部が形成されている端子部を有する樹脂製のケース部材と、
    前記ケース部材に固定されていて、配線接続部が前記端子部に形成されている段差部から露呈している電極端子と、
    前記電極端子の配線接続部と前記半導体素子の表側電極を接続するボンディング配線と、
    前記ケース部材の内側に充填され、前記絶縁性基板と前記半導体素子と前記ボンディング配線を封止する封止樹脂部材と、を備えている半導体装置。
    An insulating substrate having a first electrode pattern formed on the first main surface and a second electrode pattern formed on the second main surface;
    A base plate bonded to the first electrode pattern of the insulating substrate;
    A semiconductor element having a front side electrode and a back side electrode, wherein the back side electrode is bonded to the second electrode pattern of the insulating substrate;
    A resin case member having a terminal portion in which a stepped portion is formed with respect to the periphery;
    An electrode terminal which is fixed to the case member and exposed from a stepped portion where the wiring connection portion is formed in the terminal portion;
    Bonding wiring for connecting the wiring connection portion of the electrode terminal and the front side electrode of the semiconductor element;
    A semiconductor device comprising: a sealing resin member filled inside the case member and sealing the insulating substrate, the semiconductor element, and the bonding wiring.
  13.  前記封止樹脂部材は、エポキシ樹脂からなることを特徴とする請求項1、9、12のいずれか1項に記載の半導体装置。
     
    The semiconductor device according to claim 1, wherein the sealing resin member is made of an epoxy resin.
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016100475A (en) * 2014-11-21 2016-05-30 富士電機株式会社 Semiconductor device
WO2018087890A1 (en) * 2016-11-11 2018-05-17 三菱電機株式会社 Semiconductor device, inverter unit, and automobile
WO2018096656A1 (en) * 2016-11-25 2018-05-31 三菱電機株式会社 Semiconductor device
WO2018100600A1 (en) * 2016-11-29 2018-06-07 三菱電機株式会社 Semiconductor device, control device, and method for manufacturing semiconductor device
JP2019161083A (en) * 2018-03-15 2019-09-19 富士電機株式会社 Semiconductor device
DE112018004816T5 (en) 2017-09-05 2020-06-10 Mitsubishi Electric Corporation PERFORMANCE MODULE, METHOD FOR PRODUCING THE SAME AND PERFORMANCE CONVERTER
JP2020098885A (en) * 2018-12-19 2020-06-25 富士電機株式会社 Semiconductor device
US10971414B2 (en) 2019-03-11 2021-04-06 Fuji Electric Co., Ltd. Semiconductor device
WO2021261056A1 (en) * 2020-06-26 2021-12-30 株式会社日立パワーデバイス Power module
US11227808B2 (en) 2017-09-05 2022-01-18 Mitsubishi Electric Corporation Power module and method for fabricating the same, and power conversion device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61264732A (en) * 1985-05-20 1986-11-22 Oki Electric Ind Co Ltd Package for integrated circuit
JPH0855941A (en) * 1994-08-15 1996-02-27 Nagase Chiba Kk Electronic part sealing resin package and epoxy resin composition used for it
JPH0922973A (en) * 1995-07-07 1997-01-21 Mitsubishi Electric Corp Semiconductor device
JPH1050897A (en) * 1996-08-02 1998-02-20 Toshiba Corp Semiconductor device
JPH1084009A (en) * 1996-09-09 1998-03-31 Toshiba Corp Semiconductor device
JP2000353777A (en) * 1999-06-09 2000-12-19 Yazaki Corp Power semiconductor module and manufacture thereof
JP2001144251A (en) * 1999-11-15 2001-05-25 Nippon Inter Electronics Corp Composite semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6053060A (en) * 1983-09-02 1985-03-26 Hitachi Micro Comput Eng Ltd Semiconductor device and manufacture thereof
JP2009252838A (en) * 2008-04-02 2009-10-29 Mitsubishi Electric Corp Semiconductor device
CN104145333B (en) * 2012-04-16 2018-02-02 富士电机株式会社 Semiconductor device and semiconductor device cooler

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61264732A (en) * 1985-05-20 1986-11-22 Oki Electric Ind Co Ltd Package for integrated circuit
JPH0855941A (en) * 1994-08-15 1996-02-27 Nagase Chiba Kk Electronic part sealing resin package and epoxy resin composition used for it
JPH0922973A (en) * 1995-07-07 1997-01-21 Mitsubishi Electric Corp Semiconductor device
JPH1050897A (en) * 1996-08-02 1998-02-20 Toshiba Corp Semiconductor device
JPH1084009A (en) * 1996-09-09 1998-03-31 Toshiba Corp Semiconductor device
JP2000353777A (en) * 1999-06-09 2000-12-19 Yazaki Corp Power semiconductor module and manufacture thereof
JP2001144251A (en) * 1999-11-15 2001-05-25 Nippon Inter Electronics Corp Composite semiconductor device

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016100475A (en) * 2014-11-21 2016-05-30 富士電機株式会社 Semiconductor device
US10770376B2 (en) 2016-11-11 2020-09-08 Mitsubishi Electric Corporation Semiconductor device, inverter unit and automobile
WO2018087890A1 (en) * 2016-11-11 2018-05-17 三菱電機株式会社 Semiconductor device, inverter unit, and automobile
JPWO2018087890A1 (en) * 2016-11-11 2019-06-24 三菱電機株式会社 Semiconductor device, inverter unit and automobile
CN109952639A (en) * 2016-11-11 2019-06-28 三菱电机株式会社 Semiconductor device, inverter unit and automobile
CN109952639B (en) * 2016-11-11 2023-06-27 三菱电机株式会社 Semiconductor device, inverter unit, and automobile
WO2018096656A1 (en) * 2016-11-25 2018-05-31 三菱電機株式会社 Semiconductor device
JPWO2018096656A1 (en) * 2016-11-25 2019-04-11 三菱電機株式会社 Semiconductor device
WO2018100600A1 (en) * 2016-11-29 2018-06-07 三菱電機株式会社 Semiconductor device, control device, and method for manufacturing semiconductor device
JPWO2018100600A1 (en) * 2016-11-29 2019-03-07 三菱電機株式会社 Semiconductor device, control device, and method of manufacturing semiconductor device
US11227808B2 (en) 2017-09-05 2022-01-18 Mitsubishi Electric Corporation Power module and method for fabricating the same, and power conversion device
DE112018004816T5 (en) 2017-09-05 2020-06-10 Mitsubishi Electric Corporation PERFORMANCE MODULE, METHOD FOR PRODUCING THE SAME AND PERFORMANCE CONVERTER
JP7183551B2 (en) 2018-03-15 2022-12-06 富士電機株式会社 semiconductor equipment
JP2019161083A (en) * 2018-03-15 2019-09-19 富士電機株式会社 Semiconductor device
CN111341731A (en) * 2018-12-19 2020-06-26 富士电机株式会社 Semiconductor device with a plurality of semiconductor chips
JP2020098885A (en) * 2018-12-19 2020-06-25 富士電機株式会社 Semiconductor device
JP7247574B2 (en) 2018-12-19 2023-03-29 富士電機株式会社 semiconductor equipment
US10971414B2 (en) 2019-03-11 2021-04-06 Fuji Electric Co., Ltd. Semiconductor device
WO2021261056A1 (en) * 2020-06-26 2021-12-30 株式会社日立パワーデバイス Power module
JP7469969B2 (en) 2020-06-26 2024-04-17 株式会社 日立パワーデバイス Power Module

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