WO2015147620A1

WO2015147620A1 - Copper metallisation method intended for the production of an integrated circuit using 3d wafer-level packaging technology

Info

Publication number: WO2015147620A1
Application number: PCT/MA2014/000055
Authority: WO
Inventors: Sbiaa; Said Zahraoui
Original assignee: Nemotek Technologies S.A
Priority date: 2013-10-14
Filing date: 2014-12-15
Publication date: 2015-10-01
Also published as: MA20150146A1; MA36343B1

Abstract

The invention relates to a method for the copper metallisation of redistribution layers and cavities in a semiconductor substrate, such as through-silicon vias, in particular for the production of integrated circuits in general and of an image sensor in particular, using 3D wafer-level packaging technology.

Description

PREAMBLE

The present invention relates to a method of copper metallization of the RDL connection lines 32 and cavities of a semiconductor substrate such as through vias (Through Silicon Vias), especially for the manufacture of integrated circuits in general and image sensors in particular, using the use of Wafer-LevelPackaging technology (FIG 1A) in three dimensions (3D).

Currently existing processes in the state of the art offers aluminum-based metallization for the manufacture of integrated circuits, provides a deposit of a non-compliant layer, discontinuous bottom vias always less accessible to the deposit the walls of the vias, so that the thickness of the aluminum layer to be deposited at the bottom of the vias is always lower than the layer thickness at the other levels of the deposit, whether on the walls of the vias. vias, at the opening of the vias or on the surface of the substrate.

The uneven distribution of the deposition of the aluminum layer on the surface of the vias has a limitation in the shape and size of the vias, resulting in the use of truncated vias whose opening is wider than the bottom , and this to reduce the non-compliance of the deposit.

To repair the discontinuity of aluminum deposition it is necessary to cover the connection lines (RDL) by a thin layer of Nickel (barrier) which will repair the discontinuity of deposition of aluminum at the bottom of the vias, then the connection lines (RDL) are treated by Electroless Nickel Immersion Gold (ENIG) process comprising the deposition of a nickel-phosphorus layer and the gold "immersion" step during which the gold adheres to the nickel-plated zones.

This metallization process based on aluminum existing in the state of the art for the manufacture of integrated circuits has the disadvantage of being inefficient for industrial application, being characterized by its very high cost for the production of said integrated circuit and by the electrical performance that is not the best of said integrated circuit.

It is the object of the present invention to overcome the drawbacks of the prior art, in the case of a new method of copper-based metallization of connection lines and through vias for the manufacture of integrated circuits, the said process will make it possible to reduce the cost of production, to have an increase in electrical performance thanks to the application of copper for metallization with a resistivity of 1.7Ω-cm instead of aluminum with a resistivity of 2 , 7Q-cm, especially for the realization of interconnections in integrated circuits in three dimensions. It is necessary for the metallization to apply a most efficient process industrially and the most economical possible, especially not to achieve a very high cost of the commercial device or said integrated circuit or image sensor will be incorporated. The description which follows refers to the appended figures which represent respectively:

FIG.1A: an integrated circuit or Wafer Level Packaging image sensor in three dimensions

FIG.1B: a partial view at the level of the "RDL" connection lines 32 and vias traversing 34

FIG. 2A: a resin cavity formed on a glass substrate. FIG. 2B: front face of the semiconductor substrate 26

FIG2.C: an association of the elements of FIG. 2A and those of FIG. 2B

FIG. 2D: the photosensitive zone matrix 38 enclosed between the semiconductor substrate and the transparent substrate

FIG. 3A: sectional view and overall view of the thinning of the rear face 26 of the semiconductor substrate

FIG. 3B: sectional view and overall view of the etchings of the slices 36 and via via 34

FIG. 3C: sectional view and overall view of the coating of the rear face of the substrate by a passivation layer.

FIG. 3D: sectional view and overall view of the connection lines formed on the rear face of the semiconductor substrate.

FIG. 3E: sectional view and overall view of the deposition of a passivation layer 22 on the connection lines.

FIG. 3F: sectional view and overall view of the deposition of the weldable bosses 20 on the bare portions of the portion of the connection lines 32 "RDL" FIG. 4A: sectional view of the deposition of a barrier layer 32. e

FIG. 4B: sectional view of the deposition of a copper seed layer 32.f

FIG. 4C: sectional view of the deposition of a thick copper layer 32.g

FIG. 4D: sectional view of the metallization layer after the photolithography process. The area protected by the resin will form the connection lines thereafter. FIG. 4E: sectional view of the metallization layer after the wet etching of the copper. FIG. 4F: sectional view of the connection lines after wet etching of the titanium barrier layer, and after stripping of the photoresist.

FI6.5A: sectional view of a barrier layer 32. e deposited on a substrate 26

FIG. 5B: sectional view of a copper seed layer 32. f deposited the barrier layer.

FIG. 5C: sectional view of the substrate 26 previously covered by a seed layer, after the photolithography process, the bare zone will form the connection lines thereafter.

FIG. 5D: sectional view of the copper filling of the connection lines. FIG. 5E: sectional view of the connection lines, after stripping of the resin.

FIG. 5F: sectional view of the connection lines after wet etching of titanium barrier layer.

DESCRIPTION OF THE INVENTION

The present invention is a new copper-based metallization process connecting lines and through vias for the manufacture of an integrated circuit in general and an image sensor especially for the realization interconnections in integrated circuits in three dimensions, the said process will allow to reduce the production cost, to have an increase in the electrical performance of said integrated circuit through the application of copper for metallization with a resistivity of l, 7Q-cm instead of aluminum with a resistivity of 2,7Q-cm.

This method of metallization of the connection lines and through vias of an integrated circuit in general and of an image sensor in particular comprises:

The formation of resin cavities 28 on a transparent support substrate 30, using a photolithography process (FIG. 2A). In a first step, the front face of the semiconductor substrate 26 of which is formed a matrix of photosensitive zones 38 (active zone) and associated electronic circuits, said photosensitive zone matrix is glued against the transparent support substrate in order to protect the said photosensitive matrix during the metallization process (FIG 2B), and it is the rear face of the semiconductor substrate, which remains accessible to the metallization of image sensor, while the front face is inaccessible, enclosed between the substrate semiconductor and the transparent support substrate (FIG 2C-2D). The thinning by mechanical polishing of the rear face of the semiconductor substrate 26, for example, for a substrate of 20 centimeters in diameter; the thickness of the substrate is about 750 micrometers before thinning, then 100 micrometers after thinning. The successive etchings, slices 36 and vias 34 by plasma (FIG 3B). The vias are formed to electrically connect "RDL" connection lines to metal pads 40 (FIG 1A-2D) forming part of the electronic circuits associated with the photosensitive matrix.

In all that precedes and in what follows, the front face of the semiconductor substrate will be called the face on which the photosensitive matrix 38 has been formed. The rear face of the substrate, which has undergone successive thinning and etching. It is through the front panel that the sensor receives a bright image to convert into an electronic image. It is the rear face which carries the connection lines 32 (FIG 3D) and vias through 34 (FIG 3B), we also call the connection lines by RDL.

A passivation layer 24 (FIG 3C), which covers the entire back surface of the thinned substrate forming an electrically insulating layer, is then deposited, the passivation layer generally consisting of a silicon derivative such as silicon oxide or nitride. , or an insulating polymer. Silicon oxide is generally deposited in the vapor phase (referred to as "Chemical Vapor Deposition" or CVD). The insulating polymer 24 is sputtered as "Spray" in English (FIG 3C). After having deposited a passivation layer and before carrying out the metallization, holes are drilled in the metal pads 40 (FIG 1A-3B) at the bottom of the vias.

This copper-based metallization process, comprising: depositing a titanium-based barrier layer, a possible copper seed layer, and a thick layer of copper. The steps of deposition of the barrier layer, of a possible seed layer and the electroplating of copper are commonly referred to together by the expression metallization.

The metallization process in copper according to a first embodiment is shown diagrammatically in FIGS. 4A to 4F represent the steps of the metallization process. After having deposited the passivation layer 24, it is necessary to deposit a titanium diffusion barrier layer 32. e of about a hundred nanometers, which will prevent the migration of copper atoms under the effect of the densities of electric current applied during the operation of the integrated circuit (FIG.4A); - The titanium barrier layer is generally deposited by sputtering said "sputtering" is a vacuum thin layer deposition method; Other materials may act as a diffusion barrier, for example tantalum (Ta), nickel (Ni), nickel-boron alloy (NiB), nickel-phosphorus alloy (NiP), tantalum nitride (TaN), nitride titanium (Ti), titanium-tungsten alloy (TiW) or the combination of these materials;

Subsequently, a so-called "Seed Layer" seed layer 32.f is deposited in highly conductive copper, the layer 32.f is deposited by cathodic sputtering, this layer can also be deposited electrolessly or electrolytically (FIG. 4B);

Then a thick layer of copper 32.g of a few micrometers can be deposited by electrodeposition on the entire back side of the semiconductor substrate (FIG.4C). The electroplating is carried out by passing a current between the substrate to be coated constituting a first electrode, and a second copper electrode placed in a bath containing the copper ions, and optionally various agents intended to improve the properties of the formed coating such as that the regularity, the resistivity and the finesse of the deposit;

This copper deposit will subsequently undergo a heat treatment of 150 ° C for 30 min under an inert atmosphere (N2 or N2 + H2 mixture 5% H2) to evaporate any moisture thus organic adsorbed on the deposition surface;

The connection lines 32 are etched on the metallization layer, using a photolithography process (FIG 4D-4F), the connection lines 32 "RDL" are electrically isolated from each other, which will be used to the formation of the sensor input / output pads, (FIG 3D) represents the sectional view of the metallization layer, thus the overall view of the rear face of the semiconductor substrate after the etching steps;

The steps of the photolithography process begin with the application of a photoresist 42 in the form of a thin film on the surface of a substrate. The photoresist film is obtained by a wet spray process called "spray". It is then exposed to UV radiation, the irradiated areas will see their solubility evolve depending on the type of positive or negative resin. The specific solvents contained in the developer will make it possible to eliminate the resin exposed or not, depending on its solubility. During this step, the use of a mask, formed of opaque and transparent zones, makes it possible to define the RDL pattern that one wishes to reproduce on the seed layer 32.f (FIG.

The wet etching of the copper layer 32.g and the sprouting layer 32.f in the areas not coated with the photoresist (Fig.4E); Wet etching of the titanium layer 32. e in the areas not coated with the photoresist (Fig.4F);

Photo-resin etching which coated copper connection lines (RDL) 42 (Fig.4F);

- A passiyation layer 22 deposited on the entire metallized face, which is the back face of the semiconductor substrate, this passivation layer is then etched next to the RDL which will serve as solder pads (FIG 3E) and weldable bosses 20, referred to as "solder bumps", are deposited on the bare portions of RDL portions by a screen printing process (FIG 3F);

- After all these operations, performed collectively, one can proceed to the cutting of the plate (wafer) in individual chips each corresponding to an image sensor. These chips are coupled with lenses to form miniature cameras and then mounted in housings. The copper metallization method according to a second embodiment is shown diagrammatically in FIGS. 5A to 5F representing the steps of the metallization process:

The titanium barrier layer 32. e and the copper seed layer 32. f (FIG.4A-4B) are generally deposited similarly to the first embodiment (FIG.4A-4B);

The connection lines (RDL) are printed on the seed layer 32.f, using a photolithography process (FIG.

The steps of the photolithography process begin with the application of a photoresist layer 42 in the form of a thin film on the surface of a substrate. The photo-resin film is obtained by a wet spray process called "spray". The said surface is then exposed to UV radiation, and the irradiated zones will have their solubility evolve according to the type of resin - positive or negative. The specific solvents contained in the developer will make it possible to eliminate the resin exposed or not, depending on its solubility. In this step, a mask is used which makes it possible to form opaque and transparent zones in order to define the RDL pattern which it is desired to reproduce on the seed layer 32.f (FIG.

Subsequently, a 32 micron copper layer is deposited electrochemically by a few microns, this time the copper is deposited only on the bare zones of the seed layer 32.f (FIG. 5D);

The next step is stripping photoresist 42, as well as etching the two layers below to electrically separate the connecting lines 32g from each other (FIG.5F).

Etching the copper layer 32.g and the seed layer 32.f in the zones not coated with the photoresist (FIG. 5E);

Etching of the titanium layer 32. e in the areas not coated with the photoresist; Heat treatment of the 32g copper deposit (FIG. 5E) contained in the connection lines (RDL) 32 and in the through vias 34 (FIG. 1A-1B) intended to evaporate all the organic humidities thus adsorbed on the deposition surface (Fig.SF); this heat treatment is carried out at a temperature of 150 ° C for 30 minutes under an inert atmosphere (containing N2 or a mixture N2 + H2 at 5% H2);

A passivation layer 22 deposited on the entire metallized face, which is, it will be remembered, this passivation layer is then etched opposite the RDLs which will serve as solder pads (FIG 3E), then solderable bosses 20 called " solder bumps are deposited on the bare portions of RDL portions by a screen printing process (FIG 3F).

After all these operations, performed collectively, it is possible to cut the plate (wafer) in individual chips each corresponding to an image sensor. These chips are coupled with lenses to form miniature cameras and then mounted in housings.

The method according to the invention having mainly applications in the manufacture of very small image sensors for making cameras with a very high degree of miniaturization, such as that which one may want to incorporate into a mobile phone.

Claims

1 - Method of metallization copper-based connection line (RDL) 32 (Fig.lA) and vias through 34 (Fig.lA) for the manufacture of an integrated circuit in general and a sensor of image in particular using Wafer Level Packaging 3D technology to have better electrical performance at said image sensor, comprising the first three steps of:

- Dry etching vias 34 (Fig.lA) and slices 36 (Fig.3B);

- Coating the silicon substrate with an insulating film 24 (Fig.3C) generally made of silicon oxide or an insulating polymer;

Drilling the bottom of vias 34 (Fig.3B) and (Fig.3C) at the metal pads using a laser;

Subsequently, in the three preceding steps, the said process is characterized by the following succession of steps: a- depositing a barrier layer 32e (FIG. 4A) preventing the migration of the copper, b-coating with a seed coat 32.f ( FIG. 4B) the barrier layer 32 e (FIG. 4A) for reducing the resistance of said barrier layer,

c- fill by the copper 32.g (Fig.4C) connection lines (RDL) 32 (Fig.lA) and

(Fig. 3D) and through vias 34 (Fig.lA) and (Fig.3B) by electroplating.

thermally treating the copper deposit 32.g (FIG. 4C) contained in the connecting lines (RDL) 32 (FIG. 1A) and (FIG. 3D) and in the through vias 34 (FIG.

(Fig.3B) for the purpose of evaporating any organic moisture thus adsorbed on the deposition surface.

e-printing on the surface of the copper connection lines (RDL) 32.g by photolithography method 42 (Fig.4D);

f-etch the copper layer 32.g and the seed layer 32.f in the areas not coated with the photoresist (Fig.4E);

g- engrave the titanium layer 32. e in the areas not coated with the photoresist

(Fig. 4F);

h- etch the photo-resin of the connection lines (RDL) 42 (Fig.4F).

2- metallization process according to claim 1, characterized in that the barrier layer 32.e (Fig.4A) being deposited by sputtering or by autocatalytic means and comprises at least one of these selected materials among titanium (Ti), tantalum (Ta), nickel (Ni), nickel-boron alloy (NiB), nickel-phosphorus alloy (NiP), tantalum nitride (TaN), titanium nitride (TiN), titanium alloy tungsten (TiW).

3- metallization process according to claim 1, is characterized in that the 32.f copper copper seed layer (Fig.4B) is deposited by means of one of the methods chosen from sputtering, auto-catalytic, electrolytic sputtering . 4- A method for metallization according to ^'claim 1 is characterized in that the heat treatment of the copper plating 32. g (4c) contained in the connecting lines (RDL) 32 and the through vias 34 (Fig. lA) and (Fig.lB) is carried out at a temperature of 150 ° C for 30 minutes under an inert atmosphere (containing N2 or a mixture N2 + H2 at 5% H2).

5. metallization method according to claim 1, is characterized in that the etching of the copper layer 32.g (Fig.4E), germination 32.f (Fig.4E) and titanium 32. e (Fig. 4F) is achieved by wet chemical etching.

6 - According to another embodiment of the metallization metallization process of copper connection (RDL) 32 (Fig.lA) and through vias 34 (Fig.lA) for the manufacture of an integrated circuit in general and an image sensor using Wafer Level Packaging 3D technology to provide better electrical performance at said image sensor, comprising the first three steps of:

- Dry etching of vias 34 (Fig.lA) and slices 36 (Fig.2A) and (Fig.3B);

Coating of the silicon substrate with an insulating film 24 (Fig. 3A) generally made of silicon oxide or an insulating polymer;

Subsequently, in the three preceding steps, said process is characterized by the succession of the following steps: a- depositing a barrier layer 32 e (FIG. 5A) preventing the migration of the copper;

b-coat by a seed layer 32 f (Fig.5B) the barrier layer 32 e (Fig.5A) to reduce the strength of said barrier layer;

c) print on the surface of the copper connection lines (RDL) 32.g by photolithography method 42 (Fig.5C);

d- Fill the copper connecting lines (RDL) 32g and through vias 34

(Fig.5D) by electrodeposition;

e- Strip the photoresist of the connection lines (RDL) 42 (FIG. 5E);

f- engrave the sprouting layer 32 f in the areas not coated with the photoresist

(Fig.5E);

g-etching the titanium layer 32. e in the areas not coated with the photoresist (Fig.5F);

heat-treating the copper deposit 32.g (FIG. 5E) contained in the connection lines (RDL) 32 and in the through vias 34 (FIG. 1A) and (FIG. 1B) intended to evaporate all organic moisture thus adsorbed on the deposition surface; 7. A metallization process according to claim 6, characterized in that the barrier layer 32.e (FIG. 5A) is deposited by sputtering or by autocatalysis and comprises at least one of these selected materials. among titanium (Ti), tantalum (Ta), nickel (Ni), nickel-boron alloy (NiB), nickel-phosphorus alloy (NiP), tantalum nitride (TaN), titanium nitride (TiN) and alloy titanium-tungsten (TiW).

8. Metallization process according to claim 6, is characterized in that the copper seed layer 32. f (Fig.5B) is deposited by means of one of the methods chosen from sputtering, auto-catalytic, electrolytic sputtering .

9- Metallization process according to claim 6, is characterized in that the heat treatment of the 32g copper deposit (Fig.5E) contained in the connection lines (RDL) 32 and in through vias 34 (Fig.lA ) and (Fig.lB) is carried out at a temperature of 150 ° C for 30 minutes under an inert atmosphere (containing N2 or a mixture N2 + H2 at 5% H2).

10- metallization process according to claim 6, is characterized in that the etching of the seed layer 32.f (Fig.5E) and titanium 32. e (Fig.5F) is carried out wet.