WO2015133728A1 - Structure de bossage de soudure et son procédé de fabrication - Google Patents

Structure de bossage de soudure et son procédé de fabrication Download PDF

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WO2015133728A1
WO2015133728A1 PCT/KR2015/000818 KR2015000818W WO2015133728A1 WO 2015133728 A1 WO2015133728 A1 WO 2015133728A1 KR 2015000818 W KR2015000818 W KR 2015000818W WO 2015133728 A1 WO2015133728 A1 WO 2015133728A1
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solder
insulating layer
manufacturing
solder bump
forming
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PCT/KR2015/000818
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English (en)
Korean (ko)
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이정중
최한주
권순호
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서울대학교 산학협력단
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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Definitions

  • the present invention relates to a wiring structure of an electronic device and a method of manufacturing the same, and more particularly, to a solder bump structure and a method of manufacturing the same.
  • the flip chip bonding process requires some additional steps compared to the carrier base system, but it is replacing the carrier base system due to the higher conductivity and the reduced chip size.
  • Solder bump deposition occurs at the end of the semiconductor process, and currently used solder bump deposition processes can be done by patterning photo resist (PR) to form solder bumps on metal pads. Do it in turn.
  • PR photo resist
  • a single PR patterning process involves the process of PR coating, exposure, development and PR removal.
  • the solder bump forming process is performed at the last stage.
  • Aluminum is often used as an input / output pad of a device in a flip chip package.
  • an under bump metallurgy (UBM) layer is deposited on the aluminum pad to ensure wettability.
  • the present invention is to solve various problems, including the above problems, and to simplify the process of manufacturing a solder bump structure in general, and to provide a method for manufacturing a solder bump structure having a constant interval at a time saving and low cost. Leave.
  • these problems are illustrative, and the scope of the present invention is not limited thereby.
  • preparing a device with a conductive pad forming an insulating layer on at least a portion of the conductive pad and the device, etching the insulating layer to expose a cavity to expose the conductive pad
  • the sidewall of the insulating layer pattern may have an inclined surface so that the solder layer may be rearranged onto the conductive pad in a liquid state by the dewetting process, and the insulating layer pattern may have a cross-sectional area that goes from top to bottom. It may include a shape.
  • the spacing and size of the solder bumps may be adjusted by the spacing of the insulation layer pattern or the inclined plane angle of the insulation layer pattern.
  • the spacing and size of the solder bumps can be controlled by the amount or thickness of the solder layer applied.
  • Forming the solder layer may be deposited by a sputtering method.
  • the solder layer may include tin (Sn) or tin (Sn) alloy.
  • the plasma may be formed using a discharge gas including at least one selected from the group consisting of argon (Ar), hydrogen (H), and helium (He).
  • the forming of the solder bumps may include adjusting the spacing and size of the solder bumps by adjusting processing conditions of the plasma applied to the device, and processing conditions of the plasma may include plasma generation power and etching gas. May include the ratio or treatment time.
  • the etching of the insulating layer, the forming of the solder layer, the dewetting process by the plasma, and the removing of the insulating layer pattern may be performed in an in-situ process.
  • the insulating layer may include at least one of an oxide and a nitride.
  • the etching may include at least one of argon (Ar), carbon tetrafluoride (CF 4 ) and methane trifluoride (CHF 3 ).
  • preparing a device with a conductive pad forming an insulating layer on at least a portion of the conductive pad and the device, etching the insulating layer to expose the cavity to expose the conductive pad
  • Forming an insulating layer pattern comprising, forming a UBM layer on the entire surface on the conductive pad and the insulating layer pattern, forming a solder layer on the UBM layer, dewetting by plasma to the solder layer ( and forming a solder bump on the UBM layer under the cavity by removing a dewetting process, and removing the insulating layer pattern.
  • solder bump structure which is implemented by the method for producing a solder bump structure described above.
  • the present invention made as described above, it is possible to omit the copper (Cu) seed layer and unnecessary PR process. Thereby, the structure and process of a solder bump structure can be simplified, and the manufacturing method of the solder bump structure which can acquire a time saving and a cost saving effect can be provided.
  • the scope of the present invention is not limited by these effects.
  • FIG. 1 is a process flowchart schematically illustrating a method of manufacturing a solder bump structure according to an embodiment of the present invention.
  • FIGS. 2A through 2G are cross-sectional views illustrating a method of manufacturing a solder bump structure according to an exemplary embodiment of the present invention.
  • 3A through 3C are cross-sectional views illustrating a method of manufacturing a solder bump structure according to another exemplary embodiment of the present invention.
  • Figure 4 is an electron microscope analysis of the specimens for each step of manufacturing the solder bump structure according to the experimental example of the present invention.
  • FIG. 5 is an electron microscope analysis result of a specimen in which a solder bump structure is tested for each pitch according to another experimental example of the present invention.
  • a typical solder bump forming process is as follows. First, a UBM layer is applied on the substrate, and then a seed layer for copper plating is applied thereon.
  • the UBM layer can deposit, for example, titanium (Ti) and titanium nitride (TiN) by a sputtering method.
  • PR is applied in consideration of the height and position of the solder, and patterned in a predetermined pattern through exposure and development. Using the seed layer exposed after the patterning of the PR, copper plating is performed and tin (Sn) or tin alloy is plated on the plated copper to form solder bumps. Finally, the solder bumps are formed through a reflow process to make the composition and height of the solder bumps uniform and to increase the bonding force.
  • the solder bump forming process should go through a PR process for the seed layer and the solder, reflow process. This has the disadvantage that it is time consuming and complicated to process.
  • the present invention can simplify the process through a plasma dewetting process and provide a method of manufacturing a solder bump structure that is directly connected on the conductive pad 20.
  • FIG. 1 is a process flowchart schematically illustrating a method of manufacturing a solder bump structure 1 according to an embodiment of the present invention.
  • 2A to 2G are schematic diagrams illustrating step-by-step manufacturing processes of a solder bump structure according to an exemplary embodiment of the present invention.
  • the method of manufacturing the solder bump structure according to the exemplary embodiment of the present invention may include, for example, preparing a device 10 in which the conductive pad 20 is formed (S10).
  • the device 10 may be a semiconductor chip manufactured using a substrate such as a silicon wafer, a ceramic including glass, and a polymer.
  • the conductive pad 20 may be formed by coating and patterning a metal on a via formed in the device 10 as shown in FIG. 2A.
  • the metal may include aluminum or tungsten.
  • an insulating layer may be formed (S20).
  • the insulating layer may sequentially form the first insulating layer 30a and the second insulating layer 30b.
  • the first insulating layer 30a and the second insulating layer 30b may each include at least one of nitride or oxide.
  • the formed insulating layer may be etched to expose the conductive pad 20, and a step (S30) of forming an insulating layer pattern including the cavity 30c may be performed.
  • the PR layer 35 is formed on the second insulating layer 30b to etch the insulating layers 30a and 30b and then patterned.
  • FIG. 2B is a schematic diagram of the patterning of the PR layer 35.
  • a pattern is formed through an exposure process, a developing process, and the like according to a shape to be etched.
  • the insulating layers 30a and 30b may be etched using an etching gas.
  • the etching gas may include at least one of argon (Ar), carbon tetrafluoride (CF 4 ), and methane trifluoride (CHF 3 ).
  • Ar argon
  • CF 4 carbon tetrafluoride
  • CHF 3 methane trifluoride
  • the cavity 30c formed in the second insulating layer 30b is etched in a crater shape having an inclined surface therein, and the upper portion of the conductive pad 20 may be exposed through the cavity 30c.
  • the cross-sectional structure of the pattern of the second insulating layer 30b including the cavity 30c may have a structure in which the cross-sectional area of the second insulating layer 30b is increased from the upper side to the lower side.
  • the cross section of the cavity formed in the second insulating layer 30b may include at least one of a cone, a truncated cone, a pyramid, and a truncated pyramid.
  • the cross-sectional structure of the second insulating layer 30b including the cavity 30c may be a columnar structure in addition to the horn structure.
  • the pattern shape of the second insulating layer 30b is exemplary, and the present invention is not limited thereto.
  • a profile of the inclined surface in the cavity 30c may be adjusted according to a dry etching treatment condition, for example, plasma generation power, an etching gas ratio, and a treatment time.
  • the inclined surface of the second insulating layer 30b pattern structure may induce the aggregation of the solder layer 40a near the lower portion of the cavity 30c region when the solder layer 40a is melted by the plasma. That is, the molten solder layer 40a may easily flow along the inclined surface of the etched second insulating layer 30b by the incident ion energy, may be collected in the lower region of the cavity 30c and may be solidified after aggregation. Detailed description thereof will be described with reference to FIGS. 2D to 2F.
  • the solder layer 40a may be formed over the exposed conductive pad 20 and the insulating layer pattern.
  • the solder layer 40a may be deposited on the second insulating layer 30b having the cavity 30c and the conductive pad 20 by sputtering.
  • a process of removing an oxide film formed on an aluminum surface using an etching gas may be additionally performed before the solder layer 40a is deposited.
  • the etching gas may include, for example, hydrogen fluoride (HF) gas.
  • the solder layer 40a may be a metal material and may be an alloy including tin (Sn) or tin (Sn).
  • the amount of solder layer 40a deposited on top of the second insulating layer 30b can be deposited relatively less than the amount of solder layer 40a deposited on the conductive pad 20.
  • a small amount of solder on the top of the second insulating layer 30b can be easily separated and flow in both directions of the conical structure.
  • a step of forming a solder bump 40b in direct contact with the conductive pad 20 may be performed by performing a dewetting process on the solder layer 40a by plasma.
  • the dewetting process may be performed by, for example, a plasma generated in the P region.
  • the plasma may use a discharge gas including at least one selected from the group consisting of argon (Ar), hydrogen (H), and helium (He).
  • the solder layer 40a is melted by the thermal energy generated when the particles having high energy in the plasma collide to change into a liquid state.
  • the liquid solder easily flows downward along the direction of the arrow along the inclined surface of the sidewall of the second insulating layer 30b pattern.
  • the solder which flows in both directions, begins to agglomerate. Therefore, the second insulating layer 30b of the conical structure can help the solder layer 40a to easily aggregate on the conductive pad 2.
  • the shape in which the solder layer 40a melted in the plasma flows down along the inclined surface of the sidewall of the second insulating layer 30b pattern is agglomerated on the conductive pad 20.
  • the solder layer 40a melted by plasma finally comes into direct contact with the conductive pad 20 and has a sphere shape surrounded by a second insulating layer 30b having a cavity 30c. It is possible to form a uniform solder bump (40b).
  • the spacing and size of the solder bumps 40b may be adjusted by the interval between the second insulating layer 30b pattern or the inclined plane angle of the second insulating layer 30b pattern, and the amount of the solder layer 40a applied. Or it can be adjusted by thickness.
  • step (S60) of removing the insulating layer pattern may be performed.
  • the unnecessary second insulating layer 30b is selectively removed using dry etching or wet etching to manufacture the solder bump structures 1 uniformly formed according to a predetermined pitch. can do.
  • the plasma used for dewetting the solder layer may be, for example, an inductively coupled plasma.
  • Inductively coupled plasma mainly changes the electric field by winding a coil outside a dielectric reactor such as quartz, and an induction magnetic field is generated inside the coil.
  • the secondary induced current is a high-density plasma generated using what is formed inside the reactor.
  • the inductively coupled plasma may be formed using a discharge gas including at least one selected from the group consisting of argon, hydrogen, and helium at process pressures of several mT to several hundred mT.
  • inductively coupled plasma is a low temperature process formed at 300 ° C. or lower.
  • the low temperature process formed at 300 ° C. or less has a very advantageous advantage. Applying an appropriate bias voltage to the device in the process of generating the inductively coupled plasma can effectively control the spacing and size of the solder bumps 40b.
  • the size and dispersion degree of the solder bumps 40b on the polymer material may be controlled by adjusting the processing conditions of the inductively coupled plasma. For example, the degree of aggregation of the solder bumps 40b may be controlled according to the power applied to maintain the inductively coupled plasma. If the remaining conditions are the same, the higher the power of the inductively coupled plasma, the more the solder bumps 40b tend to aggregate.
  • 3A to 3C are cross-sectional views schematically illustrating a method of manufacturing a solder bump structure according to another embodiment of the present invention.
  • the UBM layer may be included on the insulating layer.
  • the UBM layer may be included on the insulating layer.
  • an element having an insulating layer pattern formed in the same manner as in FIGS. 2A to 2C can be prepared.
  • a UBM layer 38 for example titanium (Ti), titanium nitride (TiN) or a double layer of titanium (Ti) and titanium nitride (TiN), etc. are sequentially stacked along the pattern of the prepared second insulating layer 30b. Can be formed.
  • the solder layer 40a may be deposited on the formed UBM layer 38 by a sputtering method.
  • the dewetting process may be performed by, for example, a plasma generated in the P region.
  • the solder layer 40a is changed into a liquid state by the plasma.
  • the liquid solder flows easily in the direction of the arrow along the inclined surface of the side wall of the pattern of the second insulating layer 30b.
  • the UBM layer 38 is made of a material having a higher melting point than the solder layer 40a, for example, titanium (Ti) and / or titanium nitride (TiN), the solder layer 40a may be adjusted by adjusting plasma conditions. Is melted but the UBM layer 38 is not melted.
  • the solder layer 40a melted in the plasma is aggregated on the UBM layer 38 under the cavity 30c to form a uniform solder bump 40b having a spherical shape.
  • the solder bump structure 1 uniformly formed by selectively removing the unnecessary second insulating layer 30b and the UBM layer 38 using dry etching or wet etching after the solder bump 40b is formed. Can be prepared.
  • the addition of the UBM layer 38 can further increase the bonding force between the conductive pads 20 and the solder bumps 40b and can produce a solder bump structure 1 with better electrical conductivity.
  • the etching of the insulating layer, the forming of the solder layer, the dewetting process by the plasma, and the removing of the insulating layer pattern may be performed in-situ. It may be carried out in an (in-situ) process.
  • the process may proceed inline, or the process may be performed in the same vacuum chamber.
  • the process proceeds continuously in a vacuum state, so that a clean solder bump structure without particle inflow from the outside may be manufactured.
  • solder layer was deposited to a thickness of about 750 nm by sputtering to form a solder layer. This solder layer was subjected to hydrogen plasma treatment to form uniform solder bumps.
  • FIG. 4A and 4D show the results of analyzing a substrate on which the cavity 30c is formed by etching.
  • FIG. 4A is a result of observing the surface of the patterned substrate
  • FIG. 4D is a result of observing a cross section of the substrate cut along A-A 'of FIG. 4A. . 4 (a) and 4 (d)
  • the surface of the patterned specimen has a lattice shape
  • the cross-section of the cavity 30c is patterned into a shape of a uniform cone structure of silicon (S). ) Was formed.
  • FIGS. 4B and 4E show the results of analyzing the surface and the cross section of the specimen on which the solder layer 40a having a thickness of about 750 nm is deposited on the patterned specimen by electron microscopy.
  • FIG. 4E is the result of observing the cross section of the board
  • FIGS. 4C and 4F show the results of analyzing the surface and the cross section by electron microscope after performing hydrogen plasma for about 5 minutes on a sample on which a solder layer is deposited.
  • FIG. 4F is the result of observing the cross section of the substrate cut along A-A 'of FIG. 4C. Referring to FIGS. 4C and 4F, it can be seen that the solder layer is melted and agglomerated by hydrogen plasma to form a spherical solder bump 40b in the cavity.
  • An aluminum pad was formed to about 250 nm thick on the silicon wafer substrate.
  • silicon nitride (Si 3 N 4 ) having a thickness of about 250 nm and silicon oxide (SiO 2 ) having a thickness of about 2000 nm were sequentially formed on the aluminum pad.
  • Si 3 N 4 silicon nitride
  • SiO 2 silicon oxide
  • This solder layer was subjected to hydrogen plasma treatment to form uniform solder bumps.
  • solder layer After etching the silicon wafer substrate to form a cavity, tin (Sn) was deposited to a thickness of about 2000 nm by sputtering to form a solder layer. This solder layer was subjected to hydrogen plasma treatment to form uniform solder bumps.
  • a tin layer Sn was deposited to a thickness of about 2000 nm by sputtering to form a solder layer. This solder layer was subjected to hydrogen plasma treatment to form uniform solder bumps.
  • FIGS. 6A and 6C show the results of an electron microscope analysis of the surface of a specimen in which solder bumps 40b are formed directly on a silicon (S) pattern.
  • 6 (b) and 6 (d) show the results of analyzing the surface of the specimen on which the solder bumps 40b were formed on the titanium nitride (N) pattern by an electron microscope. It can be seen that the spherical solder bumps 40b are uniformly formed in the cavity 30c regardless of the existence of the UBM layer.
  • a solder layer may be formed by an in-situ process. That is, the solder layer 40a directly in contact with the metal wiring may be directly deposited by a sputtering method, and then plasma dewetting may be continuously performed in the same chamber to produce a uniform solder bump structure.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention porte sur un procédé de fabrication pour une structure de bossage de soudure, et sur une structure de bossage de soudure mise en œuvre par le procédé de fabrication. Le procédé de fabrication comprend les étapes suivantes : la préparation d'un dispositif ayant une plot conducteur formé sur ce dernier ; la formation d'une couche d'isolation sur le plot conducteur et sur au moins une partie du dispositif ; la formation d'un motif de couche d'isolation ayant une cavité pour présenter le plot conducteur soumettant la couche d'isolation à une gravure ; la formation d'une couche de soudure sur le plot conducteur et sur la surface avant sur le motif de couche d'isolation ; la formation d'un bossage de soudure établissant un contact direct avec le plot conducteur qui est entouré par le motif de couche d'isolation, soumettant la couche de soudure à un démouillage par plasma ; et le retrait du motif de couche d'isolation.
PCT/KR2015/000818 2014-03-06 2015-01-27 Structure de bossage de soudure et son procédé de fabrication WO2015133728A1 (fr)

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KR1020140026768A KR101542161B1 (ko) 2014-03-06 2014-03-06 솔더 범프 구조체 및 그 제조방법
KR10-2014-0026768 2014-03-06

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070017796A (ko) * 2005-08-08 2007-02-13 삼성전자주식회사 반도체 장치용 범프 형성 방법
KR100718120B1 (ko) * 2003-07-01 2007-05-15 삼성전자주식회사 플립 칩 솔더 제조 방법
KR101069980B1 (ko) * 2009-09-15 2011-10-04 삼성전기주식회사 솔더 범프 형성 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100718120B1 (ko) * 2003-07-01 2007-05-15 삼성전자주식회사 플립 칩 솔더 제조 방법
KR20070017796A (ko) * 2005-08-08 2007-02-13 삼성전자주식회사 반도체 장치용 범프 형성 방법
KR101069980B1 (ko) * 2009-09-15 2011-10-04 삼성전기주식회사 솔더 범프 형성 방법

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