WO2015132883A1 - 半導体装置および情報処理装置 - Google Patents
半導体装置および情報処理装置 Download PDFInfo
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- WO2015132883A1 WO2015132883A1 PCT/JP2014/055478 JP2014055478W WO2015132883A1 WO 2015132883 A1 WO2015132883 A1 WO 2015132883A1 JP 2014055478 W JP2014055478 W JP 2014055478W WO 2015132883 A1 WO2015132883 A1 WO 2015132883A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Definitions
- the present invention relates to a semiconductor device for obtaining a ground state of an Ising model, and more particularly to a semiconductor device that simulates a spin of an Ising model as a CMOS flip-flop and an information processing device that controls the semiconductor device as an accelerator.
- the mainstream of computer architecture is the Neumann type.
- the operation is defined by a program which is a sequential instruction sequence.
- a program which is a sequential instruction sequence.
- a program which is a sequential instruction sequence.
- a program which is a sequential instruction sequence.
- a program which is a sequential instruction sequence.
- an arithmetic unit for a specific purpose such as a GPU (Graphics Processing Unit) is composed of a Neumann architecture, and its basic operation is an instruction sequence. In sequential execution.
- the improvement in computer performance has mainly depended on the improvement of the clock frequency. Since the basis of the Neumann architecture is the sequential execution of instruction examples, performance improvement can be expected by increasing the instruction execution speed.
- the improvement in clock frequency has reached a peak around 3 GHz in the early 2000s.
- measures to achieve performance improvement by parallel processing using multi-core have become mainstream.
- ILP Instruction Level Parallelism
- TLP Thread Level Parallelism
- DLP Data Level Parallelism
- the Ising model is a statistical mechanics model for explaining the behavior of magnetic materials, and is used in the study of magnetic materials.
- the Ising model is defined as the interaction between sites (spin that takes a binary value of + 1 / ⁇ 1). It is known that obtaining the ground state of the Ising model in which the topology is a non-planar graph is an NP difficult problem. Since the Ising model expresses the problem with the interaction coefficient spreading in the spatial direction, there is a possibility that information processing using intrinsic parallelism can be realized.
- the ground state search of the Ising model can be performed with a solid-state element such as a semiconductor device, which can be realized by regularly arranging a large number of constituent elements.
- a solid-state element such as a semiconductor device, which can be realized by regularly arranging a large number of constituent elements.
- a semiconductor device includes a memory cell that stores a value of one spin of the Ising model, and a memory cell that stores an interaction coefficient from an adjacent spin that interacts with the spin. And the memory cell storing the external magnetic field coefficient of the one spin, and the product of each adjacent spin value and the corresponding interaction coefficient, and the external magnetic field coefficient by the binary majority logic
- a spin unit having a circuit for determining a next state of one of the spins, and the plurality of spin units to which the respective spins of the Ising model are assigned, while maintaining the topology of the Ising model, on a semiconductor substrate A spin array arranged and connected in a two-dimensional plane was constructed.
- the memory cell that stores the spin value of each spin unit arranged in the spin array is transferred to other memory cells and circuits.
- a dedicated power supply line that is different from a power supply line that supplies power is connected, and in each of the spin units, the value of the spin is obtained via the dedicated power supply line when executing the process of determining the next state of the spin.
- the power supply voltage supplied to the memory cell to be stored is controlled to be lowered.
- the spin vertices of the Ising model of the three-dimensional lattice are arranged in the two-dimensional plane.
- the lattice vertex array in the Z-axis direction is inserted in each interval of the lattice vertex array in the X-axis direction, and the lattice vertex array in the Y-axis direction is the same array, and the spin of each lattice vertex is assigned.
- Each spin unit is arranged on a semiconductor substrate, and the spin units are connected to each other while maintaining a three-dimensional lattice topology. It was constructed in.
- an information processing device in which a semiconductor device applicable as a CPU, RAM, HDD, and accelerator is connected to a system bus is used.
- a spin unit comprising a circuit for determining a next state of the one spin by binary majority logic in a product of adjacent spin values and the corresponding interaction coefficient, and the external magnetic field coefficient, and the Ising model
- a plurality of the spin units assigned to each of the spins maintain the topology of the Ising model In this state, a spin array arranged and connected in a two-dimensional plane on a semiconductor substrate, and an I / O interface for reading / writing memory cells of the spin unit arranged in the spin array are grouped.
- an interaction control interface for supplying a signal for permitting the interaction to each spin group, and the semiconductor device control program executed on the CPU is an Ising that expresses a target problem.
- the spin unit in the spin array on the semiconductor device to which each spin of the Ising model is assigned The initial spin arrangement, the interaction coefficient, and the external magnetic field coefficient are written, and the ground state search process of the grouped spin units is repeatedly performed a predetermined number of times, and the spin arrangement of the spin units that have reached the ground state is obtained. It was configured to obtain the solution of the target problem by reading.
- the present invention it is possible to provide a semiconductor device for obtaining a ground state of an Ising model that can be manufactured by a CMOS integrated circuit process that is widely used at present. Further, the ground state search can be performed in conformity with the device manufacturing variation caused in the semiconductor manufacturing process.
- an Ising chip 100 that is a semiconductor device for obtaining a ground state of an Ising model and an information processing apparatus 200 that controls the Ising chip 100 will be described.
- the Ising model is a statistical mechanics model for explaining the behavior of the magnetic material.
- the Ising model is defined by a spin that takes a binary value of + 1 / -1 (or 0/1, up / down), an interaction coefficient indicating the interaction between the spins, and an external magnetic field coefficient for each spin. .
- the Ising model can calculate the energy at that time from a given spin arrangement, interaction coefficient, and external magnetic field coefficient.
- the energy function E ( ⁇ ) of the Ising model is generally expressed by the following equation (Equation 1).
- ⁇ i and ⁇ j are the values of the i-th and j-th spins
- J i, j is the interaction coefficient between the i-th and j-th spins
- h i is the external magnetic field coefficient for the i-th spin
- ⁇ I, j> represents a combination of two adjacent sites
- ⁇ represents a spin arrangement.
- Obtaining the ground state of the Ising model is an optimization problem for obtaining an array of spins that minimizes the energy function of the Ising model.
- problems that are not related to a magnetic material such as factorization and traveling salesman problem can be converted into Ising models.
- the ground state of the Ising model obtained by the conversion corresponds to the solution of the original problem. From this, it can be said that the apparatus that can search the ground state of the Ising model is a computer that can be used for general purposes.
- Each side has a weighting coefficient.
- V ′ ⁇ V represents a set obtained by removing V ′ from V.
- the side (c, d, e, f in the example of FIG. 12) straddling between the divided V ′ and V ′ ⁇ V is called an edge straddling a cut or a cut edge.
- the number of cut edges is called a cut size.
- the sum of weights of cut edges is called a cut size.
- the size of the cut is c + d + e + f. 11 and 12 are examples of undirected graphs, they can be extended to directed graphs.
- the vertex set V is grouped into V ′ and V ′ ⁇ V so as to maximize the size of the cut.
- the cut size w (V ′) c + d + e + f.
- vertices belonging to the cut vertex V ′ are +1 spins
- vertices belonging to V ′ ⁇ V are ⁇ 1 spins.
- the minimum cut problem can be efficiently obtained by the Ford Falkerson algorithm according to the maximum flow minimum cut theorem only when the signs of the weights are all positive.
- the minimum cut problem is created by inverting the sign of the weight of the maximum cut problem, negative weights are often included, so the Ford Falkerson algorithm cannot be applied.
- FIG. 14 shows an example in which the maximum cut problem shown in FIG. 13 is converted into a ground state search problem of the Ising model.
- the interaction coefficients J AB , J AC , J AD , J BC , J BC , and J CD on each side in FIG. 14 are viewed, the signs of the weights in FIG. 13 are reversed. This corresponds to the conversion from the aforementioned maximum cut problem to the minimum cut problem.
- the ground state of the Ising model of FIG. 14 is searched, and the spins ⁇ A , ⁇ B , ⁇ C , and ⁇ D determined so as to minimize the energy are shown in FIG.
- an apparatus for realizing the ground state search of the Ising model as shown in FIG. 14 and its control method are shown in the present invention.
- the apparatus for realizing the ground state search of the Ising model of a three-dimensional lattice is known.
- An example is shown.
- the present invention is not limited to the Ising model of a three-dimensional lattice, and can be applied to any topology and any number of spins.
- FIG. 1 is an example of a configuration diagram of an Ising chip 100 according to the present embodiment.
- the Ising chip 100 includes a spin array 110, an I / O driver 120, an I / O address decoder 130, and an interaction address decoder 140.
- the Ising chip 100 is described on the assumption that it is mounted as a CMOS integrated circuit that is widely used at present.
- the Ising chip 100 can be realized by other solid-state devices.
- the Ising chip 100 has an SRAM compatible interface 150 for performing read / write to the spin array 110, and includes an address bus 190, a data bus 191, an R / W control line 193, and an I / O clock 192.
- the interaction control interface 160 for controlling the ground state search of the Ising model has an interaction address 180 and an interaction clock 181.
- the Ising chip 100 normally operates with a voltage supplied by the power supply line 142, but a part of the spin array 110 operates with a voltage supplied by the spin power supply line 141.
- the memory cell N that holds the spin information operates with a voltage supplied from the spin power line 141.
- the spin ⁇ i , the interaction coefficient J i, j , and the external magnetic field coefficient h i of the Ising model are all expressed by information stored in the memory cells in the spin array 110.
- the SRAM compatible interface 150 reads / writes the spin ⁇ i for setting the initial state of the spin and reading the solution after completion of the base search. Also, performing Ising model to be searched the ground state to set the customizing chip 100, interaction coefficients J i, j, and the read / write of the external magnetic field coefficient h i in SRAM compatible interface 150. Therefore, an address is given to the spin ⁇ i , the interaction coefficient J i, j , and the external magnetic field coefficient h i in the spin array 110.
- the address bus 190, the data bus 191 and the R / W control line 193 constituting the SRAM compatible interface 150 operate in synchronization with the clock input to the I / O clock 192.
- the interface does not have to be synchronous, and may be an asynchronous interface. In this embodiment, the description will be made on the assumption that the interface is a synchronous interface.
- the Ising chip 100 realizes an interaction between spins in the spin array 110 in order to perform a ground state search.
- the interaction control interface 160 controls this interaction from the outside. Specifically, an address for designating a spin group in which the interaction is performed is input as an interaction address 180 and is input to the interaction clock 181. Synchronize with each other.
- the interaction does not necessarily have to be realized by a clock synchronous circuit, and may be an asynchronous circuit. In this case, the role of the interaction clock 181 is not an input of the clock but an enable signal that permits execution of the interaction.
- the interaction control interface does not necessarily need to be a synchronous type, and may be an asynchronous type interface. However, in this embodiment, a synchronous type interface is used, and the description is based on the assumption that the interaction is performed in synchronization with the interaction clock 181. I do.
- the spin array 110 has a large number of spin units 300 (details will be described later), thereby realizing high parallelism.
- Such adaptation to manufacturing variation is generally adapted to individual differences by adding a circuit for absorbing manufacturing variation to the device and adjusting circuit constants such as resistance values in the circuit. Can be considered.
- the hardware is complicated by performing the ground state search while changing the correspondence relationship between the spin of the Ising model to be solved and the spin unit 300 in the spin array 110. Realize adapting to manufacturing variations while minimizing. This achieves high scalability.
- Information processing is realized by using one or a plurality of Ising chips 100. To that end, the interface as described above must be controlled. Therefore, the Ising chip 100 is used as a part of the information processing apparatus 200 as shown in FIG.
- the information processing apparatus 200 may be considered as an accelerator configured by the Ising chip 100 mounted on an apparatus such as a personal computer or a server that is generally used at present.
- the information processing apparatus 200 includes a CPU 210, a RAM 220, an HDD 260, and a NIC 240, which are connected by a system bus 230. This is a configuration commonly found in current personal computers and servers.
- the Ising chip controller 250 is connected to the system bus 230, and one or more Ising chips (in the example of FIG. 2, two Ising chips 100-1 and Ising chips 100-2 are connected to the system bus 230. Thereafter, the two Ising chips are simply referred to as Ising chips 100 when it is not necessary to distinguish between them.
- the Ising chip controller 250 and the Ising chip 100 correspond to accelerators, and take the form of an expansion card that is used by being inserted into a peripheral expansion interface such as PCI Express.
- the Ising chip controller 250 converts the protocol of the system bus 230 (for example, PCI Express or QPI) according to the interface of the Ising chip.
- Software that operates on the CPU 210 of the information processing apparatus 200 generally reads / writes to a specific address (so-called MMIO, Memory Mapped I / O), and passes through the Ising chip controller 250.
- the Ising chip 100 can be controlled.
- a plurality of such information processing apparatuses may be combined and used via the inter-apparatus network 290.
- the spin array 110 includes a spin unit 300 that realizes a single spin, an associated interaction coefficient and an external magnetic field coefficient, and a ground state search process. A large number of units 300 are arranged side by side.
- FIG. 5 shows an example in which an Ising model having a three-dimensional lattice topology is configured by arranging a plurality of spin units 300.
- the example of FIG. 5 is a three-dimensional lattice having a size of 3 (X-axis direction) ⁇ 3 (Y-axis direction) ⁇ 2 (Z-axis direction).
- the definition of the coordinate axis is the X-axis in the right direction of the drawing, the Y-axis in the downward direction of the drawing, and the Z-axis in the depth direction of the drawing. It doesn't matter.
- a topology other than a three-dimensional lattice for example, a tree-like topology
- it is expressed by the number of stages of the tree separately from the coordinate axes.
- a spin (vertex) of degree 5 at the maximum is required.
- the maximum order 6 is required.
- One spin unit 300 shown in FIG. 5 receives values of ⁇ j , ⁇ k , ⁇ l , ⁇ m , and ⁇ n adjacent spins (for example, when there are five adjacent spins).
- the spin unit 300 has J j, i , J k, i , J l, i , J m, i , which are the interaction coefficients with the adjacent spins. It has a memory cell that holds J n, i (an interaction coefficient with 5 adjacent spins).
- the Ising model generally has an interaction expressed by an undirected graph.
- J i, j ⁇ ⁇ i ⁇ ⁇ j as a term representing the interaction, which indicates the interaction from the i-th spin to the j-th spin.
- the general Ising model does not distinguish between the interaction from the i-th spin to the j-th spin and the interaction from the j-th spin to the i-th spin. That is, J i, j and J j, i are the same.
- this Ising model is extended to a directed graph, and the interaction from the i-th spin to the j-th spin and the interaction from the j-th spin to the i-th spin are made asymmetric. is doing. As a result, the ability to express the model increases, and many problems can be expressed with a smaller model.
- one spin unit 300 is considered as the i-th spin ⁇ i , J j, i , J k, i , J l, i , J m, i , which are interaction coefficients held by this spin unit.
- J n, i represents the interaction from the adjacent j-th, k-th, l-th, m-th and n-th spins ⁇ j , ⁇ k , ⁇ l , ⁇ m , ⁇ n to the i-th spin ⁇ i . It is a decision. This is because in FIG. 5, the arrow (interaction) corresponding to the interaction coefficient included in the spin unit 300 changes from the spin outside the spin unit 300 shown to the spin inside the spin unit 300. Corresponding to the heading.
- FIG. 3 shows a circuit for realizing the interaction between the spin units
- FIG. 4 pays attention to the word lines and bit lines that are interfaces for accessing the memory cells of the spin units from outside the Ising chip 100. It is illustrated. Note that how to connect EN, NU, NL, NR, ND, NF, and N, which are interfaces shown in the circuit for realizing the interaction of FIG. 3, between a plurality of spin units. This will be described later with reference to FIGS. Further, how to connect the word lines and bit lines in FIG. 4 between a plurality of spin units will be described later with reference to FIG.
- the spin unit 300 includes a plurality of 1-bit memory cells to hold Ising model spins ⁇ i , interaction coefficients J j, i ,... J n, i and external magnetic field coefficients h i . .
- This 1-bit memory cell is shown as N, IS0, IS1, IU0, IU1, IL0, IL1, IR0, IR1, ID0, ID1, IF0, and IF1 in the drawing. It should be noted that IS0 and IS1, IU0 and IU1, IL0 and IL1, IR0 and IR1, ID0 and ID1, and IF0 and IF1 each play a role as a pair, so ISx, IUx, and ILx are combined. , IRx, IDx, and IFx.
- the memory cell 1900 includes a data holding unit 1960 including two CMOS inverters, and data read / write to the data holding unit 1960 is realized by controlling the pass gate transistor 1950 with the word line 1920 and the bit line 1930.
- the spin unit 300 represents the i-th spin.
- the memory cell N is a memory cell for expressing the spin ⁇ i and holds the spin value.
- the spin value is + 1 / ⁇ 1 (+1 is also expressed as “up” and ⁇ 1 is expressed as “bottom”), but this corresponds to the binary value 0/1 of the memory cell. For example, +1 corresponds to 1 and ⁇ 1 corresponds to 0.
- IUx is the upper spin (-1 in the Y axis direction)
- ILx is the left spin (-1 in the X axis direction)
- IRx is the right spin (+1 in the X axis direction)
- IDx is the lower spin (Y axis).
- IFx indicates an interaction coefficient with the spin (+1 or ⁇ 1 in the Z-axis direction) connected in the depth direction.
- the Ising model when viewed from a certain spin, it has a coefficient of the influence of other spins on the own spin.
- the coefficient of influence of the own spin on other spins belongs to each other spin. That is, the spin unit 300 is connected to a maximum of 5 spins.
- the external magnetic field coefficient and the interaction coefficient correspond to three values of + 1/0 / -1. Therefore, in order to represent the external magnetic field coefficient and the interaction coefficient, a 2-bit memory cell is required.
- ISx, IUx, ILx, IRx, IDx, IFx is a combination of two memory cells with numbers 0 and 1 at the end (for example, IS0 and IS1 in the case of ISx), giving three values of + 1/0 / -1.
- ISx + 1 / -1 is expressed by IS1
- +1 is expressed when IS1 is 1
- -1 is expressed when 0.
- the external magnetic field coefficient is regarded as 0, and when IS0 is 1, either + 1 / -1 determined by IS1 is set as the external magnetic field coefficient.
- IUx, ILx, IRx, IDx, and IFx representing the interaction coefficient associate the coefficient with the bit value.
- the memory cells N, IS0, IS1, IU0, IU1, IL0, IL1, IR0, IR1, ID0, ID1, IF0, and IF1 in the spin unit 300 must be readable / writable from the outside of the Ising chip 100, respectively.
- the spin unit 300 has a bit line 410 and a word line 420 as shown in FIG.
- the spin units 300 are arranged in tiles on a semiconductor substrate, the bit lines 410 and the word lines 420 are connected, and are driven, controlled, and read by the I / O address decoder 130 and the I / O driver 120, so that a general SRAM (The memory cell in the spin unit 300 can be read / written by the SRAM compatible interface 150 of the Ising chip 100 as in the case of Static Random Access Memory. Therefore, the memory map of the Ising chip 100 can be written, and the memory map of the Ising chip 100 of the 3 ⁇ 3 ⁇ 2 three-dimensional lattice Ising model shown in FIG. 5 is shown in the memory map 2000 of FIG.
- the symbols N000 and N001 indicate the coordinates of the spin unit.
- the coordinates in the X-axis direction, the coordinates in the Y-axis direction, and the coordinates in the Z-axis direction are indicated.
- the spin unit 300 illustrated in FIG. 5 (the spin unit in the middle of the front surface of the three-dimensional lattice) is expressed as N110.
- the configuration of the spin array 110 will be described with reference to FIG. 9 from the viewpoint of layout as a semiconductor device. Since the spin array 110 of the present embodiment has a three-dimensional lattice topology as shown in FIG. 5, in order to realize it as a semiconductor device that configures a circuit on a two-dimensional plane, it is necessary to devise a layout. . Therefore, the arrangement shown in FIG. 9 is taken. It should be noted that the spin unit 300 expressed in FIG. 9 (which is given a sign depending on the position on the X, Y, and Z axes, such as Nxyz) corresponds to which vertex in the topology of the three-dimensional lattice. This is shown in FIG.
- Nx0z, Nx1z, and Nx2z are arranged in the Y-axis direction on the two-dimensional plane in FIG. 9 (the lower side in the drawing is the Y-axis positive direction), but the X-axis direction (the right side in the drawing is the X-axis positive).
- spin units having Z-axis direction coordinates of 0 and 1 are alternately arranged, such as N0y0, N0y1, N1y0, N1y1, N2y0, and N2y1.
- the spin unit 300 is physically arranged as shown in FIG. 9, on which word lines 901-1, 901-2, 901-3 and a bit line 902 as shown in FIG. -1,902-2, 902-3, 902-4, 902-5, 902-6 are wired. These word lines and bit lines are connected to the word line 420 and the bit line 410 of the spin unit 300 shown in FIG. Since each spin unit has 13 memory cells in the word line arrangement direction (the word line 420 has 13 bits), the word lines 901-1, 901-2, and 901-3 each have 13 bits.
- This update of the spin is considered to update each spin sequentially one by one.
- this method takes time proportional to the number of spins, and parallelism cannot be used. Therefore, it is desirable to perform the interaction between the spins in parallel for all the spins.
- adjacent spins spins connected to that spin (spins directly connected to a certain spin through an interaction coefficient are hereinafter referred to as adjacent spins) cannot be updated simultaneously.
- the spin units 300 in the spin array 110 are grouped so that adjacent spins are not updated simultaneously, and only one group is updated at a time. If the topology is as shown in FIG. 5, it may be divided into two groups. These two groups are updated alternately.
- the Ising chip 100 has an interaction address 180 as an input interface.
- the interaction address 180 is an interface for designating a group to be updated among the groups described above, and spins (spin units 300) belonging to the group designated by the interaction address 180 are simultaneously input by the input of the interaction clock 181. Updated.
- the spin units Nxyz are grouped into two groups, group A and group B, respectively.
- each spin unit 300 has an interface (EN) for inputting a signal permitting the spin update. Therefore, the address (group identifier) specified by the interaction address 180 is decoded by the interaction address decoder 140 to generate an update permission signal for each group.
- the group A designation signal 2510 and the group B designation signal 2520 are update permission signals for each group.
- the spin unit belonging to the group that is permitted to be updated at that time is updated by the interaction clock 181. It can be easily seen from FIG. 26 that the adjacent spins are always different in the topology of FIG. 5 by the grouping shown in FIG.
- the grouping of the spin units 300 may be further subdivided for convenience of power consumption in addition to the above-described simultaneous update collision avoidance. For example, in the example described above, update conflicts can be avoided if divided into two groups. However, if power consumption becomes a problem when all the spins are updated simultaneously, for example, one group may be further divided. For example, in the two-group division, one group is divided into four groups for convenience of power consumption, and divided into a total of eight groups.
- the spin unit 300 has a circuit for calculating the interaction and determining the next spin state independently for each spin unit.
- a circuit for determining the next state of spin is shown in FIG.
- the spin unit has EN, NU, NL, NR, ND, NF, and N as interfaces with the outside.
- EN is an interface for inputting a signal for permitting the spin update of the spin unit.
- N is an interface for outputting the spin value of the spin unit to other spin units (adjacent units in the topology of FIG. 5).
- NU, NL, NR, ND, and NF are interfaces for inputting spin values of other spin units (adjacent units in the topology of FIG. 5).
- NU is the upper spin (-1 in the Y axis direction)
- NL is the left spin (-1 in the X axis direction)
- NR is the right spin (+1 in the X axis direction)
- ND is the lower spin (Y axis).
- +1) and NF are inputs from spins connected in the depth direction (+1 or -1 in the Z-axis direction).
- NU nothing is input to the end among NU, NL, NR, ND, and NF (on the circuit, it is connected to a fixed value of 0 or 1).
- next state of the spin is determined so as to minimize the energy between adjacent spins, which is a positive value when the product of the adjacent spins and the interaction coefficient and the external magnetic field coefficient are viewed. Equivalent to judging which negative value is dominant.
- the i-th spin sigma i as a spin ⁇ j, ⁇ k, ⁇ l , ⁇ m, the sigma n are adjacent, next state of the spin sigma i is determined as follows.
- the external magnetic field coefficient may always be read as an interaction coefficient with a spin having a value of +1.
- the local energy between the i-th spin and the adjacent spin is obtained by multiplying the above-described coefficient by the value of the i-th spin and further inverting the sign.
- the local energy with respect to the j-th spin is ⁇ 1 when the i-th spin is +1, and +1 when the i-th spin is ⁇ 1. It works in the direction to reduce the local energy here.
- 3 is a circuit for performing the above-described interaction.
- XNOR exclusive OR
- the next state of the spin that minimizes the energy when only the interaction is seen is (+1 is encoded as 1 and -1 is encoded as 0). If the interaction coefficient is only + 1 / ⁇ 1, the next state of the spin can be determined by determining which of the outputs is + 1 / ⁇ 1 by majority logic. Assuming that the external magnetic field coefficient always corresponds to the interaction coefficient with the spin in the state +1, the value of the external magnetic field coefficient is simply a value to be input to the majority logic that determines the next state of the spin.
- f (I 1, I 2 , I 3, ..., I n) output of replication was also combined with the input f (I 1, I 2, I 3, ..., I n, I '1, I' 2, I '3, ..., I' n) is equal. In other words, even if two input variables are entered, the output remains unchanged.
- Ix Ix
- Ix Ix
- I 2 I 2 , I 3, ..., I n
- the coefficient 0 is realized by utilizing this property of the majority logic. Specifically, as shown in FIG. 3, by using the XOR, the value of a bit that determines the enable of a coefficient (such as IS0) is copied to the majority logic according to the value of the spin next state candidate described above. Or the reverse of them at the same time. For example, when IS0 is 0, the IS1 value and the inversion value of IS1 are simultaneously input to the majority logic, so there is no influence of the external magnetic field coefficient (the external magnetic field coefficient corresponds to 0). When IS0 is 1, the value of IS1 and the same value (duplicate) as that value are simultaneously input to the majority logic.
- the ground state search of the applied Ising model can be realized by the energy minimization by the interaction between the spins described above. There is a possibility of falling into a solution. Basically, since there is only movement in the direction of decreasing energy, once it falls into the local optimal solution, it cannot get out of it and does not reach the global optimal solution. Therefore, as an action to escape from the local optimum solution, the spin array is randomly changed by inducing a bit error of the memory cell by lowering the power supply voltage supplied to the memory cell expressing the spin.
- the memory cells IS0, IS1, IU0, IU1, IL0, IL1, IR0, IR1, ID0, ID1, IF0, and IF1 of the spin unit 300 the memory cells IS0, IS1, IU0, and IU1 that hold coefficients.
- IL 0, IL 1, IR 0, IR 1, ID 0, ID 1, IF 0, IF 1 operate with the voltage supplied through the normal power supply line 142, but the memory cell N expressing the spin operates with the voltage supplied through the spin power supply line 141.
- all the components other than the memory cells, such as logic gates for calculating the interaction operate with the voltage supplied from the normal power supply line 142.
- the bit error rate of the memory cell is proportional to the supply voltage to the memory cell.
- the bit error rate is about 10 ⁇ 9 at 1 V, and this bit error rate is suitable for the original purpose of the memory to hold the stored contents. It is a thing. Therefore, generally, such a voltage is supplied to the memory cell and used at a bit error rate suitable for holding the stored contents.
- the memory cells IS0, IS1, IU0, IU1, IL0, IL1, IR0, IR1, ID0, ID1, IF0, and IF1 are always used in this state. As the voltage is further lowered from this voltage, the bit error rate also deteriorates in proportion to the voltage drop.
- the above-described memory cell N has a low power supply voltage such as 0.6 V applied to the spin power supply line 141 so as not to fall into a local optimum solution by searching a wider solution space at the initial stage of the ground state search, for example. To perform a ground state search by interaction in a situation where a random bit error occurs.
- the state basically shifts to a state where the energy is small due to the interaction, but at the same time, the state transitions randomly due to a bit error, so that the state cannot be changed only by the interaction. A transition to is also generated, and the solution space can be searched widely.
- the ground state search proceeds, in order to stabilize the state, the voltage is gradually changed to a state where the bit error rate hardly occurs.
- the voltage at which 0.6V, which is a voltage at which a bit error rate is likely to occur is initially supplied, and is gradually brought closer to about 1V at which the bit error rate is unlikely to occur.
- a random bit error may be simulated using a random number generation circuit, instead of a random bit error due to a supply voltage to the memory cell.
- a random number generation circuit may be provided in the spin unit 300, or a random number generation circuit may be provided in the Ising chip 100 to distribute and use the random number to each spin unit. Further, a random number generation circuit may be provided outside the Ising chip 100, and the chip may deliver random numbers from outside the chip.
- FIG. 10 shows wiring necessary for realizing the topology as shown in FIG. 5 with the spin units arranged as shown in FIG. 9 when attention is paid to a certain spin unit Nxyz. By performing such wiring for each spin unit, the topology of FIG. 5 can be realized.
- FIG. 6 shows a procedure in which the CPU 210 controls the Ising chip 100 to perform a ground state search.
- step S600 an interaction coefficient and an external magnetic field coefficient of the Ising model expressing the target problem are generated. In the example of the maximum cut problem, this is to generate an Ising model as shown in FIG. 14 when a maximum cut problem as shown in FIG. 13 is given.
- a spin assignment map is generated.
- the spin assignment map is information that defines how the Ising model is assigned to the Ising chip 100 when the Ising model to be solved is solved by the Ising chip 100.
- the Ising model in FIG. 14 is a complete graph in which four spins are all-to-all connected. This must be embedded in a three-dimensional lattice as shown in FIG.
- FIG. 16 shows a spin assignment map for the Ising model of FIG.
- the side where the interaction coefficient is +1 or ⁇ 1 is shown as such, and the side where no value is added is the interaction coefficient 0 (synonymous with no connection).
- spins A, B, C, and D of the Ising model of FIG. 14 (hereinafter referred to as the original Ising model) are assigned to the spins ⁇ 000, ⁇ 100, ⁇ 010, and ⁇ 110, respectively.
- the spin ⁇ xyz corresponds to the spin unit indicated by Nxyz on the Ising chip 100.
- J A, B (interaction coefficient between spins A and B), J A, C (interaction coefficient between spins A and C), J B, D (between spins B and D) in the original Ising model (Interaction coefficient), J C, D (interaction coefficient between spins C and D) are also expressed on the Ising chip using an XY plane whose coordinate in the Z-axis direction is 0 as shown in FIG. I can do it.
- J A, D interaction coefficient between spins A and D
- J B, C (interaction coefficient between spins B and C) on the diagonal of the lattice are expressed by the XY plane. It cannot be expressed.
- the copy spin is a spin that takes the same value in conjunction with the copy source spin.
- the Ising chip 100 can realize the copy spin by simply connecting to the copy source spin with the interaction coefficient 1.
- the interaction coefficients between ⁇ 110 ⁇ 111 ⁇ 101 ⁇ 001 are all +1.
- J A, D ( ⁇ 1 in this case) of the original Ising model is set between ⁇ 000 and ⁇ 001.
- the spin C ( ⁇ 010) is copied to ⁇ 020- ⁇ 120- ⁇ 220- ⁇ 210- ⁇ 200, and J between the ⁇ 200 and the spin B ( ⁇ 100) which are copy spins of the spin C Set B and C (+1 in this example).
- FIG. 17 and FIG. 18 are examples of the spin arrangement obtained as the ground state as a result of the ground state search of the Ising model of FIG. 17 and FIG. 18 in which all the spins are inverted are also in the ground state, which corresponds to the ground state at the time of inversion in FIG.
- step S602 an initial spin array that is an initial value of the spin array is generated.
- the initial spin array is generated randomly with random numbers.
- step S603 the coefficient obtained in step S600 and the initial spin arrangement obtained in step S602 are written into the memory cell of the Ising chip 100.
- data to be written to the Ising chip 100 is shown as data 2100 in FIG. Since the portion designated as N / A in the data 2100 is an unused spin, the value is not limited.
- the random part is the initial spin arrangement randomly generated in step S602.
- the other locations containing 0/1 are the coefficients obtained in step S600. This completes the initial setting.
- step S604 the interaction address 180 is input to the Ising chip 100, and in step S605, an interaction clock 181 is generated to cause an interaction in the Ising chip 100.
- step S606 the voltage supplied to the spin power supply line 141 is controlled according to the scheduling. Such control is repeated a predetermined number of times (step S607), and after the predetermined number of times is completed, the spin arrangement is read from the Ising chip 100 to obtain an answer (step S608).
- Ising chip control procedure 2 for coping with variations in memory cell characteristics
- the characteristics of the memory cells vary due to the spin units 300 in the spin array 110.
- Vth threshold voltage
- the cause of the variation may be fixed at the time of manufacture, such as RDF (Random Doppant Fluctuation), or may vary dynamically at the time of use, such as RTN (Random Brass Noise).
- RDF Random Doppant Fluctuation
- RTN Random Telegraph Noise
- Step S701 is the same as step S600.
- step S702 a plurality (n) of spin assignment maps are created. For example, in addition to the spin assignment map shown in FIG. 16, a total of two spin assignment maps of the spin assignment map shown in FIG. 23 are generated.
- the spin assignment map shown in FIG. 23 is an Ising model equivalent to the Ising model (original Ising model) of FIG. 14 as in FIG.
- the assignment of spin units on the Ising chip corresponding to the spins A, B, C, and D of the original Ising model is different from FIG. 16, and in the example of FIG.
- the spins are assigned to ⁇ 001, ⁇ 101, ⁇ 011, and ⁇ 111.
- the role of step S702 is to generate a plurality of spin assignment maps having different spins corresponding to the spins of the original Ising model.
- the method of assigning the interaction coefficient between the spins and the position of the copy spin also change accordingly.
- step S704 an initial spin array is randomly generated with random numbers in step S703.
- coefficients and an initial spin array are set in the Ising chip 100 according to one map among the plurality of spin assignment maps generated in step S702. For example, when the first map is shown in FIG. 16, the data 2100 shown in FIG.
- steps S705 to S707 the control of the interaction clock and the interaction address for causing the interaction and the control of the power supply voltage for spin for changing the memory cell at random are performed in the same manner as in steps S604 to S606. .
- the spin array is read once from the Ising chip 100 and saved in the RAM 220 of the information processing apparatus 200 (read and placed on the RAM 220).
- the array is hereinafter referred to as an intermediate spin array).
- FIG. 1 An example of data that can be read from the Ising chip 100 at this time is shown as data 2200 in FIG.
- the part corresponding to the interaction coefficient and the external magnetic field coefficient is not different from the value (data 2100) written in the Ising chip 100 in step S704.
- the value of the spin has changed as a result of the ground state search in steps S705 to S708.
- the portion designated as N / A in the data 2200 does not need to be read because it is an unused spin.
- tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, and tmp8 (hereinafter collectively referred to as tmpX) are portions used as copy spins and need not be read out.
- step S709 the locations indicated as A, B, C, and D in the data 2200, that is, the spin values to which the spins A, B, C, and D of the original Ising model are assigned (the corresponding memory locations are indicated by dotted lines). It only needs to be read.
- step S710 After reading the intermediate spin array, in step S710, the coefficients and the intermediate spin array are written to the Ising chip 110 using a map different from the spin assignment map used so far. As a result, since the spin unit 300 different from the previous one is assigned to the spin, the influence of the variation of the spin unit 300 is averaged. By repeating this operation, the ground state search is executed while changing the correspondence between the spin and the spin unit 300 in the middle, and the influence of the variation of the spin unit 300 remains on the specific spin (for example, the specific spin The ground state search can be realized by adapting to variations.
- step S709 values in the middle of the spins A, B, C, and D are read out. Therefore, data as indicated by data 2400 in FIG. N / A is an unused spin, and the value is arbitrary.
- the interaction coefficient and the external magnetic field coefficient of the data 2400 are generated from the spin assignment map of FIG. Then, the values of the spins A, B, C, and D are applied corresponding to the map of FIG. That is, in FIG.
- step S712 is performed.
- the spin arrangement is read out and the process ends. If the end condition is not satisfied, steps S705 to S711 are repeated.
- the ground state search is performed while changing the correspondence between the spin of the Ising model in question and the spin unit 300 on the Ising chip 100.
- FIG. 27 shows a time chart when the Ising chip 100 is controlled by the procedure shown in FIG. First, in the initial setting phase, an operation corresponding to step S704 is performed. At this time, the SRAM compatible interface 150 is controlled and data 2100 is written. Note that the voltage supplied to the spin power supply line 141 is set to a voltage sufficient to hold the memory cell. Thereafter, in the ground state search phase 1, operations corresponding to steps S705 to S708 are performed. At this time, the interaction control interface 160 is controlled to perform the interaction between the group A and the group B alternately. In parallel with this, the power supply voltage supplied to the spin power supply line 141 is gradually lowered. Thereby, a ground state search is performed.
- the rearrangement phase changes the correspondence between the spin unit 300 of the Ising chip 100 and the spin of the Ising model to be solved.
- the rearrangement phase corresponds to steps S709 to S710.
- the power supply voltage of the spin power supply line 141 that has been lowered during the ground state search is restored. This is because, in the rearrangement phase, reading / writing is performed on the memory cell expressing the spin, so that the behavior is equivalent to that of a normal memory.
- the spin value is read once (data 2200 is read), and new data (data 2400) generated based on another spin assignment map is written.
- the ground state search is continued under the same control as in the ground state search phase 1.
- the voltage of the spin power supply line 141 may take over the voltage value at the end of the ground state search phase 1 or may be redone from the initial voltage (a voltage sufficient to hold the memory cell memory).
- the Ising chip 100 of the present invention searches for the ground state of a given Ising model (for example, FIG. 14), and answers the problem of FIG. 14 (the spin arrangement of the ground state) as shown in FIG. Obtainable.
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Abstract
Description
その一つの候補としてイジングモデルがある。イジングモデルは磁性体の振舞いを説明するための統計力学のモデルであり、磁性体の研究に用いられている。イジングモデルはサイト(+1/-1の2値をとるスピン)間の相互作用として定義される。トポロジが非平面グラフになるイジングモデルの基底状態を求めることはNP困難問題であることが知られている。イジングモデルは空間方向に広がった相互作用係数で問題を表現するため、本質的な並列性を利用した情報処理を実現できる可能性がある。
イジングモデルは磁性体の振舞いを説明するための統計力学のモデルである。イジングモデルは+1/-1(または、0/1、上/下)の2値をとるスピンと、スピン間の相互作用を示す相互作用係数、および、スピン毎にある外部磁場係数で定義される。
例えば、因数分解や巡回セールスマン問題など、一見すると磁性体と何ら関係の無い問題をイジングモデルに変換することができる。そして、変換して得られたイジングモデルの基底状態は、元の問題の解に対応している。このことから、イジングモデルの基底状態を探索することのできる装置は、汎用的な用途に利用可能なコンピュータであると言える。
なお、図11、及び、図12は無向グラフの例であるが、有向グラフに拡張することも出来る。
最大カット問題の具体的な例を図13に示す。この例では頂点VをV’={A,B}とV’\V={C,D}に分けるようにカットした時に、カットの大きさw(V’)=2となり、このグラフにおける最大カットとなる。
図1は、本実施例のイジングチップ100の構成図の例である。イジングチップ100はスピンアレイ110、I/Oドライバ120、I/Oアドレスデコーダ130、および、相互作用アドレスデコーダ140から構成される。本実施例ではイジングチップ100は現在広く用いられているCMOS集積回路として実装されることを想定して説明するが、他の固体素子でも実現可能である。イジングチップ100は、スピンアレイ110にリード/ライトを行うためのSRAM互換インタフェース150を持っており、アドレスバス190、データバス191、R/W制御線193、および、I/Oクロック192である。また、イジングモデルの基底状態探索の制御を行うための相互作用制御インタフェース160として、相互作用アドレス180、および、相互作用クロック181を有している。イジングチップ100は通常電源線142で供給される電圧で動作するが、スピンアレイ110の一部はスピン用電源線141で供給される電圧で動作する。具体的には、スピンアレイ110を構成するスピンユニット300(図3)が有するメモリセルのうち、スピン情報を保持するメモリセルNはスピン用電源線141で供給される電圧で動作する。
イジングチップ100ではスピンアレイ110が多数のスピンユニット300(詳細は後述する)を持つことで、高い並列性を実現している。このように空間的に多数の並列性を利用する上では、その多数の構成要素に生じる特性のばらつきに適応することが必要となる。このような製造ばらつきへの適応は、例えばデバイスに対して製造ばらつきを吸収するための回路を付加し、その回路にある抵抗値等の回路定数を調整することで個体差に適応することが一般的に考えられる。また、複数個のデバイス(トランジスタ)を並列接続することで、個体差を平均化するという方法もある。いずれの場合でも、個体差に適応するために回路やデバイスの付加ないしは冗長化を行っており、回路規模の増大を招くという副作用を持っている。
そこで、本発明では後述するように、解くべきイジングモデルのスピンと、スピンアレイ110内のスピンユニット300との対応関係を変更しながら基底状態探索を行うことで、ハードウェアが複雑化することを最小限に抑えながら、製造ばらつきに適応することを実現する。これによって、高いスケーラビリティを実現する。
このイジングチップ100を1個、または、複数個用いて情報処理を実現するわけであるが、そのためには前述したようなインタフェースを制御しなければならない。そのために、イジングチップ100は図2に示すような情報処理装置200の一部として利用される。
スピンアレイ110は、1個のスピンとそれに付随する相互作用係数、及び、外部磁場係数の保持と、基底状態探索処理を実現するスピンユニット300を基本構成単位として、スピンユニット300を多数個並べて構成する。図5はスピンユニット300を複数個並べることで、3次元格子状のトポロジを持つイジングモデルを構成する例を示している。図5の例は、3(X軸方向)×3(Y軸方向)×2(Z軸方向)の大きさの3次元格子である。座標軸の定義は図示した通り、図面右方向をX軸、図面下方向をY軸、図面奥行き方向をZ軸としているが、この座標軸は実施例の説明上便宜的に必要なだけであり、発明とは関係しない。3次元格子以外のトポロジ、例えばツリー状のトポロジなどを利用する場合には、座標軸とは別にツリーの段数等で表現することになる。図5の3次元格子状のトポロジにおいて、スピン間の相互作用をグラフとしてとらえると、最大で次数5のスピン(頂点)が必要となる。なお、外部磁場係数の接続も含めて考えると、最大で次数6が必要となる。
スピンユニット300の構成の一例を図3と図4を用いて説明する。スピンユニット300は2つの側面をもっており、便宜上、図3と図4に分けて説明するが、1個のスピンユニット300に図3と図4の構成の双方が含まれるものである。図3はスピンユニット間の相互作用を実現するための回路を図示し、図4はスピンユニットが有するメモリセルにイジングチップ100外からアクセスするためのインタフェースであるワード線とビット線に注目して図示したものである。なお、図3の相互作用を実現するための回路において図示されているインタフェースであるEN,NU,NL,NR,ND,NF,Nを、複数のスピンユニット間でどのように結線するかについては、後に図10及び図25を参照して説明する。また、図4のワード線及びビット線を複数のスピンユニット間でどのように結線するかについては、後に図9を参照して説明する。
ここで、スピンユニット300はi番目のスピンを表現するものとして説明を行う。メモリセルNはスピンσiを表現するためのメモリセルでありスピンの値を保持する。スピンの値はイジングモデルでは+1/-1(+1を上、-1を下とも表現する)であるが、これをメモリセルの2値である0/1に対応させる。例えば、+1を1、-1を0に対応させる。
スピンアレイ110の構成を、半導体装置としてのレイアウトの観点から図9で説明する。本実施例のスピンアレイ110は図5に示したように3次元格子のトポロジを持つため、2次元平面上に回路を構成する半導体装置として実現するためには、レイアウト上の工夫が必要となる。そこで、図9に示すような配置を取る。なお、図9上で表現されているスピンユニット300(NxyzというようにX軸、Y軸、Z軸上の位置によって符号を付与している)が、3次元格子のトポロジでどの頂点に対応するかを図8で示す。3×3×2の3次元格子頂点を2次元平面上に配置するために、X軸方向の格子頂点配列の間隔にZ軸方向の格子頂点配列の各格子頂点を挿入するように配置している。すなわち、図9の2次元平面上でのY軸方向(図面下側がY軸正の方向)にはNx0z,Nx1z,Nx2zというように配置されるが、X軸方向(図面右側がX軸正の方向)にはN0y0,N0y1,N1y0,N1y1,N2y0,N2y1というように、Z軸方向座標が0と1のスピンユニットが交互に配置される。
イジングモデルの基底状態探索を実現するためには、イジングモデル全体のエネルギーがより低いスピン配列になるように遷移していくように、スピン間の相互作用を実現しなければならない。このための相互作用は、与えられた相互作用係数と外部磁場係数に基づいて行われる。つまり、あるスピンの次の値を、そのスピンに接続されている他のスピンからの相互作用と、そのスピンが持つ外部磁場係数から決定する。このとき、スピンの次の値は、そのスピンが接続されている範囲内での局所的なエネルギーを最小化するような値になる。
スピンユニット300は同時に更新を行うために、相互作用を計算して次のスピンの状態を決定するための回路を、スピンユニット毎に独立して持っている。スピンの次状態を決定するための回路を図3に示す。図3ではスピンユニットは外部とのインタフェースとして、EN,NU,NL,NR,ND,NF,Nを有する。ENは当該スピンユニットのスピンの更新を許可する信号を入力するインタフェースである。Nは当該スピンユニットのスピンの値を他のスピンユニット(図5のトポロジで隣接するユニット)に出力するインタフェースである。NU,NL,NR,ND,NFはそれぞれ他のスピンユニット(図5のトポロジで隣接するユニット)の有するスピンの値を入力するためのインタフェースである。NUは上側のスピン(Y軸方向で-1)、NLは左側のスピン(X軸方向で-1)、NRは右側のスピン(X軸方向で+1)、NDは下側のスピン(Y軸方向で+1)、NFは奥行き方向に接続するスピン(Z軸方向で+1ないしは-1)からの入力である。なお、イジングモデルのトポロジを考える上で、端の処理を決める必要がある。図5のトポロジのように単に端は打ち切るのであれば、NU,NL,NR,ND,NFのうち端に対するものは何も入力しなくて良い(回路上は0ないしは1の固定値に接続するなど、未使用入力端子として適切な処理をとる)。例えばN000のスピンユニットの場合には、NU及びNLの2端子は入力が無い。
前述したスピン間の相互作用によるエネルギー最小化で、適用されたイジングモデルの基底状態探索を実現することが出来るが、これだけでは局所最適解に陥ってしまう可能性がある。基本的に、エネルギーを小さくする方向の動きしかないため、一旦局所最適解に陥るとそこから抜け出すことが出来ず、大域最適解に到達しない。そのため、局所最適解から脱出するための作用として、スピンを表現するメモリセルに供給する電源電圧を下げることで、メモリセルのビットエラーを誘発することで、スピン配列をランダムに変化させる。そのため、スピンユニット300が有するメモリセルN,IS0,IS1,IU0,IU1,IL0,IL1,IR0,IR1,ID0,ID1,IF0,IF1のうち、係数を保持するメモリセルIS0,IS1,IU0,IU1,IL0,IL1,IR0,IR1,ID0,ID1,IF0,IF1は通常電源線142で供給する電圧で動作するが、スピンを表現するメモリセルNはスピン用電源線141で供給する電圧で動作する。なお、メモリセル以外の構成要素、例えば相互作用を計算するための論理ゲート等は全て通常電源線142で供給する電圧で動作する。
図3で示したスピンユニットのインタフェースである、EN,NU,NL,NR,ND,NF,Nについて、ENの配線に関しては図25で説明した通りだが、NU,NL,NR,ND,NF,Nの配線の例については図10に示す。図10は、ある1個のスピンユニットNxyzに注目した時に、図5に示すようなトポロジを図9のように配置したスピンユニットで実現するために必要な配線を示している。このような配線をスピンユニット毎に行うことで、図5のトポロジを実現することが出来る。
このイジングチップ100を組みこんだ情報処理装置200において、イジングチップ100をCPU210が制御して基底状態探索を行う手順を図6に示す。
ステップS600において、対象問題を表現するイジングモデルの相互作用係数と外部磁場係数を生成する。これは、最大カット問題の例で言えば、図13に示すような最大カット問題が与えられた時に、図14に示すようなイジングモデルを生成することである。
ステップS603において、ステップS600で得られた係数と、ステップS602で得られた初期スピン配列を、イジングチップ100のメモリセルに書込む。この時、イジングチップ100に書き込むデータを図21にデータ2100として示す。データ2100でN/Aとされている箇所は未使用のスピンなので値は問わない。ランダムとされている箇所はステップS602でランダムに生成された初期スピン配列である。それ以外の0/1の値が入っている箇所は、ステップS600で得られた係数である。これで初期設定が完了する。
ところで、前述したようにこのようなイジングチップ100を製造すると、スピンアレイ110内のスピンユニット300によって、メモリセルの特性にばらつきが生じる。ばらつきの原因は様々であるが、メモリセルを構成するトランジスタの強い閾値電圧(Vth)がばらつき、それによってメモリセルにおいて電源電圧を下げるなど不安定な状態にしたときに、0になりやすいか、1になりやすいかの個体差が生まれてくる。ばらつきの要因はRDF(Random Dopant Fluctuation)の様に製造時に固定的に決まるものもあれば、RTN(Random Telegraph Noise)の様に使用時に動的に変化するばらつきもある。いずれにしても、ばらつきがあるメモリセルは局所最適解から抜け出そうとしてメモリセルのランダム性を得ようとするときに、偏ったランダム性を生みだすことになり、その結果として探索できる解空間の範囲を狭めてしまう。
すなわち、本発明では、基底状態探索の途中で、対象問題のイジングモデルのスピンと、イジングチップ100上のスピンユニット300の対応関係を変えながら基底状態探索を行う。スピンとスピンユニットの対応関係を変えるためには、途中のスピン配列を一時的に保存して、別のスピンユニット300に係数と共に書込み直さなければならない。これを前述した図7の動作で実現し、それによってスピンユニット300の製造ばらつきに適応したイジングチップ100を実現するものである。
まず、初期設定フェーズではステップS704に対応する動作が行われる。この時、SRAM互換インタフェース150を制御して、データ2100の書き込みを行う。なお、スピン用電源線141に供給する電圧は、メモリセルの記憶を保持するために十分な電圧とする。
その後、基底状態探索フェーズ1ではステップS705~S708に対応する動作が行われる。この時、相互作用制御インタフェース160を制御して、グループAとグループBの相互作用を交互に行う。それと並行して、スピン用電源線141に供給する電源電圧を徐々に下げていく。これによって、基底状態探索が行われる。
その後、基底状態探索フェーズ2では、基底状態探索フェーズ1と同様の制御で基底状態探索を続ける。この時、スピン用電源線141の電圧は基底状態探索フェーズ1終了時の電圧値を引き継いでも良いし、初期の電圧(メモリセルの記憶を保持するために十分な電圧)からやり直しても良い。
110 スピンアレイ
120 I/Oドライバ
130 I/Oアドレスデコーダ
140 相互作用アドレスデコーダ
141 スピン用電源線
142 通常電源線
150 SRAM互換インタフェース
160 相互作用制御インタフェース
180 相互作用アドレス
181 相互作用クロック
190 アドレスバス(SRAM互換インタフェース)
191 データバス(SRAM互換インタフェース)
192 I/Oクロック(SRAM互換インタフェース)
193 R/W制御線(SRAM互換インタフェース)
200 情報処理装置
210 CPU
220 RAM
230 システムバス
240 NIC
250 イジングチップコントローラ
260 HDD
290 装置間ネットワーク
300 スピンユニット
410,902,1930 ビット線
420,901,1920 ワード線
1900 メモリセル
1950 パスゲートトランジスタ
1960 データ保持部
N スピンを表現するメモリセル、及び、スピンの値を出力するインタフェース
IS0 外部磁場係数が0であるかどうかを示すメモリセル
IS1 外部磁場係数の+1/-1を示すメモリセル
IU0,IL0,IR0,ID0,IF0 相互作用係数が0であるかどうかを示すメモリセル
IU1,IL1,IR1,ID1,IF1 相互作用係数の+1/-1を示すメモリセル
Claims (11)
- イジングモデルの1つのスピンの値を記憶するメモリセルと、該スピンに相互作用を及ぼす隣接するスピンからの相互作用係数を記憶するメモリセルと、前記1つのスピンの外部磁場係数を記憶するメモリセルと、並びに、前記各隣接スピンの値と前記対応する相互作用係数の積、及び前記外部磁場係数において、2値の多数決論理によって前記1つのスピンの次状態を決定する回路とを有するスピンユニットが構成され、
前記イジングモデルの各スピンをそれぞれ割り付けられた複数の前記スピンユニットが、前記イジングモデルのトポロジを維持した状態で、半導体基板上の2次元平面に配置、接続されて構成されたスピンアレイを備えたことを特徴とする半導体装置。 - 前記スピンユニットを構成する前記1つのスピンの値を記憶するメモリセルは2値を表現する1ビットメモリにより構成され、
前記スピンユニットを構成する前記1つのスピンの外部磁場係数を記憶するメモリセルと、及び前記1つのスピンに相互作用を及ぼす隣接するスピンからの相互作用係数を記憶するメモリセルは、それぞれ3値を表現する1組の1ビットメモリ2個より構成されていることを特徴とする請求項1に記載の半導体装置。 - 前記スピンアレイ内に配置された各スピンユニットが有する前記スピンの値を記憶するメモリセルに、その他のメモリセル、及び回路へ電源を供給する電源線とは区別する専用の電源線が接続され、
前記各スピンユニットにおいて、前記スピンの次状態を決定する処理を実行時に、前記専用の電源線を介して前記スピンの値を記憶するメモリセルへ供給する電源電圧を下げる制御が為されることを特徴とする請求項1に記載の半導体装置。 - 前記スピンアレイ内に配置された各スピンユニットに相互作用制御インタフェースが接続され、
前記隣接して相互作用を及ぼす関係にあるスピンがそれぞれ割り付けられた前記スピンユニット同士を別々のグループに分けて、前記各グループ分けされたスピンユニットに対して、各グループに属する全てのスピンユニットにスピンの次状態を決定する処理を許可する信号を入力する信号線が接続されていることを特徴とする請求項1に記載の半導体装置。 - 前記グループ分けされたスピンユニットを、同時に実行する消費電力に応じて更に細分割したグループに分け、前記分割された各グループに属する全てのスピンユニットにスピンの次状態を決定する処理を許可する信号を入力する信号線が接続されていることを特徴とする請求項4に記載の半導体装置。
- 請求項1に記載の半導体装置において、
前記イジングモデルの各スピンをそれぞれ割り付けられた複数の前記スピンユニットが、前記イジングモデルのトポロジを維持した状態で、半導体基板上の2次元平面に配置、接続されて構成されたスピンアレイとは、
前記スピンアレイ内に配置された各スピンユニットが、3次元格子のイジングモデルの各格子頂点を2次元平面に配置する方法として、X軸方向の格子頂点配列の各間隔にZ軸方向の格子頂点配列の各格子頂点を挿入するように、及びY軸方向の格子頂点配列は同様の配列で、各格子頂点のスピンを割り付けた各スピンユニットが半導体基板上に配置され、並びに、前記各スピンユニット間を3次元格子のトポロジを維持した状態で配線接続されたことであることを特徴とする半導体装置。 - 前記メモリセルは、CMOSインバータ2個で構成されるデータ保持部と、パスゲートトランジスタとを備えることを特徴とする請求項1乃至3のいずれかの請求項に記載の半導体装置。
- CPU、RAM、HDD、及び請求項1乃至6のいずれかの請求項に記載された半導体装置をシステムバスに接続した情報処理装置であって、
前記CPU上で実行された前記半導体装置の制御プログラムは、
対象問題を表現するイジングモデルの相互作用係数と外部磁場係数を生成し、
前記イジングモデルの各スピンを前記半導体装置上の前記スピンアレイ内の前記スピンユニットへの割当てを決定し、
初期スピン配列をランダムに生成し、
前記イジングモデルの各スピンを割当てた前記半導体装置上の前記スピンアレイ内の前記スピンユニットへ、前記初期スピン配列、前記相互作用係数、及び前記外部磁場係数を書き込み、
グループ分けした前記スピンユニットの基底状態探索処理を所定の回数繰り返し実行し、
基底状態に達した前記スピンユニットのスピン配列を読み出して対象問題の解を得ることを特徴とする情報処理装置。 - CPU、RAM、HDD、及びアクセラレータとして適用が可能な半導体装置をシステムバスに接続した情報処理装置であって、
前記半導体装置は、
イジングモデルの1つのスピンの値を記憶するメモリセルと、該スピンに相互作用を及ぼす隣接するスピンからの相互作用係数を記憶するメモリセルと、前記1つのスピンの外部磁場係数を記憶するメモリセルと、並びに、前記各隣接スピンの値と前記対応する相互作用係数の積、及び前記外部磁場係数において、2値の多数決論理によって前記1つのスピンの次状態を決定する回路とを有するスピンユニットが構成され、
前記イジングモデルの各スピンをそれぞれ割り付けられた複数の前記スピンユニットが、前記イジングモデルのトポロジを維持した状態で、半導体基板上の2次元平面に配置、接続されて構成されたスピンアレイと、
前記スピンアレイ内に配置されたスピンユニットのメモリセルをリード/ライトするI/Oインタフェースと、
グループ分けされたスピンユニットに対して、グループ毎に、相互作用を許可する信号を供給する相互作用制御インタフェースとを備え、
前記CPU上で実行された前記半導体装置の制御プログラムは、
対象問題を表現するイジングモデルの相互作用係数と外部磁場係数を生成し、
前記イジングモデルの各スピンを前記半導体装置上の前記スピンアレイ内の前記スピンユニットへの割当てを決定し、
初期スピン配列をランダムに生成し、
前記イジングモデルの各スピンを割当てた前記半導体装置上の前記スピンアレイ内の前記スピンユニットへ、前記初期スピン配列、前記相互作用係数、及び前記外部磁場係数を書き込み、
グループ分けした前記スピンユニットの基底状態探索処理を所定の回数繰り返し実行し、
基底状態に達した前記スピンユニットのスピン配列を読み出して対象問題の解を得ることを特徴とする情報処理装置。 - 前記CPU上で実行された前記半導体装置の制御プログラムが、グループ分けした前記スピンユニットの基底状態探索処理を所定の回数繰り返し実行するステップは、
前記スピンユニットのグループを選択するアドレスを設定し、
前記選択したグループのスピンユニットの相互作用を起こさせるクロックを生成し、
前記スピンユニットのスピンの値を記憶するメモリセルに接続する電源線に供給される電圧をスケジューリングに沿って下げる制御を行い、
前記選択するグループを順次変えて、上記処理を所定の回数繰り返し実行するステップであることを特徴とする請求項8、または請求項9に記載の情報処理装置。 - 請求項8、または請求項9に記載の情報処理装置において、
前記CPU上で実行された前記半導体装置の制御プログラムは、
前記イジングモデルの各スピンを前記半導体装置上の前記スピンアレイ内の前記スピンユニットへの互いに異なる割当てマップを複数生成し、
第1の割当てマップに従って、前記スピンユニットへ、前記初期スピン配列、前記相互作用係数、及び前記外部磁場係数を書き込み、
グループ分けした前記スピンユニットの基底状態探索処理を所定の回数繰り返し実行し、
前記スピンユニットのスピン配列を読み出して記録し、
次に適用する割当てマップに従って、前記記録したスピン配列を新たな割当てスピンユニットの初期スピン配列とし、イジングモデルの相互作用係数と外部磁場係数を再生成して、前記スピンユニットへ、前記初期スピン配列、前記相互作用係数、及び前記外部磁場係数を書き込み、
新たな割当てマップに従って、グループ分けした前記スピンユニットの基底状態探索処理を所定の回数繰り返し実行することを特徴とする情報処理装置。
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JP2020021209A (ja) * | 2018-07-31 | 2020-02-06 | 富士通株式会社 | 最適化装置、最適化装置の制御方法及び最適化装置の制御プログラム |
JP7071638B2 (ja) | 2018-07-31 | 2022-05-19 | 富士通株式会社 | 最適化装置、最適化装置の制御方法及び最適化装置の制御プログラム |
EP3745319A1 (en) | 2019-05-29 | 2020-12-02 | Fujitsu Limited | Optimization apparatus and optimization method |
US11526740B2 (en) | 2019-05-29 | 2022-12-13 | Fujitsu Limited | Optimization apparatus and optimization method |
US11966716B2 (en) | 2019-09-06 | 2024-04-23 | Hitachi, Ltd | Apparatus and method for fully parallelized simulated annealing using a self-action parameter |
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US10191880B2 (en) | 2019-01-29 |
US20170068632A1 (en) | 2017-03-09 |
JP6177993B2 (ja) | 2017-08-09 |
JPWO2015132883A1 (ja) | 2017-03-30 |
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