WO2015124170A1 - Procédé et dispositif d'émulation d'une commande à programme enregistré - Google Patents

Procédé et dispositif d'émulation d'une commande à programme enregistré Download PDF

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Publication number
WO2015124170A1
WO2015124170A1 PCT/EP2014/053120 EP2014053120W WO2015124170A1 WO 2015124170 A1 WO2015124170 A1 WO 2015124170A1 EP 2014053120 W EP2014053120 W EP 2014053120W WO 2015124170 A1 WO2015124170 A1 WO 2015124170A1
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WO
WIPO (PCT)
Prior art keywords
time
virtual
cycle
program
real
Prior art date
Application number
PCT/EP2014/053120
Other languages
German (de)
English (en)
Inventor
Gustavo Quiros Araya
Rene Ermler
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to PCT/EP2014/053120 priority Critical patent/WO2015124170A1/fr
Publication of WO2015124170A1 publication Critical patent/WO2015124170A1/fr

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B17/00—Systems involving the use of models or simulators of said systems
    • G05B17/02—Systems involving the use of models or simulators of said systems electric
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/058—Safety, monitoring
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13186—Simulation, also of test inputs

Definitions

  • the present invention relates to a method for emulating a programmable logic controller according to the preamble of claim 1. Moreover, the present invention relates to a device for emulating a programmable logic controller according to the preamble of claim 9.
  • a programmable logic controller PLC
  • a non-real-time platform for example, Microsoft Windows operating system
  • the duration of execution of a program cycle is unpredictable and unpredictable, because this can in principle be delayed arbitrarily due to the execution of concurrent processes. If the virtual duration of the emulation is represented as a linear map of the real time required to emulate the program cycle, then the emulation is prone to misleading cycle timeouts.
  • cycle time violations in PLC emulation can be reported (for example, by alarms), which have external platform-related causes and are meaningless for the emulation.
  • time delays for the cyclic execution must be inserted in cycle time overruns in order to avoid overlapping of the successive time phases.
  • a linear mapping of the real time axis to a virtual time axis is used in the emulation of SPS.
  • a suitable increase for the linear mapping is selected. This can be determined, for example, by estimating the execution time of the program cycle during the PLC simulation. This approach avoids misleading cycle time overruns only on average chen versions in which the underlying operating system is used to a limited extent. Otherwise, the approach is vulnerable to the above problem. Although the alarms for cycle time violations could be suppressed, time shifts are unavoidable.
  • the method according to the invention for emulating a programmable logic controller comprises the provision of a computing device with an operating system which makes reference to a memory-programmable controller
  • Real-time requirement mapping a real time period to a virtual time period based on a predetermined function, predetermining a threshold for the virtual time required to emulate the at least one program cycle of a program of the programmable controller, emulating the at least one program cycle with the computing device and checking for a presence of a cycle timeout of the emulated program cycle in response to the threshold, mapping the real time period to the virtual time based on an asymptotic function.
  • a non-real-time computing device or a non real-time capable platform is used.
  • a computer with a Microsoft Windows operating system can be used.
  • the program of the programmable logic controller can be divided into several program cycles, for example, each having the same time duration. In this case, first a first program cycle is simulated with the computing device. Following this, the remaining program cycles can be emulated. This determines the virtual time required to emulate the program cycle. This virtual time period is compared to a threshold. If this limit is exceeded, for example, a cycle time violation can be concluded.
  • the real time of the PLC is first mapped to the virtual time period based on a predetermined mapping rule.
  • the real time duration is mapped onto the virtual time duration on the basis of an asymptotic function.
  • the virtual time period initially increases faster compared to the real time period and slows down towards the end of the program cycle.
  • reaching the predetermined limit value can be avoided.
  • misleading cycle time violations caused, for example, by concurrent processes of the non-real-time computing device can be avoided.
  • the asymptotic function mapping the real time period to the virtual time period approaches the predetermined threshold.
  • the limit value can be determined, for example, in advance of the emulation based on a maximum cycle duration of the program cycle.
  • the limit value can be determined during the engineering of the programmable logic controller.
  • the asymptotic function with which the real time duration is mapped onto the virtual time duration is preferred. directly proportional to the real time duration. Thus, asymptotic behavior can be easily used to model the progression of virtual time.
  • the asymptotic function with which the real time duration is mapped to the virtual time duration corresponds to a step response of a transmission element which has a proportional transmission behavior in a first-order delay.
  • the progress of the virtual time can be modeled on the basis of a step response of a PTI element. In this way, a corresponding asymptotic course of the virtual time duration can be modeled.
  • the computing device preferably comprises a virtual timer with which a virtual time is set when the emulation of the program cycle starts.
  • the emulator can have an internal clock with which the virtual time of the emulator or the computing device can be manipulated.
  • the current time of the virtual time can be set explicitly.
  • the virtual clock of the computing device can be arbitrarily set in the simulation environment.
  • the virtual time is determined by the virtual timer from a system time of the operating system of the computing device. With the PLC emulation the system time of the operating system can be used, which corresponds to the real time of the simulation environment. Thus, the virtual time can be calculated from the system time of the operating system.
  • the virtual time from the system time of the operating system is mapped using an asymptotic function.
  • the time advance of the virtual time can be calculated similarly to the above-mentioned asymptotic function.
  • faulty cycle time violations can be avoided.
  • a second program cycle of a second program is emulated with a second computing device.
  • various programmable logic controllers can be emulated simultaneously. In this way, a real system of a programmable logic controller can be modeled more accurately.
  • the device according to the invention for emulating a memory-programmable controller comprises a computing device with an operating system which is insufficient with respect to a real-time request made to the programmable controller, wherein the computing device is designed to emulate at least one program cycle of a program of the programmable logic controller with the computing device and wherein the device is configured to map a real time period to a virtual time period based on a predetermined function, to predetermine a limit value for the virtual time period required to emulate the at least one program cycle, and to provide a cycle timeout of the emulated program cycle depending on the limit value
  • the device is designed to map the real time duration to the virtual time duration on the basis of an asymptotic function.
  • Emulation of the programs is shown; 3 shows a diagram in which the temporal behavior of an emulated programmable logic controller is shown;
  • Time duration is represented on a virtual time period based on asymptotic functions
  • FIG. 5 shows a diagram which shows the difference between a linear mapping and an asymptotic mapping of the real time duration to the virtual time duration.
  • FIG. 1 shows a diagram 10 in which the time profile for a real system with two programmable logic controllers and two processes is shown.
  • the course of the real time duration t R is shown on a time axis.
  • the time course of a program 12 of a first programmable logic controller is shown.
  • the time course of a program 14 of a second programmable logic controller is shown.
  • the time course of a third and a fourth program 16, 18 is shown, which are simulated, for example.
  • the programs 12, 14, 16, 18 are each divided into predetermined program cycles, which in particular have the same time phases A, B. In the real system according to FIG. 1, all four arithmetic units execute the programs 12, 14, 16, 18 simultaneously.
  • FIG. 1 shows a diagram 10 in which the time profile for a real system with two programmable logic controllers and two processes is shown.
  • the course of the real time duration t R is shown on a time axis.
  • FIG. 2 shows a possible chronological progression of the programs 12, 14, 16, 18 according to FIG. 1 for a corresponding emulation.
  • the time phases A, B for the respective units are successively discharged one after the other. so that in the real time axis t R each time phase A, B occurs several times.
  • the virtual time t v corresponds to the real time axis of the simulated system and, in the case of simulation or emulation, forms a discontinuous sequence of timeline segments over the real time axis of the simulation system.
  • the overlapping of the segments on the real time axis t R is possible because of a parallel execution of the units. This is shown in FIG.
  • FIG 3 shows the temporal behavior of an emulated programmable logic controller for the first program 12 in a diagram 24.
  • a basic cycle time of 100 ms is specified for the user program.
  • the program 12 is thus divided into program cycles with the determined basic cycle time.
  • the emulated PLC executes each program cycle individually, analogous to the phased implementation of FIG 1. Since the real time t R and the virtual time t v are decoupled, each program cycle can begin before or after the corresponding real time of the cycle timing. However, at each beginning of the cycle, a virtual clock in the computing device can be reset so that the execution always starts with a correct virtual time.
  • the actual duration of the execution of the program - measured on the real time axis t R - depends on the underlying operating system and can in principle deviate arbitrarily from the targeted cycle time of 100 ms. However, exceeding the maximum cycle time does not mean that a cycle time violation has or would have occurred in the user program. In general, such an infringement when emulated on a non-real-time system (for example, Microsoft Windows) is not clearly identifiable and should therefore be excluded. On the other hand, these border crossings would have to be avoided because otherwise two consecutive virtual time phases could overlap. This raises the question of how the virtual time t v during the execution of the program cycle should progress. Here, different approaches can be followed.
  • no advance of the virtual time can be provided.
  • the virtual clock stops during the cycle and thus does not exceed the planned cycle time.
  • This approach would be easy to implement, but leads to the problem that all events that occur during the cycle show the same timestamp. For example, the causality of alarms on the basis of a time sequence in an operating system would not be recognizable. Therefore, an advance of the virtual time t v during execution of a program cycle is desired.
  • Another approach would be the linear progression of the virtual time t v .
  • the virtual time increases linearly with the real time t R. This can be made possible for example by the use of a counter or a linear mapping function of the real time t R. Although the time progress is given, an overlap of the planned cycle time is also possible.
  • an asymptotic advance of the virtual time t v is considered.
  • the virtual time rises asymptotically with the real time t R to a limit value T.
  • the limit value T is the time limit for the maximum cycle duration. This means that the virtual time t v runs faster at the beginning of the cycle and slows to the end of the cycle to avoid reaching the time limit. According to this approach, the time progress within the cycle is guaranteed and at the same time an exceeding of the planned cycle time is excluded. Theoretically, these two properties are always met, even with arbitrarily long execution times. In practice, however, one encounters the limitation of the finite resolution of the time values.
  • T and D are used, where T is the limit value for the asymptotic function and D is a factor with which an approaching speed to the limit value T can be set.
  • a function corresponding to a step response of a PT1 element may be used for the modeling of the progress of the virtual time t v .
  • FIG 4 graphically illustrates the asymptotic progress of the virtual time t v (vertical axis) with the real time t R (horizontal axis).
  • the threshold value T in the present embodiment corresponds to ten time units.
  • four functions are exemplified.
  • the graph 26 of the figure according to equation (1), with D 10.
  • a general observation is that the maps according to equation (2) reach the limit faster than the maps according to equation (1). With a suitable selection of the value D, however, both functions should be useful for modeling and implementing virtual time progress.
  • each simulation device or simulator of the simulation environment must have an internal clock which stores the virtual time t v for this unit (in addition to the real time of the simulation environment). This clock must enable the explicit manipulation of the virtual time t v of the emulator by setting the current time.
  • the current time of the virtual clock can in particular be set explicitly. This allows the clock to "spin" both forward and backward and is effectively used to "jump into time”. Based on this operation, the virtual clocks of the emulators in the simulation environment can be set arbitrarily. At the start of the cycle, the virtual clock with the appropriate value for the beginning of the cycle can be set for each emulator. In any case, the control of the simulation environment ensures that the individual internal virtual clocks of the respective emulation units remain synchronized during the simulation.
  • the system time of a real PLC is usually continued via timer interrupts and updated to new values.
  • the system can instead be used by the operating system, which corresponds to the real time t R of the simulation environment and which has not been modified by the emulator.
  • a useful approach for the virtual clock of the PLC simulation is therefore to calculate the virtual time from the system time of the operating system. For this calculation the functions mentioned for the time progress can be used.
  • mapping of the real time t R to the virtual time t v in a PLC simulation is based on an asymptotic function, while the mapping function used hitherto is usually linear in simulation programs. Unlike linear
  • FIG. 4 shows a diagram 34 in which the behavior of a linear time map (curve 36) and an asymptotic time map (curve 38) are shown.
  • a limit value T of 10 ten units is considered.
  • the increase in linear mapping corresponds to a factor of 0.1.
  • the approaching speed factor D in the asymptotic mapping corresponds to the value 5.
  • the linear time map (curve 36) reaches the limit value 10 of the virtual time t v at a real time t R of 100. This results in two possible situations in the execution of a program cycle. First, the execution is completed under 100 real time units t R. Regardless of the approach used, no misleading cycle time violation is caused. Alternatively, the embodiment requires 100 or more real time units t R. This can be the case, for example, with a higher load on the operating system. In linear time mapping, a cycle time violation occurs. As a result, the alarm is triggered and detects a time shift in the next execution of the next program cycle. Asymptotic time mapping still does not cause a misleading cycle time violation. Using the smaller increase in linear imaging reduces the likelihood of cycle time violations in the emulation, but never completely eliminates this problem. The presented asymptotic approach solves this problem for all possible execution times.

Abstract

L'invention concerne un procédé d'émulation d'une commande à programme enregistré, comprenant les étapes suivantes : la mise à disposition d'un dispositif de calcul muni d'un système d'exploitation qui est insuffisant pour une spécification en temps réel établie au niveau de la commande à programme enregistré ; la représentation d'une durée réelle (tR) sur une durée virtuelle (tv) au moyen d'une fonction prédéterminée ; la prédétermination d'une valeur limite (T) pour la durée virtuelle (tv) nécessaire pour l'émulation au moins d'un cycle de programme d'un programme (12) de la commande à programme enregistré ; l'émulation du ou des cycles de programme par le dispositif de calcul ; et la vérification de la présence d'un dépassement du temps de cycle du cycle de programme émulé, en fonction de la valeur limite (T), la durée réelle (tR) étant représentée sur la durée virtuelle (tv) au moyen d'une fonction asymptotique.
PCT/EP2014/053120 2014-02-18 2014-02-18 Procédé et dispositif d'émulation d'une commande à programme enregistré WO2015124170A1 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105279335A (zh) * 2015-10-30 2016-01-27 南京河海南自水电自动化有限公司 一种基于操作系统时间缩放的变速仿真器的仿真方法
EP3196717A1 (fr) * 2016-01-20 2017-07-26 Rockwell Automation Technologies, Inc. Mise à l'échelle de taux d'exécution de commande industriel émulé
WO2018024390A1 (fr) * 2016-08-01 2018-02-08 Siemens Aktiengesellschaft Détermination d'un temps d'exécution d'un programme d'application
EP3349082A1 (fr) * 2017-01-16 2018-07-18 Siemens Aktiengesellschaft Système et simulateur destinés à la simulation interruptible d'installations ou de machines dans des commandes par programme enregistré
EP3521949A1 (fr) * 2018-02-01 2019-08-07 Siemens Aktiengesellschaft Dispositif de simulation d'une machine ou d'une installation commandées ainsi que procédé

Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2001209411A (ja) * 2000-01-25 2001-08-03 Omron Corp Ｐｌｃシミュレータ

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001209411A (ja) * 2000-01-25 2001-08-03 Omron Corp Ｐｌｃシミュレータ

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105279335A (zh) * 2015-10-30 2016-01-27 南京河海南自水电自动化有限公司 一种基于操作系统时间缩放的变速仿真器的仿真方法
EP3196717A1 (fr) * 2016-01-20 2017-07-26 Rockwell Automation Technologies, Inc. Mise à l'échelle de taux d'exécution de commande industriel émulé
US10012979B2 (en) 2016-01-20 2018-07-03 Rockwell Automation Technologies, Inc. Emulated industrial control execution rate scaling
CN109478052A (zh) * 2016-08-01 2019-03-15 西门子股份公司 确定应用程序的执行时间
WO2018024390A1 (fr) * 2016-08-01 2018-02-08 Siemens Aktiengesellschaft Détermination d'un temps d'exécution d'un programme d'application
CN109478052B (zh) * 2016-08-01 2022-07-12 西门子股份公司 确定应用程序的执行时间的方法和装置
US10901794B2 (en) 2016-08-01 2021-01-26 Siemens Aktiengesellschaft Determining an execution time of an application program
CN108319533A (zh) * 2017-01-16 2018-07-24 西门子股份公司 可关断地模拟控制装置内部的设备的系统和模拟器
US20180203973A1 (en) * 2017-01-16 2018-07-19 Siemens Aktiengesellschaft System and simulator for the disengageable simulation of installations or machines within programmable logic controllers
CN108319533B (zh) * 2017-01-16 2021-07-06 西门子股份公司 可关断地模拟控制装置内部的设备的系统和模拟器
EP3349082A1 (fr) * 2017-01-16 2018-07-18 Siemens Aktiengesellschaft Système et simulateur destinés à la simulation interruptible d'installations ou de machines dans des commandes par programme enregistré
EP3521949A1 (fr) * 2018-02-01 2019-08-07 Siemens Aktiengesellschaft Dispositif de simulation d'une machine ou d'une installation commandées ainsi que procédé
CN110109372A (zh) * 2018-02-01 2019-08-09 西门子股份公司 用于模拟受控制的机器或设施的设备以及方法

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