WO2015124170A1

WO2015124170A1 - Method and apparatus for emulating a programmable logic controller

Info

Publication number: WO2015124170A1
Application number: PCT/EP2014/053120
Authority: WO
Inventors: Gustavo Quiros Araya; Rene Ermler
Original assignee: Siemens Aktiengesellschaft
Priority date: 2014-02-18
Filing date: 2014-02-18
Publication date: 2015-08-27

Abstract

The invention relates to a method for emulating a programmable logic controller by providing a computation device having an operating system that is inadequate in terms of a real-time demand made of the programmable logic controller, mapping a real period (tR) onto a virtual period (tv) using a predetermined function, predetermining a limit value (T) for the virtual period (tv) that is needed for emulating at least one program cycle of a program (12) of the programmable logic controller; emulating the at least one program cycle with the computation device, and checking the presence of a cycle time overshoot in the emulated program cycle on the basis of the limit value (T), wherein the real period (tR) is mapped onto the virtual period (tv) using an asymptotic function.

Description

description

Method and device for emulating a

Programmable logic controller

The present invention relates to a method for emulating a programmable logic controller according to the preamble of claim 1. Moreover, the present invention relates to a device for emulating a programmable logic controller according to the preamble of claim 9.

When emulating a programmable logic controller (PLC) on a non-real-time platform (for example, Microsoft Windows operating system), the duration of execution of a program cycle is unpredictable and unpredictable, because this can in principle be delayed arbitrarily due to the execution of concurrent processes. If the virtual duration of the emulation is represented as a linear map of the real time required to emulate the program cycle, then the emulation is prone to misleading cycle timeouts.

This causes two problems. On the one hand, cycle time violations in PLC emulation can be reported (for example, by alarms), which have external platform-related causes and are meaningless for the emulation. On the other hand, time delays for the cyclic execution must be inserted in cycle time overruns in order to avoid overlapping of the successive time phases.

Usually, a linear mapping of the real time axis to a virtual time axis is used in the emulation of SPS. Here a suitable increase for the linear mapping is selected. This can be determined, for example, by estimating the execution time of the program cycle during the PLC simulation. This approach avoids misleading cycle time overruns only on average chen versions in which the underlying operating system is used to a limited extent. Otherwise, the approach is vulnerable to the above problem. Although the alarms for cycle time violations could be suppressed, time shifts are unavoidable.

It is an object of the present invention to provide a way to more reliably emulate a programmable logic controller.

This object is achieved by a method having the features of patent claim 1 and a device having the features of patent claim 9. Advantageous developments of the present invention are the subject of the dependent claims.

The method according to the invention for emulating a programmable logic controller comprises the provision of a computing device with an operating system which makes reference to a memory-programmable controller

Real-time requirement, mapping a real time period to a virtual time period based on a predetermined function, predetermining a threshold for the virtual time required to emulate the at least one program cycle of a program of the programmable controller, emulating the at least one program cycle with the computing device and checking for a presence of a cycle timeout of the emulated program cycle in response to the threshold, mapping the real time period to the virtual time based on an asymptotic function.

To emulate the programmable logic controller (PLC), a non-real-time computing device or a non real-time capable platform is used. For example, a computer with a Microsoft Windows operating system can be used. The program of the programmable logic controller can be divided into several program cycles, for example, each having the same time duration. In this case, first a first program cycle is simulated with the computing device. Following this, the remaining program cycles can be emulated. This determines the virtual time required to emulate the program cycle. This virtual time period is compared to a threshold. If this limit is exceeded, for example, a cycle time violation can be concluded.

The real time of the PLC is first mapped to the virtual time period based on a predetermined mapping rule. In the present case, the real time duration is mapped onto the virtual time duration on the basis of an asymptotic function. Compared to a commonly used linear mapping of the real time period to the virtual time period, the virtual time period initially increases faster compared to the real time period and slows down towards the end of the program cycle. Thus, reaching the predetermined limit value can be avoided. Thus, misleading cycle time violations caused, for example, by concurrent processes of the non-real-time computing device can be avoided. In one embodiment, the asymptotic function mapping the real time period to the virtual time period approaches the predetermined threshold. The limit value can be determined, for example, in advance of the emulation based on a maximum cycle duration of the program cycle. For example, the limit value can be determined during the engineering of the programmable logic controller. Thus, it can be reliably determined whether cycle time overruns occur in the emulation, whereby concurrent processes of the arithmetic unit are neglected due to the asymptotic mapping.

The asymptotic function with which the real time duration is mapped onto the virtual time duration is preferred. directly proportional to the real time duration. Thus, asymptotic behavior can be easily used to model the progression of virtual time. In a further embodiment, the asymptotic function with which the real time duration is mapped to the virtual time duration corresponds to a step response of a transmission element which has a proportional transmission behavior in a first-order delay. In other words, the progress of the virtual time can be modeled on the basis of a step response of a PTI element. In this way, a corresponding asymptotic course of the virtual time duration can be modeled. The computing device preferably comprises a virtual timer with which a virtual time is set when the emulation of the program cycle starts. The emulator can have an internal clock with which the virtual time of the emulator or the computing device can be manipulated. The current time of the virtual time can be set explicitly. Thus, the virtual clock of the computing device can be arbitrarily set in the simulation environment. In one embodiment, the virtual time is determined by the virtual timer from a system time of the operating system of the computing device. With the PLC emulation the system time of the operating system can be used, which corresponds to the real time of the simulation environment. Thus, the virtual time can be calculated from the system time of the operating system.

In one embodiment, the virtual time from the system time of the operating system is mapped using an asymptotic function. Thus, the time advance of the virtual time can be calculated similarly to the above-mentioned asymptotic function. In this way, faulty cycle time violations can be avoided. Preferably, parallel to the at least one program cycle, a second program cycle of a second program is emulated with a second computing device. Thus, various programmable logic controllers can be emulated simultaneously. In this way, a real system of a programmable logic controller can be modeled more accurately.

The device according to the invention for emulating a memory-programmable controller comprises a computing device with an operating system which is insufficient with respect to a real-time request made to the programmable controller, wherein the computing device is designed to emulate at least one program cycle of a program of the programmable logic controller with the computing device and wherein the device is configured to map a real time period to a virtual time period based on a predetermined function, to predetermine a limit value for the virtual time period required to emulate the at least one program cycle, and to provide a cycle timeout of the emulated program cycle depending on the limit value The device is designed to map the real time duration to the virtual time duration on the basis of an asymptotic function.

The advantages and further developments described above in connection with the method according to the invention apply mutatis mutandis to the device according to the invention.

The present invention will now be explained in more detail with reference to the accompanying drawings. Showing:

1 shows a diagram in which the time course for a real

System is shown with multiple processes;

2 shows a diagram in which the time course in the

Emulation of the programs is shown; 3 shows a diagram in which the temporal behavior of an emulated programmable logic controller is shown;

4 shows a diagram in which the image of a real

Time duration is represented on a virtual time period based on asymptotic functions; and

5 shows a diagram which shows the difference between a linear mapping and an asymptotic mapping of the real time duration to the virtual time duration. The following detailed embodiments illustrate preferred embodiments of the present invention.

1 shows a diagram 10 in which the time profile for a real system with two programmable logic controllers and two processes is shown. The course of the real time duration t _{R is} shown on a time axis. In this case, the time course of a program 12 of a first programmable logic controller is shown. Furthermore, the time course of a program 14 of a second programmable logic controller is shown. In addition, the time course of a third and a fourth program 16, 18 is shown, which are simulated, for example. The programs 12, 14, 16, 18 are each divided into predetermined program cycles, which in particular have the same time phases A, B. In the real system according to FIG. 1, all four arithmetic units execute the programs 12, 14, 16, 18 simultaneously. FIG. 2 shows a possible chronological progression of the programs 12, 14, 16, 18 according to FIG. 1 for a corresponding emulation. During emulation or simulation, the time phases A, B for the respective units are successively discharged one after the other. so that in the real time axis t _R each time phase A, B occurs several times. However, the virtual time t _v corresponds to the real time axis of the simulated system and, in the case of simulation or emulation, forms a discontinuous sequence of timeline segments over the real time axis of the simulation system. In addition, the overlapping of the segments on the real time axis t _{R is possible} because of a parallel execution of the units. This is shown in FIG.

3 shows the temporal behavior of an emulated programmable logic controller for the first program 12 in a diagram 24. In the present case, a basic cycle time of 100 ms is specified for the user program. The program 12 is thus divided into program cycles with the determined basic cycle time. The emulated PLC executes each program cycle individually, analogous to the phased implementation of FIG 1. Since the real time t _R and the virtual time t _{v are} decoupled, each program cycle can begin before or after the corresponding real time of the cycle timing. However, at each beginning of the cycle, a virtual clock in the computing device can be reset so that the execution always starts with a correct virtual time. The actual duration of the execution of the program - measured on the real time axis t _R - depends on the underlying operating system and can in principle deviate arbitrarily from the targeted cycle time of 100 ms. However, exceeding the maximum cycle time does not mean that a cycle time violation has or would have occurred in the user program. In general, such an infringement when emulated on a non-real-time system (for example, Microsoft Windows) is not clearly identifiable and should therefore be excluded. On the other hand, these border crossings would have to be avoided because otherwise two consecutive virtual time phases could overlap. This raises the question of how the virtual time t _v during the execution of the program cycle should progress. Here, different approaches can be followed.

On the one hand, no advance of the virtual time can be provided. The virtual clock stops during the cycle and thus does not exceed the planned cycle time. This approach would be easy to implement, but leads to the problem that all events that occur during the cycle show the same timestamp. For example, the causality of alarms on the basis of a time sequence in an operating system would not be recognizable. Therefore, an advance of the virtual time t _v during execution of a program cycle is desired. Another approach would be the linear progression of the virtual time t _v . The virtual time increases linearly with the real time t _R. This can be made possible for example by the use of a counter or a linear mapping function of the real time t _R. Although the time progress is given, an overlap of the planned cycle time is also possible.

In the present case, an asymptotic advance of the virtual time t _{v is} considered. The virtual time rises asymptotically with the real time t _R to a limit value T. The limit value T is the time limit for the maximum cycle duration. This means that the virtual time t _v runs faster at the beginning of the cycle and slows to the end of the cycle to avoid reaching the time limit. According to this approach, the time progress within the cycle is guaranteed and at the same time an exceeding of the planned cycle time is excluded. Theoretically, these two properties are always met, even with arbitrarily long execution times. In practice, however, one encounters the limitation of the finite resolution of the time values. For this reason, an asymptotic function should be selected in each case, which is suitable for the usual maximum execution times. A requirement for the However, using this approach means that a linear evolution of time within one cycle is not mandatory. The modeling of the progress of the virtual time t _v can be done, for example, by means of a function which is indirectly proportional to the real time t _R. For example, a function f (t) can be used according to the following formula:

In this case, the parameters T and D are used, where T is the limit value for the asymptotic function and D is a factor with which an approaching speed to the limit value T can be set. Alternatively, a function corresponding to a step response of a PT1 element may be used for the modeling of the progress of the virtual time t _v . Such a function g (t) can be calculated, for example, according to the following formula: g (t) = T. (\ - e ^) (2)

4 graphically illustrates the asymptotic progress of the virtual time t _v (vertical axis) with the real time t _R (horizontal axis). The threshold value T in the present embodiment corresponds to ten time units. In FIG 4 four functions are exemplified. The graph 26 of the figure according to equation (1), with D = 10. The graph 28 corresponds to the figure according to equation (1) with D = 50. The graph 30 corresponds to the figure according to equation (2) with D = 10. The graph 32 corresponds to the mapping according to equation (2) with D = 50. A general observation is that the maps according to equation (2) reach the limit faster than the maps according to equation (1). With a suitable selection of the value D, however, both functions should be useful for modeling and implementing virtual time progress.

In order to enable the behavior shown in FIG. 1, each simulation device or simulator of the simulation environment must have an internal clock which stores the virtual time t _v for this unit (in addition to the real time of the simulation environment). This clock must enable the explicit manipulation of the virtual time t _{v of} the emulator by setting the current time.

The current time of the virtual clock can in particular be set explicitly. This allows the clock to "spin" both forward and backward and is effectively used to "jump into time". Based on this operation, the virtual clocks of the emulators in the simulation environment can be set arbitrarily. At the start of the cycle, the virtual clock with the appropriate value for the beginning of the cycle can be set for each emulator. In any case, the control of the simulation environment ensures that the individual internal virtual clocks of the respective emulation units remain synchronized during the simulation.

The system time of a real PLC is usually continued via timer interrupts and updated to new values. In the case of PLC emulation, the system can instead be used by the operating system, which corresponds to the real time t _{R of} the simulation environment and which has not been modified by the emulator. A useful approach for the virtual clock of the PLC simulation is therefore to calculate the virtual time from the system time of the operating system. For this calculation the functions mentioned for the time progress can be used. An implementation for the respective function would be, for example, the following: t _v = t _{v start} + T. (l - L) (3)

^ ^l R ^l R

D Alternatively, the following formula can be used: ^ R ^ R Start) _{x / Λ \} ^t v = t _{r start} + T * (le -) (4) Here t _v corresponds to the current virtual time, t _v _start to the virtual start time the current execution, T of the planned cycle duration, t _{R of} the current system time, t _R _ _{st type of} the real start time of the current execution and D the approximation speed factor.

The proposed solution for the mapping of the real time t _R to the virtual time t _v in a PLC simulation is based on an asymptotic function, while the mapping function used hitherto is usually linear in simulation programs. Unlike linear

Pictures are completely avoided with an asymptotic time mapping misleading cycle time violations.

4 shows a diagram 34 in which the behavior of a linear time map (curve 36) and an asymptotic time map (curve 38) are shown. Analogous to the illustration according to FIG. 4, a limit value T of 10 ten units is considered. The increase in linear mapping corresponds to a factor of 0.1. The approaching speed factor D in the asymptotic mapping corresponds to the value 5.

The linear time map (curve 36) reaches the limit value 10 of the virtual time t _v at a real time t _R of 100. This results in two possible situations in the execution of a program cycle. First, the execution is completed under 100 real time units t _R. Regardless of the approach used, no misleading cycle time violation is caused. Alternatively, the embodiment requires 100 or more real time units t _R. This can be the case, for example, with a higher load on the operating system. In linear time mapping, a cycle time violation occurs. As a result, the alarm is triggered and detects a time shift in the next execution of the next program cycle. Asymptotic time mapping still does not cause a misleading cycle time violation. Using the smaller increase in linear imaging reduces the likelihood of cycle time violations in the emulation, but never completely eliminates this problem. The presented asymptotic approach solves this problem for all possible execution times.

LIST OF REFERENCE NUMBERS

10 diagram

12 program

14 program

16 program

18 program

20 diagram

22 diagram

24 diagram

26 curve

28 curve

30 curve

32 curve

34 diagram

36 curve

38 curve

t _R real time duration t _v virtual time duration

T limit

Claims

claims

A method of emulating a programmable logic controller

Providing a computing device with an operating system which is insufficient with respect to a real-time request made to the programmable logic controller,

Mapping a real time duration (t _R ) to a virtual time duration (t _v ) based on a predetermined function,

Predetermining a limit value (T) for the virtual time duration (t _v ) required for emulating at least one program cycle of a program (12) of the programmable logic controller;

Emulating the at least one program cycle with the computing device,

and

Checking a presence of a cycle timeout of the emulated program cycle as a function of the limit value (T),

marked by

Mapping the real time duration (t _R ) to the virtual time duration (t _v ) using an asymptotic function.

2. The method according to claim 1, characterized in that the asymptotic function, with which the real time duration (t _R ) is mapped to the virtual time period (t _v ), approaches the predetermined limit value (T).

3. The method according to any one of the preceding claims, characterized in that the asymptotic function, with which the real time duration (t _R ) is mapped to the virtual time period (t _v ), is indirectly proportional to the real time duration (t _R ).

4. The method according to any one of claims 1 to 3, characterized in that the asymptotic function, with which the real time duration (t _R ) is mapped to the virtual time period (t _v ), a step response of a transmission element, which has a proportional transmission behavior with a first-order delay corresponds.

5. The method according to any one of the preceding claims, characterized in that the computing device is a virtual

Timer that sets a virtual time when the program cycle emulation starts.

6. The method according to claim 5, characterized in that the virtual time of the virtual timer from a

System time of the operating system of the computing device is determined.

7. A method according to claim 6, characterized in that the virtual time from the system time of the operating system is mapped using an asymptotic function.

8. The method according to any one of the preceding claims, characterized in that parallel to the at least one program cycle, a second program cycle of a second program (14) is emulated with a second computing device.

9. Device for emulating a programmable logic controller with

a computing device having an operating system which is insufficient with respect to a real-time request made to the programmable logic controller, wherein

- The computing device is adapted to emulate at least one program cycle of a program (12) of the programmable logic controller with the computing device and wherein

the device is designed to map a real time duration (t _R ) to a virtual time duration (t _v ) on the basis of a predetermined function, a limit value (T) for the virtual time duration (t _v ) required for emulating the at least one program cycle to predict and a presence cycle time over the emulated program cycle as a function of the limit value (T),

characterized in that

- The device is adapted to the real time duration (t _R ) to the virtual time period (t _v ) using an asymptotic function.