WO2015114728A1 - Module de puissance, dispositif de conversion de puissance et véhicule ferroviaire - Google Patents

Module de puissance, dispositif de conversion de puissance et véhicule ferroviaire Download PDF

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Publication number
WO2015114728A1
WO2015114728A1 PCT/JP2014/051731 JP2014051731W WO2015114728A1 WO 2015114728 A1 WO2015114728 A1 WO 2015114728A1 JP 2014051731 W JP2014051731 W JP 2014051731W WO 2015114728 A1 WO2015114728 A1 WO 2015114728A1
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Prior art keywords
normally
substrate
drain
power module
semiconductor chip
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PCT/JP2014/051731
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English (en)
Japanese (ja)
Inventor
秋山　悟
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株式会社日立製作所
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Priority to PCT/JP2014/051731 priority Critical patent/WO2015114728A1/fr
Publication of WO2015114728A1 publication Critical patent/WO2015114728A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a power module, a power conversion device, and a railway vehicle.
  • Patent Document 1 Japanese Unexamined Patent Application Publication No. 2011-166673
  • Patent Document 2 Japanese Unexamined Patent Application Publication No. 2012-199549
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2011-166673 is formed by cascode-connecting a normally-on type SiC-JFET (JunctionuncField Effect Transistor) and a normally-off type Si-MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A hybrid power device is described.
  • the SiC-JFET gate and the Si-MOSFET source are connected via a resistor, and a technique is disclosed in which a capacitor is connected in parallel to this resistor to reduce switching loss and prevent oscillation. Yes.
  • Patent Document 2 JP 2012-199549 A (Patent Document 2) describes a composite semiconductor device including a group III nitride power transistor and a low voltage transistor.
  • a damping resistor capable of providing passive oscillation control to the composite semiconductor device is connected between the gate of the group III nitride power transistor and the source of the low voltage transistor.
  • This cascode connection type switch element operates as a normally-off type element as a whole, and further has a feature of low on-resistance and high withstand voltage.
  • the source of the high breakdown voltage normally-on element and the drain of the low breakdown voltage normally-off element are electrically connected via a conductive wire. For this reason, during the switching operation, a surge voltage due to the parasitic inductance of the wire is generated, and the low-voltage normally-off type element may be destroyed.
  • the switching speed is set between the gate of the high breakdown voltage normally-on element and the source of the low breakdown voltage normally-off element. It is desirable to connect a resistor that can be controlled. By providing the resistor, it is possible to slow down the switching speed and prevent generation of a high voltage excessively applied to the low-voltage normally-off type element, EMI (Electro Magnetic Interference), and the like.
  • EMI Electro Magnetic Interference
  • the resistor is arranged so that a source of a high breakdown voltage normally-on element and a low breakdown voltage normally-off element are arranged.
  • the distance to the drain becomes long.
  • the source of the high breakdown voltage normally-on element and the drain of the low breakdown voltage normally-off element are electrically connected.
  • the wire becomes longer and the parasitic inductance of the wire increases. For this reason, even if it arrange
  • the arrangement of the high breakdown voltage normally-on element, the low breakdown voltage normally-off element, and the resistor is optimized, and the source of the high breakdown voltage normally-on element and the low breakdown voltage normally-off element are arranged.
  • the parasitic inductance of the wire that electrically connects the drain is reduced. Thereby, the reliability of the power module comprised using the switch element of a cascode connection system is improved.
  • a drain substrate on which a normally-off chip is mounted A drain substrate, a source substrate, and a gate substrate on which the mullion type chip is mounted are sequentially arranged in the first direction, and a gate resistor is arranged between the source substrate and the gate substrate. This shortens the lengths of the plurality of wires connecting the plurality of source electrodes formed on the upper surface of the normally-on chip and the drain substrate on which the normally-off chip is mounted.
  • the reliability of a power module configured using a cascode connection type switching element can be improved.
  • FIG. 6 is a layout diagram illustrating another example of a unit power module (equivalent to 1 ⁇ 4 of a 3.3 kV, 1200 A power module) configured using a cascode connection type switch element in the first embodiment.
  • FIG. 3 is a circuit diagram illustrating an example of a cascode connection type switch element according to the first embodiment.
  • (A) is a circuit diagram of the 1st switch element which consists of normally-on type JFET using silicon carbide (SiC) material, and normally-off type MOSFET.
  • SiC silicon carbide
  • FIG. 5B is a circuit diagram of a second switch element including a normally-on type MOSFET using a silicon carbide (SiC) material and a normally-off type MOSFET.
  • C is a circuit diagram of a third switch element including a normally-on type FET using a gallium nitride (GaN) material and a normally-off type MOSFET.
  • FIG. 3 is a layout diagram illustrating an example of a power module (equivalent to 3.3 kV, 1200 A) configured using a cascode connection type switch element according to the first embodiment. It is a circuit diagram which shows an example of the power converter device (three-phase inverter) in Example 2.
  • FIG. It is a block diagram which shows an example of the three-phase motor system applied to the railway vehicle in Example 3.
  • the constituent elements are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
  • FIG. 1 is a layout diagram showing an example of a unit power module (equivalent to 1 ⁇ 4 of a 3.3 kV, 1200 A power module) configured using the cascode connection type switch element according to the first embodiment.
  • the unit power module includes four high breakdown voltage normally-on elements J1, J2, J3, and J4 connected in parallel, and two low breakdown voltage normally-off elements M1 and M2 connected in parallel.
  • the normally-on type elements J1, J2, J3, and J4 have a withstand voltage of, for example, 3.3 kV and a current capacity of, for example, 75A
  • the normally-off type elements M1 and M2 have a withstand voltage of, for example, 30V and a current capacity of, for example, 150A.
  • the unit power module has a withstand voltage of, for example, 3.3 kV and a current capacity of, for example, 300A.
  • a junction field effect transistor (denoted as JFET) is exemplified as normally-on type elements J1, J2, J3, and J4, and an insulated gate field effect transistor (denoted as MOSFET) is exemplified as normally-off type elements M1 and M2.
  • JFET junction field effect transistor
  • MOSFET insulated gate field effect transistor
  • M1 and M2 normally-off type elements
  • SiC silicon carbide
  • GaN gallium nitride
  • Si silicon carbide
  • GaN gallium nitride
  • each of the normally-on elements J1, J2, J3, and J4 is formed on one semiconductor chip.
  • a semiconductor chip on which each of the normally-on elements J1, J2, J3, and J4 is formed is referred to as a normally-on chip.
  • each of the normally-off type elements M1 and M2 is formed on one semiconductor chip.
  • the semiconductor chip on which each of the normally-off type elements M1 and M2 is formed is referred to as a normally-off type chip. Therefore, the unit power module has four normally-on chips and two normally-off chips.
  • the planar shape of the normally-on type chip and the normally-off type chip in a top view is a quadrangular shape.
  • the normally-on elements J1, J2, J3, and J4 are so-called vertical elements.
  • a gate electrode GJP and a plurality of source electrodes SJP that are electrically insulated from each other are formed on the upper surface (front surface) of the normally-on chip, and a drain electrode (on the back surface opposite to the upper surface of the normally-on chip) (Not shown) is formed.
  • FIG. 1 illustrates four source electrodes SJP arranged on the upper surface of one normally-on chip and spaced apart from each other in the x direction (second direction).
  • the normally-on elements J1, J2, J3, and J4 are not limited to vertical elements, but may be so-called horizontal elements in which a drain electrode is formed on the top surface of a normally-on chip.
  • the normally-off type elements M1 and M2 are so-called vertical elements.
  • a gate electrode GMP and a plurality of source electrodes SMP that are electrically insulated from each other are formed on the upper surface (front surface) of the normally-off chip, and a drain electrode (illustration is shown) on the lower surface (back surface) opposite to the upper surface of the normally-off chip. (Omitted) is formed.
  • FIG. 1 exemplifies four source electrodes SMP arranged on the upper surface of one normally-on chip and spaced apart from each other in the y direction (first direction) orthogonal to the x direction.
  • the normally-off elements M1 and M2 are not limited to vertical elements, but may be so-called lateral elements in which a drain electrode is formed on the top surface of a normally-off chip.
  • the gate electrodes GJP of the normally-on elements J1, J2, J3, and J4 are electrically connected to the source electrodes SMP of the normally-off elements M1 and M2, and the source electrode SJP is connected to the normally-on element M1.
  • M2 are electrically connected to the drain electrode, and the drain electrode is electrically connected to a drain terminal that is electrically connected to the outside.
  • the gate electrodes MJP of the normally-on elements M1 and M2 are electrically connected to a gate terminal that is electrically connected to the outside, and the source electrode SMP is electrically connected to a source terminal that is electrically connected to the outside.
  • the drain electrode is electrically connected to the source electrode SMP of the normally-on type element J1, J2, J3, J4.
  • a gate resistance (resistor) Rgi for adjusting the switching speed is provided between the gate electrode GJP of the normally-on type elements J1, J2, J3, and J4 and the source electrode SMP of the normally-off type elements M1 and M2. ing.
  • the unit power module has a base substrate BS.
  • a first drain substrate DJ1 for normally-on elements J1 and J2 made of a metal material On this base substrate BS, a first drain substrate DJ1 for normally-on elements J1 and J2 made of a metal material, a second drain substrate DJ2 for normally-on elements J3 and J4, and a first drain for normally-off elements M1
  • the substrate DM1, the second drain substrate DM2 for the normally-off type element M2, the source substrate S, and the gate substrate G are disposed so as to be electrically insulated from each other.
  • a landing pad (pad electrode) LPAD for the gate resistance Rgi made of a metal material is disposed on the base substrate BS so as to be electrically insulated from each substrate.
  • drain substrates for normally-on elements first drain substrate DJ1 and second drain substrate DJ2
  • drain substrates for normally-off elements first drain substrate DM1 and second drain substrate DM2
  • source substrate S source substrate S
  • the arrangement of the gate substrate G and the landing pad LPAD will be specifically described.
  • Drain substrate for normally-on elements In the unit power module, as drain substrates for normally-on elements, a first drain substrate DJ1 for normally-on elements J1 and J2 and a second drain for normally-on elements J3 and J4 A substrate DJ2 is formed on the base substrate BS.
  • first drain substrate DJ1 On the first drain substrate DJ1, a normally-on chip on which a normally-on element J1 is formed and a normally-on chip on which a normally-on element J2 is formed are mounted. On the second drain substrate DJ2, a normally-on chip is mounted. A normally-on chip on which the normally-on element J3 is formed and a normally-on chip on which the normally-on element J4 is formed are mounted.
  • the first drain substrate DJ1 and the second drain substrate DJ2 are arranged apart from each other in the x direction.
  • the first drain substrate DJ1 includes a first part on which a normally-on chip on which the normally-on element J1 is formed and a normally-on chip on which the normally-on element J2 is formed, and the first part. And a second portion to which a drain terminal junction (not shown) is connected to be electrically connected to the outside.
  • the second drain substrate DJ2 includes a normally-on chip on which the normally-on element J3 is formed, a first part on which the normally-on chip on which the normally-on element J4 is formed, and the first part. And a second portion to which a drain terminal junction (not shown) that is electrically connected to the outside is connected.
  • drain substrate for normally-off type element In the unit power module, a first drain substrate DM1 for normally-off type element M1 and a second drain substrate DM2 for normally-off type element M2 are provided on base substrate BS as drain substrates for normally-off type element. Is formed.
  • first drain substrate DM1 On the first drain substrate DM1, a normally-off type chip on which a normally-off type element M1 is formed is mounted, and on the second drain substrate DM2, a normally-off type chip on which a normally-off type element M2 is formed is mounted.
  • the first drain substrate DM1 and the second drain substrate DM2 are disposed apart from each other in the x direction. Further, the first drain substrate DM1 is provided at a position adjacent to the first portion of the first drain substrate DJ1 in the y direction, and the second drain substrate DM2 is disposed in the y direction with respect to the first portion of the second drain substrate DJ2. It is provided in the position adjacent to.
  • the planar shape of the first drain substrate DM1 and the second drain substrate DM2 in a top view is a quadrangular shape (including a curved corner (R shape)), and the length of the side along the x direction is the y direction. Longer than the length of the side along. That is, the side along the x direction is a long side, and the side along the y direction is a short side.
  • the source substrate S has a first portion extending in the x direction and a second portion connected to the first portion and extending in the y direction.
  • the first portion of the source substrate S is a base substrate BS opposite to the first drain substrate DM1 and the second drain substrate DM2 across the first portion of the first drain substrate DJ1 and the first portion of the second drain substrate DJ2. Formed on top.
  • the second portion of the source substrate S extends between the first drain substrate DJ1 and the second drain substrate DJ2 and between the first drain substrate DM1 and the second drain substrate DM2, and is electrically connected to the outside. It is also a part to which a connecting portion (not shown) of the source terminal for making a proper connection is connected.
  • the gate substrate G is a base substrate BS opposite to the first portion of the first drain substrate DJ1 and the first portion of the second drain substrate DJ2, with the first portion extending in the x direction of the source substrate S interposed therebetween. Formed above and extends in the x direction.
  • the gate resistance landing pad LPAD includes a first portion extending in the x direction of the source substrate S, a first portion of the first drain substrate DJ1, and a first portion of the second drain substrate DJ2. It is arranged between.
  • eight gate resistor landing pads LPAD are provided.
  • the first drain substrate DM1 for the normally-off type element M1 the first portion of the first drain substrate DJ1 for the normally-on type elements J1 and J2, and the landing for the gate resistance Rgi.
  • the pad LPAD, the first portion of the source substrate S, and the gate substrate G are arranged in this order apart from each other.
  • the second drain substrate DM2 for the normally-off type element M2 the first portion of the second drain substrate DJ2 for the normally-on type elements J3 and J4, and the gate resistance Rgi
  • the landing pad LPAD, the first portion of the source substrate S, and the gate substrate G are arranged so as to be separated from each other in this order.
  • Drain electrode of normally-on type element The drain electrode of normally-on type element J1 is formed on the lower surface of the normally-on type chip on which normally-on type element J1 is formed.
  • the drain electrode and first drain substrate DJ1 For example, bonding is performed using a solder material made of tin (Sn) -silver (Ag) -copper (Cu).
  • solder material made of tin (Sn) -silver (Ag) -copper (Cu).
  • the drain electrode of the normally-on element J2 and the first drain substrate DJ1, the drain electrode of the normally-on element J3 and the second drain substrate DJ2, the drain electrode of the normally-on element J4 and the second drain substrate DJ2 are respectively Joined using solder material.
  • the drain electrode of the normally-off type element M1 is formed on the lower surface of the normally-off type chip on which the normally-off type element M1 is formed.
  • the drain electrode and the first drain substrate DM1 are made of, for example, tin (Sn ) -Silver (Ag) -copper (Cu).
  • the drain electrode of the normally-off type element M2 and the second drain substrate DM2 are joined using a solder material.
  • the source electrode SJP and gate electrode GJP of the normally-on type elements J1, J2, J3 and J4 and the source electrode of the normally-off type elements M1 and M2 are as follows.
  • the SMP, the gate electrode GMP, and each substrate are electrically connected using conductive wires.
  • Source electrode of normally-on type element In the normally-on type chip in which the normally-on type element J1 is formed, a plurality of source electrodes SJP of the normally-on type element J1 are formed on the upper surface thereof.
  • FIG. 1 illustrates four source electrodes SJP that are spaced apart from each other in the x direction.
  • the first drain substrate DM1 to be mounted is electrically connected by a plurality of wires Wj. That is, one end of each of the plurality of wires Wj is joined to the plurality of source electrodes SJP of the normally-on type element J1, and the other end of each of the plurality of wires Wj is a normally-off type chip in which the normally-off type element M1 is formed.
  • the first drain substrate DM1 between the periphery and the periphery of the first drain substrate DM1 is joined.
  • a metal material such as copper (Cu) or aluminum (Al) can be exemplified.
  • a method of bonding by ultrasonic vibration at room temperature is used for bonding the plurality of wires Wj. Thereby, the source electrode SJP of the normally-on type element J1 and the drain electrode of the normally-off type element M1 are electrically connected.
  • the plurality of source electrodes SJP of the normally-on type element J2 and the first drain substrate DM1 on which the normally-off type chip on which the normally-off type element M1 is formed are electrically connected by the plurality of wires Wj.
  • the source electrode SJP of the normally-on type element J2 and the drain electrode of the normally-off type element M1 are electrically connected.
  • the plurality of source electrodes SJP of the normally-on type element J3 and the second drain substrate DM2 on which the normally-off type chip on which the normally-off type element M2 is formed are electrically connected by the plurality of wires Wj.
  • the source electrode SJP of the normally-on type element J3 and the drain electrode of the normally-off type element M2 are electrically connected.
  • the plurality of source electrodes SJP of the normally-on type element J4 and the second drain substrate DM2 on which the normally-off type chip on which the normally-off type element M2 is formed are electrically connected by the plurality of wires Wj.
  • the source electrode SJP of the normally-on type element J4 and the drain electrode of the normally-off type element M2 are electrically connected.
  • the side along the x direction of the first drain substrate DM1 facing the normally-on chip on which the normally-on element J1 is formed and the normally-on chip on which the normally-on element J2 is formed is defined as a long side.
  • the normally-on type chip in which the normally-on type chip in which the normally-on type element J1 is formed and the normally-on type chip in which the normally-on type element J2 is formed have respective long sides along the x direction.
  • the normally-off chip is mounted on the first drain substrate DM1 so that the long side of the normally-off chip on which the normally-off element M1 is formed is along the x direction.
  • the side along the x direction of the second drain substrate DM2 facing the normally-on chip on which the normally-on element J3 is formed and the normally-on chip on which the normally-on element J4 is formed has a long side.
  • the normally-on type chip in which the normally-on type element J3 is formed and the normally-on type chip in which the normally-on type element J4 is formed have the long sides along the x direction. Mounted on the first portion of the drain substrate DJ2. Further, the normally-off chip is mounted on the second drain substrate DM2 so that the long side of the normally-off chip on which the normally-off element M2 is formed is along the x direction.
  • the long side of the normally-on chip on which the normally-on type elements J1 and J2 are respectively formed and the long side of the normally-off type chip on which the normally-off type element M1 is formed are opposed and parallel to each other.
  • a normally-on type chip and a normally-off type chip are arranged.
  • the long side of the normally-on chip on which the normally-on type elements J3 and J4 are respectively formed and the long side of the normally-off type chip on which the normally-off type element M2 is formed face each other and are parallel to each other.
  • a normally-on type chip and a normally-off type chip are arranged.
  • the first drain substrate is arranged.
  • the length in the x direction of the region where the plurality of wires Wj of the DM1 and the second drain substrate DM2 are joined increases. Thereby, the number of the plurality of wires Wj can be increased, or the thickness of the plurality of wires Wj can be increased, and the parasitic inductance caused by the plurality of wires Wj can be reduced.
  • gate electrode of normally-on type element In the normally-on type chip in which the normally-on type element J1 is formed, the gate electrode GJP of the normally-on type element J1 is formed on the upper surface thereof.
  • Gate electrode GJP and landing pad LPAD to which one connection terminal of gate resistance Rgi is connected are electrically connected by wire Wgj
  • landing pad LPAD to which the other connection terminal of gate resistance Rgi is connected to the source substrate S is electrically connected by a wire Wgi.
  • the gate electrode GJP of the normally-on type element J1 and the source terminal (source electrodes SMP of the normally-off type elements M1 and M2) that are electrically connected to the outside are electrically connected via the gate resistance Rgi.
  • the material of the wires Wgi and Wgj is the same metal material as that of the wire Wj described above. Further, both connection terminals of the gate resistor Rgj are electrically connected to the landing pad LPAD by a solder material or the like.
  • the gate electrode GJP of the normally-on element J2 and the source substrate S are electrically connected via the gate resistor Rgj.
  • the gate electrode GJP of the normally-on type element J2 and the source terminal (source electrodes SMP of the normally-off type elements M1 and M2) that are electrically connected to the outside are electrically connected via the gate resistance Rgi. .
  • the gate electrode GJP of the normally-on element J3 and the source substrate S are electrically connected via the gate resistor Rgj.
  • the gate electrode GJP of the normally-on type element J3 and the source terminal (source electrodes SMP of the normally-off type elements M1 and M2) that are electrically connected to the outside are electrically connected via the gate resistance Rgi. .
  • the gate electrode GJP of the normally-on element J4 and the source substrate S are electrically connected via the gate resistor Rgj.
  • the gate electrode GJP of the normally-on type element J4 and the source terminal (source electrodes SMP of the normally-off type elements M1 and M2) that are electrically connected to the outside are electrically connected via the gate resistance Rgi. .
  • the gate resistance Rgj is located on the opposite side of the normally-off chip on which the normally-off elements M1 and M2 are formed, with the normally-on chip on which the normally-on elements J1, J2, J3, and J4 are formed.
  • the normally-off chip, the normally-on chip, and the gate resistor Rgj can be sequentially arranged in the y direction. That is, the normally-on chip and the normally-off chip can be arranged close to each other.
  • the plurality of wires Wj that connect the source electrode SJP of the normally-on elements J1 and J2 and the first drain substrate DM1 and the source electrode SJP of the normally-on elements J3 and J4 and the second drain substrate DM2 are connected.
  • the length of the plurality of wires Wj can be minimized, and the parasitic inductance due to the plurality of wires Wj can be reduced.
  • Source electrode of normally-off type element In the normally-off type chip in which the normally-off type element M1 is formed, a plurality of source electrodes SMP of the normally-off type element M1 are formed on the upper surface thereof.
  • FIG. 1 illustrates four source electrodes SMP that are spaced apart from each other in the y direction.
  • the plurality of source electrodes SMP and the second portion of the source substrate S are electrically connected by a plurality of wires Ws.
  • the material of the plurality of wires Ws is the same metal material as that of the wire Wj described above.
  • the source electrode SMP of the normally-off type element M1 and the source terminal that is electrically connected to the outside are electrically connected.
  • the plurality of source electrodes SMP of the normally-off type element M2 and the second portion of the source substrate S are electrically connected by the plurality of wires Ws.
  • the source electrode SMP of the normally-off type element M2 and the source terminal that is electrically connected to the outside are electrically connected.
  • Gate electrode of normally-off type element In the normally-off type chip in which the normally-off type element M1 is formed, the gate electrode GMP of the normally-off type element M1 is formed on the upper surface thereof.
  • the gate electrode GMP and the gate substrate G are electrically connected by a wire Wgm.
  • the material of the wire Wgm is the same metal material as that of the wire Wj described above.
  • the gate electrode GMP of the normally-off type element M1 and the gate terminal that is electrically connected to the outside are electrically connected.
  • the gate electrode GMP of the normally-off type element M2 and the gate substrate G are electrically connected by the wire Wgm.
  • the gate electrode GMP of the normally-off type element M2 and the gate terminal that is electrically connected to the outside are electrically connected.
  • the normally-off type chip, the normally-on type chip, the gate resistor Rgi, the source substrate S, and the gate substrate G are sequentially arranged on the base substrate BS in the y direction. Then, the normally-on type chip and the normally-off type chip are arranged so that the long side of the normally-on type chip and the long side of the normally-off type chip face each other and are parallel along the x direction.
  • the distance between the source electrode SJP of the normally-on type elements J1 and J2 and the first drain substrate DM1 on which the normally-off type chip on which the normally-off type element M1 is formed can be shortened, so that both are electrically connected.
  • the length of the plurality of wires Wj can be minimized.
  • the two are electrically connected.
  • the length of the plurality of wires Wj can be minimized.
  • FIG. 2 is a layout diagram showing another example of a unit power module (equivalent to 1 ⁇ 4 of a 3.3 kV, 1200 A module) configured using the cascode connection type switching element in the first embodiment.
  • the difference between the unit power module shown in FIG. 2 and the unit power module shown in FIG. 1 is the number of normally-on elements. That is, the unit power module shown in FIG. 1 has four normally-on chips and two normally-off chips, but the unit power module shown in FIG. 2 has eight normally-on chips and two normally-off chips. Has a mold tip. That is, a unit power module having a breakdown voltage of 3.3 kV and a current capacity of 300 A, for example, is configured using eight normally-on elements. By using eight normally-on elements, a normally-on element having a small current capacity, for example, 37.5 A can be used.
  • two normally-on chips are arranged on one side in the y direction of the normally-off chip on which the normally-off type element M1 is formed and on one side in the ⁇ y direction opposite to the y direction. They are spaced apart. That is, a normally-on chip having a normally-on element J1 and a normally-on chip having a normally-on element J2 are disposed on one side in the y direction, and a normally-on element is disposed on one side in the ⁇ y direction.
  • a normally-on chip in which J5 is formed and a normally-on chip in which normally-on element J6 is formed are arranged.
  • two normally-on chips are arranged separately from the normally-off chip on one side in the y direction of the normally-off chip on which the normally-off element M2 is formed and on one side in the ⁇ y direction opposite to the y direction.
  • a normally-on chip having a normally-on element J3 and a normally-on chip having a normally-on element J4 are disposed on one side in the y direction, and a normally-on element is disposed on one side in the -y direction.
  • a normally-on chip in which J7 is formed and a normally-on chip in which normally-on element J8 is formed are arranged.
  • the normally-on element J1, the normally-on element J2, the normally-on element J3, and the normally-on element J4 are sequentially arranged in the x direction
  • J7 and normally-on element J8 are sequentially arranged in the x direction.
  • the four normally-on chips on which the normally-on elements J1, J2, J5, and J6 are respectively formed are mounted on one first drain substrate DJ1, and the normally-on element J1 and the normally-on element
  • the drain electrodes of J2, normally-on type element J5, and normally-on type element J6 are electrically connected.
  • four normally-on chips on which normally-on elements J3, J4, J7, and J8 are respectively formed are mounted on one second drain substrate DJ2, and are normally-on element J3 and normally-on type.
  • the drain electrodes of the element J4, normally-on type element J7, and normally-on type element J8 are electrically connected.
  • the gate resistance Rgj is provided on the opposite side of the first drain substrate DM1 across the first portion of the first drain substrate DJ1 (portion where the normally-on chip is mounted). Similarly, the gate resistor Rgj is provided on the opposite side of the second drain substrate DM2 across the first portion of the second drain substrate DJ2 (portion where the normally-on chip is mounted).
  • the unit power module shown in FIG. 2 can obtain the same effects as the unit power module shown in FIG. That is, the plurality of wires Wj that electrically connect the source electrodes SJP of the normally-on elements J1, J2, J5, and J6 and the first drain substrate DM1 on which the normally-off chip on which the normally-off element M1 is formed are mounted. The length can be minimized. Similarly, a plurality of wires Wj for electrically connecting the source electrodes SJP of the normally-on elements J3, J4, J7, and J8 and the second drain substrate DM2 on which the normally-off chip on which the normally-off element M2 is formed is mounted. Can be minimized. As a result, parasitic inductance due to the plurality of wires Wj can be reduced, so that the reliability of a power module configured using a cascode connection type switching element can be improved.
  • FIG. 3 is a circuit diagram illustrating an example of a cascode connection type switching element according to the first embodiment.
  • A is a circuit diagram of the 1st switch element which consists of normally-on type JFET using silicon carbide (SiC) material, and normally-off type MOSFET.
  • FIG. 5B is a circuit diagram of a second switch element including a normally-on type MOSFET using a silicon carbide (SiC) material and a normally-off type MOSFET.
  • C is a circuit diagram of a third switch element including a normally-on type FET using a gallium nitride (GaN) material and a normally-off type MOSFET.
  • SiC-JFET chip a semiconductor chip on which a normally-on JFET using a silicon carbide (SiC) material is formed.
  • SiC-MOSFET chip A semiconductor chip on which a normally-on type MOSFET using a silicon carbide (SiC) material is formed is referred to as a SiC-MOSFET chip.
  • GaN-FET chip A semiconductor chip on which a normally-off type MOSFET is formed is referred to as a MOSFET chip.
  • the first switch element shown in FIG. 3 (a) is a cascode connection type switch element configured using a normally-on type element using a JFET made of silicon carbide (SiC).
  • the drains of the SiC-JFET chips J1 to J (n) are electrically connected to the drain terminal DT, and the gates of the SiC-JFET chips J1 to J (n) are electrically connected to the source terminal ST via the gate resistance Rgi. Is done.
  • the sources of the SiC-JFET chips J1 to J (n) and the drains of the normally-off type MOSFET chips M1 to M (n) are connected via conductive wires (the wires Wj shown in FIGS. 1 and 2 described above). Are electrically connected.
  • the power module in the first embodiment can minimize the parasitic inductance Lj of this wire, the surge voltage generated by the switching operation is small. Thereby, a highly reliable power module is obtained.
  • the gates of normally-off type MOSFET chips M1 to M (n) are connected to the gate terminal GT via the gate resistance Rgm.
  • the second switch element shown in FIG. 3 (b) is a cascode connection type switch element configured using a normally-on type element made of MOSFET made of silicon carbide (SiC).
  • the drains of the SiC-MOSFET chips CM1 to CM (n) are electrically connected to the drain terminal DT, and the gates of the SiC-MOSFET chips CM1 to CM (n) are electrically connected to the source terminal ST via the gate resistance Rgi. Is done.
  • the sources of the SiC-MOSFET chips CM1 to CM (n) and the drains of the normally-off type MOSFET chips M1 to M (n) are connected via conductive wires (the wires Wj shown in FIGS. 1 and 2 described above). Are electrically connected.
  • the same effect as that of the first switch element described above can be obtained. Further, by adopting a trench type gate structure in the normally-on type SiC-MOSFET, there is an advantage that the on-resistance of the entire second switch element can be reduced as compared with the planar type gate structure.
  • the third switch element shown in FIG. 3 (c) is a cascode connection type switch element configured by using a normally-on element FET (eg, HEMT: High Electron Mobility Transistor) made of gallium nitride (GaN). It is.
  • the drains of the GaN-FET chips G1 to G (n) are electrically connected to the drain terminal DT, and the gates of the GaN-FET chips G1 to G (n) are electrically connected to the source terminal ST via the gate resistance Rgi. Is done.
  • the sources of the GaN-FET chips G1 to G (n) and the drains of the normally-off type MOSFET chips M1 to M (n) are connected via conductive wires (the wires Wj shown in FIGS. 1 and 2 described above). Are electrically connected.
  • the same effect as the first switch element described above can be obtained. Furthermore, since FETs made of gallium nitride (GaN) can be formed on a silicon (Si) substrate or a sapphire substrate, the manufacturing cost is lower than FETs using silicon carbide (SiC) as a material. It will be cheaper. Therefore, there is an advantage that the cost of the power module can be reduced.
  • GaN gallium nitride
  • FIG. 4 is a layout diagram illustrating an example of a power module (equivalent to 3.3 kV, 1200 A) configured using the cascode connection type switching element according to the first embodiment.
  • the unit power modules shown in FIG. 1 are arranged in 2 rows and 2 columns on the base substrate BS, and a total of four unit power modules are arranged.
  • the two unit power modules arranged in the x direction are arranged side by side in the same manner.
  • the two unit power modules arranged in the y direction are arranged side by side in an inverted manner in the y direction. That is, the normally-off type chip on which the normally-off type elements M1 and M2 are formed is arranged on the inside, the normally-off type chip on which the normally-on type elements J1, J2, J3, and J4 are formed is arranged on the outside.
  • a gate resistor Rgi is disposed outside the normally-off chip on which the elements J1, J2, J3, and J4 are formed.
  • Each substrate to which each semiconductor chip is connected via solder is disposed on the base substrate BS with a creeping distance secured so as to be electrically insulated from each other.
  • the above-mentioned substrates include a first drain substrate DM1 for normally-off type element M1, a second drain substrate DM2 for normally-off type element M2, a first drain substrate DJ1 for normally-on type elements J1 and J2, and a normally-on type element J3. , J4 second drain substrate DJ2, source substrate S, gate substrate G, and landing pad LPAD for gate resistance Rgi.
  • the gate substrate G of one unit power module and the gate substrate G of the other unit power module are electrically connected via a wire Wgg. It becomes a potential.
  • the source substrate S of one unit power module and the source substrate S of the other unit power module are electrically connected via a wire Wss. The same potential.
  • a gate junction terminal Gc for electrical connection to the outside of the power module is disposed.
  • the gate junction terminal Gc and the gate substrate G are connected to the wire Wgt. It is electrically connected via. Therefore, the gate drive signal from the outside of the power module is transmitted to the normally-off type elements M1, M2 inside the power module via the gate junction terminal Gc, the wire Wgt, the gate substrate G, the wire Wgm, and the gate electrode GMP.
  • a source sense terminal Sse is disposed between the gate substrate G and the periphery of the base substrate BS, and the source sense terminal Sse is electrically connected to the source substrate S via a wire Wse.
  • the source sense terminal Sse is provided to output a part of the source current as a sense current to the outside of the power module.
  • a drain sense terminal Dse is disposed between the gate substrate G and the periphery of the base substrate BS, and the drain sense terminal Dse is electrically connected to the drain substrate DJ1 via a wire Wde.
  • the drain sense terminal Dse is provided to output a part of the drain current as a sense current to the outside of the power module.
  • the four first drain substrates DJ1 and the four second drain substrates DJ2 for the normally-on type elements are electrically connected to each other by using bus bar wiring or the like (not shown) and have the same potential. It is electrically connected to a drain terminal that is electrically connected to the outside of the power module.
  • the four source substrates S are also electrically connected to each other and have the same potential, and are electrically connected to drain terminals that are electrically connected to the outside of the power module.
  • the screw hole SH is a screw hole for connecting the base substrate BS to a heat radiating fin or the like.
  • the power module is resin-sealed by, for example, a transfer mold method and provided as a power module product.
  • the power module configured by the cascode connection type switching element described in the first embodiment can be used for a power conversion device.
  • the power converter in Example 2 is demonstrated using FIG.
  • FIG. 5 is a circuit diagram illustrating an example of a power conversion device (three-phase inverter) in the second embodiment.
  • the three-phase inverter includes six cascode switch circuits SWU, SWV, SWW, SWX, SWY, SWZ, and drive circuits GDU corresponding to these cascode switch circuits SWU, SWV, SWW, SWX, SWY, SWZ, GDV, GDW, GDX, GDY, GDZ.
  • Cascode / switch circuits SWU, SWV, SWW, SWX, SWY, SWZ each correspond to the power module shown in FIG. 4 and all have the same configuration.
  • FIG. 5 shows one normally-on type element JU, JV, JW, JX, JY, JZ and one normally-off in each of the cascode switch circuits SWU, SWV, SWW, SWX, SWY, SWZ. Only the mold elements MU, MV, MW, MX, MY, MZ are described.
  • a plurality of normally-on elements are connected in parallel, and a plurality of normally-off elements are connected in parallel.
  • a cascode switch circuit SWU and a cascode switch circuit SWX that operate as one phase are connected in series between a power supply voltage VCC (for example, 1,500 V), and the cascodes connected in series are connected.
  • VCC power supply voltage
  • the switch circuit SWU and the cascode switch circuit SWX perform a switching operation complementarily with each other according to the input signal.
  • an output signal for driving the U phase of the three-phase motor LOAD as the load device is output from the connection point U between the cascode switch circuit SWU and the cascode switch circuit SWX.
  • a cascode switch circuit SWV and a cascode switch circuit SWY that operate as one phase are connected in series between the power supply voltage VCC to form an inverter circuit, and the cascode switch circuit connected in series.
  • the SWV and the cascode switch circuit SWY perform a switching operation in a complementary manner according to the input signal.
  • an output signal for driving the V phase of the three-phase motor LOAD as the load device is output from the connection point V between the cascode switch circuit SWV and the cascode switch circuit SWY.
  • a cascode switch circuit SWW and a cascode switch circuit SWZ that operate as one phase are connected in series between the power supply voltage VCC to form an inverter circuit, and the cascode switch circuit connected in series
  • the SWW and the cascode switch circuit SWZ perform a switching operation complementarily with each other in accordance with an input signal.
  • an output signal for driving the W phase of the three-phase motor LOAD as the load device is output from the connection point W between the cascode switch circuit SWW and the cascode switch circuit SWZ.
  • the three-phase inverter in the second embodiment can be used in a three-phase motor system that drives the three-phase motor LOAD.
  • the normally-on elements JU, JV, JW, JX, JY, JZ are, for example, JFETs using a silicon carbide (SiC) material.
  • the normally-off type elements MU, MV, MW, MX, MY, and MZ are MOSFETs using, for example, a silicon (Si) material and incorporate a free wheel diode (Free Wheel Diode).
  • a symbol C shown in the figure indicates a capacitor, and P and N indicate a positive side of the power supply voltage VCC and a negative side of the power supply voltage VCC, respectively.
  • the cascode switch circuits SWU, SWV, SWW, SWX, SWY, SWZ (power module) in the second embodiment use cascoat connection type switch elements, the on-resistance can be lowered.
  • the parasitic inductance of the wire can be reduced. The destruction of the element can be avoided. Thereby, even if the drive current of the three-phase motor LOAD is large, it is possible to achieve both low loss and high reliability of the three-phase inverter.
  • the three-phase motor system including the power conversion device described in the second embodiment can be used for a railway vehicle.
  • a three-phase motor system applied to a railway vehicle in Embodiment 3 will be described with reference to FIG.
  • the inverter three-phase inverter shown in FIG. 5
  • DC / AC using the power module shown in FIG. 4
  • the inverter apparatus for AC trains using the converter AC / DC used will be described.
  • FIG. 6 is a block diagram illustrating an example of a three-phase motor system applied to the railway vehicle according to the third embodiment.
  • Electric power is supplied to the railway vehicle from the overhead line RT via the panda graph PG.
  • the high-voltage AC voltage of the overhead line RT is, for example, 25 kV or 15 kV.
  • This high-voltage AC voltage is stepped down to an AC voltage of 1.5 V, for example, by an insulating main transformer MTR.
  • the stepped-down AC voltage is converted to a DC voltage of 1.5 kV by converter AC / DC.
  • the DC voltage is converted into an AC voltage by the inverter DC / AC via the capacitor CL, and a desired three-phase AC voltage is output to the three-phase motor M3, thereby driving the three-phase motor M3.
  • the configuration of the power module in the converter AC / DC and the configuration of the power module in the inverter DC / AC are the same as the configuration of the power module described in the first embodiment.
  • the symbol WHL indicates a wheel.
  • the power module described in the first embodiment can be applied to the converter AC / DC and the inverter DC / AC constituting the three-phase motor system of the railway vehicle.
  • the power module described in the first embodiment it is possible to reduce the loss of the converter circuit portion and the inverter circuit portion, so that it is possible to reduce heat dissipation fins and the like, thereby reducing the volume of the three-phase motor system. it can.
  • the floor of a railway vehicle can be reduced by downsizing the underfloor parts including a three-phase motor system.
  • the underfloor parts including a three-phase motor system.
  • Electric power can be stored in the storage battery SB without returning.
  • the regeneration efficiency of the railway vehicle can be improved.
  • the life cycle cost of the railway system can be reduced.

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Abstract

La présente invention concerne une technologie permettant d'améliorer la fiabilité d'un module de puissance mettant en œuvre un élément de commutation à montage de type cascode. Dans un module de puissance mettant en œuvre un élément de commutation formé d'un montage cascode d'un élément normalement non passant et d'un élément normalement passant, un substrat de drain sur lequel est montée une puce normalement passante, un substrat de source et un substrat de grille sont disposés dans cet ordre dans une première direction et une résistance de grille est disposée entre le substrat de source et le substrat de grille. Il en résulte une réduction de la longueur d'une pluralité de fils qui relient une pluralité d'électrodes source formées sur la surface supérieure de la puce normalement passante et le substrat de drain sur lequel est montée la puce normalement passante.
PCT/JP2014/051731 2014-01-28 2014-01-28 Module de puissance, dispositif de conversion de puissance et véhicule ferroviaire WO2015114728A1 (fr)

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Cited By (1)

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US11101259B2 (en) 2017-07-26 2021-08-24 Denso Corporation Semiconductor device

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US6614281B1 (en) * 1999-06-11 2003-09-02 Siemens Aktiengesellschaft Method and device for disconnecting a cascode circuit with voltage-controlled semiconductor switches
US20040130021A1 (en) * 2002-10-31 2004-07-08 International Rectifier Corporation High power silicon carbide and silicon semiconductor device package
US8228113B2 (en) * 2009-10-30 2012-07-24 Infineon Technologies Ag Power semiconductor module and method for operating a power semiconductor module
WO2013046439A1 (fr) * 2011-09-30 2013-04-04 ルネサスエレクトロニクス株式会社 Dispositif à semi-conducteur
JP2013229547A (ja) * 2012-03-26 2013-11-07 Toshiba Corp 半導体装置および半導体モジュール

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Publication number Priority date Publication date Assignee Title
US6614281B1 (en) * 1999-06-11 2003-09-02 Siemens Aktiengesellschaft Method and device for disconnecting a cascode circuit with voltage-controlled semiconductor switches
US20040130021A1 (en) * 2002-10-31 2004-07-08 International Rectifier Corporation High power silicon carbide and silicon semiconductor device package
US8228113B2 (en) * 2009-10-30 2012-07-24 Infineon Technologies Ag Power semiconductor module and method for operating a power semiconductor module
WO2013046439A1 (fr) * 2011-09-30 2013-04-04 ルネサスエレクトロニクス株式会社 Dispositif à semi-conducteur
JP2013229547A (ja) * 2012-03-26 2013-11-07 Toshiba Corp 半導体装置および半導体モジュール

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