WO2015111206A1

WO2015111206A1 - Computer system, server module, and storage module

Info

Publication number: WO2015111206A1
Application number: PCT/JP2014/051608
Authority: WO
Inventors: 雄太郎情野; 功大原; 実板倉
Original assignee: 株式会社日立製作所
Priority date: 2014-01-27
Filing date: 2014-01-27
Publication date: 2015-07-30

Abstract

The present invention achieves high speed, high availability data transfer between a storage module server modules and. If a plurality of servers and storage devices are connected by PCIe interface cables or the like, which are easily erroneously inserted or erroneously removed by a user, modules which process faults are inserted between PCIe root ports and the cables. Without intervening in processing that pertains to normal PCIe commands and data transfer accompanying the normal PCIe commands, the fault-processing modules propagate the commands/data. If a fault is ever generated in a PCIe link, closing processing is requested only for the faulty link without propagating fault information (ERR_FATAL message) to a disk controller. An OS in which closing processing has been requested and a program operating on the OS perform the closing processing only on the faulty link.

Description

Computer system, server module and storage module

The present invention relates to a system, a server module, and a storage module that realize high-speed, high-reliability, and highly-available data transfer between a server module and a storage module.

Conventionally, as a computer system for connecting a server and a storage device accessed by the server, a computer system in which a server and a storage are connected via a network such as a SAN (Storage Area Network) is known (Patent Document 1). .

Patent Document 1 describes “a storage subsystem having a host bus adapter (HBA) and a target bus adapter (TBA), and a FiberChannel (FC) switch for connecting the interface between the HBA and the TBA. A computer system is described in which a plurality of hosts and a plurality of storage subsystems are connected to each other via an FC switch to constitute a SAN.

In the SAN computer system as described above, there is no connection between the processor in the server serving as the host and the I / O device as the HBA, and between the processor in the disk controller of the storage apparatus and the I / O device as the TBA. In general, a PCI express (R) (PCIe) interface described in (1) and an HBA and a TBA connected via an FC switch are connected by an FC interface. Within the HBA and TBA, protocol conversion processing is performed to convert the PCIe and FC interfaces. The FC interface constitutes a SAN with optical cables, FC switches, and the like.

US Pat. No. 7,770,208

Recently, as a method for improving the performance of communication between a server and a storage device, a method of directly connecting the server and the storage device by PCIe without connecting by FC is being studied. This is because the performance overhead is reduced by eliminating the protocol conversion processing between the FC and PCIe, which was performed by the HBA and TBA for communication between the server and the storage apparatus.

As described above, the computer system using the same interface (that is, the PCIe interface) as the interface of the storage device internal communication or the server device internal communication as the interface used for communication between the server and the storage device is the storage device internal communication or server. Compared to a computer system that uses an interface different from the interface for internal device communication (that is, an FC interface), communication performance is superior, but there is a problem that fault tolerance is inferior.

For example, in the PCIe interface, it is impossible to distinguish between a component level failure such as cable disconnection or a specific port failure and a fatal failure of the entire network. Therefore, when the PCIe interface is connected between the server and the storage device, an unexpected link-down failure due to cable removal is detected as a serious failure (ERR_FATAL message) called a SuppleDown error at the PCIe root port in the disk controller of the storage device. The The PCIe root port converts the error into a SERROR signal defined by PCIe and propagates an error to the PCIe root complex. The PCIe root complex notifies the received SERROR signal to the OS on the disk controller as a Non-Maskable Interrupt (NMI). The OS that has received the NMI blocks the entire disk controller.

If a single disk controller has multiple PCIe ports and a server is connected to each port, a link down failure between a certain server and a certain disk controller will trigger and block the entire disk controller. This will also affect all other servers.

If the server and storage device are FC, even if a link down failure occurs due to cable removal or disconnection inside the cable, the failure is detected by the TBA in the storage device to which the cable was connected, and the cause of the failure is specified. Since the NMI is not notified to the disk controller OS by processing the failure according to the failure factor identified by the device driver of the TBA operating on the OS of the storage apparatus, the failure spreads to the entire disk controller. Must not.

The present invention has been made in view of the above-described problems. That is, it is an object to improve fault tolerance without impairing the merit of direct connection by PCIe between a server and a storage device capable of improving performance.

A typical example of the invention disclosed in the present application is as follows. That is, a computer system having a first server module including a first memory and a first processor, and a storage module connected to the server module via a network and including a second memory and a second processor. The server module further includes a first transfer module that controls data transfer between the first memory and the second memory, and the storage module transmits the first transfer via the network. A first port connected to the module; and a failure processing module that controls processing relating to a failure of the computer system, wherein the failure processing module associates the first port with an identifier of the first transfer module. A first failure message that manages configuration information and is received via the first port Is converted into a second failure message that includes an identifier of the first transfer module based on the configuration information and notifies the failure of the first transfer module, and the second failure message is converted to the storage module. It transmits to a 2nd processor, It is characterized by the above-mentioned.

According to the present invention, in a computer system including a server and a storage device, high-speed data transfer between the server and the storage device is executed without going through protocol conversion processing by the server module processor and the storage module processor. Furthermore, the fault tolerance of the computer system can be improved.

Issues, configurations, and effects other than those described above will be clarified by the description of the following examples.

It is a block diagram which shows the structural example of the computer system of the Example of this invention. It is a block diagram explaining the software configuration of the server module of the Example of this invention. It is a block diagram explaining the software configuration of the storage module of the Example of this invention. It is a block diagram explaining the structural example of the transfer module of the Example of this invention. It is a block diagram explaining the example of a structure of the failure processing module of the Example of this invention. It is a block diagram explaining the structural example of the access arbitration part in the failure processing module of the Example of this invention. It is a graph explaining the example of a process of the transfer determination part in the access arbitration part of the Example of this invention. It is a chart explaining the example of the memory information of the information storage part in the information management part of the Example of this invention. It is a sequence diagram explaining an example of the initialization process in the computer system of the Example of this invention. It is a sequence diagram explaining an example of the initialization process in the failure processing module of the Example of this invention. It is a sequence diagram explaining an example of the initialization process in the failure processing module of the Example of this invention. It is a sequence diagram explaining an example of the data transfer process in the computer system of the Example of this invention. It is a sequence diagram explaining an example of the data transfer process in the computer system of the Example of this invention. It is a sequence diagram explaining an example of failure detection and failure blockage processing in the computer system of the embodiment of the present invention. It is a sequence diagram explaining an example of failure detection and failure blockage processing in the failure processing module of the embodiment of the present invention. It is a sequence diagram explaining an example of failure detection and failure blockage processing in the failure processing module of the embodiment of the present invention. It is a sequence diagram explaining an example of failure detection and failure blockage processing in the computer system of the embodiment of the present invention. It is a sequence diagram explaining an example of failure detection and failure blockage processing in the failure processing module of the embodiment of the present invention. It is a sequence diagram explaining an example of the failure obstruction | occlusion cancellation | release process in the computer system of the Example of this invention. It is a sequence diagram explaining an example of the failure obstruction | occlusion cancellation | release process in the failure processing module of the Example of this invention. It is a sequence diagram explaining an example of the failure obstruction | occlusion cancellation | release process in the failure processing module of the Example of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration example of a computer system according to an embodiment of this invention.

The computer system according to the embodiment includes a plurality of server modules 200, a storage module 300, and a plurality of channels 400.

The example shown in FIG. 1 includes a server module 200-1, a server module 200-2, a storage module 300-1, a channel 400-1, a channel 400-2, a channel 400-3, and a channel 400-4. In the example of FIG. 1, a PCIe interface is used for communication between the server module and the storage module. Similarly, the PCIe interface is used for storage module internal communication and server module internal communication. In this way, by using the same interface in a computer system having a plurality of modules, the interface is compared with a computer system that uses an interface (that is, an FC interface) that is different from the interface of the server apparatus internal communication within the storage module. This eliminates the need for command conversion due to the difference between the two and provides a computer system with a high communication speed.

The server module 200 is a computer that executes a predetermined job. The storage module 300 is a computer that stores data used by the server module 200. In this embodiment, the storage module 300 provides LU (Logical Unit) to each server module 200.

The server module 200 includes a processor 210, a memory 220, a transfer module 230, a route complex 240, and an I / F 260. Each component included in the server module 200 is connected to each other via an I / O bus. The I / O bus includes a PCI bus, a PCIe bus, a system bus, and the like. The present invention is not limited to the type of I / O bus that connects each configuration.

The processor 210 executes a program stored in the memory 220. The functions of the server module 200 can be realized by the processor 210 executing the program stored in the memory 220.

The memory 220 stores a program executed by the processor 210 and information necessary for executing the program. The program and information stored in the memory 220 will be described later with reference to FIG.

Note that the program and information stored in the memory 220 may be stored in an LU or the like provided by the storage module 300. In this case, the processor 210 acquires a program and information from a storage area in which a program such as an LU is stored, and loads the acquired program and information into the memory 220.

The transfer module 230 controls data transfer between the server module 200 and the storage module 300. The detailed configuration of the transfer module 230 will be described later with reference to FIG.

The route complex 240 is an I / O controller that arbitrates communication between the processor 210 and the transfer module 230. The root complex 240 has a plurality of root ports 241, and each root port is connected to the transfer module 230 via an I / O bus.

For example, when the I / O bus connecting the devices is a PCIe bus, the root complex 240 corresponds to a root complex defined by PCIe, and the root port 241 corresponds to a root port defined by PCIe. To do.

The I / F 260 is a connector for connecting to the channel 400.

In addition, as a mounting method of the transfer module 230, a method of mounting as a chip (LSI) on the substrate of the server module 200 or a method of mounting on an adapter such as an HBA can be considered. However, the present invention is not limited to the mounting method of the transfer module 230.

The storage module 300 includes a disk controller 310, an I / F 360, a storage device 370, and a failure processing module 380. Each component included in the storage module 300 is connected to each other via an I / O bus. The I / O bus includes a PCI bus, a PCIe bus, a SAS (Serial Attached SCSI) interface, a system bus, and the like. The present invention is not limited to the type of I / O bus that connects each configuration.

The disk controller 310 controls the storage area and controls the correspondence between the server module 200 and the storage area. The disk controller 310 includes a processor 320, a memory 330, and a root complex 340.

In this embodiment, the storage module 300 has two disk controllers, a disk controller 310-1 and a disk controller 310-2. This is to improve fault tolerance by making the disk controller redundant.

The disk controller 310-1 is connected to the failure processing module 380-1, and the disk controller 310-2 is connected to the failure processing module 380-2. The disk controllers 310-1 and 310-2 are connected to the storage device 370, respectively.

The processor 320 executes a program stored in the memory 330. When the processor 320 executes the program stored in the memory 330, the function of the storage module 300 can be realized.

The memory 330 stores a program executed by the processor 320 and information necessary for executing the program. The program and information stored in the memory 330 will be described later with reference to FIG.

Note that the program and information stored in the memory 330 may be stored in the storage device 370 or the like. In this case, the processor 320 acquires a program and information from the storage device 370 and the like, and loads the acquired program and information into the memory 330.

The route complex 340 is an I / O controller that arbitrates communication between the processor 320 and the failure processing module 380. The root complex 340 has a plurality of root ports 341, and each root port is connected to the failure processing module 380 via an I / O bus.

For example, when the I / O bus connecting the devices is a PCIe bus, the root complex 340 corresponds to the root complex defined by PCIe, and the root port 341 corresponds to the root port defined by PCIe. To do.

The I / F 360 is a connector for connecting to the channel 400.

The storage device 370 is a device for storing data. For example, an HDD (Hard Disk Drive) and an SSD (Solid State Drive) can be considered.

In this embodiment, the storage module 300 configures a RAID using a plurality of storage devices, generates an LU from the RAID volume, and provides the LU to the server module 200. The LU stores programs such as the OS 221 (see FIG. 2) and the application 223 (see FIG. 2) and information necessary for executing the programs.

In addition, as a mounting method of the failure processing module 380, a method of mounting as a chip (LSI) on the substrate of the storage module 300 or a method of mounting on an adapter such as TBA is conceivable. However, the present invention is not limited to the mounting method of the failure processing module 380.

The channel 400 is a connection line for connecting the I / O buses of the server module 200 and the storage module 300, and a metal cable or the like is used.

Here, the connection relationship in the computer system will be described.

In the server module 200-1, the I / F 260-1 of the server module 200-1 and the I / F 360-1 of the storage module 300 are connected via the channel 400-1, and the server module 200-1 is connected via the channel 400-3. The I / F 260-2 of 200-1 and the I / F 360-3 of the storage module 300 are connected.

In the server module 200-2, the I / F 260-3 of the server module 200-2 and the I / F 360-2 of the storage module 300 are connected via the channel 400-2, and the server module 200-2 is connected via the channel 400-4. The I / F 260-4 of 200-2 and the I / F 360-4 of the storage module 300 are connected.

Each I / F 360 of the storage module 300 is connected to the disk controller 310-1 of the I / F 360-1 and I / F 360-2, and connected to the disk controller 310-2 of the I / F 360-3 and I / F 360-4. Is done. Accordingly, each server module 200 is connected to the two disk controllers 310-1 and 310-2 on a one-to-one basis.

In this embodiment, the two disk controllers 310-1 and 310-2 are both active. For this reason, each of the two disk controllers 310-1 and 310-2 executes the I / O processing to improve the processing performance. Further, even when a failure occurs in the disk controller 310-1, the disk controller 310-2 can continue the I / O processing. This allows business to continue.

FIG. 2 is a block diagram illustrating the software configuration of the server module 200 according to the embodiment of this invention.

The memory 220 stores a program for realizing the OS 221 and the application 223.

The OS 221 manages the server module 200. The OS 221 includes a storage access unit 222 that controls access between the server module 200 and the storage module 300. For example, the storage access unit 222 may be realized using a device driver that operates the transfer module 230.

The OS 221 has functions such as a file system (not shown).

Application 223 executes a predetermined job. The present invention is not limited to the type of application.

FIG. 3 is a block diagram illustrating the software configuration of the storage module 300 according to the embodiment of this invention.

In FIG. 3, the memory 330 included in the disk controller 310-1 will be described as an example. The memory 330 included in the disk controller 310-2 has the same software configuration.

The memory 330 stores a program for realizing the storage control unit 331.

The storage control unit 331 controls I / O processing between the server module 200 and the storage module 300. The storage control unit 331 includes an I / O processing unit 332, a storage device control unit 333, an initialization processing unit 334, and a failure processing unit 335.

The I / O processing unit 332 receives an I / O request from the server module 200, and controls write processing and read processing based on the I / O request. The storage device control unit 333 controls writing processing and reading processing for the storage device 370.

The initialization processing unit 334 receives the initialization request from the server module 200 via the failure processing module 380, and controls the writing process of the ID information and initialization information of the I / O device based on the initialization request. . If the I / O bus connecting the devices is a PCIe bus, the ID information may be control information such as Bus Number defined by PCIe, and Max Payload Size defined by PCIe.

The failure processing unit 335 receives a failure notification from the server module 200 or the channel 400 via the failure processing module 380, and based on the failure notification, collects and reads the log of the I / O device that has detected the failure, and The process of closing the failure occurrence port of the I / O device that has detected the failure and the blockage release notification from the failure processing module 380 are received, and the return to the normal I / O process is controlled based on the blockage release notification.

Note that the I / O processing unit 332, the initialization processing unit 334, and the failure processing unit 335 can be realized by using a device driver that operates the transfer module 230, for example. The storage device control unit 333 can be realized by using a device driver that operates the storage device 370.

FIG. 4 is a block diagram illustrating a configuration example of the transfer module 230 according to the embodiment of this invention.

The transfer module 230 includes a data transfer unit 231, a protocol engine 234, an end point unit 235, a plurality of connection ports 236 and 237, and a power management unit 238.

The data transfer unit 231 controls data transfer between the memory 220 of the server module 200 and the memory 330 of the storage module 300. The data transfer unit 231 of this embodiment includes a DMA controller 232 and a data inspection unit 233.

The DMA controller 232 controls DMA transfer between the memory 220 of the server module 200 and the memory 330 of the storage module 300. The data inspection unit 233 adds and deletes the data guarantee code. Further, the data inspection unit 233 confirms data consistency based on the guarantee code. Note that the data guarantee code may be DIF (Data Integrity Field).

In a general computer system, the server module handles data in units of 512 bytes, and the storage module handles data in units of 520 bytes with a data guarantee code added to the data. Data handled by the server module 200 and the storage module 300 of this embodiment is the same as that of a general computer system.

The protocol engine 234 converts a command used by the server module 200 and a command used by the storage module 300.

The endpoint unit 235 outputs a register for holding control information for operating the I / O device and information from the data transfer unit 231 and the power management unit 238 to the outside through the connection ports 236 and 237. It has the function to do. For example, when the I / O bus connected to another device via the connection ports 236 and 237 is a PCIe bus, the endpoint unit 235 corresponds to an Endpoint defined by PCIe, and sets the PCIe configuration register. And output PCIe packets and control signals.

The endpoint unit 235-1 has a SAN HBA function, and the endpoint unit 235-2 has a SAN TBA function. The endpoint unit 235-1 is controlled by the OS 221 that is software operating on the server module 200 and the storage access unit 222, and the endpoint unit 235-2 is controlled by the storage control unit 331 that is software operating on the storage module 300. Be controlled.

Connection ports 236 and 237 are ports for connecting to other devices. The connection ports 236-1 and 236-2 are connected to the root port 241, and the connection ports 237-1 and 237-2 are connected to the I / F 260. For example, when an I / O bus that connects devices is a PCIe bus, PCIe ports are used as the connection ports 236 and 237.

In the computer system of this embodiment, the connection port 236-1 of the transfer module 230-1 of the server module 200-1 is connected to the root port 241-1, the connection port 236-2 is connected to the root port 241-2, The connection port 237-1 is connected to the I / F 260-1, the connection port 237-2 is connected to the I / F 260-2, and the connection port 236-1 of the transfer module 230-1 of the server module 200-2 is a root port. 241-3, connection port 236-2 is connected to root port 241-4, connection port 237-1 is connected to I / F 260-3, and connection port 237-2 is connected to I / F 260-4. Is done.

The power management unit 238 has a function of performing power management of the transfer module 230. When the power-on signal from the processor 210 of the server module 200 is received via the endpoint unit 235-1, the power management unit 238 passes through the endpoint unit 235-2. And has a function of transmitting a WAKE signal to the I / F 260. For example, when the I / O bus connecting the devices is a PCIe bus, the WAKE signal can be a WAKE # sideband signal defined by PCIe.

FIG. 5 is a block diagram illustrating a configuration example of the failure processing module 380 according to the embodiment of this invention.

The failure processing module 380 includes an access arbitration unit 381, an information management unit 382, a port control unit 383, a failure processing control unit 384, and a plurality of connection ports 385 and 386.

The access arbitration unit 381 has a function of determining whether or not to transfer the packet of the I / O bus from the connection port 385 or the connection port 386 to the opposite connection port 386 or 385 and the failure processing control unit 384; It has a function of outputting a packet generated by the failure processing control unit 384 to the outside via the connection port 385 or the connection port 386. The internal structure will be described later with reference to FIG.

The information management unit 382 includes a plurality of information storage units 3820, and holds information necessary for processing performed by the failure processing unit 335. Access to the information storage unit 3820 is performed by the failure processing control unit 384.

The information storage unit 3820-1 stores related information regarding the I / O bus connected through the connection port 385-1, and the information storage unit 3820-2 is connected through the connection port 385-2. Stores information related to the I / O bus.

Details of the information stored in the information storage unit 3820 will be described later with reference to FIG.

The port control unit 383 includes a WAKE signal detection unit 3830, a cable non-connection signal detection unit 3831, and a port disable control unit 3832.

The WAKE signal detection unit 3830 has a function of detecting the WAKE signal received at the connection port 385.

The cable non-connection signal detection unit 3831 detects, via the connection port 385, a cable non-connection signal indicating that the I / O bus link between the I / F 360 and the channel 400 has been disconnected due to cable disconnection or erroneous disconnection. It has the function to do. When the I / O bus connecting devices is a PCIe bus, the presence detection function of the PCIe hot plug controller can be used to detect the cable disconnection signal.

Based on information from the information management unit 382, the port disable control unit 3832 disconnects the link of the I / O bus connected to the connection port 385 and stops the subsequent link establishment operation, and the established link establishment. It has a function of resuming the operation and restoring the link of the I / O bus.

The failure processing control unit 384 includes a WAKE signal generation unit 3840, a CfgWr processing unit 3841, a SupplyDown detection unit 3842, a failure notification Msg generation unit 3843, a CfgRd processing unit 3844, a reinitialization processing unit 3845, an occlusion release notification Msg generation unit 3848, An ERR_FATAL processing unit 3847 is provided.

The WAKE signal generation unit 3840 generates a WAKE signal based on the WAKE detection signal from the WAKE signal detection unit 3830 of the port control unit 383 and the information on the blockage from the information management unit 382 (see FIG. 8), and the connection port 386 To the root port 341. For example, when the I / O bus connecting the devices is a PCIe bus, the WAKE signal can be a WAKE # sideband signal defined by PCIe.

The CfgWr processing unit 3841 has a function of writing the write data of the write instruction to the information management unit 382 in response to the write instruction to the configuration register for the transfer module 230 transferred from the access arbitration unit 381. For example, when the I / O bus connecting the devices is a PCIe bus, the write instruction may be a CfgWr packet defined by PCIe. Further, it has a function of generating a Cpl packet for writing completion notification based on information (see FIG. 8) relating to a failure and blockage from the information management unit 382 and transmitting it from the connection port 386 to the root port 341.

The supply down detection unit 3842 stores the failure information in the information management unit 382 based on the cable disconnection signal from the cable disconnection signal detection unit 3831 of the port control unit 383, and generates the failure notification Msg in the failure notification Msg generation unit 3843. It has a function to request.

The failure notification Msg generation unit 3843 generates a failure notification Msg by referring to the information on the failure and ID of the information management unit 382 (see FIG. 8) based on the requests from the supply down detection unit 3842 and the ERR_FATAL processing unit 3847. It has a function of transmitting from the connection port 386 to the root port 341 via the access arbitration unit 381. For example, when the I / O bus connecting the devices is a PCIe bus, the failure notification Msg may be a Vendor Defined Message type Msg packet or a Message Signaled Interrupt type MWr packet defined by PCIe.

The CfgRd processing unit 3844 responds to the read instruction to the configuration register for the transfer module 230 transferred from the access arbitration unit 381, based on information (see FIG. 8) regarding the failure and blockage from the information management unit 382. The information stored in the unit 382 is transmitted as response data from the connection port 386 to the root port 341 via the access arbitration unit 381. For example, when the I / O bus connecting the devices is a PCIe bus, the CfgRd packet defined by PCIe and the response data may be a CplD packet.

The reinitialization processing unit 3845 stores the information in the information management unit 382 based on the WAKE detection signal from the WAKE signal detection unit 3830 of the port control unit 383 and the information on the blockage from the information management unit 382 (see FIG. 8). The information on the blockage (see FIG. 8) is cleared, the ID and the information on initialization (see FIG. 8) are used to generate a write instruction to the configuration register for the transfer module 230, and the access arbitration unit 381 is used. A function for transmitting from the connection port 385 to the I / F 360, a function for receiving a completion notification for the above-described write instruction transferred from the access arbitration unit 381, and information on a failure stored in the information management unit 382 (see FIG. 8) and the block release notification Msg generation unit 3846 are requested to generate the block release notification Msg. It has the ability. For example, when the I / O bus connecting the devices is a PCIe bus, the write instruction may be a CfgWr packet, and the completion notification for the write instruction may be a Cpl packet defined by PCIe.

Based on the request from the reinitialization processing unit 3845, the blockage release notification Msg generation unit 3846 refers to the information on the ID of the information management unit 382 (see FIG. 8), generates the blockage release notification Msg, and accesses the arbitration unit 381. And has a function of transmitting from the connection port 386 to the root port 341. For example, when the I / O bus connecting the devices is a PCIe bus, the shutdown release notification Msg may be a Vendor Defined Message type Msg packet or a Message Signaled Interrupt type MWr packet defined in PCIe. .

The ERR_FATAL processing unit 3847 stores the failure information in the information management unit 382 in response to the serious failure notification of the server module 200 or the channel 400 transferred from the access arbitration unit 381, and the failure notification Msg generation unit 3843 has a failure. A function of requesting generation of the notification Msg; For example, when the I / O bus connecting the devices is a PCIe bus, the notification of the serious failure may be an ERR_FATAL type Msg packet defined by PCIe.

Connection ports 385 and 386 are ports for connecting to other devices. In the present embodiment, the connection ports 385-1 and 385-2 are connected to the I / F 360, and the connection ports 386-1 and 386-2 are connected to the root port 341. For example, when the I / O bus connecting the devices is a PCIe bus, PCIe ports are used as the connection ports 385 and 386.

In the computer system of this embodiment, the connection port 385-1 of the failure processing module 380-1 of the storage module 300 is connected to the I / F 360-1, and the connection port 385-2 is connected to the I / F 360-2. The port 386-1 is connected to the root port 341-1, the connection port 386-2 is connected to the root port 341-2, and the connection port 385-1 of the failure processing module 380-2 is connected to the I / F 360-3. The connection port 385-2 is connected to the I / F 360-4, the connection port 386-1 is connected to the root port 341-3, and the connection port 386-2 is connected to the root port 341-4.

FIG. 6 is a block diagram illustrating a configuration example of the access arbitration unit 381 in the failure processing module 380 according to the embodiment of this invention.

The access arbitration unit 381 includes a plurality of transfer determination units 3810, a packet arbitration unit 3811, a plurality of packet buffers 3812, and a packet buffer 3813.

The transfer determination unit 3810 selects the packet of the I / O bus transmitted from the packet buffer 3812 or the packet buffer 3813 based on the information on the failure and blockage of the information management unit 382 (see FIG. 8). Or a function for determining whether to transfer to the packet buffer 3812, a function for determining whether to transfer to the failure processing control unit 384 via the packet arbitration unit 3811, and a packet buffer 3812 if the packet is determined to be transferred, Alternatively, it has a function of transferring to the packet buffer 3813 or the failure processing control unit 384 and discarding the packet when it is determined not to transfer. A method for determining the packet type will be described later with reference to FIG.

In addition, the transfer determination unit 3810-1 performs a transfer feasibility determination process in communication between the packet buffer 3812-1 and the packet buffer 3813-1, and the transfer determination unit 3810-2 includes a packet buffer 3812-2 and a packet buffer 3813. -2 in the communication between -2 is performed.

The packet arbitration unit 3811 arbitrates the I / O bus packet transferred from the transfer determination unit 3810 and transmits the packet to the failure processing control unit 384, and the I / O bus generated by the failure processing control unit 384. It has a function of transmitting a packet to the packet buffer 3812 or the packet buffer 3813 based on the packet information.

The packet buffer 3812 is connected to the connection port 385 of the failure processing module 380, and has a function of buffering an I / O bus packet received from the connection port 385 and transmitting the packet to the transfer determination unit 3810, a transfer determination unit 3810, or , And has a function of transmitting the packet received from the packet arbitration unit 3811 to the connection port 385. The packet buffer 3812-1 is connected to the connection port 385-1, and the packet buffer 3812-2 is connected to the connection port 385-2.

The packet buffer 3813 is connected to the connection port 386 of the failure processing module 380, and has a function of buffering an I / O bus packet received from the connection port 386 and transmitting the packet to the transfer determination unit 3810, a transfer determination unit 3810, or , And has a function of transmitting the packet received from the packet arbitration unit 3811 to the connection port 386. The packet buffer 3813-1 is connected to the connection port 386-1, and the packet buffer 3813-2 is connected to the connection port 386-2.

For example, when the I / O bus connecting the devices is a PCIe bus, the packet processed by the access arbitration unit may be a Transaction Layer Packet (TLP) defined by PCIe.

FIG. 7 is a chart illustrating a processing example of the transfer determination unit 3810 in the access arbitration unit 381 according to the embodiment of this invention.

CfgRd indicates ConfigurationReadRequest, CfgWr indicates ConfigurationWriteRequest, and is a TLP for reading and writing the configuration registers of the transfer module 230 and the failure processing module 380 to perform configuration and initialization. MRd indicates MemoryReadRequest, and MWr indicates MemoryWriteRequest, which is a TLP for the transfer module 280 to read / write data from / to the

memories

220 and 330. CplD indicates CompletionData, and is a TLP for performing a data response to CfgRd and MRd. Cpl indicates Completion and is a TLP for performing no data response to CfgWr.

The transfer determination unit 3810 has a function of performing transfer determination processing shown in Table 3815. The table 3815 includes elements of a column of packet type 3816, a column of failure and blocking state 3817, a column of transfer availability 3818 to the opposite connection port, and a column of transfer availability 3819 to the failure processing control unit.

In the transfer determination unit 3810, in the combination of each element in the column of the packet type 3816 and the element in the row failure and blocking state 3817 corresponding to each element described above, whether or not transfer to the opposite port in the row corresponding to the combination described above is possible. Each process of 3818 and transfer permission / unavailability 3819 to the failure processing control unit is performed.

For example, when the packet is CfgRd, if no failure or blockage has occurred, the packet is transferred to the opposite connection port 385 or the connection port 386 and not transferred to the failure processing control unit 384, and a failure or blockage occurs. In the case of “medium”, the process is not transferred to the opposite connection port 385 or the connection port 386, but is transferred to the failure processing control unit 384. A description of processing examples in the case of other packet types is omitted.

The transfer determination process shown in Table 3815 can be realized by configuring a logic circuit as a state machine.

FIG. 8 is a chart for explaining an example of information stored in the information storage unit 3820 in the information management unit 382 according to the embodiment of this invention.

The information storage unit 3820 has a register for storing information shown in the table 3821, and is read and written via the failure processing control unit 384. The information storage unit 3820 stores chart information for each of the plurality of transfer modules 230 to which the failure processing module 380 is connected. In the table 3821, the storage information includes transfer module ID information 3822, transfer module initialization information 3823, I / F failure information 3824, and I / F blocking state 3825.

Transfer module ID information 3822 and transfer module initialization information 3823 are control information for operating the transfer module 230. The transfer module ID information 3822 indicates the correspondence between the ID of the transfer module and the identifier of the I / F 360 of the storage module 300 to which the transfer module is connected (or the identifier of the connection port 385-1 of the failure processing module). .

The I / F failure information 3824 is failure information related to the I / O bus between the failure processing module 380 and the server module 200 detected by the failure processing module 380.

The I / F blocking state 3825 is status information indicating whether the connection port 385 is blocked according to an instruction from the failure processing unit 335.

For example, when the I / O bus connecting the devices is a PCIe bus, an implementation method may be considered in which the register of the information storage unit 3820 is configured as a configuration register defined by PCIe.

9 to 21, processing examples in the embodiment of the present invention will be described using sequence diagrams. In these descriptions, a PCIe bus will be described as an example of an I / O bus that connects devices. The description will be made using signal names and packet names defined by PCIe, but the present invention is not limited to the type of I / O bus. The black circles in the sequence diagram indicate the start point of the sequence indicated by the arrow line, and the arrow at the tip of the arrow line indicates the end point of the sequence. In addition, the intersection of the arrow line and the vertical line indicates that the sequence indicated by the arrow line passes through the part indicated by the vertical line and is involved in the processing. The sequence indicated by the arrow line does not pass through the portion indicated by the vertical line, indicating that it is not involved in the processing. Note that the sequence progresses downward and indicates that time passes.

9 to 11, an example of the initialization process in the embodiment of the present invention will be described.

FIG. 9 is a sequence diagram illustrating an example of initialization processing in the computer system according to the embodiment of this invention. FIG. 9 shows a flow of processing executed when the server module 200-1 is powered on and the transfer module 230-1 is initialized from the storage module 300.

In the processor 210-1 of the server module 200-1 that is turned on, the processing of the OS 221 is executed. The processor 210-1 executing the processing of the OS 221 transmits a power-on signal and is received by the transfer module 230-1 (step S100).

Upon receipt of the power-on signal, the transfer module 230-1 outputs a WAKE signal and is received by the failure processing module 380-1 via the channel 400-1 (step S101).

The failure processing module 380-1 that has received the WAKE signal outputs the WAKE signal and receives it by the processor 320-1 of the storage module 300 (step S102).

In the processor 320-1, which is executing the processing of the storage control unit 331, the processing of the initialization processing unit 334 is executed. The initialization processing unit 334 executes ID information write processing to identify the transfer module 230-1, and issues a CfgWr packet to the transfer module 230-1 (step S103).

When the failure processing module 380-1 transfers the CfgWr packet for writing ID information in step S103 to the channel 400-1, the failure processing module 380-1 performs processing for copying the write information of the CfgWr packet and stores the ID information (step S104). .

The transfer module 230-1 receives the CfgWr packet for writing the ID information in step S103, writes the write information to the configuration register of the endpoint unit 235-2, and sends the Cpl packet as a write completion notification to the processor of the storage module 300. It is issued to 320-1 (step S105).

When the processor 320-1 executing the initialization processing unit 334 receives the Cpl packet in step S105 and confirms the completion of writing, the processor 320-1 then initializes to set control information of the transfer module 230-1. Information writing processing is executed, and a CfgWr packet is issued to the transfer module 230-1 (step S106).

The processing when the failure processing module 380-1 receives the CfgWr packet at step S106 (step S107) is step S104, and the processing when the transfer module 230-1 receives the CfgWr packet at step S106 (step S108) is step. Since the process is the same as S105, the description is omitted.

When the processor 320-1 executing the initialization processing unit 334 receives the Cpl packet in step S108 and confirms the completion of writing, the processor 320-1 completes the initialization processing.

The above is the description of the initialization process example, but the internal processing of the failure processing module 380-1 in the initialization process example of FIG. 9 will be described in detail with reference to FIG. 10 and FIG.

FIG. 10 is a sequence diagram illustrating an example of initialization processing in the failure processing module 380-1 according to the embodiment of this invention. FIG. 10 shows a processing flow in the failure processing module 380-1 when the failure processing module 380-1 receives the WAKE signal from the transfer module 230-1.

The port control unit 383 receives a WAKE signal from the channel 400-1 via the connection port 385-1 (step S150).

In the port control unit 383, the WAKE signal detection unit 3830 detects the WAKE signal in step S150 and transmits the WAKE detection signal to the failure processing control unit 384 (step S151).

The failure processing control unit 384 detects the WAKE detection signal at step S151, refers to the I / F blockage state 3825 of the information storage unit 3820-1 of the information management unit 382, and confirms that no blockage has occurred (step S152). ).

Since it is confirmed in step S152 that no blockage has occurred, a WAKE signal is generated by the WAKE signal generation unit 3840, and is transmitted to the root complex 340-1 via the connection port 386-1 (step S153). . The operation when the I / F closed state 3825 indicates a closed state will be described later with reference to FIG.

FIG. 11 is a sequence diagram illustrating an example of initialization processing in the failure processing module 380-1 according to the embodiment of this invention. FIG. 11 shows a case where the failure processing module 380-1 receives a CfgWr packet for writing ID information from the processor 320-1 and a case where a Cpl packet for writing completion notification is received from the transfer module 230-1. The flow of processing in the failure processing module 380-1 is shown.

First, processing when the failure processing module 380-1 receives a CfgWr packet for writing ID information from the processor 320-1 will be described.

The access arbitration unit 381 receives the CfgWr packet for writing ID information from the root complex 340-1 via the connection port 386-1 (step S160).
In the access arbitration unit 381, the transfer determination unit 3810-1 refers to the I / F failure information 3824 and the I / F blockage state 3825 in the information storage unit 3820-1 of the information management unit 382 to determine whether the failure and blockage are not blocked. The occurrence is confirmed (step S161).

Since it is confirmed in step S161 that no failure or blockage has occurred, the CfgWr packet in step S160 is transferred to the opposite connection port, based on the transfer determination process (see table 3815 in FIG. 7) of the transfer determination unit 3810-1. Then, it is determined to transfer to the failure processing control unit 384 (step S162).

The access control unit 381 transfers the CfgWr packet for writing the ID information to the channel 400-1 via the connection port 385-1 based on the transfer permission determination in step S162 (step S163), and further performs failure processing control. The data is transferred to the unit 384 (step S164).

In the failure processing control unit 384, the CfgWr processing unit 3841 processes the CfgWr packet for writing ID information transferred in step S164. Specifically, the write request, such as the write address and data length, is analyzed and written to the transfer module ID information 3822 of the information storage unit 3820-1 of the information management unit 382 (step S165).

Next, processing in the failure processing module 380-1 when a Cpl packet for writing completion notification is received from the transfer module 230-1 will be described.

The access arbitration unit 381 receives a Cpl packet for writing completion notification for writing ID information from the channel 400-1 via the connection port 385-1 (step S166).
In the access arbitration unit 381, the transfer determination unit 3810-1 refers to the I / F failure information 3824 and the I / F blockage state 3825 in the information storage unit 3820-1 of the information management unit 382 to determine whether the failure and blockage are not blocked. The occurrence is confirmed (step S167).

Since it is confirmed in step S167 that no failure or blockage has occurred, the Cpl packet in step S167 is transferred to the opposite connection port based on the transfer determination process of the transfer determination unit 3810-1 (see Table 3815 in FIG. 7). Then, it is determined that it is not transferred to the failure processing control unit 384 (step S168).

The access control unit 381 transfers the Cpl packet for writing completion notification to the root complex 340-1 via the connection port 386-1 based on the transfer permission determination in step S168 (step S169).

For the processing in the failure processing module regarding the CfgWr packet for writing initialization information and the Cpl packet for writing completion notification in FIG. 9, the CfgWr packet for writing ID information in FIG. Since it is the same as the process of the Cpl packet for notification, description is abbreviate | omitted.

The above is the explanation of FIG.

12 and 13 are sequence diagrams illustrating an example of data transfer processing in the computer system according to the embodiment of this invention.

FIG. 12 shows the flow of read processing executed when the server module 200-1 reads data from the storage module 300. FIG. 13 shows a flow of write processing executed when the server module 200-1 writes data to the storage module 300. In the following description, a case where an I / O request is issued to the disk controller 310-1 of the storage module 300 will be described as an example.

First, the data reading process will be described.

When the processor 210-1 executing the processing of the OS 221 receives a read request for data stored in the storage module 300 from the application 223, the processor 210-1 executes the storage access unit 222 (not shown).

The storage access unit 222 sets a buffer in the memory 220-1 for temporarily storing data to be read. In addition, the storage access unit 222 writes transfer information including an address for storing data read from the storage module 300 in a buffer, an address length, and the like in the memory 220-1 (not shown).

The processor 210-1 executing the process of the storage access unit 222 transmits a read request to the processor 320-1 executing the storage control unit 331 that executes the process of the storage control unit 331 (step S200). The read request is a command used in the server module 200-1. Therefore, the command is different from the command used in the storage module 300. That is, the protocols handled by the server module 200-1 and the storage module 300 are different.

In the following description, a command used by the server module 200-1 is described as a server command, and a command used by the storage module 300 is described as a storage command.

Upon receiving a read request (server command) from the processor 210-1, the transfer module 230-1 converts the read request into a storage command, and executes the processing of the storage control unit 331 on the converted read request (storage command) It transmits to the processor 320-1 which is doing (step S201). Specifically, the following processing is executed by the transfer module 230-1.

The data transfer unit 231 analyzes the received read request (server command). Since the received read request (server command) is a server command transmitted to the storage module 300, the data transfer unit 231 instructs the protocol engine 234 to convert the command.

The protocol engine 234 converts the received read request (server command) from a server command to a storage command, and outputs the converted read request (storage command) to the data transfer unit 231.

The data transfer unit 231 transmits the input read request (storage command) to the processor 320-1 of the storage module 300.

The above is the description of the processing in step S201.

Upon receiving the read request (storage command), the processor 320-1 executing the processing of the storage control unit 331 reads the data to be read from the storage device 370 and copies the read data to the memory 330-1. (Not shown). Specifically, the following processing is executed by the storage control unit 331.

The processor 320-1 executing the processing of the I / O processing unit 332 issues a read request to the storage device 370 based on the read request (storage command), and executes the storage device control unit 333. Based on the issued read request, the processor 320-1 executing the processing of the storage device control unit 333 reads predetermined data from the storage device 370 and outputs the data to the I / O processing unit 332. The processor 320-1 executing the processing of the I / O processing unit 332 copies the input data to the memory 330-1 (not shown).

In this embodiment, since the read request (storage command) is converted into a storage command in advance by the transfer module 230-1, the I / O processing unit 332 does not need to execute a command conversion process.

Next, the processor 320-1 executing the storage control unit 331 writes an address for reading the copied data, an address book, and the like in the memory 330-1 (not shown). Further, the storage control unit 331 transmits a DMA transfer request to the transfer module 230-1 (step S202).

When the transfer module 230-1 receives the DMA transfer request, the transfer information such as the address for storing data in the buffer and the address length is transferred from the memory 220-1 of the server module 200-1 via the processor 210-1. Read (step S203, step S204). Also, transfer information such as an address and address length for reading the copied data is read from the memory 330-1 of the storage module 300 via the processor 320-1 (steps S205 and S206).

The transfer module 230-1 refers to the transfer information acquired in steps S205 and S206, and reads the data copied to the memory 330-1 via the processor 320-1 (steps S207 and S208).

Specifically, the DMA controller 232 of the data transfer unit 231 reads the data copied to the memory 330-1 via the processor 320-1 based on the addresses acquired in Step S205 and Step S206. Note that the DMA controller 232 reads data for each predetermined data unit. For example, data of 520 bytes is read.

Next, the transfer module 230-1 refers to the transfer information acquired in steps S203 and S204, and writes the read data to the memory 220-1 of the server module 200-1 via the processor 210-1 (step S209).

Specifically, the following processing is executed.

The data inspection unit 233 of the data transfer unit 231 converts the read data into a data format on the server module 200-1 side. For example, the data inspection unit 233 deletes the data guarantee code assigned to the read data. As a result, the data is converted into 512-byte data handled by the server module 200.

The data transfer unit 231 specifies the buffer area of the memory 220-1 to which the converted data is written, based on the addresses acquired in step S203 and step S204. Further, the DMA controller 232 of the data transfer unit 231 writes the converted data in the specified buffer area of the memory 220-1.

For example, the data transfer unit 231 specifies the buffer area of the memory 220-1 by adjusting the alignment. This is because the address length of the data handled by the server module 200-1 and the data handled by the storage module 300 are different, and the address of the buffer area stored in the memory 220-1 needs to be adjusted.

The data transfer unit 231 repeatedly executes the above-described processing until all the data to be read is read.

The data transfer unit 231 may confirm the consistency of the read data based on the data guarantee code. When an error is detected in the read data, the data transfer unit 23
1 may read data from the memory 330-1 of the storage module 300 again, or may notify the storage controller 331 that a data error has been detected.

The above is the description of the processing in step S209.

In this embodiment, in step S208 and step S209, data is read from the memory 330 of the storage module 300 via the processor 320-1 and written to the memory 220 of the server module 200 via the processor 210-1. did. However, the transfer module 230 may directly access the

memories

330 and 220 without going through the processors 320-1 and 210-1. In this case, high-speed processing can be achieved by excluding processing in intermediate devices such as the processor 320-1 and the processor 210-1.

Next, the transfer module 230-1 writes all the data to be read into the memory 220-1, and then transmits a DMA transfer completion notification to the processor 320-1 executing the storage control unit 331 (step S210). ).

After receiving the DMA transfer completion notification in step S210, the processor 320-1 executing the processing of the storage control unit 331 transmits a completion notification (storage command) to the transfer module 230-1 (step S211). ).

After receiving the completion notification (storage command) in step S211, the transfer module 230-1 converts the completion notification (storage command) from the storage command to the server command, and sends the converted completion notification (server command) to the OS 221. Is transmitted to the processor 210-1 executing (step S212). Note that the command conversion process is the same as that in step S201, and a description thereof will be omitted.

Next, the data writing process will be described.

When the processor 210-1 executing the processing of the OS 221 receives a data write request from the application 223 to the storage module 300, the processor 210-1 executes the storage access unit 222 (not shown).

The storage access unit 222 copies the write target data to the memory 220-1. Further, the storage access unit 222 writes transfer information including an address for reading data copied to the memory 220-1 and an address length to the memory 220-1 (not shown).

The processor 210-1 executing the processing of the storage access unit 222 transmits a write request (server command) to the processor 320-1 executing the processing of the storage control unit 331 (step S250).

Upon receiving the write request (server command) in step S250, the transfer module 230-1 converts the write request (server command) from a server command to a storage command, and the converted write request (storage command). The data is transmitted to the processor 320-1 that is executing the processing of the storage control unit 331 (step S251). Specifically, the following processing is executed.

The data transfer unit 231 analyzes the received write request (server command). Since the received write request (server command) is a server command transmitted to the storage module 300, the data transfer unit 231 instructs the protocol engine 234 to convert the command.

The protocol engine 234 converts the received write request (server command) from a server command to a storage command, and outputs the converted write request (storage command) to the data transfer unit 231.

The data transfer unit 231 transmits the input write request (storage command) to the processor 320-1 executing the processing of the storage control unit 331 of the storage module 300.

The above is the description of the processing in step S251.

When the processor 320-1 executing the processing of the storage control unit 331 receives a write request (storage command), it sets a buffer for temporarily storing data to be written. Further, the processor 320-1 executing the processing of the storage control unit 331 writes transfer information such as an address and address length for storing data to be written in the buffer into the memory 330-1 (illustrated). (Omitted).

Next, the processor 320-1 executing the processing of the storage control unit 331 transmits a DMA transfer request to the transfer module 230-1 (step S252).

When the transfer module 230-1 receives the DMA transfer request in step S252, the transfer module 230-1 receives the transfer information including the address for reading the copied data, the address length, and the like from the memory 220-1 of the server module 200-1. The processor 320-1 reads the transfer information (step S253, step S254), and the transfer information such as the address and address length for storing the write target data in the buffer from the memory 330-1 of the storage module 300. -1 is read (step S255, step S256).

Specifically, the DMA controller 232 of the data transfer unit 231 acquires an address for reading the data copied from the server module 200-1, and stores the write target data from the storage module 300 in the buffer. Get the address.

The transfer module 230 refers to the transfer information acquired in steps S253 and S254, and reads the data copied to the memory 220-1 via the processor 210-1 (steps S257 and S258).

Specifically, the DMA controller 232 of the data transfer unit 231 obtains the data copied to the memory 220-1 based on the address obtained in steps S253 and S254 for reading the copied data. Read out via the processor 210-1. Note that the DMA controller 232 reads data for each predetermined data unit. For example, 512-byte data is read out.

Next, the transfer module 230-1 refers to the transfer information acquired in steps S255 and S256, and writes the read data to the memory 330-1 of the storage module 300 via the processor 320-1 (step S259). ). Specifically, the following processing is executed.

The data inspection unit 233 of the data transfer unit 231 converts the data read in step S257 and step S258 into a data format on the storage module 300 side. For example, the data inspection unit 233 gives a data guarantee code to the read data. As a result, the data is converted into 520-byte data handled by the storage module 300.

The data transfer unit 231 specifies the buffer area of the memory 330-1 to which the converted data is written based on the address for storing the data to be written acquired in Step S255 and Step S256 in the buffer. . Further, the DMA controller 232 of the data transfer unit 231 writes the converted data to the specified buffer area of the memory 330-1 via the processor 320-1.

For example, the data transfer unit 231 specifies the buffer area of the memory 330-1 by adjusting the alignment.

The data transfer unit 231 repeatedly executes the above-described processing until all the write target data is written.

The above is the description of the processing in step S259.

In this embodiment, the example in which data is written to and read from the

memories

220 and 330 via the processor 320-1 and the processor 210-1 in step S257, step S258, and step S259 has been mainly described. However, the transfer module 230 may directly access the

memories

Next, the transfer module 230-1 writes all data to be written to the memory 330-1, and then transmits a DMA transfer completion notification to the processor 320-1 executing the processing of the storage control unit 331. (Step S260).

After receiving the DMA transfer completion notification in step S260, the processor 320-1 executing the processing of the storage control unit 331 transmits a completion notification (storage command) to the transfer module 230-1 (step S261). ).

After receiving the completion notification (storage command) in step S261, the transfer module 230-1 converts the completion notification (storage command) from the storage command to the server command, and converts the converted completion notification (server command) to the storage access. The data is transmitted to the processor 210-1 executing the processing of the unit 222 (step S262). Note that the command conversion process is the same as that in step S251, and a description thereof will be omitted.

12 and FIG. 13, the read request in step S201, the write request in step S251, the DMA transfer request in step S202, the step S252, the transfer data write in step S259, the step S210, which passes through the failure processing module 380-1. The DMA transfer completion notification in step S260, the completion notifications in step S211 and step S261 are communicated by PCIe MWr packets, the transfer information read in steps S205 and S255, and the transfer data read in step S207 are the PCIe MRd packets. The transfer information acquisition in steps S206 and S256 and the transfer data acquisition in step S208 are communicated by a PCIe CplD packet. When these PCIe packets pass through the failure processing module 380-1, they are transferred to the transfer determination processing of the transfer determination unit 3810-1 of the access arbitration unit 381 in the failure processing module 380-1 (see Table 3815 in FIG. 7). Processed based on. In the case of normal data communication as shown in FIGS. 12 and 13, since no failure or blockage has occurred, only the process of transferring to the opposite communication path is performed (not shown).

14 to 18, an example of failure detection and failure blockage processing in the embodiment of the present invention will be described.

FIG. 14 is a sequence diagram illustrating an example of failure detection and failure blockage processing in the computer system according to the embodiment of this invention. FIG. 14 shows a case where the failure processing module 380-1 detects a failure and a port connected to the failed I / O bus is blocked when a failure occurs in the channel 400-1. Shows the flow of processing executed.

In the channel 400-1, the cable connecting the server module 200-1 and the storage module 300 is disconnected, and the failure processing module receives a signal indicating the disconnection (step S300). This cable disconnection becomes a supple down error in PCIe and a FATAL failure as an unintended link down failure.

The failure processing module 380-1 detects a cable break as a FATAL failure of the I / O bus (step S301), issues a failure notification Msg, and receives it by the processor 320-1 of the storage module 300 (step S302). . The failure notification Msg includes the ID information of the transfer module 230-1. The ID information of the transfer module 230-1 may be specified by the configuration information 3820.

The PCIe stipulates that a FATAL failure is notified using an ERR_FATAL type Msg packet, but the failure notification Msg in step S302 can be realized by issuing a Vender Defined Message type Msg packet. As a result, it is possible to prevent the occurrence of NMI that is caused when the processor 320-1 receives ERR_FATAL.

In the processor 320-1, which executes the storage control unit 331, the failure processing unit 335 is executed by receiving the failure notification Msg in step S302. The failure processing unit 335 executes a log collection / reading process and issues a CfgRd packet for log collection / reading to the transfer module 230-1 based on the ID information included in the received failure notification Msg (step S303). .

The failure processing module 380-1 that has received the CfgRd packet for log collection read in step S303 responds to the log collection read in place of the transfer module 230-1 that is unable to communicate due to cable disconnection, and receives a collection request. The received log data is returned to the processor 320-1 as a CplD packet (step S304). As the log to be read, initialization information, failure information, etc. relating to the transfer module 230-1 stored in the failure processing module 380-1 can be considered.

When the processor 320-1 executing the failure processing unit 335 receives the CplD packet in step S304 and completes the log collection, the processor 320-1 executes processing for closing the site where the failure has occurred, and notifies the failure notification in step S303. Based on the ID information included in Msg, a CfgWr packet for writing a port closing instruction is issued to the transfer module 230-1 (step S305). In this embodiment, the failure notification Msg means a FATAL failure, and the port closing finger processing is always performed regardless of the failure factor. However, if the failure notification Msg means a plurality of failure levels or factors, The failure information may be used to analyze the failure level and the failure factor to determine whether or not the blockage is possible.

The failure processing module 380-1 that has received the CfgWr packet for writing the port block instruction in step S305 is connected to the failure channel 400-1 in place of the transfer module 230-1 that cannot communicate due to cable disconnection. A process for disabling the connection port 385-1 of the failure processing module 380-1 is performed (step S306), and a Cpl packet for a closure completion response is returned to the processor 320-1 (step S307).

When the connection port 385-1 is disabled in step S306, the interface between the transfer module 230-1 including the channel 400-1 connected to the connection port 385-1 is also blocked, and the server module 200-1 and the storage module I / O bus communication between 300 is disabled. That is, it can be regarded as a state in which the faulty part is disconnected from the storage module 300.

When the processor 320-1 executing the failure processing unit 335 receives the Cpl packet in step S307 and confirms the completion of the port block write, the processor 320-1 completes the port block process.

The above is the description of the failure detection and failure blocking processing example. The processing in the failure processing module 380-1 in the processing example of FIG. 14 will be described in detail with reference to FIGS.

FIG. 15 is a sequence diagram illustrating an example of failure detection processing in the failure processing module 380-1 according to the embodiment of this invention. FIG. 15 shows a failure when the failure processing module 380-1 detects a failure of the channel 400-1 and when the failure processing module 380-1 receives a CfgRd packet for log collection reading from the processor 320-1. The flow of processing in the processing module 380-1 is shown.

First, processing when the failure processing module 380-1 detects a failure in the channel 400-1 will be described.

The port control unit 383 receives the cable non-connection signal due to the cable disconnection of the channel 400-1 via the connection port 385-1 (step S350).

In the port control unit 383, the cable non-connection number detection unit 3831 detects the cable non-connection signal in step S350, and the information is transmitted to the failure processing control unit 384 (step S351).

When the failure down control unit 384 detects the cable disconnection signal in step S351 by the supply down detection unit 3842, the fault processing control unit 384 receives the cable disconnection signal from the management information in the information storage unit 3820-1 of the information management unit 382. The management information of the transfer module connected to the port is specified, and the fault information indicating the occurrence of the FATAL fault and the cable disconnection is written in the I / F fault information 3824 of the management information (step S352).

Thereafter, the failure notification Msg generation unit 3843 uses the identifier (ID information) of the transfer module 230-1 connected to the connection port that has received the cable disconnection signal based on the transfer module ID information 3822 of the information storage unit 3820-1. Is acquired (step S353). Further, a failure notification Msg to which the acquired ID information is added is generated and transmitted from the connection port 386-1 to the route complex 340-1 via the access arbitration unit 381 (step S354).

Next, processing in the failure processing module 380-1 when the failure processing module 380-1 receives a CfgRd packet for log collection reading from the processor 320-1 will be described.

The access arbitration unit 381 sends a CfgRd packet for log collection reading of the transfer module 230-1 specified by the ID information from the route complex 340-1 or the processor 320-1 via the connection port 386-1. Receive (step S355). The route complex 340-1 and the processor 320-1 recognize that a failure has occurred in the transfer module 230-1 specified by the ID information described above based on the failure notification Msg received from the failure processing module 380-1. Because it is.

In the access arbitration unit 381, the transfer determination unit 3810-1 refers to the I / F failure information 3824 of the information storage unit 3820-1 of the information management unit 382 and confirms that a failure has occurred (step S356). ).

Since it is confirmed in step S356 that a failure has occurred, the CfgRd packet in step S355 is not transferred to the opposite connection port based on the transfer determination process (see table 3815 in FIG. 7) of the transfer determination unit 3810-1. And is determined to be transferred to the failure processing control unit 384 (step S357).

The access control unit 381 transfers the CfgRd packet for log collection reading to the failure processing control unit 384 based on the transfer permission / inhibition determination in step S357 (step S358).

In the failure processing control unit 384, the CfgRd processing unit 3844 processes the CfgRd packet for log collection and reading transferred in step S358. Specifically, the read request such as the read address and the data length is analyzed, and a request for reading the information to be read is issued from the information storage unit 3820-1 of the information management unit 382 (step S359).

In response to the read request in step S359, the CfgRd processing unit 3844 acquires log information from the information management unit 382 (step S360), generates a CplD packet as log data, and connects to the connection port via the access arbitration unit 381. The transmission is transmitted from 386-1 to the root complex 340-1 (step S361).

The above is the explanation of FIG. Next, FIG. 16 will be described.

FIG. 16 is a sequence diagram illustrating an example of failure detection processing in the failure processing module 380-1 according to the embodiment of this invention, and illustrates a continuation of the sequence in FIG. FIG. 16 shows the flow of processing in the failure processing module 380-1 when the failure processing module 380-1 receives a CfgWr packet for writing a port closing instruction from the processor 320-1.

The access arbitration unit 381 receives the CfgWr packet for writing the port closing instruction from the route complex 340-1 via the connection port 386-1 (step S370).

In the access arbitration unit 381, the transfer determination unit 3810-1 refers to the I / F failure information 3824 of the information storage unit 3820-1 of the information management unit 382 and confirms that a failure has occurred (step S371). ).

Since it is confirmed in step S371 that a failure has occurred, the CfgWr packet in step S370 is sent to the opposite connection port 385-1 based on the transfer determination process (see table 3815 in FIG. 7) of the transfer determination unit 3810-1. Is not transferred, but is determined to be transferred to the failure processing control unit 384 (step S372).

The access control unit 381 transfers the CfgWr packet for writing the port closing instruction to the failure processing control unit 384 based on the transfer permission determination in step S372 (step S373).

In the failure processing control unit 384, the CfgWr processing unit 3841 processes the CfgWr packet for writing the port closing instruction transferred in step S373. Specifically, the write request such as the write address and data length is analyzed, and the status indicating the blocked state is written in the I / F blocked state 3825 of the information storage unit 3820-1 of the information management unit 382 (step S374).

The CfgWr processing unit 3841 generates a Cpl packet as a response indicating the completion of writing in step S374, and transmits the Cpl packet from the connection port 386-1 to the route complex 340-1 via the access arbitration unit 381 (step S375). ).

When the block status is written in the I / F block state 3825 of the information storage unit 3820-1 in step S374, the port disable control unit 3832 of the port control unit 383 determines that the block is blocked (step S376), and the target connection The port 385-1 is disabled and blocked (step S377). Port blocking can be realized by a PCIe port power-off process by the PCIe hot plug controller.

In the connection port 385-1 blocked in step S377, the I / O bus link establishment process is not performed, so the connection port 385-1 including the channel 400-1 connected to the connection port 385-1 is connected to the connection port 385-1. The interface between them is also blocked (step S378). Since the port blocking process is performed for each connection port, even if the connection port 385-1 is blocked, the connection port 385-2 that is not the blocking target can perform a normal communication operation.

The above is the explanation of FIG.

FIGS. 17 and 18 are sequence diagrams illustrating an example of failure detection and failure blocking processing when a failure of a different factor occurs from the description of FIGS. 14 to 16.

FIG. 17 shows that when a failure occurs in the transfer module 230-1, the failure processing module 380-1 detects the failure, and the port connected to the I / O bus where the failure has occurred is blocked. The flow of processing executed in this case is shown.

In the transfer module 230-1, a hardware failure occurs, a PCIe ERR_FATAL type Msg packet for reporting a FATAL failure is issued, and the failure processing module 380-1 receives it via the channel 400-1 (step S1). S400).

The failure processing module 380-1 detects the ERR_FATAL reception in step S400 as an I / O bus FATAL failure (step S401), issues a failure notification Msg, and receives it in the processor 320-1 of the storage module 300. (Step S402). The failure notification Msg includes the ID information of the transfer module 230-1.

The failure notification Msg in step S402 is the same packet as the failure notification Msg in step S302 in FIG.

Processing of processor 320-1 when receiving failure notification Msg in step S402, log collection and reading (step S403), return of log data by failure processing module 380-1 (step S404), port by processor 320-1 The process of blocking instruction writing (step S405), failure side port disable processing (step S406) and blocking completion response (step S407) by the failure processing module 380-1 is the same processing as steps S302 to S307 in FIG. Therefore, the description is omitted.

In FIG. 17, the ERR_FATAL from the transfer module 230-1 is converted into a failure notification Msg by the failure processing module 380-1 and notified to the processor 320-1, so that the processor 320-1 receives the ERR_FATAL. It is possible to prevent the occurrence of NMI that is caused.

The above is the description of the failure detection and failure blocking processing example. The processing in the failure processing module 380-1 in the processing example of FIG. 17 will be described in detail with reference to FIG.

FIG. 18 is a sequence diagram illustrating an example of failure detection processing in the failure processing module 380-1 according to the embodiment of this invention. FIG. 18 shows the flow of processing in the failure processing module 380-1 when the failure processing module 380-1 receives ERR_FATAL from the transfer module 230-1 via the channel 400-1.

The access arbitration unit 381 receives the ERR_FATAL Msg packet from the channel 400-1 via the connection port 385-1 (step S450).

The access arbitration unit 381 does not transfer the ERR_FATAL Msg packet in step S450 to the opposite connection port 386-1 based on the transfer determination process (see Table 3815 in FIG. 7) of the transfer determination unit 3810-1, and performs failure processing control. It determines with transferring to the part 384 (step S451).

The access control unit 381 transfers the ERR_FATAL Msg packet to the failure processing control unit 384 based on the transfer availability determination in step S451 (step S452).

In the failure processing control unit 384, the ERR_FATAL Msg packet transferred in step S452 is processed by the ERR_FATAL processing unit 3847. Specifically, failure information indicating the occurrence of a FATAL failure and ERR_FATAL reception is written in the I / F failure information 3824 of the information storage unit 3820-1 of the information management unit 382 (step S453).

Thereafter, the failure notification Msg generation unit 3843 acquires the ID information of the transfer module 230-1 from the transfer module ID information 3822 of the information storage unit 3820-1 (step S454). Further, a failure notification Msg to which the acquired ID information is added is generated and transmitted from the connection port 386-1 to the route complex 340-1 via the access arbitration unit 381 (step S455).

The above is an explanation of an example of failure detection and failure blockage processing in this embodiment.

19 to 21, an example of the failure block release process in the embodiment of the present invention will be described.

FIG. 19 is a sequence diagram illustrating an example of the failure block release process in the computer system according to the embodiment of this invention. FIG. 19 shows that the failure processing module 380-1 re-initializes the transfer module 230-1 after the maintenance replacement of the failed part, the blocked state of the connection port is released, and the I / O processing can operate normally. The flow of processing to recover to the state is shown.

The transfer module 230-1 or the cable of the channel 400-1 as described in FIGS. 14 and 17 is replaced for maintenance (step S500). At this time, the server module 200-1 is powered off and the storage module 200 is powered on.

The server module 200-1 is powered on, and the processor 210-1 of the server module 200-1 executes the processing of the OS 221. The processor 210-1 executing the processing of the OS 221 transmits a power-on signal and is received by the transfer module 230-1 (step S501).

The transfer module 230-1 that has received the power-on signal transmits a WAKE signal, which is received by the failure processing module 380-1 (S502).

The failure processing module 380-1 that has received the WAKE signal in step S502 performs processing for enabling the connection port 385-1 of the failure processing module 380-1 that has been blocked due to a failure (step S503).

When the connection port 385-1 is enabled in step S503, the block state of the interface with the transfer module 230-1 including the channel 400-1 connected to the connection port 385-1 is also released, and the server module 200-1 The state is restored to the state where the I / O bus communication between the storage modules 300 can be performed. That is, the storage module 300 is reconnected to the part that was previously disconnected due to a failure.

In the normal initialization process of FIG. 9, the failure processing module 380-1 that has received the WAKE signal transmits the WAKE signal to the processor 320-1, and the transfer module is processed by the initialization processing unit 334 of the storage control unit 331. When 230-1 is initialized but the connection port 385-1 of the failure processing module 380-1 is blocked, the failure processing module 380-1 does not transmit a WAKE signal to the processor 320-1. The failure processing module 380-1 uses the ID information and initialization information of the transfer module 230-1 stored during the normal initialization process to re-transfer the transfer module 230-1 on behalf of the processor 320-1. Perform initialization processing. Hereinafter, the reinitialization process will be specifically described.

In step S503, the connection port 385-1 is enabled, the blocked state of the interface with the transfer module 230-1 is released, and the I / O bus between the server module 200-1 and the storage module 300 can communicate. Then, the failure processing module 380-1 issues a CfgWr packet for writing ID information to the transfer module 230-1 in order to re-initialize the transfer module 230-1 (step S504). This CfgWr packet is the same packet as the CfgWr packet for writing ID information in step S103 of FIG.

The transfer module 230-1 receives the CfgWr packet for writing the ID information in step S504, writes the write information into the configuration register of the endpoint unit 235-2, and sends the Cpl packet as a write completion notification to the failure processing module 380- 1 (step S505).

When the failure processing module 380-1 receives the Cpl packet in step S505 and confirms the completion of writing, the failure processing module 380-1 writes initialization information to the transfer module 230-1 to set control information of the transfer module 230-1. A CfgWr packet for is issued (step S506). This CfgWr packet is the same packet as the CfgWr packet for writing the initialization information in step S106 of FIG.

The process when the transfer module 230-1 receives the CfgWr packet in step S506 (step S507) is the same as that in step S505, and thus the description thereof is omitted.

When the failure processing module 380-1 receives the Cpl packet in step S507 and confirms the completion of the writing, the reinitialization processing is completed, and the block release notification Msg for notifying that the failure block release processing is completed is sent to the processor. It is issued to 320-1 (step S508). Note that the block release notification Msg includes the ID information of the transfer module 230-1.

When the processor 320-1 executing the failure processing unit 335 receives the blockage release notification Msg in step S508, the processor 320-1 refers to the ID information included in the blockage release notification Msg and blocks the portion that has been blocked. After confirming that the cancellation processing has been completed, the processing of the failure processing unit 335 is completed. That is, the normal I / O processing can be resumed.

The above is the description of the failure block release processing example, but the processing inside the failure processing module 380-1 in the processing example of FIG. 19 will be described in detail with reference to FIGS.

FIG. 20 is a sequence diagram illustrating an example of the failure block release process in the failure processing module according to the embodiment of this invention. FIG. 20 shows a processing flow in the failure processing module 380-1 when the failure processing module 380-1 receives the WAKE signal from the transfer module 230-1.

The port control unit 383 receives a WAKE signal from the channel 400-1 via the connection port 385-1 (step S550).

In the port control unit 383, the WAKE signal detection unit 3830 detects the WAKE signal in step S550, and transmits the WAKE detection signal to the failure processing control unit 384 (step S551).

The failure processing control unit 384 detects the WAKE detection signal in step S551, refers to the I / F blockage state 3825 of the information storage unit 3820-1 of the information management unit 382, and confirms the blockage occurrence state (step S552). .

Since it is confirmed in step S552 that the blockage has occurred, the block state of the I / F blockage state 3825 in the information storage unit 3820-1 is cleared by the process of the reinitialization processing unit 3845 (step S553).

When the block status of the I / F block state 3825 is cleared in step S553, the port disable control unit 3832 of the port control unit 383 determines that the block state is released (step S554), and determines the target connection port 385-1. It is enabled and the closed state is released (step S555). The release of the port blockage can be realized by a power-on process of the PCIe port by the PCIe hot plug controller.

In the connection port 385-1 that has been released from the block in step S555, the interface with the transfer module 230-1 including the channel 400-1 connected to the connection port 385-1 is also released from the block (step S556). ) Since the I / O bus link establishment process between the transfer module 230-1 and the failure processing module 380-1 is performed, the I / O bus is restored to a communicable state.

Next, the reinitialization processing unit 3845 obtains the transfer module I / D information 3822 of the information storage unit 3820-1 of the information management unit 382 in order to reinitialize the transfer module 230-1 (step S557). Then, a CfgWr packet for writing ID information is generated and transmitted from the connection port 385-1 to the channel 400-1 via the access arbitration unit 381 (step S558).

The above is the explanation of FIG.

FIG. 21 is a sequence diagram illustrating an example of the failure block release process in the failure processing module 380-1 according to the embodiment of this invention. FIG. 21 shows a processing flow in the failure processing module 380-1 when the failure processing module 380-1 receives a Cpl packet for writing completion notification for initialization information writing from the transfer module 230-1. .

The access arbitration unit 381 receives a Cpl packet for writing completion notification for initialization information writing from the channel 400-1 via the connection port 385-1 (step S560).
In the access arbitration unit 381, the transfer determination unit 3810-1 refers to the I / F failure information 3824 and the I / F blockage state 3825 in the information storage unit 3820-1 of the information management unit 382, and detects the occurrence of the failure. Confirmation is made (step S561).

Since it is confirmed in step S561 that a failure has occurred, the Cpl packet in step S561 is sent to the opposite connection port 386-1 based on the transfer determination process (see table 3815 in FIG. 7) of the transfer determination unit 3810-1. It is determined not to transfer, and it is determined to transfer to the failure processing control unit 384 (step S562).

The access control unit 381 transfers the Cpl packet for writing completion notification to the failure processing control unit 384 based on the transfer permission / inhibition determination in step S562 (step S563).

In the failure processing control unit 384, the re-initialization processing unit 3845 processes the Cpl packet for writing completion notification transferred in step S563, and the initialization information for re-initialization of the transfer module 230-1 is processed. The writing process is completed (step S564).

The reinitialization processing unit 3845 clears all the fault information in the I / F fault information 3824 of the information storage unit 3820-1 of the information management unit 382, and completes reinitialization (step S565).

Thereafter, the ID information of the transfer module 230-1 is acquired from the transfer module ID information 3822 of the information storage unit 3820-1 by the blocking release notification Msg generation unit 3846 (step S566). Further, a blockage release notification Msg to which the acquired ID information is added is generated and transmitted from the connection port 386-1 to the root complex 340-1 via the access arbitration unit 381 (step S567).

The internal processing of the failure processing module 380-1 when receiving the Cpl packet for writing completion notification in step S505 in FIG. 19 is the same as the processing from step S560 to step S564 in FIG. Is omitted.

Further, since the internal processing of the failure processing module 380-1 in the case of transmitting the CfgWr packet for writing initialization information in step S506 in FIG. 19 is the same processing as that in steps S557 and S558, the description will be made. Omitted. However, the information acquired by the process corresponding to step S557 is not the ID information of step S557 but the information of the transfer module initialization information 3823 of the information storage unit 3820-1.

The above is an explanation of an example of the failure blocking process in this embodiment.

In this embodiment, the storage controller 331 is made redundant using two disk controllers 310, but the present invention is not limited to this. For example, two storage control units 331 may be realized by logically dividing one disk controller 310.

As described above, in the embodiment, the server module 200 and the storage module 300 transmit a command whose protocol is not converted to the transfer module 230, and the transfer module 230 converts the protocol. Therefore, there is an effect of reducing the overhead of data transfer due to protocol conversion.

In addition, since the transfer module 230 directly accesses the memory 220 of the server module 200 and the memory 330 of the storage module 300, the transfer module 230 can perform high-speed processing between the memories without going through the processor 210 of the server module 200 and the processor 320 of the storage module 300. Data transfer can be realized.

In the present invention, the fault processing module 380 is mounted on the storage module 300 in order to increase the fault tolerance of the computer system including the transfer module 230 described above.

When the failure processing module 380 is not installed, when a serious failure occurs in the I / O bus such as the transfer module 230 or the channel 400, the storage control unit 331 that detects the failure blocks the entire disk controller 310, Since all the server modules 200 using the disk controller 310 detect a failure of the storage module 300 and the disk controller 310 becomes a non-redundant configuration, the availability of the entire system is lowered.

On the other hand, when the failure processing module 380 is installed, if a serious failure occurs in the I / O bus such as the transfer module 230 or the channel 400, the failure processing module 380 detects the above-mentioned serious failure and separates it. By reporting the failure to the storage control unit 331, the storage control unit 331 is not blocked for the entire disk controller 310. Further, the failure processing module 380 requests blockage processing only for the failed link, and the storage control unit 331 requested to perform blockage blocks the connection port 385 connected to the failure link to the failure processing module 380. By instructing the processing, only the failed link can be blocked. Therefore, only the server module 200 related to the failure detects the failure of the storage module 300, and the deterioration of the availability of the entire system can be minimized.

As described above, the present invention can improve the fault tolerance of the system by the fault processing module 380 without impairing the merit of improving the I / O performance by the transfer module 230.

200 Server module 210 Processor 220 Memory 221 OS
222 storage access unit 223 application 230 transfer module 231 data transfer unit 232 DMA controller 233 data inspection unit 234 protocol engine 235 endpoint unit 236 connection port 237 connection port 238 power management unit 240 root complex 241 root port 260 I / F
300 Storage Module 310 Disk Controller 320 Processor 330 Memory 331 Storage Control Unit 332 I / O Processing Unit 333 Storage Device Control Unit 334 Initialization Processing Unit 335 Fault Processing Unit 340 Root Complex 341 Root Port 360 I / F
370 Storage Device 380 Failure Processing Module 381 Access Arbitration Unit 3810 Transfer Determination Unit 3811 Packet Arbitration Unit 3812 Packet Buffer 3813 Packet Buffer 3815 Transfer Determination Processing Table 3816 Packet Type 3817 Failure and Blocking State 3818 Transfer Enable / Disable 3819 Failure Processing Control 382 Information management unit 3820 Information storage unit 3821 Register 3822 Transfer module ID information 3823 Transfer module initialization information 3824 I / F failure information 3825 I / F block state 383 Port control unit 3830 WAKE signal detection unit 3831 Connection signal detection unit 3832 Port disable control unit 384 Fault processing control unit 3840 WAKE signal generation unit 3841 CfgWr processing unit 3842 SupplyDown detection Part 3843 failure notification Msg generator 3844 CfgRd processor 3845 reinitializing processor 3846 unblocking notification Msg generator 3847 ERR_FATAL processor 385 connection port 386 the connection ports 400 channel

Claims

A computer system comprising: a first server module including a first memory and a first processor; and a storage module connected to the server module via a network and including a second memory and a second processor. ,
The server module further includes a first transfer module that controls data transfer between the first memory and the second memory;
The storage module includes a first port connected to the first transfer module via the network, and a failure processing module that controls processing related to a failure of the computer system,
The failure processing module manages configuration information associating the first port with an identifier of the first transfer module, and receives a first failure message received via the first port as the configuration information. Based on the first transfer module, the second transfer message including the identifier of the first transfer module and notifying the failure of the first transfer module is converted to the second processor of the storage module. Send,
A computer system characterized by that.
The computer system according to claim 1,
A second server module comprising a third memory, a third processor, and a second transfer module for controlling data transfer between the third memory and the second memory;
The storage module further comprises a second port connected to the second transfer module via the network,
The failure processing module manages the second port and the identifier of the second transfer module in association with each other in the configuration information, and receives a third failure message received via the second port, Based on the configuration information, the second transfer module including the identifier of the second transfer module is converted into a fourth failure message notifying the failure of the second transfer module, and the fourth failure message is converted to the second of the storage module. Send to the processor,
A computer system characterized by that.
The computer system according to claim 1,
When the failure processing module receives an access request from the second processor to the first transfer module after transmitting the second failure message to the second processor of the storage module, the failure processing module Sending a response message to the access request to the second processor without sending it to the first transfer module;
A computer system characterized by that.
The computer system according to claim 3,
The failure processing module manages log information of the first transfer module, and the access request from the second processor to the first transfer module is a log information acquisition request related to the first transfer module. Sending the response message including the log information to the second processor;
A computer system characterized by that.
The computer system according to claim 3,
The failure processing module corresponds to the first transfer module based on the configuration information when the access request from the second processor to the first transfer module is a block request for the first transfer module. A first port to be identified, a process of closing the first port is performed, and the response message is transmitted to the second processor.
A computer system characterized by that.
The computer system according to claim 1,
A network connecting the storage module and the server module is a network based on PCIe (PCI Express).
A computer system characterized by that.
The computer system according to claim 1,
Upon receiving the first transfer module identifier notification message for the first server module from the storage module, the failure processing module transfers the message to the first server module and is included in the notification message. The computer system is characterized in that the configuration information is generated using an identifier of the first transfer module.
The computer system according to claim 1,
The storage module includes a plurality of storage devices, and the second processor configures at least one logical volume on the plurality of storage devices, and provides the logical volume to the first server module.
A computer system characterized by that.