JP2013513137A - Information processing apparatus and data transfer method - Google Patents

Abstract

An information processing apparatus and a data transfer method that improve the availability of a system while improving the reliability of a data transfer path.
Information having a data transfer path that branches from a root node to a plurality of nodes in a tree shape and is communicably connected therebetween, and serial data transmission is performed between the root node and the plurality of nodes. A processing device, provided between at least one set of nodes of the plurality of nodes, between two inter-node data transfer paths for performing serial data transmission, and at both ends of the inter-node data transfer path Each of the terminal nodes is provided to one of the nodes that is a transmission destination, and each of the terminal nodes is received from one of the other nodes that is a transmission destination via the other terminal node. When the transmitted data is transferred, the reply data from the transmission destination node to the transmission source node is used for data transfer to the transmission destination node. Wherein BACKGROUND OF and a routing processing unit that executes by using the inter-node data transfer path and same the internodal data transfer path 2

Description

  The present invention relates to an information processing apparatus and a data transfer method, and more particularly to a technique for improving the availability of a system while improving the reliability of a data transfer path.

  Storage devices that provide a large-scale data storage area using a magnetic recording medium such as a large number of hard disk drives (hereinafter referred to as “HDDs”) have become widely used. With the expansion of the data storage area, the capacity of individual file data to be stored is also increasing, and high-speed data transfer performance is also required for the data transfer path used for data I / O. ing.

  In such a storage apparatus, processing of data I / O between a host computer using the storage apparatus and a storage medium such as an HDD in the storage apparatus, that is, a data write request or a data read request from the host, A channel adapter (CHannel Adapter) that is controlled by a storage control device (hereinafter referred to as a disk controller (DK) as commonly used) and controls communication between the DKC and between the DKC and the DKC and the host. , CHA), or data transfer between DKC and a disk adapter (DisK Adapter, DKA) that controls communication between the DKC and a recording medium such as an HDD, for example, PCI (Peripheral Component Instead of the conventional parallel transfer method such as Interconnect) bus, for example, PCI Express ( Recorded trademark, serial transfer system represented by the following "PCIe") is adapted to is adopted. This is due to a technical problem such as difficulty in controlling the signal synchronization timing in the conventional parallel transfer system due to a request for high-speed data transfer.

  When adopting a data transfer path based on PCIe in the storage apparatus, it becomes a problem to ensure reliability and availability as the storage apparatus. For example, in Patent Document 1, in a PCIe communication system, an abnormality occurred in a root complex connected to a plurality of endpoints via a PCIe switch in a tree structure, and routing information was changed in the PCIe switch. Even in this case, a configuration is described in which a response can be returned to the data transmission source before the change.

JP 2007-316755 A

  As described above, the topology of the tree structure is adopted in PCIe, and a connection form on hardware in which a data transfer path (path) forms a loop between nodes is not allowed. This restriction is also clearly defined in PCI Express Base Specification Revision 2.0, which is a technical standard of PCIe established by PCI-SIG (registered trademark, The Peripheral Component Interconnect Special Interest Group) (for example, 1.3 PCI Express Fabric Topology). Please refer to.) This restriction in terms of topology also applies to Patent Document 1 described above. The contents of the above-mentioned document, PCI Express Base Specification Revision 2.0, are incorporated into the present specification as a reference (incorporated by reference).

  On the other hand, the storage control device adopts a configuration in which a path through which data transfer is performed is duplicated in hardware in order to achieve both reliability and availability of data transfer. Therefore, when applying PCIe to data transfer, for example, when setting a detour path that can be used when a failure occurs in any of the PCIe switches between PCIe switches included in different branches constituting the tree structure The data transfer path is required to be duplicated.

  However, with such a hardware configuration, a loop that is not permitted by the PCIe technical standard is configured between the two PCIe switches, so PCIe is directly adopted for such a hardware configuration. I can't do it.

  The present invention has been made in view of such a background, and a main object of the present invention is to provide an information processing apparatus and a data transfer method capable of improving the availability of the system while improving the reliability of the data transfer path. And

  In order to achieve the above object, one of the present invention has a data transfer path for branching from a root node to a plurality of nodes in a tree-like manner so as to be communicable between the root node, the plurality of nodes, An information processing apparatus for performing serial data transmission between the two nodes, the inter-node data transfer path for performing serial data transmission, provided between at least one set of the plurality of nodes. , Provided at each of the terminal nodes that are the nodes at both ends of the inter-node data transfer path, and each of the terminal nodes is transmitted to any of the nodes that are the destination nodes via the other terminal node When transferring data received from any of the other nodes that are nodes, return data from the transmission destination node to the transmission source node, An information processing apparatus and a routing processing unit that executes by using the inter-node data transfer path and said same node data transfer paths used for data transfer to Shinsaki node.

  Other problems and solutions to be disclosed by the present application will be made clear by the embodiments of the invention and the drawings.

  ADVANTAGE OF THE INVENTION According to this invention, the information processing apparatus which improves the availability as a system, improving the reliability of a data transfer path, and the data transfer method can be provided.

2 is a diagram showing a schematic configuration of a storage apparatus 10. FIG. 2 is an example of a hardware configuration of a storage control device 12. 2 is an example of a hardware configuration of a microprocessor 121; 3 is an example of a software configuration of a microprocessor 121. 3 is an example of a hardware configuration of a PCIe switch 126. 3 is an example of a software configuration of a PCIe switch 126. It is an example of the data structure of the transaction layer packet transferred by PCIe. It is a schematic diagram which shows the flow of the packet through the path | route which connects between PCIe switches. It is an example of the routing table 1216A stored in the PCIe switch A. It is an example of the routing table 1216B stored in the PCIe switch B. 12 is an example of an initial setting process flow of a routing table 1216. FIG. 7 is a schematic diagram illustrating a packet flow when devices D5 and D6 are not mounted in FIG. It is an example of the routing table 1216A stored in the PCIe switch A when the devices D5 and D6 are not mounted. It is an example of the routing table 1216B stored in the PCIe switch B when the devices D5 and D6 are not mounted. FIG. 7 is a schematic diagram illustrating a packet flow when a failure occurs in the device D3 in FIG. It is an example of a routing table 1216A stored in the PCIe switch A when a failure occurs in the device D3. It is an example of a routing table 1216B stored in the PCIe switch B when a failure occurs in the device D3. It is an example of the port blockage processing flow in the case of a device failure. FIG. 10 is a schematic diagram showing a packet flow when the device D5 is added in FIG. It is an example of the routing table 1216A stored in the PCIe switch A when the device D5 is added. It is an example of the routing table 1216B stored in the PCIe switch B when the device D5 is added. It is an example of a device addition correspondence processing flow. FIG. 7 is a schematic diagram illustrating a packet flow when a failure occurs in a path connecting the fifth port of the PCIe switch in FIG. 6. It is an example of a routing table 1216A stored in the PCIe switch A when a failure occurs in the path connecting the No. 5 port of the PCIe switch. It is an example of a routing table 1216B stored in the PCIe switch B when a failure occurs in the path connecting the No. 5 port of the PCIe switch. It is an example of the failure path alternative processing flow between PCIe switches. It is explanatory drawing regarding the response process at the time of the path | pass failure between PCIe switches, and has shown the read operation in a normal state. It is explanatory drawing regarding the response process at the time of the path | pass failure between PCIe switches, and has shown the read operation at the time of the conventional failure occurrence. It is explanatory drawing regarding the response process at the time of the path | pass failure between PCIe switches, and has shown the read operation at the time of the failure generation in a present Example. 20D is a transaction layer packet data structure example in the response process of FIG. 20C. It is an example of the port failure detection processing flow of a PCIe switch. It is an example of a routing table 1216A stored in the PCIe switch A having an alternative port number. It is an example of a routing table 1216B stored in the PCIe switch B having an alternative port number. It is an example of the fault path | route alternative processing flow between PCIe switches using an alternative port number.

Configuration of Storage Device 10 Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 shows a schematic configuration of a storage apparatus 10 described as an embodiment. As shown in the figure, one or more server apparatuses 20 are connected to the storage apparatus 10 via a communication network 30. Although one storage apparatus 10 is shown in the example of FIG. 1, one or more other storage apparatuses 10 may be connected to the communication network 30.

  The communication network 30 is a LAN (Local Area Network), a WAN (Wide Area Network), a SAN (Storage Area Network), the Internet, a public communication network, a dedicated line, or the like. Communication performed via the communication network 30 is, for example, TCP / IP, iSCSI (Internet Small Computer System Interface), Fiber Channel Protocol, FICON (Fibre Connection) (registered trademark), ESCON (Enterprise System Connection). ) (Registered trademark), ACONARC (Advanced Connection Architecture) (registered trademark), FIBARC (Fibre Connection Architecture) (registered trademark), and the like.

  The server apparatus 20 is an information processing apparatus (computer) that uses a storage area (data storage area) provided by the storage apparatus 10. The server device 20 is configured using a personal computer, a mainframe, an office computer, or the like. When accessing the storage area, the server device 20 transmits a data frame (hereinafter abbreviated as a frame) including a data I / O request (data write request, data read request, etc.) to the storage device 10.

  The storage device 10 is, for example, a disk array device. The storage device 10 accesses the recording medium in response to the I / O request sent from the server device 20 and sends data and a response to the server device 20. The storage apparatus 10 includes one or more channel adapters (CHAnel) (hereinafter referred to as “CHA”) 11, a disk controller (DisK Controller, hereinafter referred to as “DKC”) 12, and one or more disk adapters (DisK Adapter, hereinafter referred to as “DKA”). ) 13, a storage device 14, and a service processor (SerVice Processor, hereinafter referred to as “SVP”) 15.

  The CHA 11 receives a frame sent from the server device 20 and includes a processing response to the data I / O request included in the received frame (for example, read data, read completion report, write completion report). The frame is transmitted to the server device 20. In the following description, it is assumed that the frame is a fiber channel frame (FC frame (FC)). The CHA 11 has an external communication interface (hereinafter referred to as “external communication I / F”) having a port (communication port) for communicating with the server device 20, an internal port having a port (communication port) for communicating with a processor, a local memory, and the like. A communication interface (hereinafter referred to as “internal communication I / F”) is provided.

  The external communication I / F is configured using a NIC (Network Interface Card), an HBA (Host Bus Adapter), or the like. The processor is configured using a CPU (Central Processing Unit), an MPU (Micro Processing Unit), and the like. The local memory is a RAM (Random Access Memory) or a ROM (Read Only Memory). A microprogram is stored in the local memory. Various functions provided by the CHA 11 are realized by the processor reading and executing the microprogram from the local memory. The internal communication I / F communicates with the DKC 12 and the DKA 13 via the internal communication path. In this embodiment, PCIe is used as the internal communication I / F.

  The DKC 12 performs processing related to data transfer performed between the CHA 11 and the DKA 13 in response to the data I / O request included in the frame received by the CHA 11. As will be described later, a microprocessor (MicroProcessor, hereinafter referred to as “MP”) provided in the DKC 12 delivers data (data read from the storage device 14 and data written to the storage device 14) between the CHA 11 and the DKA 13. Then, staging (reading data from the storage device 14) or destaging (writing to the storage device 14) of data stored in the cache memory in the DKC 12 is performed.

  The DKA 13 communicates with the storage device 14 when reading data from the storage device 14 or writing data to the storage device 14. The DKA 13 includes an internal communication I / F, a processor, a local memory, and a drive interface (hereinafter “drive I / F”). A microprogram is stored in the local memory. Various functions provided by the DKA 13 are realized by the processor reading and executing the microprogram from the local memory. The internal communication I / F communicates with the CHA 11 and DKC 12 via the internal communication path. The processor is configured using a CPU, MPU, or the like. The local memory is, for example, a RAM or a ROM. The drive I / F communicates with the storage device 14.

  The storage device 14 includes a plurality of storage drives 141. The storage drive 141 is, for example, a SAS (Serial Attached SCSI), SATA (Serial ATA), FC (Fibre Channel), PATA (Parallel ATA), SCSI, or other type of HDD, or a semiconductor storage device (Solid State Drive), hereinafter referred to as “SSD”. ]).

  The storage device 14 provides a storage area in units of logical storage areas provided by controlling the storage drive 141 by a method such as RAID (Redundant Arrays of Inexpensive (or Independent) Disks). This logical storage area is, for example, a logical device (LDEV 142 (LDEV: Logical DEVice)) configured using a RAID group (parity group). Further, the storage apparatus 10 provides a logical storage area (hereinafter referred to as LU (Logical Unit, Logical Volume)) configured using the LDEV 142 to the server apparatus 20. The storage apparatus 10 manages the correspondence (relationship) between the LU and the LDEV 142, and the storage apparatus 10 identifies the LDEV 142 corresponding to the LU or the LU corresponding to the LDEV 142 based on this correspondence.

  The SVP 15 controls each component of the storage apparatus 10 and monitors the state. The SVP 15 is a personal computer, an office computer, or the like. The SVP 15 communicates with the components of the storage apparatus 10 such as the CHA 11, DKC 12, and DKA 13 through communication means such as an internal communication path or LAN, and obtains operation information from each component and provides it to the management apparatus 40. To do. The SVP 15 performs setting, control, and maintenance (including software installation and update) of each component based on control information and operation information sent from the management device 40.

  The management device 40 is a computer that is communicably connected to the SVP 15 via a LAN or the like. The management device 40 includes a user interface using a GUI (Graphical User Interface), a CLI (Command Line Interface), or the like for controlling and monitoring the storage device 10.

Configuration of Disk Control Unit (DKC) 12 Next, the hardware configuration of the DKC 12 in this embodiment will be described with reference to FIG. FIG. 2 is a diagram illustrating an example of the hardware configuration of the DKC 12. The DKC 12 includes an MP (microprocessor) 121, an MCH (Memory Controller Hub) 122, an MPA (MicroProcessor Adapter) 124, and PCIe switches 126A and 126B. The MP 121, the MCH 122, the MPA 124, and the PCIe switches (terminal nodes) 126A and 126B are communicably connected by a tree-shaped data transfer path adopting the PCIe protocol. Therefore, in the DKC 12, the MP 121 is positioned as a root node (root complex), the MCH 122, the MPA 124, and the PCIe switches 126A and 126B as nodes.

  FIG. 3A shows an example of the configuration of the MP 121. The MP 121 includes a processor 1212 configured using a CPU, MPU, DMA (Direct Memory Access), etc., and as described above, data between the server device 20 and the storage device 14 via the CHA 11 and the DKA 13. The main functions of the DKC 12 such as controlling transfer are realized. Such a function is performed by reading and executing a microprogram stored in advance in a local memory 1213 provided in each MP 121. The internal communication I / F 1211 communicates with the CHA 11, the DKA 13, and the memory 123 via an internal communication path.

  FIG. 3B shows an example of the configuration of software that operates on the MP 121. A microprogram executed by the processor 1212 to realize the functions of the data control unit 1214 and the routing information management unit 1215 and PCIe switches 126A and 126B described later are transferred to the local memory 1213 of the MP 121 by PCIe protocol communication. A routing table 1216 in which a path that is a transfer route of the data packet to be set is set is stored. The data control unit 1214 has a function of controlling overall data processing performed in the DKC 12. The routing information management unit 1215 updates information recorded in a routing table 1216 described later at a predetermined timing, and transfers the information to the PCIe switches 126A and 126B described later. The routing table 1216 is stored in advance in the local memory 1213 of the MP 121 in accordance with the configuration of the storage apparatus 10, and is transferred to each of the PCIe switches 126A and 126B when the storage apparatus 10 is initially turned on, and used for data packet transfer control there. Is done.

  In the example of FIG. 2, four MPs 121 are provided in the DKC 12, but the number of MPs 121 may be other than this.

  The MCH 122 includes a bridge circuit that controls communication between the MP 121 and the memory 123 or another peripheral device such as the MPA 124. In the present embodiment, the MCH 122 includes four PCIe protocol communication ports 122-1 to 122-4, and performs communication with the MPA 124.

  The memory 123 is composed of a RAM or a ROM, for example, a control memory for storing a program for controlling data processing of the entire DKC 12, data read from the storage device 14, or data to be written to the storage device 14. Used as a shared memory that provides a storage area for temporary storage.

  The MPA 124 has a function of relaying data transfer between the MP 121 and the PCIe switches 126A and 126B. In the example of FIG. 2, the MPA 124 can communicate with the communication ports 122-1 to 122-4 of the MCH 122 by the PCIe protocol. Communicates with the four connected communication ports 124-1 to 124-4, the communication ports 126 A- 1 and 126 A- 2 of the PCIe switch 126 A, and the communication ports 126 B- 1 and 126 B- 2 of the PCIe switch 126 B using the PCIe protocol. It has four communication ports 124-5 to 124-8 that are connected to each other. Data I / O to the storage device 14 is transferred through these communication ports 124-1 to 124-8.

  On the other hand, the MPA 124 is communicably connected to each of the PCIe switches 126A and 126B through the sideband communication path 125. The sideband communication path 125 is used for transferring control data in the DKC 12 other than the data I / O. The sideband communication path 125 can be configured as an appropriate serial communication path, for example, and is used as a data transfer path when receiving and storing data of the routing table 1216 from the MP 121 in this embodiment.

  The communication ports 126A-3 to 126A-N of the PCIe switch 126A are communicably connected to any one of the devices 1 to m (130) by the PCIe protocol. Similarly, the communication ports 126B-3 to 126B-N of the PCIe switch 126B are communicably connected to any one of the devices m + 1 to n by the PCIe protocol.

  The devices 1 to n are nodes like the PCIe switches 126A and 126B, and correspond to either CHA11 or DKA13 included in the DKC 12, and specifically, communication of the PCIe protocol provided in the CHA11 and DKA13. PCIe transmit / receive chip at the port.

  Further, a PCIe protocol communication path is used between the PCIe switch 126A and the PCIe switch 126B in order to enable data transfer between the device groups of the devices 1 to m and the device groups of the devices m + 1 to n. A certain inter-switch path 127 (inter-node data transfer path) is provided. As described above, in the storage apparatus 10, it is not allowed to hinder the operation only by the failure of one communication path (path). Therefore, as shown in FIG. It is considered a heavy system. However, as described above, such a duplex path cannot be set in the communication path of the PCIe protocol that originally allows only the tree structure. Therefore, this embodiment proposes a configuration that enables the setting of such a duplex switch path 127.

Configuration of PCIe Switch 126 Next, the PCIe switch 126 will be described. An example of the hardware configuration of the PCIe switch 126 is shown in FIG. 4A, and an example of the software configuration is shown in FIG. 4B. The PCIe switch 126 mainly includes a CPU 1261, a memory 1262, and a PHY 1263, and is generally supplied as one ASIC (Application Specific Integrated Circuit) chip. The CPU 1261, the memory 1262, and the PHY 1263 are communicably connected to each other via an internal communication path.

  For example, a memory 1262 configured as a non-volatile memory such as a flash memory stores microprograms for realizing the main functions of the PCIe switch 126 such as PCIe data packet transfer control. Read and execute the microprogram. The PHY 1263 is a circuit block including a PCIe transmission / reception circuit including a serial-parallel conversion circuit for serial data transferred as a data packet by the PCIe protocol and parallel data processed in the PCIe switch 126.

  As shown in FIG. 4B, the PCIe switch 126 is provided with a routing processing unit 1264 as software for realizing the function. The routing processing unit 1264 has a routing control function for determining the transfer route of each data packet of the PCIe protocol in the data transfer control executed in the PCIe switch 126, and the CPU 1261 reads out and executes the corresponding program from the memory 1262. It is realized by doing.

  Similarly, the routing table 1216 is stored in the memory 1262, and is a data table that the routing processing unit 1264 refers to when executing the routing control of this embodiment. As described above, the routing table 1216 is initially generated by the MP 121, transferred from the MCH 122 and MPA 124 to the respective PCIe switches 126 A and 126 B via the sideband communication path 125, and stored in the memory 1262. A specific configuration example of the routing table 1216 will be described later.

Configuration of Data Packet FIG. 5 shows an example of a data structure of a transaction layer packet (hereinafter referred to as “TLP”) that is a data packet used in the PCIe protocol. The TLP includes a header section 301 and a data section 302 as shown in the figure. The header section 301 includes, for example, transaction type, bus number, device number, function number, tag number, and destination address data, and the data section 302 includes actual data as a payload transferred by TLP.

  In this embodiment, in the header portion 301 of the TLP, the transmission source address 303 is recorded in the block of the bus number and the device number, and the transmission destination address 304 is recorded in a part of the original transmission destination address. The TLP is generated in the PHY 1263 of each PCIe switch 126, and the transmission source address 303 and the transmission destination address 304 are recorded. In the data portion 302, message data specific to this embodiment, which will be described later, may be recorded.

Next, routing control related to the inter-switch path 127 between the PCIe switches 126A and 126B in the present embodiment will be described. FIG. 6 is a schematic diagram showing a TLP transfer flow through the inter-switch path 127 between the PCIe switches 126A and 126B. Hereinafter, the PCIe switches 126A and 126B are simply referred to as the PCIe switch 126 when referred to as a single PCIe switch without distinguishing from each other. The same applies to the routing tables 1216A and 1216B described later.

  In the example of FIG. 6, each of the PCIe switches 126 </ b> A and 126 </ b> B includes communication ports 0 to 5. The number as the identification ID attached to the communication port may be another identification code. In the PCIe switch 126A, the communication ports 0 to 5 are connected to the communication port R1, the devices D1 to D3, and the two inter-switch paths 127 of the MPA 124, respectively. In the PCIe switch 126B, the communication ports 0 to 5 are connected to the communication port R2, the devices D4 to D6, and the two inter-switch paths 127 of the MPA 124, respectively.

  In FIG. 6, broken lines with arrows at both ends indicate TLP transfer paths via the PCIe switches 126A and 126B. In the example of FIG. 6, the TLP received from the device D1 (130) at the communication port 1 of the PCIe switch 126A is received from the communication port 4 through the inter-switch path 127 at the communication port 4 of the PCIe switch 126B. It is transmitted to the device D5. Since the PCIe standard is based on the tree structure topology as described above, the completion notification for the TLP transmitted from the device D1 to the device 5 through the communication port 4 of the PCIe switch 126A is similarly the communication port of the PCIe switch 126B. 4 needs to be returned to the device D1. In other words, a TLP transmitted from one device to another device through the PCIe switch 126A and the PCIe switch 126B and a completion notification for the TLP must be transferred through the same inter-switch path 127 in both round trips. Note that the completion notification will be described later with reference to FIG. 20A.

Configuration of Routing Table 1216 Next, the configuration of the routing table 1216 set to realize the packet transfer control illustrated in FIG. 6 will be described. 7A and 7B show setting examples of routing tables 1216A and 1216B stored in the PCIe switch 126A and the PCIe switch 126B, respectively. As described above, the routing table 1216 is generated by the MP 121, transferred to the PCIe switches 126A and 126B, and stored in the memory 1262.

  In the routing table 1216, entries A1, B1, transmission source IDs A2, B2, transmission destination IDs A3, B3, port numbers A4, B4, and enable flags A5, B5 are recorded. The entries A1 and B1 are IDs for identifying the data entries recorded in each routing table 1216 from each other. The transmission source IDs A2 and B2 are IDs (D1 in the example of FIG. 6) for mutually identifying devices that are TLP transmission sources. The transmission destination IDs A3 and B3 are IDs (D5 in the example of FIG. 6) for mutually identifying devices that are transmission destinations of the TLP. Port numbers A4 and B4 (inter-node data transfer path information) are IDs for identifying the communication ports to which TLPs are transmitted in each PCIe switch 126 (4 in the example of FIG. 6). The enable flags A5 and B5 are flags indicating whether or not the TLP transfer path specified in each entry A1 and B1 is usable. In the corresponding entries A1 and B1, 1 is recorded in the enable flags A5 and B5, respectively, if the TLP transfer path is usable and 0 if not usable.

  Now, referring to FIG. 7A, for the PCIe switch 126A, the port number A4 is 4 and the enable flag A5 is 1 in the entry A1 “12” in which the transmission source IDA2 is “D1” and the transmission destination IDA3 is “D5”. . This is because when the TLP is transferred from the device D1 to the device D5, the inter-switch path 127 to which 4 is assigned as the port number A4 is set to be used, and the path is usable. I mean.

  Similarly, referring to FIG. 7B, for the PCIe switch 126B, in the entry B1 “25” in which the transmission source IDB2 is “D5” and the transmission destination IDB3 is “D1”, the port number B4 is 4 and the enable flag B5 is 1. is there. This is because when the TLP is transferred from the device D5 to the device D1, the inter-switch path 127 to which 4 is assigned as the port number A4 is set to be used, and the path is usable. I mean.

  The routing processing unit 1264 of the PCIe switches 126A and 126B refers to the routing table 1216 stored in the memory 1262 and executes TLP transfer from the device D1 to the device D5 and returns a completion notification in response thereto, respectively. can do.

Initial Setting Processing of Routing Table 1216 Next, the initial setting processing of the routing table 1216 of FIGS. 7A and 7B described above will be described. FIG. 8 shows an example of an initial setting process flow of the routing table 1216. This initial setting process is executed by the routing information management unit 1215 of the MP 121 when the power of the storage apparatus 10 is turned on and power is supplied to the DKC 12. Hereinafter, when the MP 121 is described as an operation subject, it means that the MP 121 executes a program corresponding to the function of the routing information management unit 1215. Further, in FIG. 8 and other figures described later, “S” attached to a reference numeral indicating each processing step means a step.

  First, the MP 121 acquires the configuration information collected by the SVP 15 regarding the storage device 10 from the SVP 15 after the DKC 12 is turned on, and uses the information stored in the routing table 1216 held in its own local memory as necessary. (S601). The configuration information related to the storage device 10 may be manually input to the SVP 15 by the administrator or the like from the management device 40.

  For example, when the MP 121 detects that the device D6 in FIG. 6 is removed from the configuration information of the storage apparatus 10 newly acquired from the SVP 15, the MP 121 has a routing table 1216 held in its local memory. , The enable flags A5 and B5 associated with the device 6 are changed from 1 to 0. As a result, it is set on the routing table 1216 that the transfer path including the device D6 cannot be used.

  Next, the MP 121 reads the updated information in the routing table 1216 from the local memory 1213 (S602), and transfers it to the MPA 124 via the MCH 122 (S603). The MPA 124 transmits the received information of the routing table 1216 to the PCIe switches 126A and 126B through the sideband communication path 125 (S604). The PCIe switches 126A and 126B store the received information of the routing table 1216 in the respective memories 1262 (S605).

  According to the above processing, the information in the routing table 1216 stored in each PCIe switch 126 can be updated to the latest state every time the storage apparatus 10 is powered on. Can reliably transfer the TLP using the always available path.

Next, a case where the devices D5 and D6 are not mounted in the storage apparatus 10 in the configuration illustrated in FIG. 6 will be described. FIG. 9 is a schematic diagram illustrating a packet flow when the devices D5 and D6 are not mounted in FIG. 10A and 10B show routing tables 1216A and 1216B used by the PCIe switches 126A and 126B, respectively, corresponding to FIG.

  In this case, it is clear that none of the PCIe switches 126A and 126B can use the path including the devices D5 and D6 as a transmission source or transmission destination device. Therefore, in FIG. 10A and FIG. As shown, the enable flags A5 and B5 associated with the entries A1 and B1 including “D5” or “D6” in the transmission source IDs A2 and B2 and the transmission destination IDs A3 and B3 are set to 0. Yes. Such a state occurs, for example, when the storage apparatus 10 is powered on in a state where the storage devices corresponding to the devices D5 and D6 are not connected.

Processing when a failure has occurred in some devices Next, a case where a failure has occurred in the device D3 in the configuration illustrated in FIG. 6 will be described. FIG. 11 is a schematic diagram illustrating a packet flow when a failure occurs in the device D3 in FIG. Each of the PCIe switches 126A and 126B has a function of constantly monitoring the state of each communication port 126-n by its own CPU 1261 as its general function. It is possible to cope with it. 12A and 12B show routing tables 1216A and 1216B used by the PCIe switches 126A and 126B, respectively, corresponding to FIG.

  In this case, it is clear that none of the PCIe switches 126A and 126B can use a path including the device D3 as a transmission source or transmission destination device. Therefore, in FIG. 12A and FIG. As shown, the enable flags A5 and B5 associated with the entries A1 and B1 including “D3” in the transmission source IDs A2 and B2 and the transmission destination IDs A3 and B3 are set to 0.

Communication Port Blocking Process Corresponding to Device Failure The communication port blocking process executed by the PCIe switch 126 when the above-described device failure occurs will be described. FIG. 13 shows an example of a communication port blocking process flow. The communication port blocking process is executed by the routing processing unit 1264 of the PCIe switch 126. In the example of FIG. 13, it is assumed that the routing processing unit 1264 monitors the status of each device connected through each communication port, but a configuration in which a monitoring unit is provided separately may be employed.

  First, the routing processing unit 1264 always determines whether there is an abnormality in the state of the device D connected to the PCIe switch 126 to which the routing processing unit 1264 belongs, for example, by monitoring data I / O with the device D (S1101). S1102), when a failure is detected in a certain device (S1102, Yes), the communication port 126-n (communication port 3 in the device D3 in FIG. 11) connected to the device D that has detected the failure is blocked. In addition, the enable flags A5 and B5 associated with the port numbers A4 and B4 of the communication port 126-n to be blocked in the routing table 1216 are set to 0. Then, the routing processing unit 1264 notifies the MP 121 through the sideband communication path 125, the MPA 124, and the MCH 122 that a failure has occurred in the device D and the corresponding communication port 126-n has been blocked (S1104). Upon receiving the notification, the MP 121 can transmit information etc. requesting the management apparatus 40 to cope with the failure through the SVP 15.

  According to the processing described above, the PCIe switch 126 detects a device failure and closes the corresponding communication port 126-n, thereby making it impossible to reliably use the data transfer path including the failed device. It is possible to provide information that prompts a person etc. to cope with a device failure.

Processing when Device is Added Next, a case where the device D5 is added in the configuration in which the devices D5 and D6 illustrated in FIG. 9 are not mounted will be described. FIG. 14 is a schematic diagram showing a packet flow when the device D5 is added in FIG. 15A and 15B show routing tables 1216A and 1216B used by the PCIe switches 126A and 126B, respectively, corresponding to FIG.

  In this case, any of the PCIe switches 126A and 126B can use the path including the device D5 as a transmission source or transmission destination device, while the path including the device D6 still cannot be used. 15A and 15B, for the entries A1 and B1 including the device D5 as a transmission source or transmission destination device, the corresponding enable flags A5 and B5 are changed from 0 to 1. In addition, as indicated by being surrounded by broken lines, the enable flags A5 and B5 associated with the entries A1 and B1 including “D6” in the transmission source IDs A2 and B2 and the transmission destination IDs A3 and B3 are still 0. Is set.

Device Expansion Support Processing The device expansion support processing executed by the PCIe switch 126 at the time of device expansion described above will be described. FIG. 16 shows an example of a device addition support processing flow. The device expansion support processing is performed by the MP 121 executing a corresponding microprogram stored in the local memory.

  First, after the device is added, the MP 121 first relates to the storage device 10 from the SVP 15 when the storage device 10 is first turned on or when the management device 40 receives an instruction to execute the device addition corresponding process through the SVP 15. The configuration information collected by the SVP 15 is acquired (S1401).

  Next, with respect to the information stored in the routing table 1216 held in its own local memory, the MP 121 includes an entry A1 including a device (device D5 in the example of FIG. 14) added as a transmission source or transmission destination device. , B1 enable flags A5 and B5 are changed from 0 to 1 (S1402). The configuration information related to the storage device 10 may be manually input to the SVP 15 by the administrator or the like from the management device 40.

  Next, the MP 121 reads the updated information in the routing table 1216 from the local memory, and transfers it to the MPA 124 via the MCH 122 (S1403). The MPA 124 transmits the received information of the routing table 1216 to the PCIe switches 126A and 126B through the sideband communication path 125 (S1404). The PCIe switches 126A and 126B store the received information of the routing table 1216 in the respective memories 1262 (S1405).

  According to the processing described above, even when a device serving as a transmission source or a transmission destination of a data packet is added, the PCIe switch 126 can automatically use a data transfer path including the added device thereafter. become able to.

Processing when a failure occurs in the inter-switch path 127 Next, in the configuration illustrated in FIG. 6, the PCIe switches 126A and 126B out of the two inter-switch paths 127 connecting the PCIe switches 126A and 126B. A case where a failure has occurred in the path 127 that connects the communication ports 5 to each other will be described. FIG. 17 is a schematic diagram showing a packet flow when a failure occurs in the inter-switch path 127 using the communication port 5 of the PCIe switch 126 in FIG. 18A and 18B show routing tables 1216A and 1216B used by the PCIe switches 126A and 126B, respectively, corresponding to FIG.

  In this case, none of the PCIe switches 126A and 126B can use the path including the communication port 5 when transferring the data packet to the other PCIe switches 126A and 126B. Accordingly, in FIGS. 18A and 18B, the entries A1 and B1 including “5” as the port numbers A4 and B4 of the transmission source devices A2 and B2 or the transmission destination devices A3 and B3 are surrounded by broken lines. , They are changed to “4”. In FIG. 18A and FIG. 18B, the corresponding portions are described as “5 → 4” for easy understanding. However, if “4” indicating the used communication port after the change is actually recorded, It ’s enough.

Fault path substitution process using MP 121 The fault path substitution process executed by the MP 121 when a fault occurs in the inter-switch path 127 described above will be described. FIG. 19 shows an example of the fault path replacement processing flow. The fault path replacement process is performed by the MP 121 cooperating with the process executed by the corresponding microprogram stored in the local memory and the process by the routing processing unit 1264 of the PCIe switch 126.

  First, the routing processing unit 1264 of the PCIe switch 126 continues monitoring whether a failure has occurred in the communication ports (communication ports 4 and 5 in the example of FIG. 6) included in the inter-switch path 127 while the storage apparatus 10 is operating. If it is detected that a failure has occurred in any one of the communication ports (S1701, Yes), the MP 121 is notified that a failure has occurred in the communication port included in the inter-switch path 127 (S1702). ).

  Receiving the notification, the MP 121 generates a failure with respect to the information stored in the routing table 1216 held in its own local memory as the port numbers A4 and B4 of the transmission source devices A2 and B2 or the transmission destination devices A3 and B3. , For the entries A1 and B1 including the communication port (communication port “5” in the example of FIG. 17), the other normal communication port number (communication port “4” in the example of FIG. 17). Change (S1703).

  Next, the MP 121 reads the updated information of the routing table 1216 from the local memory, and transfers it to the MPA 124 via the MCH 122 (S1704). The MPA 124 transmits the received information of the routing table 1216 to the PCIe switches 126A and 126B through the sideband communication path 125 (S1705). The PCIe switches 126A and 126B store the received information of the routing table 1216 in the respective memories 1262 (S1706).

  According to the processing described above, even when a failure occurs in any of the inter-switch paths 127, the data packet transfer between the PCIe switches 126 can be continued. Can be improved.

Next, a response process executed in the PCIe switch 126 when a failure occurs in the inter-switch path 127 described above will be described. 20A to 20C are schematic diagrams illustrating response processing in the PCIe switch 126 of the present embodiment, taking as an example a case where a read request is transmitted from a certain device X to another device Y to the other device via the PCIe switch. is there.

  When the data transfer path from the device X to the device Y via the PCIe switch 126 is normal, the read request transmitted from the device X is transferred by the PCIe switch and received by the device Y as shown in FIG. . The device Y that has received the read request reads out the data related to the request, transmits it to the PCIe switch together with the completion notification, and is transferred to the device X by the PCIe switch. Through this series of data transfer processing, the device X can confirm that the read request transmitted by itself has been processed normally.

  FIG. 20B exemplifies a response process that is conventionally executed when a failure occurs in the PCIe switch in the process of FIG. 20A and the PCIe switch cannot transfer the read request to the device Y that is the transmission destination of the read request. Yes. In this case, since the PCIe switch cannot receive the completion notification from the device Y even though it tries to transfer the read request to the device Y, the PCIe switch waits for reception of the completion notification for a certain period of time. Thereafter, it is determined that a timeout error has occurred, and a completion notification including a message to that effect is transmitted to the device X. Therefore, the device X can confirm the read request transmission result only after the timeout error processing in the PCIe switch, and there is a possibility that the data processing efficiency is lowered.

  FIG. 20C illustrates the response process at the PCIe switch in the present embodiment. As described with reference to FIG. 19, in the case of the present embodiment, the PCIe switch 126 can detect that a failure has occurred in the communication port by the function of its own routing processing unit 1264. Therefore, as schematically illustrated, the PCIe switch determines that the read request from the device X is to be transmitted to the destination device Y through the failed data transfer path. In this case, without sending a read request from the device X to the device Y, a completion notification including information indicating that a transmission error has occurred in the device X can be returned immediately. For this reason, the device X can proceed without waiting for timeout error information from the PCIe switch as in the prior art, and can prevent a decrease in data processing efficiency.

Example of Data Configuration Used for Response Processing FIG. 21 shows a configuration example of completion notification data that the PCIe switch transmits to the device X that is the source of the read request in the response processing executed when the path failure occurs illustrated in FIG. Yes. The completion notification includes information indicating that it is a completion notification, a transmission source ID, and a transmission destination ID in the header portion, as in the normal completion notification, while the data portion includes Information indicating that a data transfer path has failed and cannot be transferred, for example, an error code, a communication port ID in which a failure has occurred, a physical layer error counter value described later, and the like can be stored. This eliminates the need for the MP121 microprogram or the like to separately perform error information processing. The data structure example of the read request shown in FIG. 21 is the same as the conventional one, and the transaction type may be a write request other than the read request.

Communication Port Failure Detection Processing Next, the communication port failure detection step (S1701) executed in the failure path replacement processing of FIG. 19 will be described in more detail with reference to this embodiment. FIG. 22 shows an example of a port failure detection processing flow executed by the routing processing unit 1264 of the PCIe switch 126 in this embodiment.

  While the storage apparatus 10 is in operation, the routing processing unit 1264 continuously monitors whether the PHY 1263 constituting each communication port 126-n is operating normally (S2001, No), and any PHY 1263 fails. When it is determined that a failure has occurred in the physical layer of the data transfer path including the communication port 126-n that the PHY 1263 configures (S2001, Yes), the physical layer failure held in the routing processing unit 1264 The detection counter is incremented (S2002).

  Next, the routing processing unit 1264 determines whether the counter value of the physical layer failure determination counter exceeds the threshold value set in the routing processing unit 1264 in advance for failure determination (S2003), and determines that it has not exceeded. In the case (S2003, No), the processing is returned to S2001 and the physical layer monitoring of each communication port 126-n is continued.

  When the routing processing unit 1264 determines that the counter value exceeds the threshold value (S2003, Yes), the routing processing unit 1264 determines the detected counter value and the ID of the communication port 126-n where the failure has occurred (for example, The physical layer failure information of the communication port 126-n including the port numbers “4” and “5” in FIG. 6) is transferred to the MP 121 (S2004). The MP 121 can update the routing table 1216 held by the MP 121 based on the received physical layer failure information.

Failure Path Replacement Processing at PCIe Switch 126 Next, a configuration for autonomously executing failure path replacement processing at the PCIe switch 126 without intervention of processing by the MP 121 will be described. FIG. 23A and FIG. 23B show setting examples of the routing table 1216 used when executing the fault path replacement process by the PCIe switch 126. These routing tables 1216A and 1216B differ from the routing table 1216 of this embodiment illustrated in FIGS. 7A and 7B in that the items of alternative port numbers A41 and B41 are added.

  The PCIe switch 126 executes data transfer processing between devices by using the communication port 126-n recorded in the items of the port numbers A4 and B4 when normal. When the routing processing unit 1264 detects that a failure has occurred in the communication port 126-n used in the normal state, the alternative port number recorded in association with the communication port 126-n in which the failure has occurred. Data transfer processing is performed using another communication port 126-n specified by A41 and B41. In the example of FIGS. 23A and 23B, in accordance with the configuration illustrated in FIG. 6, the communication ports 126-n whose port numbers A4 and B4 are “4” and “5” are respectively designated as alternative port numbers A41 and B41. , “5”, “4” are set.

  Next, a failure path replacement process flow in the PCIe switch 126 using the routing tables 1216A and 1216B in FIGS. 23A and 23B in which the alternative port numbers A41 and B41 are set will be described. FIG. 24 shows an example of a fault path replacement process flow in the PCIe switch 126.

  First, the routing processing unit 1264 of the PCIe switch 126 continues monitoring whether a failure has occurred in the communication ports (communication ports 4 and 5 in the example of FIG. 6) included in the inter-switch path 127 while the storage apparatus 10 is operating. However, if it is detected that a failure has occurred in one of the communication ports (S2201, Yes), the substitute port numbers A41 and B41 are recorded with reference to the routing table 1216 held by itself. It is determined whether it is present (S2202).

  If it is determined that it is recorded (S2202, Yes), the routing processing unit 1264 executes data transfer processing for the failed communication port 126-n using the alternative port numbers A41 and B41 that are set thereafter. (S2203). When it is determined that the alternative port numbers A41 and B41 are not recorded (S2202, No), the routing processing unit 1264 records the port number corresponding to the communication port 126-n in which the failure occurrence is detected in the routing table 1216. Enable flags A5 and B5 are changed to 0 (S2204), and data transfer processing using the communication port 126-n is not performed thereafter.

  According to the processing described above, even when a failure occurs in any of the inter-switch paths 127, the PCIe switch 126 can switch to the alternative communication port 126-n and continue to transfer the data packet. The reliability and availability of the storage apparatus 10 can be improved without increasing the processing load of the MP 121.

  In the above embodiment, the processing executed for the inter-switch path 127 provided in the same DKC 12 has been described. However, the present invention can be applied to two different DKCs 12 or switches provided in different device housings. The present invention can also be applied to a dual data transfer path provided between them.

  According to the embodiments of the present invention described in detail above, it is possible to provide a storage control device and a data transfer method that improve the availability of the system while improving the reliability of the data transfer path.

  Although the present embodiment has been described above, the above embodiment is intended to facilitate understanding of the present invention and is not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

Claims (11)

An information processing apparatus that has a data transfer path that branches from a root node to a plurality of nodes in a tree shape and that is communicably connected, and performs serial data transmission between the root node and the plurality of nodes. And
Two inter-node data transfer paths for performing the serial data transmission provided between at least one set of the plurality of nodes;
Provided in each of the terminal nodes that are the nodes at both ends of the inter-node data transfer path, and each of the terminal nodes is a transmission source to one of the nodes that are transmission destinations via the other terminal node When transferring data received from any of the other nodes, the inter-node data used for data transfer from the transmission destination node to the transmission source node is used for data transfer to the transmission destination node. A routing processing unit that transfers data using the same inter-node data transfer path as the transfer path;
An information processing apparatus comprising: The information processing apparatus according to claim 1,
The information processing apparatus is a storage control apparatus that controls data I / O between a recording medium and a computer.
Serial data transmission between the root node and the plurality of nodes is performed according to the PCI Express (registered trademark) standard, and the terminal node is a switch for PCI Express,
The plurality of nodes include a disk adapter that controls data I / O with a recording medium, and a channel adapter that controls communication with the computer,
Information indicating which of the inter-node data transfer paths is used to perform data transfer in association with each combination of the source node and the destination node Holds data transfer path information between nodes,
The routing processing unit acquires the inter-use node data transfer path information based on the transmission source node and the transmission destination node recorded in the data to be transferred,
The root node collects information indicating a connection state of each node through the data transfer path, generates the inter-node data transfer path information based on the collected information, and transfers the information to the terminal node.
When the routing processing unit detects that it cannot communicate with either the transmission source node or the transmission destination node, the inter-node data is included in the inter-use node data transfer path information including the transmission source node or the transmission destination node. Record information that the transfer path cannot be used,
When the routing processing unit detects that communication is possible with respect to the transmission source node or the transmission destination node that has detected that communication cannot be performed, the data transfer path between used nodes including the transmission source node or the transmission destination node In the information, record information that the inter-node data transfer path is available,
When the routing processing unit detects that any of the inter-node data transfer paths cannot be used, notifies the root node to that effect,
The root node records the inter-node data transfer path that can be used instead of the unusable inter-node data transfer path for the inter-use node data transfer path information generated by itself, and the inter-use node data Transfer forwarding path information to the terminal node;
When the routing processing unit receives data to be transferred to the destination node that uses the inter-node data transfer path that cannot be used from the source node, information indicating that the data cannot be transferred to the destination node. Transmitting to the source node;
Information processing device. The information processing apparatus according to claim 1,
Information indicating which of the inter-node data transfer paths is used to perform data transfer in association with each combination of the source node and the destination node Holds data transfer path information between nodes,
The routing processing unit acquires the inter-use node data transfer path information based on the transmission source node and the transmission destination node recorded in the data to be transferred.
Information processing device. The information processing apparatus according to claim 3,
The root node collects information indicating a connection state of each node through the data transfer path, generates the inter-use node data transfer path information based on the collected information, and transfers the information to the terminal node;
Information processing device. The information processing apparatus according to claim 1,
When the routing processing unit detects that it cannot communicate with either the transmission source node or the transmission destination node, the data transfer path information between the used nodes including the detected transmission source node or transmission destination node includes the node Record information that the inter-data transfer path cannot be used,
Information processing device. The information processing apparatus according to claim 5,
When the routing processing unit detects that communication is possible with respect to the transmission source node or the transmission destination node that has detected that communication cannot be performed, the data transfer path between used nodes including the transmission source node or the transmission destination node In the information, record information that the inter-node data transfer path is usable.
Information processing device. The information processing apparatus according to claim 3,
When the routing processing unit detects that any of the inter-node data transfer paths cannot be used, notifies the root node to that effect,
The root node records the inter-node data transfer path that can be used instead of the unusable inter-node data transfer path for the inter-use node data transfer path information generated by itself, and the inter-use node data Forwarding forwarding path information to the terminal node;
Information processing device. The information processing apparatus according to claim 1,
When the routing processing unit receives data to be transferred to the destination node that uses the inter-node data transfer path that cannot be used from the source node, information indicating that the data cannot be transferred to the destination node. Transmitting to the source node;
Information processing device. The information processing apparatus according to claim 3,
The routing processing unit holds, in the inter-node data transfer path information, information on the inter-node data transfer path that substitutes when any of the inter-node data transfer paths cannot be used,
When it is detected that any of the inter-node data transfer paths can no longer be used, the inter-node data transfer path information is referred to and can be used in place of the unusable inter-node data transfer path Perform data transfer using the node-to-node data transfer path,
Information processing device. The information processing apparatus according to claim 1,
The information processing apparatus is a storage control apparatus that controls data I / O between a recording medium and a computer.
Serial data transmission between the root node and the plurality of nodes is performed according to the PCI Express (registered trademark) standard, and the terminal node is a switch for PCI Express,
The plurality of nodes include a disk adapter that controls data I / O with a recording medium and a channel adapter that controls communication between the computers.
Information processing device. In a data transfer path for communicatively connecting between a plurality of nodes branched from a root node to a plurality of nodes, a method for transferring data serially transmitted between the root node and the plurality of nodes,
The data transfer path includes two inter-node data transfer paths for performing the serial data transmission, which are provided between at least one set of the plurality of nodes.
The terminal nodes that are the nodes at both ends of the inter-node data transfer path are connected to one of the nodes that are transmission destinations of each of the terminal nodes via the other terminal node. When transferring data received from any of the nodes, the return data from the destination node to the source node is the same as the inter-node data transfer path used for data transfer to the destination node. Transfer using the inter-node data transfer path;
Data transfer method.

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