WO2015103960A1 - 一种具有多种时间常数的整流限幅电路和无源射频标签 - Google Patents

一种具有多种时间常数的整流限幅电路和无源射频标签 Download PDF

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Publication number
WO2015103960A1
WO2015103960A1 PCT/CN2015/070145 CN2015070145W WO2015103960A1 WO 2015103960 A1 WO2015103960 A1 WO 2015103960A1 CN 2015070145 W CN2015070145 W CN 2015070145W WO 2015103960 A1 WO2015103960 A1 WO 2015103960A1
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Prior art keywords
type mos
mos transistor
drain
terminal
gate
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PCT/CN2015/070145
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English (en)
French (fr)
Inventor
吴边
韩富强
漆射虎
罗远明
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卓捷创芯科技(深圳)有限公司
无锡智速科技有限公司
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Publication of WO2015103960A1 publication Critical patent/WO2015103960A1/zh
Priority to US15/201,621 priority Critical patent/US9899934B2/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/043Conversion of ac power input into dc power output without possibility of reversal by static converters using transformers or inductors only
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0701Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management
    • G06K19/0715Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management the arrangement including means to regulate power transfer to the integrated circuit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J50/12Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H02M7/062Avoiding or suppressing excessive transient voltages or currents
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/32Means for protecting converters other than automatic disconnection
    • H02M1/322Means for rapidly discharging a capacitor of the converter for protecting electrical components or for preventing electrical shock

Definitions

  • the invention belongs to the technical field of radio frequency identification, and specifically relates to a rectifying limiting circuit with multiple time constants and a passive radio frequency tag comprising the rectifying limiting circuit.
  • the Radio Frequency Identification (RFID) tag itself does not have a battery, and it relies on the electromagnetic energy transmitted by the card reader. Because of its simple structure and economical utility, it has been widely used in logistics management, asset tracking and mobile medical.
  • a passive RFID tag When a passive RFID tag is in operation, it absorbs the electromagnetic energy emitted by the reader from the surrounding environment. After absorbing energy, the passive RFID tag rectifies a part of the energy into a DC power supply for the internal circuit of the passive RFID tag; the passive RFID tag also inputs another part of the energy into the internal modulation and demodulation circuit, and the modulation and demodulation circuit will The amplitude modulated signal carried in the energy is demodulated and the demodulated signal is sent to the digital baseband portion of the passive RFID tag for processing.
  • the electromagnetic energy absorbed by the passive RFID tag from the surrounding environment also changes as the passive RFID tag operates.
  • the signal strength received by the passive RFID tag is also strong, so that the voltage induced on the coil exceeds the voltage used by the rectifier module in the chip.
  • the voltage withstand voltage of the transistor causes permanent damage to the transistor, causing the RFID tag to fail.
  • the passive RFID tag transmits data to the card reader through load modulation, and the coil at the card reader end detects the impedance change of the RFID tag end coil to acquire data.
  • the passive RFID tag is too far from the card reader
  • the load modulation signal coupled from the RFID tag end is likely to cause saturation of the reader receiving end, and the communication fails. This failure is more likely to occur under the RTF communication mode (Reader Talk First) where the reader first issues a command and then waits for an RFID tag to answer.
  • the card reader first transmits energy to the tag, which is downlink communication. After the tag couples the energy and reads the demodulated signal therein, the tag performs a demodulation command and the processing result is processed. Send back to the card reader, this is the uplink communication.
  • the tag demodulation and uplink communication are limited energy transmitted by the card reader in downlink communication. If the energy is too low, the tag cannot demodulate the command well and perform uplink communication, that is, the card reader cannot read the data in the tag. Therefore, the card reader needs to be closer to the tag to send the tag in the downlink communication phase.
  • an amplitude limiting processing circuit needs to be applied inside the RFID tag chip circuit to ensure that the voltage across the antenna on the RFID tag is limited. A predetermined value.
  • the technical problem to be solved by the embodiments of the present invention is to provide a rectification limiting circuit and a passive radio frequency tag with multiple time constants, which are implemented by adjusting the bleed path of the passive radio frequency tag.
  • the control of the circuit voltage prevents the reader from receiving saturation and effectively increases the read/write distance of the tag.
  • a rectifying limiter circuit having a plurality of time constants comprising:
  • a resonant capacitor connected in parallel with the resonant inductor between the first antenna end and the second antenna end, for forming a resonant circuit with the resonant inductor, receiving an external electromagnetic field and coupling it to the rectifier circuit;
  • a rectifier circuit having an input end connected to the first antenna end and the second antenna end, configured to convert the AC power coupled by the resonant circuit into a DC power supply and output to an external load circuit, and simultaneously output one of the two outputs through the parallel connection
  • the drain circuit is grounded to output the charge to the ground when the field strength is too strong;
  • the input ends of the two drain passages are respectively connected to the output end of the rectifier circuit, and the control ends of the two drain passages are respectively controlled by a first control circuit and a second control circuit having different time constants, the two channels are discharged
  • the output of the flow path is connected and grounded.
  • the first control circuit includes a second current mirror tube, a first resistor, a second resistor, a fifth N-type MOS transistor, a sixth N-type MOS transistor, and a first P-type MOS transistor.
  • the second current mirror tube source is connected to the power terminal, the drain is grounded through the first resistor connected in series and the second resistor, the gate is connected to the bias voltage terminal, and the source of the fifth N-type MOS transistor is connected a drain terminal of the second current mirror tube is connected to an output end of the first control circuit, a gate thereof is connected to the control signal end, and a source of the first P-type MOS transistor is connected to the second current mirror tube a drain terminal connected to an output end of the first control circuit, a gate thereof connected to a gate of the sixth N-type MOS transistor, and a drain of the sixth N-type MOS transistor being connected to the first control circuit
  • the output terminal is grounded, and the gate of the first P-type MOS transistor and the gate of the sixth N-type MOS transistor are connected to a control signal end opposite to the gate control signal of the fifth N-type MOS transistor.
  • the second control circuit includes a third current mirror tube, a third resistor, a fourth resistor, a logic series switch unit, a first capacitor, a second capacitor, and a seventh N-type MOS transistor.
  • the third current mirror tube source is connected to the power supply terminal, the drain is grounded through a third resistor and a fourth resistor connected in series, the gate is connected to the bias voltage terminal, and the logic series switch unit input terminal is connected to the a drain end of the third current mirror tube, the output end is connected to the output end of the second control circuit, the first capacitor is connected in parallel with the second capacitor, and the first capacitor is connected to the anode of the second capacitor and connected to the logic series switch unit The output terminal is connected to the cathode of the second capacitor and grounded.
  • the source terminal of the seventh N-type MOS transistor is grounded, the gate is connected to the control signal end, and the drain thereof is connected to the output end of the second control circuit.
  • Another object of embodiments of the present invention is to provide a passive radio frequency tag including the above-described rectifying limiter circuit having a plurality of time constants.
  • the rectification limiting circuit with multiple time constants of the present invention has two discharge paths connected in parallel at the output end of the rectifying circuit, and the control ends of the two discharging paths are respectively composed of analog signals having different time constants, that is, two paths.
  • the analog signal control of the voltage amplitude has different rising and falling speeds.
  • the first analog control signal is a set of parallel connected logic switches with small time constants, which can quickly output signals and no output signals. Inter-switching, so that the first discharge path controlled by it switches between the open discharge and the off state, thereby achieving fast control;
  • the second analog control signal is composed of a logic series switch unit and a capacitor.
  • the circuit has a large time constant, and the state of the output signal and the non-output signal are switched slowly, so that the second discharge path controlled by the switch is slower in switching between the discharge and the off state, and the control is slow. Slow.
  • the invention applies different time constants to the control ends of the two discharge paths, that is, analog control signals for voltage amplitude adjustment at different switching speeds, thereby realizing switching between full opening and complete closing of the two discharging paths, according to the antenna
  • the amount of terminal charge and the energy level at which the tag is placed are adaptive Discharge, to improve the demodulation ability of the tag, and improve the read and write distance of the tag.
  • FIG. 1 is a structural view showing a first embodiment of a circuit of the present invention
  • FIG. 2 is a structural view showing the second embodiment of the overall structure of the circuit of the present invention.
  • FIG. 3 is a structural view showing a third embodiment of the overall structure of the circuit of the present invention.
  • FIG. 4 is a structural view showing the fourth embodiment of the overall structure of the circuit of the present invention.
  • Figure 5 is a structural diagram of a first control circuit of the present invention.
  • Figure 6 is a block diagram showing the structure of a second control circuit of the present invention.
  • Figure 7 is a structural view showing a first embodiment of the second control circuit of the present invention.
  • Figure 8 is a structural view showing the second embodiment of the second control circuit of the present invention.
  • Figure 9 is a connection diagram of a first control circuit and a second control circuit of the present invention.
  • Figure 10 is a structural diagram of a first embodiment of a threshold unit of the present invention.
  • Figure 11 is a structural view showing a second embodiment of the threshold unit of the present invention.
  • Figure 12 is a block diagram showing a third embodiment of the threshold unit of the present invention.
  • FIG. 1 is a structural diagram of a first embodiment of a circuit according to the present invention, and a rectifying limiting circuit having a plurality of time constants according to the present invention includes:
  • a resonant capacitor C which is connected in parallel with the resonant inductor L between the first antenna end in1 and the second antenna end in2 for forming a resonant circuit with the resonant inductor L, receiving an external electromagnetic field and coupling it to the rectifier circuit;
  • a rectifier circuit having an input end connected to the first antenna end in1 and the second antenna end in2 for converting the AC power coupled by the resonant circuit into a DC power supply and outputting to an external load circuit, and simultaneously connecting one output end thereof through parallel connection
  • the two drain paths are grounded to discharge the charge to ground when the field strength is too strong;
  • the input ends of the two drain passages are respectively connected to the output end of the rectifier circuit, and the control ends of the two drain passages are respectively controlled by a first control circuit and a second control circuit having different time constants, the two channels are discharged
  • the output of the flow path is connected and grounded.
  • the invention applies different time constants to the control ends of the two discharge paths, that is, analog control signals for voltage amplitude adjustment at different switching speeds, thereby realizing switching between full opening and complete closing of the two discharging paths, according to the antenna
  • the amount of terminal charge and the energy level of the tag are adaptively discharged to improve the demodulation capability of the tag and increase the read/write distance of the tag.
  • the rectifier circuit includes a first rectifying branch and a second rectifying branch connected in parallel between the first antenna end in1 and the second antenna end in2.
  • the first rectifying branch is a bridge rectifying circuit, one output end of which is grounded, and the other output end V dd_out is connected to an external load circuit for converting the AC power coupled by the resonant circuit into a DC power supply to supply power to the external load circuit .
  • the second rectifying branch is a fifth diode D5 and a sixth diode D6 connected between the first antenna end in1 and the second antenna end in2, the fifth diode D5 and the sixth two
  • the cathode ends of the pole tubes D6 are connected and connected to the input ends of the two discharge passages.
  • the structure of the second embodiment of the second rectifying branch is as shown in FIG. 2.
  • the second rectifying branch is connected to the fifth diode between the first antenna end in1 and the second antenna end in2.
  • a tube D5 and a sixth diode D6, and a seventh diode D7 and an eighth diode D8, the fifth diode D5 and the sixth diode D6 are connected to the cathode end and connected to the first drain
  • the seventh diode D7 and the cathode end of the eighth diode D8 are connected and connected to the input end of the second drain path.
  • the second embodiment structure of the second rectifying branch shown in Fig. 2 increases the control flexibility for further limiting the bleeder current.
  • the size of the rectifying devices D5, D6, D7, and D8 can be further optimized and adjusted according to the leakage bleed path controlled by the control signals of different time constants, so that the leakage current actually entering the bleed path is different at different limiting points.
  • the current is sized to achieve system optimization.
  • further considerations for the dimensions of the D5, D6, D7, and D8 devices can meet the electrostatic breakdown voltage specification requirements that the chip pins that are in contact with the outside world can withstand without affecting the overall system performance, which is equivalent to adding one. Relatively independent control of the design parameters makes it easy to achieve a more optimized reliability design.
  • the third embodiment of the second rectifying branch is structured as shown in FIG. 3, and the second rectifying branch is a third N-type MOS transistor NM3 connected between the first antenna end in1 and the second antenna end in2.
  • a fourth N-type MOS transistor NM4 a gate and a drain of the third N-type MOS transistor NM3 are respectively connected to the first antenna terminal, and a gate and a drain of the fourth N-type MOS transistor NM4 are respectively connected to the second antenna terminal.
  • the source of the third N-type MOS transistor NM3 is connected to the source of the fourth N-type MOS transistor NM4 and is connected to the input terminals of the two drain paths.
  • the fourth embodiment of the second rectifying branch is structured as shown in FIG. 4, and the second rectifying branch is a third N-type MOS transistor NM3 connected between the first antenna end in1 and the second antenna end in2. a fourth N-type MOS transistor NM4, and a tenth N-type MOS transistor NM10 and an eleventh N-type MOS transistor NM11, wherein the gate and the drain of the third N-type MOS transistor NM3 are respectively connected to the first antenna terminal, and fourth The gate and the drain of the N-type MOS transistor NM4 are respectively connected to the second antenna terminal, and the source of the third N-type MOS transistor NM3 is connected to the source of the fourth N-type MOS transistor NM4 and is connected to the input end of the first drain-discharge path
  • the gate and the drain of the tenth N-type MOS transistor NM10 are respectively connected to the first antenna end, and the gate and the drain of the eleventh N-type MOS transistor NM11 are respectively connected to the second antenna end, and
  • the fourth embodiment of the second rectifying branch shown in Fig. 4 increases the control flexibility for further limiting the bleeder current.
  • the size of the rectifying devices NM3, NM4, NM10, and NM11 can be further optimized and adjusted corresponding to the leakage bleed path controlled by the control signals of different time constants, so that the leakage current actually entering the bleed path is different at different limiting points.
  • the current is sized to achieve system optimization.
  • further considerations for the size of the NM3, NM4, NM10, and NM11 devices can meet the electrostatic breakdown voltage specification requirements that the chip pins that are in contact with the outside world can withstand without affecting the overall system performance, which is equivalent to adding one. Relatively independent control of the design parameters makes it easy to achieve a more optimized reliability design.
  • the two bleed paths are a first N-type MOS transistor NM1 and a second N-type MOS transistor NM2 connected in parallel, and the drains of the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 are connected to the The output end of the rectifier circuit, as described above, the drains of the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 can be connected to the output terminal of the rectifier circuit at the same time, or can be connected to the two channels separately
  • the gate of the first N-type MOS transistor NM1 is connected to the output terminal Lim1 of the first control circuit, and the source is grounded to form the first A drain path
  • the gate of the second N-type MOS transistor NM2 is connected to the output terminal Lim2 of the second control circuit, and the source is grounded to form a second drain path.
  • FIG. 5 is a structural diagram of a first control circuit of the present invention, the first control circuit including a second current mirror PM5, a first resistor R1, a second resistor R2, a fifth N-type MOS transistor NM5, and a sixth N-type MOS.
  • the source of the second current mirror PM5 is connected to the power terminal vdd_out, the drain is grounded through the first resistor R1 and the second resistor R2 connected in series, and the gate is connected to the bias voltage terminal Vbias .
  • the source of the fifth N-type MOS transistor NM5 is connected to the drain terminal of the second current mirror tube PM5, the drain is connected to the output terminal Lim1 of the first control circuit, and the gate thereof is connected to the control signal terminal, the first P
  • the source of the MOS transistor PM1 is connected to the drain terminal of the second current mirror PM5, the drain is connected to the output terminal Lim1 of the first control circuit, and the gate thereof is connected to the gate of the sixth N-type MOS transistor NM6.
  • the drain of the sixth N-type MOS transistor NM6 is connected to the output terminal Lim1 of the first control circuit, the source is grounded, the gate of the first P-type MOS transistor PM1 and the gate of the sixth N-type MOS transistor NM6 The pole is connected to the control signal end opposite to the gate control signal of the fifth N-type MOS transistor NM5.
  • the gate of the fifth N-type MOS transistor NM5 is connected to the test signal tes t1, and the first P The gate of the MOS transistor PM1 and the gate of the sixth N-type MOS transistor NM6 are connected to the test signal opposite to test1.
  • the test signal test1 of the gate terminal of the fifth N-type MOS transistor NM5 is 1, the fifth N-type MOS transistor NM5 is turned on, and 0, the first P-type MOS transistor PM1 is also turned on, and the sixth N-type MOS transistor NM6 is not turned on, and the output terminal Lim1 of the first control circuit outputs a signal to the control end of the first drain-discharge path, that is, the first N
  • the gate of the MOS transistor NM1 opens the first bleed path, and discharges the charge between the first antenna end in1 and the second antenna end in2 to the ground; when the fifth N-type MOS transistor NM5 is at the gate end
  • test1 is 0, the fifth N-type MOS transistor NM5 is not turned on, and 1, the first P-type MOS transistor PM1 is not turned on, and the sixth N-type MOS transistor NM6 is turned on, and the charge of the first control circuit output terminal Lim1 is pulled down to the ground, so that Lim1 has no output signal, then the first N
  • the first resistor R1 and the second resistor R2 are connected in series between the drain of the second current mirror tube PM5 and the ground. According to Ohm's law, the current output by the second current mirror PM5 is at the first resistor R1 and the second resistor R2.
  • the voltage generated after the series connection is transmitted to the Lim1 node by the logic switch composed of PM1 and NM5. Therefore, by setting the resistance values of the first resistor R1 and the second resistor R2, the output of the first control circuit Lim1 can be adjusted.
  • FIG. 6 is a structural diagram of a second control circuit of the present invention, the second control circuit including a third current mirror tube PM6, a third resistor R3, a fourth resistor R4, a logic series switching unit, a first capacitor C1, and a second capacitor C2, and a seventh N-type MOS transistor NM7.
  • the source of the third current mirror PM6 is connected to the power terminal vdd_out, the drain is grounded through the third resistor R3 and the fourth resistor R4 connected in series, and the gate is connected to the bias voltage terminal Vbias .
  • the input end of the logic series switch unit is connected to the drain end of the third current mirror tube PM6, the output end is connected to the output end Lim2 of the second control circuit, and the first capacitor C1 is connected in parallel with the second capacitor C2, the first capacitor C1 Connected to the positive terminal of the second capacitor C2 and connected to the output end of the logic series switching unit, the first capacitor C1 is connected to the cathode of the second capacitor C2 and grounded, and the source terminal of the seventh N-type MOS transistor NM7 is grounded, the gate Connected to the control signal terminal, the drain of which is connected to the output terminal Lim2 of the second control circuit.
  • the third resistor R3 and the fourth resistor R4 are connected in series between the drain of the third current mirror PM6 and the ground. According to Ohm's law, the current output by the third current mirror PM6 is at the third resistor R3 and the fourth resistor R4.
  • the voltage generated after the series connection is transmitted to the Lim2 node by the logic series switching unit, so by setting the The magnitude of the resistance of the third resistor R3 and the fourth resistor R4 can adjust the voltage amplitude of the output terminal Lim2 of the second control circuit.
  • the larger the Lim2 the larger the channel opened by the second N-type MOS transistor NM2 controlled by the second resistor. The faster the discharge rate.
  • the logic series switching unit is at least one logic switch, wherein a source terminal of the eighth N-type MOS transistor NM8 is connected to a source terminal of the second P-type MOS transistor PM2 and is connected to the third current mirror tube. a drain terminal of the NM6 serves as an input terminal of the logic series switching unit, and a drain terminal of the eighth N-type MOS transistor NM8 is connected to a drain terminal of the second P-type MOS transistor PM2 as an output terminal of the logic series switching unit.
  • a gate terminal of the eighth N-type MOS transistor NM8 is connected to the control signal terminal, and a gate terminal of the second P-type MOS transistor PM2 is connected to a control signal terminal opposite to a gate terminal control signal of the eighth N-type MOS transistor NM8.
  • the gate of the eighth N-type MOS transistor NM8 is connected to the demodulation signal demod, and the gate of the second P-type MOS transistor PM2 is connected to the demodulation signal opposite to demod.
  • the logic series switch unit is two logic switches.
  • the first logic switch has the same structure as the eighth type N.
  • the drain terminal of the MOS transistor NM8 is connected to the drain terminal of the second P-type MOS transistor PM2 as the output terminal of the first logic switch.
  • the source terminal of the ninth N-type MOS transistor NM9 is connected to the source terminal of the third P-type MOS transistor PM3 and is connected to the output terminal of the first logic switch as the input terminal of the second logic switch.
  • the drain terminal of the ninth N-type MOS transistor NM9 is connected to the drain terminal of the third P-type MOS transistor PM3 as the output terminal of the logic series switching unit, and the gate termination control of the ninth N-type MOS transistor NM9 a signal terminal, a gate end of the third P-type MOS transistor PM3 is connected to a control signal end opposite to a gate terminal control signal of the ninth N-type MOS transistor NM9.
  • the ninth N-type MOS transistor The gate of the NM9 is connected to the test signal test2, and the gate of the third P-type MOS transistor PM3 is connected to the test signal opposite to test2. As shown in Figure 8.
  • the first capacitor C1 is connected in parallel with the second capacitor C2, and the first capacitor C1 is connected to the anode of the second capacitor C2 and connected to the output end of the logic series switching unit, and the first capacitor C1 is connected to the cathode of the second capacitor C2 and Grounding, the source terminal of the seventh N-type MOS transistor NM7 is grounded, the gate is connected to the control signal terminal test2, and the drain thereof is connected to the output terminal Lim2 of the second control circuit.
  • the output terminal of the logic series switching unit that is, the output terminal Lim2 of the second control circuit, becomes slow, and the first capacitor C1 and the second capacitor The larger the capacitance of capacitor C2, the slower the change of Lim2, and the speed is affected by the capacitance of C1 and C2 capacitors.
  • the gate of the eighth N-type MOS transistor NM8 is terminated with the demodulation signal demod, and the gate of the second P-type MOS transistor PM2 is connected with the solution of demod.
  • the seventh N-type MOS transistor NM7 gate terminal is connected to the demodulation signal at the same time
  • the demod signal of the gate terminal of the eighth N-type MOS transistor NM8 is 1, the eighth N-type MOS transistor NM8 is turned on, and 0, the second P-type MOS transistor PM2 is turned on, the logic series switching unit outputs, and the output terminal Lim2 of the second control circuit outputs a signal to the control end of the second drain circuit, that is, the gate of the second N-type MOS transistor NM2 a pole, the second draining path is opened, the charge between the first antenna end in1 and the second antenna end in2 is discharged to the ground, and the logic series switching unit outputs the first capacitor C1 and the second capacitor C2 charging, its charging time determines the speed of the Lim2 signal voltage amplitude changes.
  • the seventh N-type MOS transistor NM7 is not turned on.
  • the eighth N-type MOS transistor NM8 is not turned on, and 1, the second P-type MOS transistor PM2 is not turned on, and the seventh N-type MOS transistor NM7 is turned on, and the charge of the output terminal Lim2 of the second control circuit is pulled down to the ground, so that Lim2 has no output signal, then the second N The MOS transistor NM2 is in an off state, the second bleed passage is closed and does not discharge, and the electric charge between the first antenna end in1 and the second antenna end in2 is maintained.
  • the logic series switch unit is two logic switches as shown in FIG. 8, since the first logic switch and the second logic switch are connected in series, only when the first logic switch and the second logic switch are simultaneously turned on
  • the output of the second control circuit, Lim2 has a signal output, that is, when the demod and test2 signals are simultaneously 1, the Lim2 signal output.
  • the control signal of the gate terminal of the seventh N-type MOS transistor NM7 can be arbitrarily adopted. Signal or yes signal. If adopted The signal is equivalent to the system design level.
  • the demod signal is “1”, and The signal is “0”.
  • the limiting circuit needs to limit the rectifier, that is, the output of the second control circuit Lim2 must have The signal is output to enable the second drain circuit to conduct current discharge.
  • the indicators to be optimized for the performance of the specific RF system designed are not repeated here.
  • the gate ends of the second current mirror PM5 and the third current mirror PM6 are simultaneously connected to the bias voltage terminal Vbias , and the second current mirror PM5 and the third current mirror PM6 are proportional to each other.
  • the bias voltage terminal Vbias has an input bias voltage
  • the second current mirror PM5 and the third current mirror PM6 are turned on, and the power supply vdd_out terminal current flows through the second current mirror PM5 and the third current mirror PM6.
  • the source drains flow into the first control circuit and the second control circuit, respectively.
  • the first control circuit and the second control circuit are turned on after the power supply terminal voltage vdd_out reaches a certain voltage amplitude.
  • the present invention connects the gates of the second current mirror PM5 and the third current mirror PM6 to the first current mirror PM4, respectively, as shown in FIG. 9, the source of the first current mirror PM4 Connected to the power supply terminal vdd_out, the drain is grounded through the threshold unit.
  • the first current mirror tube PM4, the second current mirror tube PM5, and the third current mirror tube PM6 form a strict mirror.
  • the image forming structure controls the opening and closing of the second current mirror PM5 and the third current mirror PM6 by using the opening and closing of the first current mirror PM4 to control the opening and closing of the first control circuit and the second control circuit.
  • the purpose is that when the power terminal voltage vdd_out is higher than the sum of the threshold voltage of the first current mirror PM4 and the threshold voltage of the threshold unit, the first current mirror PM4 is turned on, and the drain connected to the gate has a drain
  • the output voltage acts as a bias voltage of the current mirror such that the second current mirror PM5 and the third current mirror PM6 are turned on; when the power terminal voltage vdd_out is lower than the threshold voltage of the first current mirror PM4 and the threshold voltage of the threshold unit In the sum, the first current mirror PM4 is turned off, and the drain connected to the gate has no output voltage, and the second current mirror PM5 and the third current mirror PM6 are also turned off, and the power terminal voltage vdd_out cannot pass the second.
  • the threshold unit may be at least one diode connected in series, or at least one P-type MOS transistor connected in series, or at least one N-type MOS transistor connected in series.
  • the cathode end of any diode is connected to the anode end of the adjacent diode to form a series structure, and the anode end of the first diode is connected to the drain end of the first current mirror tube PM4 as the input end of the threshold unit, and finally a diode cathode end is grounded to the output of the threshold unit, as shown in FIG. 10;
  • the drain terminal of any P-type MOS transistor is connected to the source terminal of the adjacent P-type MOS transistor to form a series structure, and the source of the first P-type MOS transistor is connected to the first current
  • the drain terminal of the mirror tube PM4 is the input end of the threshold unit, the drain of the last P-type MOS transistor is grounded to be the output end of the threshold unit, and the gates of the P-type MOS tubes are connected to the drain, as shown in the figure 11;
  • any N-type MOS transistor source terminal and an adjacent N-type MOS transistor The drain terminals are connected to form a series structure, and the drain of the first N-type MOS transistor is connected to the drain terminal of the first current mirror PM4 as the input terminal of the threshold unit, and the source of the last N-type MOS transistor is grounded.
  • the gates of the N-type MOS transistors are connected to the drain, as shown in FIG.
  • Another object of the present invention is to provide a passive radio frequency tag comprising the above-described rectifying limiter circuit having multiple time constants, wherein the output of the rectifying limiter circuit of the passive radio frequency tag is connected in parallel with two discharge drain paths.
  • the control ends of the two discharge paths are respectively controlled by a first control circuit and a second control circuit, and the first control circuit causes the first control circuit to have an output signal quickly according to the opening and closing of the set of switch tubes Switching between the output signal and the no-output signal, so that the first-stage discharge discharge path controlled by the switch can quickly switch between the open discharge and the off state, thereby realizing rapid discharge of the antenna end charge; and the second control The circuit has a set of capacitors at the output end, so that the second control circuit switches between the output signal and the no-output signal at a slower speed, so that the second discharge discharge path controlled by the second is slowly turned on and discharged.
  • Switching between the two states is turned off to achieve slow bleed of the antenna terminal charge.
  • the invention applies different time constants to the control ends of the two discharge paths, that is, analog control signals for voltage amplitude adjustment at different switching speeds, thereby realizing switching between full opening and complete closing of the two discharging paths, according to the antenna
  • the amount of terminal charge and the energy level of the tag are adaptively discharged to improve the demodulation capability of the tag and increase the read/write distance of the tag.

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Abstract

一种具有多种时间常数的整流限幅电路以及包含该整流限幅电路的无源射频标签,通过对整流限幅电路的两路放电通路的控制端分别施予不同时间常数的,即以不同切换速度进行电压幅度调整的模拟控制信号,实现对两路放电通路的完全打开到完全关闭进行切换,根据天线端电荷量的大小以及标签所处于的能量水平情况进行适应性的放电,以提高标签的解调能力,并提升标签的读写距离。

Description

一种具有多种时间常数的整流限幅电路和无源射频标签 技术领域
本发明属于射频识别技术领域,具体是指一种具有多种时间常数的整流限幅电路以及包含该整流限幅电路的无源射频标签。
背景技术
无源射频识别(Radio Frequency Identification,RFID)标签本身不带电池,其依靠读卡器发送的电磁能量工作。由于它结构简单、经济实用,因而其在物流管理、资产追踪以及移动医疗领域获得了广泛的应用。
无源RFID标签工作时,其会从周围环境中吸收读卡器发送的电磁能量。无源RFID标签在吸收能量之后,将一部分能量整流为直流电源,以供无源RFID标签内部电路工作;无源RFID标签还将另一部分能量输入内部的调制解调电路,调制解调电路会对该能量中携带的幅度调制信号进行解调,并将解调后的信号发送给无源RFID标签的数字基带部分处理。
由于无源RFID标签与读卡器的距离是变化的,因此,当无源RFID标签工作时,其从周围环境中吸收的电磁能量也是变化的。当无源RFID标签离读卡器太近或读卡器发送的电磁能量太强时,无源RFID标签接收到的信号强度也较强,以至线圈上感应的电压超过了芯片中整流器模块所用的晶体管的耐压极限,造成晶体管的永久性损坏,导致RFID标签失效。
无源RFID标签通过负载调制的方式传输数据到读卡器,读卡器端的线圈探测到RFID标签端线圈的阻抗变化从而获取数据。当无源RFID标签离读卡器太 近或读卡器发送的电磁能量太强时,从RFID标签端耦合回来的负载调制信号容易造成读卡器接受端的饱和,以至通讯失败。这种失败在读卡器首先发命令然后等待RFID标签应答的RTF通讯模式(Reader Ta lk First)下更容易发生。
同时,在RTF通讯模式(Reader Talk First)下,读卡器首先向标签发送能量,此为下行通讯,标签耦合该能量并读取其中的解调信号后,标签执行解调命令并将处理结果发回至读卡器,此为上行通讯。如果采取半双工通讯方式,那么在上行通讯过程中,由于读卡器已经停止向标签发送能量,因此标签进行命令解调以及上行通讯均是依靠读卡器下行通讯时发送的有限的能量,如果能量过低,则标签无法很好的解调命令并执行上行通讯,即读卡器无法读取标签中的数据,因此,需要将读卡器更加的靠近标签以在下行通讯阶段为标签发送更多的能量来使得标签可以完成整个命令解调及上行通讯。简而言之,当标签中能量过低时,将极大的影响标签的读写距离,因此,需要对标签的电源端进行有效的控制管理,当标签端电压过高时,需要尽快的打开放电通路以将多余电荷泄放出去;当标签端电压过低时,需要关闭标签的所有泄放通路以实现电源的最有效化使用。
为了解决上述耐压可靠性和读卡器接受饱和,以及标签上行通讯过程中的能量保持问题,RFID标签芯片电路内部需要施加幅度限制处理电路,以确保RFID标签上的天线两端电压被限制在一个预定的数值。
发明内容
本发明实施例所要解决的技术问题在于,提供一种具有多种时间常数的整流限幅电路和无源射频标签,通过对无源射频标签的泄放通路进行调整来实现 对电路电压的控制,防止读卡器端接收饱和现象的发生,并有效提升标签的读写距离。
为实现上述目的,本发明所采取的技术方案为:
一种具有多种时间常数的整流限幅电路,所述电路包括:
谐振电容,与谐振电感并联连接于第一天线端与第二天线端之间,用于与谐振电感组成谐振电路,接收外部电磁场并将其耦合至整流电路;
整流电路,其输入端连接至第一天线端与第二天线端,用于将所述谐振电路耦合的交流电源转换为直流电源并输出至外部负载电路,同时其一路输出端通过并联连接的两路泄流通路接地,用于在场强过强时将电荷输出至地;
所述两路泄流通路的输入端分别连接至整流电路的输出端,两路泄流通路的控制端分别由具有不同时间常数的第一控制电路和第二控制电路控制,所述两路泄流通路的输出端相连并接地。
进一步的,所述第一控制电路包括第二电流镜管、第一电阻、第二电阻、第五N型MOS管、第六N型MOS管以及第一P型MOS管,
所述第二电流镜管源极连接至电源端,漏极通过串联连接的第一电阻与第二电阻接地,栅极连接至偏置电压端,所述第五N型MOS管的源极接所述第二电流镜管的漏极端,漏极接第一控制电路的输出端,其栅极接控制信号端,所述第一P型MOS管的源极接所述第二电流镜管的漏极端,漏极接所述第一控制电路的输出端,其栅极连接至所述第六N型MOS管的栅极,第六N型MOS管的漏极接所述第一控制电路的输出端,源极接地,所述第一P型MOS管的栅极和第六N型MOS管的栅极连接至与所述第五N型MOS管栅极端控制信号相反的控制信号端。
更进一步的,所述第二控制电路包括第三电流镜管、第三电阻、第四电阻、逻辑串联开关单元、第一电容、第二电容,以及第七N型MOS管,
所述第三电流镜管源极连接至电源端,漏极通过串联连接的第三电阻和第四电阻接地,栅极连接至偏置电压端,所述逻辑串联开关单元输入端连接至所述第三电流镜管的漏极端,输出端接第二控制电路的输出端,所述第一电容与第二电容并联连接,第一电容与第二电容的正极相连并连接至逻辑串联开关单元的输出端,第一电容与第二电容的负极相连并接地,所述第七N型MOS管的源极端接地,栅极接控制信号端,其漏极接所述第二控制电路的输出端。
本发明实施例的另一目的在于提供一种包括上述具有多种时间常数的整流限幅电路的无源射频标签。
本发明所述具有多种时间常数的整流限幅电路,在整流电路的输出端并联连接两路放电通路,所述两路放电通路的控制端分别由具有不同时间常数的模拟信号,即两路电压幅度有不同的上升与下降的变化速度的模拟信号控制,第一路模拟控制信号为一组并联连接的逻辑开关,具有较小的时间常数,可快速的在有输出信号与无输出信号之间切换,使得受其控制的第一路放电通路在打开放电与关闭两种状态之间进行切换的速度较快,从而实现快速控制;第二路模拟控制信号为由逻辑串联开关单元与电容组成的回路,具有较大的时间常数,有输出信号与无输出信号状态切换较慢,从而使得受其控制的第二路放电通路在打开放电与关闭两种状态之间切换的速度较慢,控制速度缓慢。本发明通过对两路放电通路的控制端分别施予不同时间常数的,即以不同切换速度进行电压幅度调整的模拟控制信号,实现对两路放电通路的完全打开到完全关闭进行切换,根据天线端电荷量的大小以及标签所处于的能量水平情况进行适应性的 放电,以提高标签的解调能力,并提升标签的读写距离。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明的电路总体结构实施例一结构图;
图2是本发明的电路总体结构实施例二结构图;
图3是本发明的电路总体结构实施例三结构图;
图4是本发明的电路总体结构实施例四结构图;
图5是本发明的第一控制电路结构图;
图6是本发明的第二控制电路结构框图;
图7是本发明的第二控制电路实施例一结构图;
图8是本发明的第二控制电路实施例二结构图;
图9是本发明的第一控制电路和第二控制电路连接结构图;
图10是本发明阈值单元第一实施例结构图;
图11是本发明阈值单元第二实施例结构图;
图12是本发明阈值单元第三实施例结构图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清 楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
图1是本发明的电路总体结构实施例一结构图,本发明所述一种具有多种时间常数的整流限幅电路包括:
谐振电容C,其与谐振电感L并联连接于第一天线端in1与第二天线端in2之间,用于与谐振电感L组成谐振电路,接收外部电磁场并将其耦合至整流电路;
整流电路,其输入端连接至第一天线端in1与第二天线端in2,用于将所述谐振电路耦合的交流电源转换为直流电源并输出至外部负载电路,同时其一路输出端通过并联连接的两路泄流通路接地,用于在场强过强时将电荷输出至地;
所述两路泄流通路的输入端分别连接至整流电路的输出端,两路泄流通路的控制端分别由具有不同时间常数的第一控制电路和第二控制电路控制,所述两路泄流通路的输出端相连并接地。
本发明通过对两路放电通路的控制端分别施予不同时间常数的,即以不同切换速度进行电压幅度调整的模拟控制信号,实现对两路放电通路的完全打开到完全关闭进行切换,根据天线端电荷量的大小以及标签所处于的能量水平情况进行适应性的放电,以提高标签的解调能力,并提升标签的读写距离。
如图1所示,所述整流电路包括并联连接于第一天线端in1与第二天线端in2之间的第一整流支路和第二整流支路。
所述第一整流支路为桥式整流电路,其一输出端接地,另一输出端Vdd_out连接至外部负载电路,用于将谐振电路耦合的交流电源转换为直流电源为外部负 载电路提供电源。
所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第五二极管D5和第六二极管D6,所述第五二极管D5和第六二极管D6的阴极端相连并连接至所述两路泄流通路的输入端。
第二整流支路的第二种实施例结构如图2所示,该实施例中所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第五二极管D5和第六二极管D6,以及第七二极管D7和第八二极管D8,所述第五二极管D5和第六二极管D6阴极端相连并连接至第一路泄流通路的输入端,所述第七二极管D7和第八二极管D8阴极端相连并连接至第二路泄流通路的输入端。
相对于图1所示的第一种实施例结构,图2所示的第二整流支路的第二种实施例结构增加了进一步限幅泄放电流的控制灵活性。对应于不同时间常数的控制信号所控制的漏电泄放通路,整流器件D5,D6,D7,和D8的尺寸可以进一步优化调整,使得真正进入泄放通路的漏电流在不同的限幅点有不同电流大小,以达到系统优化的目的。同时,对D5,D6,D7,和D8器件尺寸的进一步考量,可以满足与外界接触的芯片管脚所能够承受的静电击穿电压指标需求,而不影响整体系统的性能,等同于增加了一个相对独立控制的设计参数,易于达到更优化的可靠性设计。
第二整流支路的第三种实施例结构如图3所示,所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第三N型MOS管NM3和第四N型MOS管NM4,所述第三N型MOS管NM3栅极和漏极分别连接至第一天线端,第四N型MOS管NM4栅极和漏极分别连接至第二天线端,第三N型MOS管NM3源极连接至第四N型MOS管NM4源极并连接至所述两路泄流通路的输入端。
第二整流支路的第四种实施例结构如图4所示,所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第三N型MOS管NM3和第四N型MOS管NM4,以及第十N型MOS管NM10和第十一N型MOS管NM11,所述第三N型MOS管NM3栅极和漏极分别连接至第一天线端,第四N型MOS管NM4栅极和漏极分别连接至第二天线端,第三N型MOS管NM3源极连接至第四N型MOS管NM4源极并连接至第一路泄流通路的输入端;所述第十N型MOS管NM10栅极和漏极分别连接至第一天线端,第十一N型MOS管NM11栅极和漏极分别连接至第二天线端,第十N型MOS管NM10源极连接至第十一N型MOS管NM11源极并连接至第二路泄流通路的输入端。
相对于图3所示的第三种实施例结构,图4所示的第二整流支路的第四种实施例结构增加了进一步限幅泄放电流的控制灵活性。对应于不同时间常数的控制信号所控制的漏电泄放通路,整流器件NM3,NM4,NM10,和NM11的尺寸可以进一步优化调整,使得真正进入泄放通路的漏电流在不同的限幅点有不同电流大小,以达到系统优化的目的。同时,对NM3,NM4,NM10,和NM11器件尺寸的进一步考量,可以满足与外界接触的芯片管脚所能够承受的静电击穿电压指标需求,而不影响整体系统的性能,等同于增加了一个相对独立控制的设计参数,易于达到更优化的可靠性设计。
所述两路泄流通路为并联连接的第一N型MOS管NM1和第二N型MOS管NM2,所述第一N型MOS管NM1和第二N型MOS管NM2的漏极连接至所述整流电路的输出端,如前所述,第一N型MOS管NM1和第二N型MOS管NM2的漏极可连接后同时连接至整流电路的输出端,也可以分成两路分别连接至整流电路的输出端,第一N型MOS管NM1的栅极接第一控制电路输出端Lim1,源极接地形成第 一路泄流通路,第二N型MOS管NM2的栅极接第二控制电路输出端Lim2,源极接地形成第二路泄流通路。
图5是本发明的第一控制电路结构图,所述第一控制电路包括第二电流镜管PM5、第一电阻R1、第二电阻R2、第五N型MOS管NM5、第六N型MOS管NM6以及第一P型MOS管PM1。
所述第二电流镜管PM5源极连接至电源端vdd_out,漏极通过串联连接的第一电阻R1与第二电阻R2接地,栅极连接至偏置电压端Vbias
所述第五N型MOS管NM5的源极接所述第二电流镜管PM5的漏极端,漏极接第一控制电路的输出端Lim1,其栅极接控制信号端,所述第一P型MOS管PM1的源极接所述第二电流镜管PM5的漏极端,漏极接所述第一控制电路的输出端Lim1,其栅极连接至所述第六N型MOS管NM6的栅极,第六N型MOS管NM6的漏极接所述第一控制电路的输出端Lim1,源极接地,所述第一P型MOS管PM1的栅极和第六N型MOS管NM6的栅极连接至与所述第五N型MOS管NM5栅极端控制信号相反的控制信号端,本实施例中,所述第五N型MOS管NM5的栅极接测试信号tes t1,则第一P型MOS管PM1的栅极和第六N型MOS管NM6的栅极接与test1相反的测试信号
Figure PCTCN2015070145-appb-000001
当第五N型MOS管NM5栅极端的测试信号test1为1时,第五N型MOS管NM5导通,而
Figure PCTCN2015070145-appb-000002
为0,第一P型MOS管PM1也导通,第六N型MOS管NM6不导通,第一控制电路的输出端Lim1输出信号至第一路泄流通路的控制端,即第一N型MOS管NM1的栅极,使所述第一路泄流通路打开,将第一天线端in1与第二天线端in2之间的电荷泄放至地;当第五N型MOS管NM5栅极端的test1为0时,第五N型MOS管NM5不导通,而
Figure PCTCN2015070145-appb-000003
为1,第一P型MOS管PM1也不导通,第六N型MOS管NM6导通,将第一控制电路输出端Lim1 的电荷下拉至地,使得Lim1无输出信号,则第一N型MOS管NM1处于断开状态,第一路泄流通路关闭不放电,第一天线端in1与第二天线端in2之间的电荷维持。
所述第一电阻R1与第二电阻R2串联连接于第二电流镜管PM5漏极与地之间,根据欧姆定律,第二电流镜管PM5输出的电流在第一电阻R1与第二电阻R2串联后产生的电压即被由PM1和NM5组成的逻辑开关传递到Lim1节点,所以,通过设定该第一电阻R1与第二电阻R2的阻值大小,即可调整第一控制电路输出端Lim1的电压幅度,Lim1越大,则受其控制的第一N型MOS管NM1打开的沟道越大,放电速度就越快。
图6是本发明的第二控制电路结构图,所述第二控制电路包括第三电流镜管PM6、第三电阻R3、第四电阻R4、逻辑串联开关单元、第一电容C1、第二电容C2,以及第七N型MOS管NM7。
所述第三电流镜管PM6源极连接至电源端vdd_out,漏极通过串联连接的第三电阻R3和第四电阻R4接地,栅极连接至偏置电压端Vbias。所述逻辑串联开关单元输入端连接至第三电流镜管PM6的漏极端,输出端接第二控制电路的输出端Lim2,所述第一电容C1与第二电容C2并联连接,第一电容C1与第二电容C2的正极相连并连接至逻辑串联开关单元的输出端,第一电容C1与第二电容C2的负极相连并接地,所述第七N型MOS管NM7的源极端接地,栅极接控制信号端,其漏极接所述第二控制电路的输出端Lim2。
所述第三电阻R3与第四电阻R4串联连接于第三电流镜管PM6漏极与地之间,根据欧姆定律,第三电流镜管PM6输出的电流在第三电阻R3与第四电阻R4串联后产生的电压即被逻辑串联开关单元传递到Lim2节点,所以,通过设定该 第三电阻R3与第四电阻R4的阻值大小,即可调整第二控制电路输出端Lim2的电压幅度,Lim2越大,则受其控制的第二N型MOS管NM2打开的沟道越大,放电速度越快。
所述逻辑串联开关单元为至少一个逻辑开关,所述至少一个逻辑开关中,第八N型MOS管NM8的源极端与第二P型MOS管PM2的源极端相连并连接至第三电流镜管NM6漏极端作为所述逻辑串联开关单元的输入端,所述第八N型MOS管NM8的漏极端与第二P型MOS管PM2的漏极端相连作为所述逻辑串联开关单元的输出端,所述第八N型MOS管NM8的栅极端接控制信号端,所述第二P型MOS管PM2的栅极端连接至与所述第八N型MOS管NM8栅极端控制信号相反的控制信号端,本实施例中,所述第八N型MOS管NM8的栅极接解调信号demod,则第二P型MOS管PM2的栅极接与demod相反的解调信号
Figure PCTCN2015070145-appb-000004
如图7所示。
作为对本发明所述逻辑串联开关单元的另一种实施例结构,所述逻辑串联开关单元为两个逻辑开关,如图8所示,所述第一个逻辑开关的结构如上,第八N型MOS管NM8的漏极端与第二P型MOS管PM2的漏极端相连作为第一个逻辑开关的输出端。第二个逻辑开关中,第九N型MOS管NM9的源极端与第三P型MOS管PM3的源极端相连并连接至所述第一个逻辑开关的输出端作为第二逻辑开关的输入端,所述第九N型MOS管NM9的漏极端与第三P型MOS管PM3的漏极端相连作为所述逻辑串联开关单元的输出端,所述第九N型MOS管NM9的栅极端接控制信号端,所述第三P型MOS管PM3的栅极端连接至与所述第九N型MOS管NM9栅极端控制信号相反的控制信号端,本实施例中,所述第九N型MOS管NM9的栅极接测试信号test2,则第三P型MOS管PM3的栅极接与test2相反的测试信号
Figure PCTCN2015070145-appb-000005
如图8。
第一电容C1与第二电容C2并联连接,所述第一电容C1与第二电容C2的正极相连并连接至逻辑串联开关单元的输出端,第一电容C1与第二电容C2的负极相连并接地,所述第七N型MOS管NM7的源极端接地,栅极接控制信号端test2,其漏极接所述第二控制电路的输出端Lim2。由于所述第一电容C1与第二电容C2的电荷存储作用,使得逻辑串联开关单元的输出端即第二控制电路的输出端Lim2电压输出变得缓慢,且所述第一电容C1与第二电容C2电容值越大,Lim2的变化越缓慢,其速度受C1和C2电容容值的影响。
当所述逻辑串联开关单元为如图7所示的一个逻辑开关时,第八N型MOS管NM8栅极端接解调信号demod,第二P型MOS管PM2的栅极接与demod相反的解调信号
Figure PCTCN2015070145-appb-000006
第七N型MOS管NM7栅极端同时接解调信号
Figure PCTCN2015070145-appb-000007
当第八N型MOS管NM8栅极端的demod信号为1时,第八N型MOS管NM8导通,而
Figure PCTCN2015070145-appb-000008
为0,第二P型MOS管PM2导通,逻辑串联开关单元输出,第二控制电路的输出端Lim2输出信号至第二路泄流通路的控制端,即第二N型MOS管NM2的栅极,使所述第二路泄流通路打开,将第一天线端in1与第二天线端in2之间的电荷泄放至地,同时,逻辑串联开关单元输出为第一电容C1和第二电容C2充电,其充电时间决定了Lim2信号电压幅度的变化快慢。而由于第七N型MOS管NM7栅极端的
Figure PCTCN2015070145-appb-000009
为0,第七N型MOS管NM7不导通。当第八N型MOS管NM8栅极端的demod信号为0时,第八N型MOS管NM8不导通,而
Figure PCTCN2015070145-appb-000010
为1,第二P型MOS管PM2也不导通,而第七N型MOS管NM7导通,将第二控制电路输出端Lim2的电荷下拉至地,使得Lim2无输出信号,则第二N型MOS管NM2处于断开状态,第二路泄流通路关闭不放电,第一天线端in1与第二天线端in2之间的电荷维持。
当所述逻辑串联开关单元为如图8所示的两个逻辑开关时,由于第一逻辑开关与第二逻辑开关成串联连接结构,只有当第一逻辑开关与第二逻辑开关同时导通时,第二控制电路的输出端Lim2才有信号输出,即要求demod与test2信号同时为1时,Lim2才有信号输出。而第七N型MOS管NM7栅极端的控制信号可任意采用
Figure PCTCN2015070145-appb-000011
信号或者是
Figure PCTCN2015070145-appb-000012
信号。如果采用
Figure PCTCN2015070145-appb-000013
信号,相当于在系统设计的层面,当系统处于接受并解调下行信号时,demod信号为“1”,而
Figure PCTCN2015070145-appb-000014
信号为“0”,为了确保解调器工作而不至于在过强能量情况下发生解调失败,此限幅电路需要对整流器发生限幅作用,即该第二控制电路的输出端Lim2要有信号输出,以实现将所述第二路泄流通路导通进行电流泄放。对于该电路的控制原理,即采用demod信号或者test2信号,或者其它的什么信号作为控制信号,涉及所设计的具体射频系统性能优化所要达到的指标,此处不再一一赘述。
所述第二电流镜管PM5和第三电流镜管PM6的栅极端同时连接至偏置电压端Vbias,且所述第二电流镜管PM5和第三电流镜管PM6的尺寸成比例关系,当偏置电压端Vbias有输入偏置电压时,第二电流镜管PM5和第三电流镜管PM6导通,则电源vdd_out端电流流过第二电流镜管PM5和第三电流镜管PM6的源漏极并分别流入所述第一控制电路和第二控制电路中。
作为对本发明进一步优化的实施结构,为了控制所述第一控制电路和第二控制电路的工作点,使第一控制电路和第二控制电路在电源端电压vdd_out达到一定的电压幅度后才打开进行工作,本发明将所述第二电流镜管PM5和第三电流镜管PM6的栅极分别连接至第一电流镜管PM4,如图9所示,所述第一电流镜管PM4的源极连接至电源端vdd_out,漏极通过阈值单元接地。如此结构,将上述第一电流镜管PM4、第二电流镜管PM5以及第三电流镜管PM6构成严格的镜 像映射结构,利用第一电流镜管PM4的打开与关闭,控制第二电流镜管PM5和第三电流镜管PM6的打开与关闭,达到控制第一控制电路和第二控制电路打开与关闭的目的,即当电源端电压vdd_out高于所述第一电流镜管PM4的阈值电压及阈值单元的阈值电压之和时,第一电流镜管PM4导通,其与栅极短接的漏极有输出电压作为电流镜的偏置电压,使得第二电流镜管PM5和第三电流镜管PM6打开;当电源端电压vdd_out低于所述第一电流镜管PM4的阈值电压及阈值单元的阈值电压之和时,第一电流镜管PM4截止,其与栅极短接的漏极无输出电压,则第二电流镜管PM5和第三电流镜管PM6也截止,电源端电压vdd_out无法通过第二电流镜管PM5和第三电流镜管PM6流入第一控制电路和第二控制电路内,则第一控制电路和第二控制电路均不工作。
由于第一电流镜管PM4的阈值电压固定存在,则通过设定所述阈值单元内的单向导通元器件的数量来决定该阈值单元的阈值电压之和。该阈值单元可以为至少一个串联连接的二极管,或者是至少一个串联连接的P型MOS管,或者是至少一个串联连接的N型MOS管。
所述至少一个二极管中,任一二极管阴极端与相邻二极管阳极端连接形成串联结构,第一个二极管阳极端连接至第一电流镜管PM4的漏极端为所述阈值单元的输入端,最后一个二极管阴极端接地为所述阈值单元的输出端,如图10;
所述至少一个P型MOS管中,任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构,第一个所述P型MOS管的源极连接至第一电流镜管PM4的漏极端为所述阈值单元的输入端,最后一个P型MOS管的漏极接地为所述阈值单元的输出端,各P型MOS管的栅极均与漏极相连,如图11;
所述至少一个N型MOS管中,任一N型MOS管源极端与相邻N型MOS管的 漏极端连接形成串联结构,第一个所述N型MOS管的漏极连接至第一电流镜管PM4的漏极端为所述阈值单元的输入端,最后一个N型MOS管的源极接地为所述阈值单元的输出端,各N型MOS管的栅极均与漏极相连,如图12。
本发明另一目的在于提供一种包括上述具有多种时间常数的整流限幅电路的无源射频标签,所述该无源射频标签的整流限幅电路输出端并联连接有两路放电泄流通路,所述两路放电通路的控制端分别由第一控制电路和第二控制电路所控制,所述第一控制电路根据一组开关管的打开与关闭使得第一控制电路快速的在有输出信号与无输出信号之间切换,从而使受其控制的第一路放电泄流通路快速的在打开放电与关闭两种状态之间进行切换,实现对天线端电荷的快速泄放;而第二控制电路由于在输出端设有一组电容,使得第二控制电路在有输出信号与无输出信号之间切换的速度较慢,从而使受其控制的第二路放电泄流通路缓慢的在打开放电与关闭两种状态之间进行切换,实现对天线端电荷的慢速泄放。本发明通过对两路放电通路的控制端分别施予不同时间常数的,即以不同切换速度进行电压幅度调整的模拟控制信号,实现对两路放电通路的完全打开到完全关闭进行切换,根据天线端电荷量的大小以及标签所处于的能量水平情况进行适应性的放电,以提高标签的解调能力,并提升标签的读写距离。

Claims (13)

  1. 一种具有多种时间常数的整流限幅电路,其特征在于,所述电路包括:
    谐振电容,与谐振电感并联连接于第一天线端与第二天线端之间,用于与谐振电感组成谐振电路,接收外部电磁场并将其耦合至整流电路;
    整流电路,其输入端连接至第一天线端与第二天线端,用于将所述谐振电路耦合的交流电源转换为直流电源并输出至外部负载电路,同时其一路输出端通过并联连接的两路泄流通路接地,用于在场强过强时将电荷输出至地;
    所述两路泄流通路的输入端分别连接至整流电路的输出端,两路泄流通路的控制端分别由具有不同时间常数的第一控制电路和第二控制电路控制,所述两路泄流通路的输出端相连并接地。
  2. 根据权利要求1所述的具有多种时间常数的整流限幅电路,其特征在于,所述整流电路包括并联连接于第一天线端与第二天线端之间的第一整流支路和第二整流支路,所述第一整流支路的输出端连接至外部负载电路,所述第二整流支路的输出端通过并联连接的两路泄流通路接地。
  3. 根据权利要求2所述的具有多种时间常数的整流限幅电路,其特征在于,所述第二整流支路为连接于第一天线端与第二天线端之间的第五二极管和第六二极管,所述第五二极管和第六二极管阴极端相连并连接至所述两路泄流通路的输入端。
  4. 根据权利要求2所述的具有多种时间常数的整流限幅电路,其特征在于,所述第二整流支路为连接于第一天线端与第二天线端之间的第五二极管和第六二极管,以及第七二极管和第八二极管,所述第五二极管和第六二极管阴极端相连并连接至第一路泄流通路的输入端,所述第七二极管和第八二极管阴极端相连并连接至第二路泄流通路的输入端。
  5. 根据权利要求2所述的具有多种时间常数的整流限幅电路,其特征在于,所述第二整流支路为连接于第一天线端与第二天线端之间的第三N型MOS管和第四N型MOS管,所述第三N型MOS管栅极和漏极分别连接至第一天线端,第四N型MOS管栅极和漏极分别连接至第二天线端,第三N型MOS管源极连接至第四N型MOS管源极并连接至所述两路泄流通路的输入端。
  6. 根据权利要求2所述的具有多种时间常数的整流限幅电路,其特征在于,所述第二整流支路为连接于第一天线端与第二天线端之间的第三N型MOS管和第四N型MOS管,以及第十N型MOS管和第十一N型MOS管,所述第三N型MOS管栅极和漏极分别连接至第一天线端,第四N型MOS管栅极和漏极分别连接至第二天线端,第三N型MOS管源极连接至第四N型MOS管源极并连接至第一路泄流通路的输入端;所述第十N型MOS管栅极和漏极分别连接至第一天线端,第十一N型MOS管栅极和漏极分别连接至第二天线端,第十N型MOS管源极连接至第十一N型MOS管源极并连接至第二路泄流通路的输入端。
  7. 根据权利要求1所述的具有多种时间常数的整流限幅电路,其特征在于,所述两路泄流通路为并联连接的第一N型MOS管和第二N型MOS管,所述第一N型MOS管和第二N型MOS管的漏极连接至所述整流电路的输出端,第一N型MOS管的栅极接第一控制电路输出端,源极接地,第二N型MOS管的栅极接第二控制电路输出端,源极接地。
  8. 根据权利要求1所述的具有多种时间常数的整流限幅电路,其特征在于,所述第一控制电路包括第二电流镜管、第一电阻、第二电阻、第五N型MOS管、第六N型MOS管以及第一P型MOS管,
    所述第二电流镜管源极连接至电源端,漏极通过串联连接的第一电阻与第 二电阻接地,栅极连接至偏置电压端,所述第五N型MOS管的源极接所述第二电流镜管的漏极端,漏极接第一控制电路的输出端,其栅极接控制信号端,所述第一P型MOS管的源极接所述第二电流镜管的漏极端,漏极接所述第一控制电路的输出端,其栅极连接至所述第六N型MOS管的栅极,第六N型MOS管的漏极接所述第一控制电路的输出端,源极接地,所述第一P型MOS管的栅极和第六N型MOS管的栅极连接至与所述第五N型MOS管栅极端控制信号相反的控制信号端。
  9. 根据权利要求1所述的具有多种时间常数的整流限幅电路,其特征在于,所述第二控制电路包括第三电流镜管、第三电阻、第四电阻、逻辑串联开关单元、第一电容、第二电容,以及第七N型MOS管,
    所述第三电流镜管源极连接至电源端,漏极通过串联连接的第三电阻和第四电阻接地,栅极连接至偏置电压端,所述逻辑串联开关单元输入端连接至所述第三电流镜管的漏极端,输出端接第二控制电路的输出端,所述第一电容与第二电容并联连接,第一电容与第二电容的正极相连并连接至逻辑串联开关单元的输出端,第一电容与第二电容的负极相连并接地,所述第七N型MOS管的源极端接地,栅极接控制信号端,其漏极接所述第二控制电路的输出端。
  10. 根据权利要求9所述的具有多种时间常数的整流限幅电路,其特征在于,所述逻辑串联开关单元为至少一个逻辑开关,所述至少一个逻辑开关中,第八N型MOS管的源极端与第二P型MOS管的源极端相连并连接至所述第三电流镜管的漏极端作为所述逻辑串联开关单元的输入端,所述第八N型MOS管的漏极端与第二P型MOS管的漏极端相连作为所述逻辑串联开关单元的输出端,所述第八N型MOS管的栅极端接控制信号端,所述第二P型MOS管的栅极端连 接至与所述第八N型MOS管栅极端控制信号相反的控制信号端。
  11. 根据权利要求1所述的具有多种时间常数的整流限幅电路,其特征在于,所述第一控制电路通过第二电流镜管连接至电源端,第二控制电路通过第三电流镜管连接至电源端,所述第二电流镜管和第三电流镜管栅极分别连接至第一电流镜管的栅极端,所述第一电流镜管的源极连接至电源端,漏极通过阈值单元接地。
  12. 根据权利要求11所述的具有多种时间常数的整流限幅电路,其特征在于,所述阈值单元为至少一个串联连接的二极管,或者是至少一个串联连接的P型MOS管,或者是至少一个串联连接的N型MOS管,
    所述至少一个二极管中,任一二极管阴极端与相邻二极管阳极端连接形成串联结构,第一个二极管阳极端连接至第一电流镜管的漏极端为所述阈值单元的输入端,最后一个二极管阴极端接地为所述阈值单元的输出端;
    所述至少一个P型MOS管中,任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构,第一个所述P型MOS管的源极连接至第一电流镜管的漏极端为所述阈值单元的输入端,最后一个P型MOS管的漏极接地为所述阈值单元的输出端,各P型MOS管的栅极均与漏极相连;
    所述至少一个N型MOS管中,任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构,第一个所述N型MOS管的漏极连接至第一电流镜管的漏极端为所述阈值单元的输入端,最后一个N型MOS管的源极接地为所述阈值单元的输出端,各N型MOS管的栅极均与漏极相连。
  13. 一种无源射频标签,其特征在于,所述无源射频标签包括如权利要求1-12中任一所述的具有多种时间常数的整流限幅电路。
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