WO2015101146A1 - 功率放大器输出功率控制电路 - Google Patents

功率放大器输出功率控制电路 Download PDF

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Publication number
WO2015101146A1
WO2015101146A1 PCT/CN2014/093425 CN2014093425W WO2015101146A1 WO 2015101146 A1 WO2015101146 A1 WO 2015101146A1 CN 2014093425 W CN2014093425 W CN 2014093425W WO 2015101146 A1 WO2015101146 A1 WO 2015101146A1
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Prior art keywords
pmos transistor
current
power
resistor
drain
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PCT/CN2014/093425
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English (en)
French (fr)
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赵骞
张黎阳
龙华
程珍娟
唐东杰
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国民技术股份有限公司
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Application filed by 国民技术股份有限公司 filed Critical 国民技术股份有限公司
Publication of WO2015101146A1 publication Critical patent/WO2015101146A1/zh
Priority to US15/139,087 priority Critical patent/US9595933B2/en
Priority to US15/418,748 priority patent/US9887679B2/en
Priority to US15/853,835 priority patent/US10044334B2/en
Priority to US15/853,950 priority patent/US9973164B1/en
Priority to US15/854,738 priority patent/US10044335B2/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the invention belongs to the field of power amplifiers, and in particular to a power amplifier output power control circuit.
  • the output power of the power amplifier needs to be controlled.
  • the power amplifiers are required to output different output powers.
  • first limiting the power supply voltage of the amplifier.
  • the output of the power controller acts as the supply voltage of the amplifier, and the output of the power controller is controlled by the Ramp signal (ramp signal) so that the power supply voltage of the amplifier follows the Ramp signal change, thereby achieving output power control.
  • the power coupler detects the output power through the directional coupler on the periphery of the chip, returns the power value to the baseband, and the baseband changes the output power correspondingly through the power controller (or adjusts the input power), and the power control is realized by the feedback.
  • the third requires an additional power coupler design, and the design cost is high; the first and second common defects are the power mismatch resulting in power mismatch, which is not affected by power control feedback. The effects of the loop, resulting in inaccurate power control.
  • a power amplifier output power control circuit comprising:
  • a first PMOS transistor a gate connected to an output end of the first operational amplifier, a source connected to an external power source, and a drain connected to the ground through the voltage dividing network;
  • the power terminal is connected to the drain of the first PMOS transistor, the input terminal is connected to the signal to be amplified, and the output terminal is amplified;
  • a current sampling module forming a sampling current for current sampling of the first PMOS transistor, and providing a negative feedback signal to a positive input end of the first operational amplifier according to the sampling current, so that a total output power of the power amplifier is unchanged And wherein the negative feedback signal is input to a positive input terminal of the first operational amplifier through the voltage dividing network.
  • the current sampling module includes one or more PMOS transistors, and the one or more PMOS transistors form a mirror relationship with the first PMOS transistor to replicate the current of the first PMOS transistor, and according to The current is adjusted to output the negative feedback signal; or
  • the current sampling module samples the current of the first PMOS transistor and outputs the negative feedback signal after the current-voltage-current conversion.
  • the negative feedback signal is a current signal, the negative feedback The signal is inversely proportional to the voltage value of the power supply terminal of the power amplifier.
  • the current sampling module includes a second PMOS transistor, a second current mirror, and a third current mirror
  • the second PMOS transistor forms a first current mirror with the first PMOS transistor, the first A current mirror, the second current mirror, and the third current mirror are sequentially connected, and the third current mirror outputs the negative feedback signal.
  • the second current mirror includes a first NMOS transistor and a second NMOS transistor
  • the third current mirror includes a third PMOS transistor and a fourth PMOS transistor
  • a gate of the second PMOS transistor is connected to an output end of the first operational amplifier, and a source is connected to the power source, a drain and a drain of the first NMOS transistor;
  • a gate of the first NMOS transistor is connected to a drain of the first NMOS transistor and a gate of the second NMOS transistor, a source of the first NMOS transistor and the second NMOS transistor is grounded, and a drain of the second NMOS transistor a pole is connected to a drain of the third PMOS transistor;
  • a gate of the third PMOS transistor is connected to a drain of the third PMOS transistor, and a source of the third PMOS transistor and the fourth PMOS transistor are connected to the power source.
  • the drain of the four PMOS transistors outputs the negative feedback signal.
  • the current sampling module further includes a second operational amplifier, and the positive input terminal and the negative input terminal of the second operational amplifier are respectively drained with the first PMOS transistor and the second PMOS transistor The poles are connected, and the output of the second operational amplifier is connected to the gates of the first PMOS transistor and the second PMOS transistor.
  • the current sampling module includes a second PMOS transistor that forms a first current mirror with the first PMOS transistor and a turn for current-voltage-current conversion Change device
  • a gate of the second PMOS transistor is connected to an output end of the first operational amplifier, a source is connected to the power source, a drain is connected to an input end of the conversion device, and an output end of the conversion device outputs the Negative feedback signal.
  • the current sampling module further includes a second operational amplifier, and the positive input terminal and the negative input terminal of the second operational amplifier are respectively drained with the first PMOS transistor and the second PMOS transistor The poles are connected, and the output of the second operational amplifier is connected to the gates of the first PMOS transistor and the second PMOS transistor.
  • the voltage dividing network includes a first resistor and a second resistor, the first end of the first resistor is connected to the negative feedback signal and is coupled to the positive input terminal of the first operational amplifier Connected, the second end of the first resistor is grounded; the first end of the second resistor is connected to the drain of the first PMOS transistor, and the second end is connected to the first end of the first resistor.
  • the voltage dividing network includes a first resistor, a third resistor, and a fourth resistor, a first end of the first resistor being coupled to a positive input terminal of the first operational amplifier, and a second terminal Grounding; the first end of the third resistor is connected to the negative feedback signal, the second end is connected to the first end of the first resistor; the first end of the fourth resistor is opposite to the first PMOS tube a drain connection, the second end being coupled to the first end of the third resistor.
  • the current sampled and fed back adjusts the voltage value of the power terminal of the power amplifier, when the current of the first PMOS transistor becomes larger, The voltage value becomes small, and when the current of the first PMOS transistor becomes small, the voltage value becomes large, and thus can be maintained
  • the total output power of the power amplifier is unchanged, thereby weakening the correspondence between the load impedance change and the output power, so that the power control is more accurate.
  • FIG. 1 is a block diagram showing an embodiment of a power amplifier output power control circuit
  • FIG. 2 is a circuit schematic diagram of a power amplifier gain attenuating circuit in an embodiment
  • FIG. 3 is a circuit schematic diagram of a power amplifier gain attenuating circuit in another embodiment
  • FIG. 4 is a block diagram of a power amplifier output power control circuit in another embodiment.
  • the power amplifier output power control circuit includes a first operational amplifier AMP0, a first PMOS transistor MP0, a power amplifier AMP2, a current sampling module 102, and a voltage dividing network 104.
  • the first operational amplifier AMP0, the first PMOS transistor MP0 and the power amplifier AMP2 constitute a power controller 101
  • the power amplifier AMP2 is a radio frequency power amplifier
  • the power controller 101 is controlled by the size of the power control signal Vramp. The magnitude of the voltage at the power supply terminal of the power amplifier AMP2, thereby achieving power control of the power amplifier AMP2.
  • the negative input terminal of the first operational amplifier AMP0 receives the power control signal Vramp;
  • the gate of the first PMOS transistor MP0 is connected to the output terminal of the first operational amplifier AMP0, the source of the first PMOS transistor MP0 is connected to the external power supply, and the drain of the first PMOS transistor MP0 is grounded through the voltage dividing network 104;
  • the power amplifier AMP2 The power terminal Vcc is connected to the drain of the first PMOS transistor MP0, the input terminal of the power amplifier AMP2 is connected to the signal RFin to be amplified, and the output terminal of the power amplifier AMP2 amplifies the signal RFout to the load (not shown); the current sampling module 102 pairs
  • the current Icc of a PMOS transistor MP0 (refers to the drain current of the first PMOS transistor MP0) is sampled to form a sampling current Isense, and a negative feedback signal Ifeedback is supplied to the positive input terminal of the first operational amplifier AMP0 according to the sampling current Isense, so that the power
  • the negative feedback signal Ifeedback is a current signal
  • the negative feedback signal Ifeedback is inversely proportional to the voltage value of the power supply terminal Vcc of the power amplifier AMP2.
  • the current sampling module 102 proportionally samples the current Icc flowing through the first PMOS transistor MP0 to form a sampling current Isense, and the negative feedback signal (current) Ifeedback after adjusting the sampling current Isense to an appropriate ratio is fed back to the Vx of the conventional power controller 101. (ie the positive input of the first operational amplifier AMP0) is on the point.
  • the principle is that when the load change of the power amplifier AMP2 causes the current Icc to change, the sampled and fed back signal Ifeedback adjusts the voltage value of the power supply terminal Vcc of the power amplifier AMP2, so that the total output power of the amplified signal RFout of the output of the power amplifier AMP2 can be maintained. It is unchanged, so as to weaken the correspondence between the load impedance change and the output power, so that the power control is more accurate.
  • the current sampling module 102 includes one or a plurality of PMOS transistors, the one or more PMOS transistors forming a mirror relationship with the first PMOS transistor MP0 to replicate the current Icc of the first PMOS transistor, and adjusting the current Icc according to the first PMOS transistor MP0 to output a negative feedback signal Ifeedback .
  • the current sampling module 102 includes a second PMOS transistor MP1, a second current mirror 202, and a connected third current mirror 203.
  • the second PMOS transistor MP1 forms a first current mirror 201 with the first PMOS transistor MP0.
  • the first current mirror 201, the second current mirror 202, and the third current mirror 203 are sequentially connected, and the third current mirror 203 outputs a negative feedback signal Ifeedback.
  • the second current mirror 202 includes a first NMOS transistor MN0, a second NMOS transistor MN1, and the third current mirror image 203 includes a third PMOS transistor MP2 and a fourth PMOS transistor MP3.
  • the gate of the second PMOS transistor MP1 is connected to the output terminal of the first operational amplifier AMP0, the source of the second PMOS transistor MP1 is connected to the power supply, the drain of the second PMOS transistor MP1 and the drain of the first NMOS transistor MN0;
  • the gate of the NMOS transistor MN0 is connected to its own drain and the gate of the second NMOS transistor MN1, the sources of the first NMOS transistor MN0 and the second NMOS transistor MN1 are grounded, and the drain of the second NMOS transistor MN1 and the third PMOS
  • the drain of the transistor MP2 is connected; the gate of the third PMOS transistor MP2 is connected to the drain of the third PMOS transistor MP3, and the source of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 is connected to the power source, and the fourth The drain of the PMOS transistor MP3 outputs a negative feedback signal Ifeedback.
  • the second current mirror 202 and the third current mirror 203 can be removed for circuits that do not require high image accuracy.
  • the current sampling module 102 samples the first PMOS.
  • the current Icc of the tube MP0, and the negative feedback signal Ifeedback is output after the current-voltage-current conversion.
  • the current sampling module 102 includes a second PMOS transistor MP1 that forms a first current mirror 201 with the first PMOS transistor MP0 and a conversion device 204 for current-voltage-current conversion.
  • the gate of the second PMOS transistor MP1 is connected to the output terminal of the first operational amplifier AMP0, the source of the second PMOS transistor MP1 is connected to the power source, and the drain of the second PMOS transistor MP1 is connected to the input terminal of the conversion device 204, and the conversion device 204
  • the output terminal outputs a negative feedback signal Ifeedback, and the conversion device 204 can be a current voltage conversion chip.
  • the current-voltage conversion can realize a certain gate voltage through the NMOS transistor connected by the gate and drain, and can also realize the resistance voltage drop by the current flowing through the resistor; the voltage-current conversion can also be realized by the gate-connected MOS tube or the resistor. The voltage difference across the terminals achieves current.
  • the current sampling module 102 further includes a second operational amplifier, and the positive input terminal and the negative input terminal of the second operational amplifier are respectively connected to the first PMOS transistor MP0 and the second PMOS transistor MP1.
  • the drain is connected, and the output of the second operational amplifier is connected to the gates of the first PMOS transistor MP0 and the second PMOS transistor MP1.
  • the positive input terminal of the second operational amplifier AMP1 is connected to the drain terminal of the first PMOS transistor MP0 to realize precise current mirroring of the first PMOS transistor MP0 and the second PMOS transistor MP1.
  • the core function of the second operational amplifier AMP1 is to force the drain terminals of the first PMOS transistor MP0 and the second PMOS transistor MP1 to be equal, so that the mirror image is more accurate. For circuits that do not require high image accuracy, the second operational amplifier AMP1 can be removed.
  • the voltage dividing network 104 includes a first resistor R1 and a second resistor R0.
  • the first end of the first resistor R1 is connected to a negative feedback signal Ifeedback, and is coupled to the first operational amplifier AMP0.
  • the positive input terminal is connected, the second end of the first resistor R1 is grounded; the first end of the second resistor R0 is connected to the drain of the first PMOS transistor MP0, and the second end of the second resistor R0 is connected to the first resistor R1 Connected at one end.
  • the positive input terminal of the first operational amplifier AMP0 (ie, at the Vx point of the power controller 101) will have a voltage equal to the negative input terminal voltage of the first operational amplifier AMP0 (power control signal Vramp).
  • the relationship between the voltage value "Vcc" of the power supply terminal Vcc of the GaAs power amplifier AMP2 and the voltage value "Vx" of the positive input terminal of the first operational amplifier AMP0 and the voltage value "Vramp" of the negative input terminal of the first operational amplifier AMP0 is as follows :
  • R0 and R1 in the equation are the resistance values of the second resistor R0 and the first resistor R1, respectively.
  • the feedback point of the negative feedback signal Ifeedback is not limited only to the positive input terminal (Vx point) of the first operational amplifier, and the second resistor R0 can be split into two resistors: a third resistor R02 and a The four resistor R01, that is, the voltage dividing network 104 includes a first resistor R1, a third resistor R02, and a fourth resistor R01.
  • the first end of the first resistor R1 is connected to the positive input terminal of the first operational amplifier AMP0, the second end of the first resistor R1 is grounded; the first end of the third resistor R02 is connected to the negative feedback signal Ifeedback, and the third resistor R02 The second end is connected to the first end of the first resistor R1; the first end of the fourth resistor R01 is connected to the drain of the first PMOS transistor MP0, and the second end of the fourth resistor R01 is connected to the third resistor R02 The first end of the connection.
  • the sum of the resistance values of the fourth resistor R01 and the third resistor R02 is equal to the resistance value of the second resistor R0, and the negative feedback signal Ifeedback can be fed back to the intermediate point position of the fourth resistor R01 and the third resistor R02.
  • the load impedance change causes the Icc of the first PMOS transistor MP0 to become larger
  • the current flowing through the second PMOS transistor MP1 and the first NMOS transistor MN0 increases, and flows through the second.
  • the currents of the NMOS transistor MN1 and the third PMOS transistor MP2 also increase, and the current flowing through the fourth PMOS transistor MP3 also increases.
  • the potential of the positive input terminal of the first operational amplifier AMP0 is controlled by the feedback loop, which is equal to the potential of the negative input terminal of the first operational amplifier AMP0, so the current flowing through the first resistor R1 is always equal to Vramp/R1.
  • PMOS transistor and NMOS transistor are a P-channel MOS transistor and an N-channel MOS transistor, respectively.
  • a communication terminal including the power amplifier output power control circuit described above.
  • the communication terminal can be a mobile phone, a PAD, a walkie-talkie, or the like.

Abstract

一种功率放大器输出功率控制电路，与功率放大器连接，包括：第一运算放大器（AMP0），负输入端接收功率控制信号；第一PMOS管，栅极与第一运算放大器（AMP0）的输出端连接、源极接外部电源、漏极通过一分压网络（104）接地；功率放大器的电源端与第一PMOS管的漏极连接、输入端接入待放大信号、输出端放大信号；电流采样模块（102），对第一PMOS管的电流采样形成采样电流，根据采样电流向第一运算放大器（AMP0）的正输入端提供负反馈信号，使得功率放大器的总输出功率不变。该方案可以维持功率放大器总输出功率不变，从而实现弱化负载阻抗变化与输出功率之间的对应关系，使得功率控制更加精确。

Description

功率放大器输出功率控制电路 技术领域
本发明属于功率放大器领域，尤其涉及一种功率放大器输出功率控制电路。
背景技术
在功率放大器设计中，尤其是饱和功率放大器设计中，需要对功率放大器的输出功率做控制，在不同通讯强度的应用环境中，要求功率放大器可以输出不同的输出功率。
目前，常规的功率控制方法有三种：第一，限制放大器的电源电压。功率控制器的输出作为放大器的电源电压，通过Ramp信号(斜坡信号)控制功率控制器的输出，使得放大器的电源电压跟随Ramp信号变化，从而实现输出功率控制。第二，电流检测反馈型。通过检测放大器的工作电流，反馈给基带做处理，基带再通过功率控制器改变放大器的工作电流，通过该反馈完成功率控制。第三，功率耦合器，通过芯片外围的定向耦合器检测输出功率，将功率值返回给基带，基带通过功率控制器(或者调整输入功率)相应改变输出功率，通过该反馈实现功率控制。
以上三种方法中，第三种需要额外的功率耦合器设计，设计成本偏高；第一种和第二种共有的缺陷是功率放大器的负载失配导致功率变化，该变化不受功率控制反馈环的影响，从而导致功率控制不够准确。
发明内容
基于此，有必要提供一种通过负反馈弱化功率放大器的负载失配与输出功率的关系，使得功率控制更为准确的功率放大器输出功率控制电路。
一种功率放大器输出功率控制电路，包括：
分压网络；
第一运算放大器，负输入端接收功率控制信号；
第一PMOS管，栅极与所述第一运算放大器的输出端连接，源极接外部电源，漏极通过所述分压网络接地；
功率放大器，电源端与所述第一PMOS管的漏极连接，输入端接入待放大信号，输出端放大信号；
电流采样模块，对所述第一PMOS管的电流采样形成采样电流，根据所述采样电流向所述第一运算放大器的正输入端提供负反馈信号，使得所述功率放大器的总输出功率不变，其中，所述负反馈信号通过所述分压网络输入到所述第一运算放大器的正输入端。
在其中一个实施例中，所述电流采样模块包括一个或多个PMOS管，该一个或多个PMOS管与所述第一PMOS管形成镜像关系以复制所述第一PMOS管的电流，且根据该电流加以调整后输出所述负反馈信号；或
所述电流采样模块采样所述第一PMOS管的电流，并通过电流-电压-电流的转换后输出所述负反馈信号。
在其中一个实施例中，所述负反馈信号为电流信号，所述负反馈 信号与所述功率放大器的电源端的电压值成反比。
在其中一个实施例中，所述电流采样模块包括第二PMOS管、第二电流镜像和第三电流镜像，所述第二PMOS管与所述第一PMOS管形成第一电流镜像，所述第一电流镜像、所述第二电流镜像和所述第三电流镜像依次连接，所述第三电流镜像输出所述负反馈信号。
在其中一个实施例中，所述第二电流镜像包括第一NMOS管、第二NMOS管，所述第三电流镜像包括第三PMOS管和第四PMOS管；
所述第二PMOS管的栅极与所述第一运算放大器的输出端连接，源极接所述电源，漏极与所述第一NMOS管的漏极；
所述第一NMOS管的栅极与本身的漏极以及所述第二NMOS管的栅极连接，所述第一NMOS管和第二NMOS管的源极接地，所述第二NMOS管的漏极与所述第三PMOS管的漏极连接；
所述第三PMOS管的栅极与本身的漏极以及所述第四PMOS管的栅极连接，所述第三PMOS管和所述第四PMOS管的源极接所述电源，所述第四PMOS管的漏极输出所述负反馈信号。
在其中一个实施例中，所述电流采样模块还包括第二运算放大器，所述第二运算放大器的正输入端和负输入端分别与所述第一PMOS管和所述第二PMOS管的漏极连接，所述第二运算放大器的输出端与所述第一PMOS管和所述第二PMOS管的栅极连接。
在其中一个实施例中，所述电流采样模块包括与所述第一PMOS管形成第一电流镜像的第二PMOS管和用于电流-电压-电流转换的转 换装置；
所述第二PMOS管的栅极与所述第一运算放大器的输出端连接，源极接所述电源，漏极与所述转换装置的输入端连接，所述转换装置的输出端输出所述负反馈信号。
在其中一个实施例中，所述电流采样模块还包括第二运算放大器，所述第二运算放大器的正输入端和负输入端分别与所述第一PMOS管和所述第二PMOS管的漏极连接，所述第二运算放大器的输出端与所述第一PMOS管和所述第二PMOS管的栅极连接。
在其中一个实施例中，所述分压网络包括第一电阻和第二电阻，所述第一电阻的第一端接入所述负反馈信号，并与所述第一运算放大器的正输入端连接，所述第一电阻的第二端接地；所述第二电阻的第一端与所述第一PMOS管的漏极连接，第二端与所述第一电阻的第一端连接。
在其中一个实施例中，所述分压网络包括第一电阻、第三电阻和第四电阻，所述第一电阻的第一端与所述第一运算放大器的正输入端连接，第二端接地；所述第三电阻的第一端接入所述负反馈信号，第二端与所述第一电阻的第一端连接；所述第四电阻的第一端与所述第一PMOS管的漏极连接，第二端与所述第三电阻的第一端连接。
上述功率放大器输出功率控制电路中，当功率放大器负载变化引起第一PMOS管的电流变化时，采样并反馈的电流会调整功率放大器的电源端的电压值，当第一PMOS管的电流变大时，该电压值变小，当第一PMOS管的电流变小时，该电压值变大，因此可以维持 功率放大器总输出功率不变，从而实现弱化负载阻抗变化与输出功率之间的对应关系，使得功率控制更加精确。
附图说明
图1是一个实施例功率放大器输出功率控制电路的模块示意图；
图2是一个实施例中的功率放大器增益衰减电路的电路原理图；
图3是另一个实施例中的功率放大器增益衰减电路的电路原理图；
图4是另一个实施例中功率放大器输出功率控制电路的模块示意图。
具体实施方式
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
结合图1至4，功率放大器输出功率控制电路包括第一运算放大器AMP0、第一PMOS管MP0、功率放大器AMP2、电流采样模块102和分压网络104。其中，参考图3和4，第一运算放大器AMP0、第一PMOS管MP0和功率放大器AMP2构成功率控制器101，功率放大器AMP2为射频功率放大器，功率控制器101通过功率控制信号Vramp的大小来控制功率放大器AMP2的电源端的电压值大小，从而实现对功率放大器AMP2的功率控制。
第一运算放大器AMP0的负输入端接收功率控制信号Vramp； 第一PMOS管MP0的栅极与第一运算放大器AMP0的输出端连接，第一PMOS管MP0的源极接外部电源，第一PMOS管MP0的漏极通过分压网络104接地；功率放大器AMP2的电源端Vcc与第一PMOS管MP0的漏极连接，功率放大器AMP2的输入端接入待放大信号RFin，功率放大器AMP2的输出端放大信号RFout到负载(图未示)；电流采样模块102对第一PMOS管MP0的电流Icc(指的是第一PMOS管MP0的漏极电流)采样形成采样电流Isense，且根据采样电流Isense向第一运算放大器AMP0的正输入端提供负反馈信号Ifeedback，使得功率放大器AMP2的总输出功率不变，其中，负反馈信号Ifeedback通过分压网络104输入到第一运算放大器AMP0的正输入端。
更具体地，负反馈信号Ifeedback为电流信号，负反馈信号Ifeedback与功率放大器AMP2的电源端Vcc的电压值成反比。电流采样模块102等比例采样流过第一PMOS管MP0的电流Icc，形成采样电流Isense，将采样电流Isense调整为适当比例之后的负反馈信号(电流)Ifeedback反馈到传统的功率控制器101的Vx(即第一运算放大器AMP0的正输入端)点上。其原理是，当功率放大器AMP2负载变化引起电流Icc变化时，采样并反馈的信号Ifeedback会调整功率放大器AMP2的电源端Vcc的电压值，因此可以维持功率放大器AMP2的输出的放大信号RFout总输出功率不变，从而实现弱化负载阻抗变化与输出功率之间的对应关系，使得功率控制更加精确。
参考图2，在其中一个实施例中，电流采样模块102包括一个或 多个PMOS管，该一个或多个PMOS管与第一PMOS管MP0形成镜像关系以复制第一PMOS管的电流Icc，且根据该第一PMOS管MP0的电流Icc加以调整后输出负反馈信号Ifeedback。
在进一步的实施例中，电流采样模块102包括第二PMOS管MP1、第二电流镜像202和连接的第三电流镜像203，第二PMOS管MP1与第一PMOS管MP0形成第一电流镜像201，第一电流镜像201、第二电流镜像202和所述第三电流镜像203依次连接，第三电流镜像203输出负反馈信号Ifeedback。
在进一步的实施例中，第二电流镜像202包括第一NMOS管MN0、第二NMOS管MN1，第三电流镜像203包括第三PMOS管MP2和第四PMOS管MP3。
第二PMOS管MP1的栅极与第一运算放大器AMP0的输出端连接、第二PMOS管MP1的源极接电源、第二PMOS管MP1的漏极与第一NMOS管MN0的漏极；第一NMOS管MN0的栅极与本身的漏极以及第二NMOS管MN1的栅极连接，第一NMOS管MN0和第二NMOS管MN1的源极接地，第二NMOS管MN1的漏极与第三PMOS管MP2的漏极连接；第三PMOS管MP2的栅极与本身的漏极以及第四PMOS管MP3的栅极连接，第三PMOS管MP2和第四PMOS管MP3的源极接电源，第四PMOS管MP3的漏极输出负反馈信号Ifeedback。对镜像精确度要求不高的电路，可以去除第二电流镜像202和第三电流镜像203。
参考图3，在另一个实施例中，电流采样模块102采样第一PMOS 管MP0的电流Icc，并通过电流-电压-电流的转换后输出负反馈信号Ifeedback。
在进一步实施例中，电流采样模块102包括与第一PMOS管MP0形成第一电流镜像201的第二PMOS管MP1和用于电流-电压-电流转换的转换装置204。
第二PMOS管MP1的栅极与第一运算放大器AMP0的输出端连接，第二PMOS管MP1的源极接电源，第二PMOS管MP1的漏极与转换装置204的输入端连接，转换装置204的输出端输出负反馈信号Ifeedback，转换装置204可以是电流电压转换芯片。
另外，电流-电压转换可以通过栅漏连接的NMOS管实现一定栅电压，也可以通过流经电阻的电流实现电阻压降；电压-电流转换同样可以采用栅连接的MOS管实现，也可以利用电阻两端的电压差实现电流。
参考图2和3，在优选的实施例中，电流采样模块102还包括第二运算放大器，第二运算放大器的正输入端和负输入端分别与第一PMOS管MP0和第二PMOS管MP1的漏极连接，第二运算放大器的输出端与第一PMOS管MP0和第二PMOS管MP1的栅极连接。
第二运算放大器AMP1的正输入端接第一PMOS管MP0的漏端，实现第一PMOS管MP0和第二PMOS管MP1的精确电流镜像。特别地，第二运算放大器AMP1的核心作用是强迫第一PMOS管MP0和第二PMOS管MP1的漏端电压相等，使得镜像更加准确。对镜像精确度要求不高的电路，可以去除第二运算放大器AMP1。
在其中一个实施例中，参考图1至3，分压网络104包括第一电阻R1和第二电阻R0，第一电阻R1的第一端接入负反馈信号Ifeedback，并与第一运算放大器AMP0的正输入端连接，第一电阻R1的第二端接地；第二电阻R0的第一端与第一PMOS管MP0的漏极连接，第二电阻R0的第二端与第一电阻R1的第一端连接。
参考图2，通过该连接的负反馈作用，第一运算放大器AMP0的正输入端(即功率控制器101的Vx点处)电压将等于第一运算放大器AMP0的负输入端电压(功率控制信号Vramp)，GaAs功率放大器AMP2的电源端Vcc的电压值“Vcc”与第一运算放大器AMP0的正输入端的电压值“Vx”以及第一运算放大器AMP0的负输入端的电压值“Vramp”的关系如下式：
Figure PCTCN2014093425-appb-000001
其中，式中的R0、R1分别是第二电阻R0和第一电阻R1的电阻值。
在另一个实施例中，负反馈信号Ifeedback的反馈点不仅仅限制于第一运算放大器的正输入端(Vx点)，可以将第二电阻R0拆分成两个电阻：第三电阻R02和第四电阻R01，即分压网络104包括第一电阻R1、第三电阻R02和第四电阻R01。第一电阻R1的第一端与第一运算放大器AMP0的正输入端连接，第一电阻R1的第二端接地；第三电阻R02的第一端接入负反馈信号Ifeedback，第三电阻R02的第二端与第一电阻R1的第一端连接；第四电阻R01的第一端与第一PMOS管MP0的漏极连接，第四电阻R01的第二端与第三电阻R02 的第一端连接。第四电阻R01和第三电阻R02的电阻值之和等于第二电阻R0的电阻值，负反馈信号Ifeedback可以反馈在第四电阻R01和第三电阻R02的中间点位置。
以图2实施例为例说明电路工作原理，假设负载阻抗变化导致第一PMOS管MP0的Icc变大，则流过第二PMOS管MP1以及第一NMOS管MN0的电流增大，流过第二NMOS管MN1和第三PMOS管MP2的电流也增大，流过第四PMOS管MP3的电流也增大。第一运算放大器AMP0的正输入端电位受反馈环路控制，恒等于第一运算放大器AMP0的负输入端电位，因此流过第一电阻R1的电流恒等于Vramp/R1。当第四PMOS管MP3的电流增大了，而流过第一电阻R1的电流不变，必然导致流过第二电阻R0的电流减小，从而导致第二电阻R0两端的压降减小，即功率放大器AMP2的电源端Vcc的电压值降低，总之，电流Icc增大时功率放大器AMP2的电源端Vcc的电压值降低，总输出功率可以维持不变。假设负载阻抗变化导致电流Icc变小，同理可以推出功率放大器AMP2的电源端Vcc的电压值升高，总输出功率可以维持不变。
可以理解的是，上述的PMOS管和NMOS管分别为P沟道MOS管和N沟道MOS管。
此外，还提供了一种通信终端，包括上述的功率放大器输出功率控制电路。该通信终端可以是手机、PAD、对讲机等。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等， 均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种功率放大器输出功率控制电路，其特征在于，包括：
    分压网络；
    第一运算放大器，负输入端接收功率控制信号；
    第一PMOS管，栅极与所述第一运算放大器的输出端连接，源极接外部电源，漏极通过所述分压网络接地；
    功率放大器，电源端与所述第一PMOS管的漏极连接，输入端接入待放大信号，输出端放大信号；
    电流采样模块，对所述第一PMOS管的电流采样形成采样电流，根据所述采样电流向所述第一运算放大器的正输入端提供负反馈信号，使得所述功率放大器的总输出功率不变，其中，所述负反馈信号通过所述分压网络输入到所述第一运算放大器的正输入端。
  2. 根据权利要求1所述的功率放大器输出功率控制电路，其特征在于，所述电流采样模块包括一个或多个PMOS管，该一个或多个PMOS管与所述第一PMOS管形成镜像关系以复制所述第一PMOS管的电流，且根据该电流加以调整后输出所述负反馈信号；或
    所述电流采样模块采样所述第一PMOS管的电流，并通过电流-电压-电流的转换后输出所述负反馈信号。
  3. 根据权利要求1或2所述的功率放大器输出功率控制电路，其特征在于，所述负反馈信号为电流信号，所述负反馈信号与所述功率放大器的电源端的电压值成反比。
  4. 根据权利要求1或2所述的功率放大器输出功率控制电路，其特征在于，所述电流采样模块包括第二PMOS管、第二电流镜像和第三电流镜像，所述第二PMOS管与所述第一PMOS管形成第一电流镜像，所述第一电流镜像、所述第二电流镜像和所述第三电流镜像依次连接，所述第三电流镜像输出所述负反馈信号。
  5. 根据权利要求4所述的功率放大器输出功率控制电路，其特征在于，所述第二电流镜像包括第一NMOS管、第二NMOS管，所述第三电流镜像包括第三PMOS管和第四PMOS管；
    所述第二PMOS管的栅极与所述第一运算放大器的输出端连接、源极接所述电源、漏极与所述第一NMOS管的漏极；
    所述第一NMOS管的栅极与本身的漏极以及所述第二NMOS管的栅极连接，所述第一NMOS管和第二NMOS管的源极接地，所述第二NMOS管的漏极与所述第三PMOS管的漏极连接；
    所述第三PMOS管的栅极与本身的漏极以及所述第四PMOS管的栅极连接，所述第三PMOS管和所述第四PMOS管的源极接所述电源，所述第四PMOS管的漏极输出所述负反馈信号。
  6. 根据权利要求4所述的功率放大器输出功率控制电路，其特征在于，所述电流采样模块还包括第二运算放大器，所述第二运算放大器的正输入端和负输入端分别与所述第一PMOS管和所述第二PMOS管的漏极连接，所述第二运算放大器的输出端与所述第一PMOS管和所述第二PMOS管的栅极连接。
  7. 根据权利要求1或2所述的功率放大器输出功率控制电路， 其特征在于，所述电流采样模块包括与所述第一PMOS管形成第一电流镜像的第二PMOS管和用于电流-电压-电流转换的转换装置；
    所述第二PMOS管的栅极与所述第一运算放大器的输出端连接，源极接所述电源，漏极与所述转换装置的输入端连接，所述转换装置的输出端输出所述负反馈信号。
  8. 根据权利要求7所述的功率放大器输出功率控制电路，其特征在于，所述电流采样模块还包括第二运算放大器，所述第二运算放大器的正输入端和负输入端分别与所述第一PMOS管和所述第二PMOS管的漏极连接，所述第二运算放大器的输出端与所述第一PMOS管和所述第二PMOS管的栅极连接。
  9. 根据权利要求1所述的功率放大器输出功率控制电路，其特征在于，所述分压网络包括第一电阻和第二电阻，所述第一电阻的第一端接入所述负反馈信号，并与所述第一运算放大器的正输入端连接，所述第一电阻的第二端接地；所述第二电阻的第一端与所述第一PMOS管的漏极连接，第二端与所述第一电阻的第一端连接。
  10. 根据权利要求1所述的功率放大器输出功率控制电路，其特征在于，所述分压网络包括第一电阻、第三电阻和第四电阻，所述第一电阻的第一端与所述第一运算放大器的正输入端连接，第二端接地；所述第三电阻的第一端接入所述负反馈信号，第二端与所述第一电阻的第一端连接；所述第四电阻的第一端与所述第一PMOS管的漏极连接，第二端与所述第三电阻的第一端连接。
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