WO2015101145A1 - Power amplifier and gain reduction circuit thereof - Google Patents
Power amplifier and gain reduction circuit thereof Download PDFInfo
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- WO2015101145A1 WO2015101145A1 PCT/CN2014/093423 CN2014093423W WO2015101145A1 WO 2015101145 A1 WO2015101145 A1 WO 2015101145A1 CN 2014093423 W CN2014093423 W CN 2014093423W WO 2015101145 A1 WO2015101145 A1 WO 2015101145A1
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- power tube
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- 230000003321 amplification Effects 0.000 claims abstract description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 6
- 230000003313 weakening effect Effects 0.000 claims abstract description 3
- 239000003990 capacitor Substances 0.000 claims description 26
- 230000000903 blocking effect Effects 0.000 claims description 25
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
Definitions
- the invention belongs to the field of power amplifiers, and in particular to a power amplifier and a gain attenuation circuit thereof.
- Power amplifiers usually have multiple gain modes, such as high gain / low gain mode, or high gain / medium gain / Low gain three modes.
- Traditional gain implementations can be:
- a power amplifier gain attenuating circuit comprising:
- a gain attenuating unit which inputs an input signal, an externally supplied driving signal and a bias voltage, and attenuates the input signal according to the driving signal and the bias voltage to output a secondary input signal;
- Amplification unit with:
- Offset input accessing the bias voltage
- the output signal of the gain is output.
- the power amplifier gain attenuation circuit can control the gain attenuation unit output according to an external driving signal After the input signal is weakened, the secondary input signal is output, and the amplifying unit performs gain amplification on the weakened secondary input signal, thereby effectively achieving gain attenuation, and the phase jump caused by the attenuation is small.
- Figure 1 is a block diagram of a power amplifier gain attenuating circuit
- FIG. 2 is a circuit schematic diagram of a power amplifier gain attenuating circuit in an embodiment
- FIG. 3 is a circuit schematic diagram of a power amplifier gain attenuating circuit in another embodiment.
- a power amplifier gain attenuating circuit includes an amplifying unit 100 and a gain attenuating unit 200.
- Gain attenuation unit 200 access the input signal RF in, the bias voltage of the driving signal V mode and the externally supplied externally provided, and according to the driving signal V mode, the bias voltage output of the secondary input to the input signal RF in is weakened signal.
- the amplifying unit 100 has: a bias input terminal a for accessing a bias voltage; a signal input terminal for accessing a secondary input signal The output d for outputting the output signal of the gain.
- the gain attenuating unit 200 is one or a plurality of parallel.
- the secondary input signal of the previous output serves as the latter input signal RF in .
- the plurality of first DC blocking capacitors C1 of the plurality of gain attenuating units 200 are combined into one DC blocking capacitor, that is, replaced by a first DC blocking capacitor C1; Of course, it can be multiple.
- the amplifying unit 100 can be made to achieve the gain of the corresponding stage. For example, referring to FIG.
- the amplifying unit 100 when the gain attenuating unit 200 is one, the amplifying unit 100 can cause the high-gain or low-gain rear output of the input signal. Referring to FIG. 3, when the gain attenuating unit 200 is two, the amplifying unit 100 can cause the high-gain, medium-gain or low-gain rear output of the input signal.
- the above-mentioned driving signal V mode includes a high level and a low level.
- the gain attenuating unit 200 When the gain attenuating unit 200 is connected to the (drive signal V mode ) low level, the gain attenuating unit 200 is turned off, and the input signal RF in is not weakened; when the gain attenuating unit 200 is connected (driving signal V mode ) to a high level, the gain attenuating unit 200 turns on, weakening the input signal RF in .
- the gain attenuating unit 200 attenuates the input signal RF in , specifically, directly blocks and pulls a low level, and then generates a secondary input signal.
- the gain attenuating unit 200 includes a first DC blocking capacitor C1 and a first resistor R1.
- One end of the first DC blocking capacitor C1 is used to access the input signal RF in , and the first DC blocking capacitor outputs a secondary input signal;
- the base of the first power transistor Q1 is connected to the driving signal V mode , specifically through the resistor R4 Driving signal V mode ;
- the first power tube Q1 emitter is grounded, the collector of the first power tube Q1 is connected to the other end of the first DC blocking capacitor C1;
- the base of the third power tube Q3 is connected to the bias voltage,
- the collector of the three power tube Q3 is connected to the first power source, and the emitter of the third power tube Q3 is connected to the emitter of the second power tube Q2 via the first resistor R1;
- the emitter of the second power tube Q2 and the base of the second power tube Q2 Connected, the collector of the second power transistor Q2 is connected to the other end of the first DC blocking capacitor C1.
- the gain attenuating unit 200 can block the input signal and pull the low level to generate the secondary input signal under the control
- the secondary input signal of the previous output is used as the latter input signal RF in , that is, the input signal RF in is separated from the gain attenuating unit 200 on the left side of the figure.
- the direct capacitor C4 front-end input after which the secondary input signal is output from the rear end of the resistor R7, and the secondary input signal is input as the input signal RF in of the first DC-blocking capacitor C1 in the gain-attenuating unit 200 on the right side of the figure.
- the amplification unit 100 includes a first amplifier 110 and a second amplifier 120.
- the first amplifier 110 has a first bias input terminal a for accessing the bias voltage, a first signal input terminal b for accessing the secondary input signal, that is, a signal input terminal of the amplifying unit 100.
- a first output terminal f for outputting the primary output signal of the first gain; and a control terminal c for accessing the control signal c, that is, the amplifying unit 100.
- the second amplifier 120 has a second bias input terminal e for accessing the bias voltage, and a bias input terminal of the amplifying unit 100. a second signal input terminal f for accessing the primary output signal; and a second output terminal d for outputting the output signal of the second gain, that is, the output terminal d of the amplification unit 100.
- the first amplifier 110 includes a fourth power tube Q4, a fifth power tube Q5, a second DC blocking capacitor C2, and a second resistor. R2, the first inductor L1.
- the base of the fourth power tube Q4 serves as the first bias input terminal a, and the collector of the fourth power tube Q4 is connected to the first power source Vccb
- the emitter of the fourth power transistor Q4 is connected to the base of the fifth power transistor Q5 via the second resistor R2, and the collector of the fifth power transistor Q5 serves as the first output terminal f and is coupled to the first inductor L1.
- One end of the first inductor L1 is connected to the second power source Vcc1
- the emitter of the fifth power tube Q5 is grounded, and one end of the second DC blocking capacitor C2 is used as the first signal input terminal b, and the second DC blocking capacitor
- the other end of C2 is connected to the base of the fifth power transistor Q5.
- the second amplifier 120 includes a sixth power tube Q6, a seventh power tube Q7, a third DC blocking capacitor C3, and a third resistor. R3, the second inductor L2.
- the base of the sixth power tube Q6 serves as the first bias input terminal e, and the collector of the sixth power tube Q6 is connected to the first power source Vccb
- the emitter of the sixth power transistor Q6 is connected to the base of the seventh power transistor Q7 via the third resistor R3, and the collector of the seventh power transistor Q7 serves as the output terminal d of the amplifying unit 100 and is coupled to the first inductor L1.
- One end of the second inductor L2 is connected to the third power source Vcc2, the emitter of the seventh power tube Q7 is grounded, and one end of the third DC blocking capacitor C3 is used as the second signal input terminal b and the fifth power tube.
- the collector of Q5 is connected, and the other end of the third DC blocking capacitor C3 is connected to the base of the seventh power transistor Q7.
- the gain attenuating unit 200 when the driving signal V mode1 is at a low level, the first power transistor Q1 is in an off state, the gain attenuating unit 200 basically does not introduce gain attenuation, and the overall circuit is in a high gain mode; when the driving signal is at a high level, the first Power tube Q1 is in an on state, gain attenuation unit 200 introduces gain attenuation, and the overall circuit is in a low gain mode.
- the power tube is a triode.
- the first power transistor Q1, the second power transistor Q2, and the third power transistor Q3 are turned on, so that the base voltage of the fifth power transistor Q4 is lowered, so that the first amplifier coefficient of primary output signals (collector of transistor Q4 fifth power) output 110 of a low gain, so that the final output signal RF out of the gain factor of the second amplifier 120 also becomes low.
- the gain attenuating unit 200 when the driving signals V mode1 and V mode2 are both low level, the gain attenuating unit 200 does not operate, and the amplifying unit 100 is in the high gain mode; when one of the driving signals V mode1 and V mode2 is high At the level, one of the gain attenuating units 200 operates, the other does not work, and the amplifying unit 100 is in the medium gain mode; when the driving signals V mode1 and V mode2 are both high, the gain attenuating unit 200 operates simultaneously, and the amplifying unit 100 is at a low level. Gain mode.
- a power amplifier including a bias voltage generating circuit, a driving signal generating circuit, and the above-described power amplifier gain attenuating circuit is also provided.
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Abstract
A gain reduction circuit of a power amplifier comprises: a gain reduction unit, accessing an input signal, an externally provided driving signal and a bias voltage, and weakening the input signal according to the driving signal and the bias voltage and then outputting a secondary input signal; an amplification unit, provided with a bias input end and accessing the bias voltage; a signal input end, accessing a secondary input signal; and an output end, outputting a gained output signal. The gain reduction circuit of the power amplifier can effectively implement gain reduction, and a phase jump resulting from the reduction is very small.
Description
本发明属于功率放大器领域，尤其涉及一种功率放大器及其增益衰减电路。 The invention belongs to the field of power amplifiers, and in particular to a power amplifier and a gain attenuation circuit thereof.
功率放大器通常都有多种增益模式，如高增益 / 低增益两种模式，或者高增益 / 中增益 /
低增益三种模式。传统的增益实现方式可以有： Power amplifiers usually have multiple gain modes, such as high gain / low gain mode, or high gain / medium gain /
Low gain three modes. Traditional gain implementations can be:
（ 1 ） 通过调整偏置电路的电压 /
电流值，是电路工作在不同的偏置情况下，从而实现增益切换。该方法的缺点是高增益和低增益落差不大。 (1) by adjusting the voltage of the bias circuit /
The current value is the circuit operating under different bias conditions to achieve gain switching. The disadvantage of this method is that the high gain and low gain drop are not large.
（ 2 ）
通过不同信号通道的切换实现高低增益模式切换。该方法的缺点是芯片面积大，切换增益有可能导致相位不连续。 ( 2 )
High and low gain mode switching is achieved by switching between different signal channels. The disadvantage of this method is that the chip area is large, and the switching gain may cause phase discontinuity.
基于此，有必要提供一种 功率放大器增益衰减电路 ，旨在解决 高增益和低增益落差不大 的问题。 Based on this, it is necessary to provide a power amplifier gain reduction circuit designed to solve the problem of low gain and low gain drop.
一种功率放大器增益衰减电路，包括： A power amplifier gain attenuating circuit comprising:
增益衰减单元，接入输入信号、外部提供的驱动信号和偏置电压，并根据该驱动信号、偏置电压对所述输入信号的进行削弱后输出次级输入信号；
a gain attenuating unit, which inputs an input signal, an externally supplied driving signal and a bias voltage, and attenuates the input signal according to the driving signal and the bias voltage to output a secondary input signal;
放大单元，具有： Amplification unit with:
偏置输入端，接入所述偏置电压； Offset input, accessing the bias voltage;
信号输入端，接入所述次级输入信号；以及 a signal input terminal for accessing the secondary input signal;
输出端，输出经增益的输出信号 。 At the output, the output signal of the gain is output.
上述功率放大器增益衰减电路可以根据外部的驱动信号控制增益衰减单元输出
对输入信号的进行削弱后输出次级输入信号 ， 放大单元对该被削弱的次级输入信号进行增益放大， 如此有效实现增益衰减，衰减带来的相位跳变很小。 The power amplifier gain attenuation circuit can control the gain attenuation unit output according to an external driving signal
After the input signal is weakened, the secondary input signal is output, and the amplifying unit performs gain amplification on the weakened secondary input signal, thereby effectively achieving gain attenuation, and the phase jump caused by the attenuation is small.
图 1 是功率放大器增益衰减电路的模块示意图； Figure 1 is a block diagram of a power amplifier gain attenuating circuit;
图 2 是一个实施例中的功率放大器增益衰减电路的电路原理图； 2 is a circuit schematic diagram of a power amplifier gain attenuating circuit in an embodiment;
图 3 是另一个实施例中的功率放大器增益衰减电路的电路原理图。 3 is a circuit schematic diagram of a power amplifier gain attenuating circuit in another embodiment.
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
如图 1 所示，一种功率放大器增益衰减电路，包括放大单元 100 、增益衰减单元 200 。 As shown in FIG. 1, a power amplifier gain attenuating circuit includes an amplifying unit 100 and a gain attenuating unit 200.
增益衰减单元 200 接入输入信号 RFin 、外部提供的驱动信号
Vmode 和外部提供的偏置电压，并根据该驱动信号 Vmode 、偏置电压对输入信号
RFin 的进行削弱后输出次级输入信号。Gain attenuation unit 200 access the input signal RF in, the bias voltage of the driving signal V mode and the externally supplied externally provided, and according to the driving signal V mode, the bias voltage output of the secondary input to the input signal RF in is weakened signal.
放大单元 100 ，具有：用于接入偏置电压的偏置输入端 a ；用于接入次级输入信号的信号输入端 b
；用于输出经增益的输出信号的输出端 d 。 The amplifying unit 100 has: a bias input terminal a for accessing a bias voltage; a signal input terminal for accessing a secondary input signal
The output d for outputting the output signal of the gain.
在优选的实施例中，增益衰减单元 200 为一个或为并联的多个，当增益衰减单元 200
为多个时，前一个输出的次级输入信号作为后一个的输入信号 RFin 。另外，参考图 3 ，当增益衰减单元 200
为多个时，多个增益衰减单元 200 中的多个第一隔直电容 C1 合并为一个隔直电容，即以一个第一隔直电容 C1
代替；当然也可以是多个。如此，通过外部的驱动信号 Vmode 控制相应个数的增益衰减单元 200 工作，可以使得放大单元 100
实现相应级的增益。例如，参考图 2 ，增益衰减单元 200 为一个时，可以使得放大单元 100 对输入信号实现高增益或低增益的后输出。参考图 3
，增益衰减单元 200 为两个时，可以使得放大单元 100 对输入信号实现高增益、中增益或低增益的后输出。In a preferred embodiment, the gain attenuating unit 200 is one or a plurality of parallel. When the gain attenuating unit 200 is plural, the secondary input signal of the previous output serves as the latter input signal RF in . In addition, referring to FIG. 3, when the gain attenuating unit 200 is plural, the plurality of first DC blocking capacitors C1 of the plurality of gain attenuating units 200 are combined into one DC blocking capacitor, that is, replaced by a first DC blocking capacitor C1; Of course, it can be multiple. Thus, by controlling the operation of the corresponding number of gain attenuating units 200 by the external driving signal V mode , the amplifying unit 100 can be made to achieve the gain of the corresponding stage. For example, referring to FIG. 2, when the gain attenuating unit 200 is one, the amplifying unit 100 can cause the high-gain or low-gain rear output of the input signal. Referring to FIG. 3, when the gain attenuating unit 200 is two, the amplifying unit 100 can cause the high-gain, medium-gain or low-gain rear output of the input signal.
需要说明的是，本实施例中，上述的驱动信号 Vmode 包括高电平和低电平。It should be noted that, in this embodiment, the above-mentioned driving signal V mode includes a high level and a low level.
当增益衰减单元 200 接入（驱动信号 Vmode ）低电平时，增益衰减单元 200
截止，未削弱输入信号 RFin ；当增益衰减单元 200 接入（驱动信号 Vmode ）高电平时，增益衰减单元
200 导通，削弱输入信号 RFin 。When the gain attenuating unit 200 is connected to the (drive signal V mode ) low level, the gain attenuating unit 200 is turned off, and the input signal RF in is not weakened; when the gain attenuating unit 200 is connected (driving signal V mode ) to a high level, the gain attenuating unit 200 turns on, weakening the input signal RF in .
增益衰减单元 200 将输入信号 RFin
的进行削弱，具体是隔直并拉低电平，后产生次级输入信号。The gain attenuating unit 200 attenuates the input signal RF in , specifically, directly blocks and pulls a low level, and then generates a secondary input signal.
在其中一个实施例中，参考图 2 和 3 ，增益衰减单元 200 包括第一隔直电容 C1 、第一电阻 R1
、第一功率管 Q1 、第二功率管 Q2 和第三功率管Q3。 In one embodiment, referring to FIGS. 2 and 3, the gain attenuating unit 200 includes a first DC blocking capacitor C1 and a first resistor R1.
The first power tube Q1, the second power tube Q2, and the third power tube Q3.
第一隔直电容 C1 的一端用于接入输入信号 RFin
，第一隔直电容输出次级输入信号；第一功率管 Q1 的基极接入驱动信号 Vmode ，具体是经过电阻 R4 接入驱动信号
Vmode 的；第一功率管 Q1 发射极接地，第一功率管 Q1 的集电极与第一隔直电容 C1 的另一端连接；第三功率管 Q3
的基极接入偏置电压，第三功率管 Q3 的集电极接于第一电源，第三功率管 Q3 的发射极经第一电阻 R1 与第二功率管 Q2 的发射极连接；第二功率管 Q2
的发射极与本身的基极连接，第二功率管 Q2 的集电极与第一隔直电容 C1 的另一端连接。由此可知，增益衰减单元 200 在驱动信号
Vmode 的控制下，可以将输入信号的进行隔直并拉低电平后产生次级输入信号。One end of the first DC blocking capacitor C1 is used to access the input signal RF in , and the first DC blocking capacitor outputs a secondary input signal; the base of the first power transistor Q1 is connected to the driving signal V mode , specifically through the resistor R4 Driving signal V mode ; the first power tube Q1 emitter is grounded, the collector of the first power tube Q1 is connected to the other end of the first DC blocking capacitor C1; the base of the third power tube Q3 is connected to the bias voltage, The collector of the three power tube Q3 is connected to the first power source, and the emitter of the third power tube Q3 is connected to the emitter of the second power tube Q2 via the first resistor R1; the emitter of the second power tube Q2 and the base of the second power tube Q2 Connected, the collector of the second power transistor Q2 is connected to the other end of the first DC blocking capacitor C1. It can be seen that the gain attenuating unit 200 can block the input signal and pull the low level to generate the secondary input signal under the control of the driving signal V mode .
参考图 3 ，当增益衰减单元 200 为并联的多个时，前一个输出的次级输入信号作为后一个的输入信号
RFin ，即输入信号 RFin 从图示左边的增益衰减单元 200 中的隔直电容 C4 前端输入，其后从电阻 R7
的后端输出次级输入信号，而该次级输入信号作为图示右边的增益衰减单元 200 中的第一隔直电容 C1 的输入信号 RFin 输入。Referring to FIG. 3, when the gain attenuating unit 200 is a plurality of parallel, the secondary input signal of the previous output is used as the latter input signal RF in , that is, the input signal RF in is separated from the gain attenuating unit 200 on the left side of the figure. The direct capacitor C4 front-end input, after which the secondary input signal is output from the rear end of the resistor R7, and the secondary input signal is input as the input signal RF in of the first DC-blocking capacitor C1 in the gain-attenuating unit 200 on the right side of the figure.
在其中一个实施例中，参考图 2 和 3 ，放大单元 100 包括第一放大器 110 和第二放大器 120
；第一放大器 110 具有：用于接入偏置电压的第一偏置输入端 a ；用于接入次级输入信号的第一信号输入端 b ，即放大单元 100 的信号输入端 b
；用于输出经第一次增益的初级输出信号的第一输出端 f ；以及用于接入控制信号控制端 c ，即放大单元 100 的控制端 c 。 In one embodiment, referring to Figures 2 and 3, the amplification unit 100 includes a first amplifier 110 and a second amplifier 120.
The first amplifier 110 has a first bias input terminal a for accessing the bias voltage, a first signal input terminal b for accessing the secondary input signal, that is, a signal input terminal of the amplifying unit 100.
a first output terminal f for outputting the primary output signal of the first gain; and a control terminal c for accessing the control signal c, that is, the amplifying unit 100.
第二放大器 120 具有：用于接入偏置电压的第二偏置输入端 e ，同放大单元 100 的偏置输入端 a
；用于接入初级输出信号的第二信号输入端 f ；以及用于输出经第二次增益的输出信号的第二输出端 d ，即放大单元 100 的输出端 d 。 The second amplifier 120 has a second bias input terminal e for accessing the bias voltage, and a bias input terminal of the amplifying unit 100.
a second signal input terminal f for accessing the primary output signal; and a second output terminal d for outputting the output signal of the second gain, that is, the output terminal d of the amplification unit 100.
本实施例中，第一放大器 110 包括第四功率管 Q4 、第五功率管 Q5 、第二隔直电容 C2 、第二电阻
R2 、第一电感 L1 。 In this embodiment, the first amplifier 110 includes a fourth power tube Q4, a fifth power tube Q5, a second DC blocking capacitor C2, and a second resistor.
R2, the first inductor L1.
第四功率管 Q4 的基极作为第一偏置输入端 a ，第四功率管 Q4 的集电极接第一电源 Vccb
，第四功率管 Q4 的发射极经第二电阻 R2 与第五功率管 Q5 的基极连接，第五功率管 Q5 的集电极作为第一输出端 f 并与第一电感 L1
的一端连接，第一电感 L1 的另一端接第二电源 Vcc1 ，第五功率管 Q5 的发射极接地，第二隔直电容 C2 的一端作为第一信号输入端 b ，第二隔直电容
C2 的另一端与第五功率管 Q5 的基极连接。 The base of the fourth power tube Q4 serves as the first bias input terminal a, and the collector of the fourth power tube Q4 is connected to the first power source Vccb
The emitter of the fourth power transistor Q4 is connected to the base of the fifth power transistor Q5 via the second resistor R2, and the collector of the fifth power transistor Q5 serves as the first output terminal f and is coupled to the first inductor L1.
One end of the first inductor L1 is connected to the second power source Vcc1, the emitter of the fifth power tube Q5 is grounded, and one end of the second DC blocking capacitor C2 is used as the first signal input terminal b, and the second DC blocking capacitor
The other end of C2 is connected to the base of the fifth power transistor Q5.
本实施例中，第二放大器 120 包括第六功率管 Q6 、第七功率管 Q7 、第三隔直电容 C3 、第三电阻
R3 、第二电感 L2 。 In this embodiment, the second amplifier 120 includes a sixth power tube Q6, a seventh power tube Q7, a third DC blocking capacitor C3, and a third resistor.
R3, the second inductor L2.
第六功率管 Q6 的基极作为第一偏置输入端 e ，第六功率管 Q6 的集电极接第一电源 Vccb
，第六功率管 Q6 的发射极经第三电阻 R3 与第七功率管 Q7 的基极连接，第七功率管 Q7 的集电极作为放大单元 100 的输出端 d 并与第一电感 L1
的一端连接，第二电感 L2 的另一端接第三电源 Vcc2 ，第七功率管 Q7 的发射极接地，第三隔直电容 C3 的一端作为第二信号输入端 b 与第五功率管
Q5 的集电极连接，第三隔直电容 C3 的另一端与第七功率管 Q7 的基极连接。 The base of the sixth power tube Q6 serves as the first bias input terminal e, and the collector of the sixth power tube Q6 is connected to the first power source Vccb
The emitter of the sixth power transistor Q6 is connected to the base of the seventh power transistor Q7 via the third resistor R3, and the collector of the seventh power transistor Q7 serves as the output terminal d of the amplifying unit 100 and is coupled to the first inductor L1.
One end of the second inductor L2 is connected to the third power source Vcc2, the emitter of the seventh power tube Q7 is grounded, and one end of the third DC blocking capacitor C3 is used as the second signal input terminal b and the fifth power tube.
The collector of Q5 is connected, and the other end of the third DC blocking capacitor C3 is connected to the base of the seventh power transistor Q7.
参考图 2 ，当驱动信号 Vmode1 处于低电平时，第一功率管 Q1
处于截止状态，增益衰减单元 200 基本不引入增益衰减，整体电路处于高增益模式；当驱动信号处于高电平时，第一功率管 Q1 处于导通状态，增益衰减单元 200
引入增益衰减，整体电路处于低增益模式。Referring to FIG. 2, when the driving signal V mode1 is at a low level, the first power transistor Q1 is in an off state, the gain attenuating unit 200 basically does not introduce gain attenuation, and the overall circuit is in a high gain mode; when the driving signal is at a high level, the first Power tube Q1 is in an on state, gain attenuation unit 200 introduces gain attenuation, and the overall circuit is in a low gain mode.
其中，参考图 3 ，上述的功率管为三极管。当外部输入的驱动信号 Vmode1
为高电平时，第一功率管 Q1 、第二功率管 Q2 、第三功率管 Q3 导通，使第五功率管 Q4 的基极电压变低，使得第一放大器 110 （第五功率管 Q4
的集电极）输出的初级输出信号的第一次增益的系数变低，最后致使第二放大器 120 的输出信号 RFout 的增益系数也变低。Wherein, referring to FIG. 3, the power tube is a triode. When the externally input driving signal V mode1 is at a high level, the first power transistor Q1, the second power transistor Q2, and the third power transistor Q3 are turned on, so that the base voltage of the fifth power transistor Q4 is lowered, so that the first amplifier coefficient of primary output signals (collector of transistor Q4 fifth power) output 110 of a low gain, so that the final output signal RF out of the gain factor of the second amplifier 120 also becomes low.
基于上述图 3 的实施例，当驱动信号 Vmode1 、
Vmode2 均为低电平时，增益衰减单元 200 不工作，放大单元 100 处于高增益模式；当驱动信号
Vmode1 、 Vmode2 其中之一为高电平时，增益衰减单元 200 其中一个工作，另一个不工作，放大单元
100 处于中增益模式；当驱动信号 Vmode1 ， Vmode2 均为高电平时，增益衰减单元 200
同时工作，放大单元 100 处于低增益模式。Based on the embodiment of FIG. 3 above, when the driving signals V mode1 and V mode2 are both low level, the gain attenuating unit 200 does not operate, and the amplifying unit 100 is in the high gain mode; when one of the driving signals V mode1 and V mode2 is high At the level, one of the gain attenuating units 200 operates, the other does not work, and the amplifying unit 100 is in the medium gain mode; when the driving signals V mode1 and V mode2 are both high, the gain attenuating unit 200 operates simultaneously, and the amplifying unit 100 is at a low level. Gain mode.
此外，还提供了一种功率放大器，包括偏置电压产生电路、驱动信号产生电路以及上述的功率放大器增益衰减电路。
Further, a power amplifier including a bias voltage generating circuit, a driving signal generating circuit, and the above-described power amplifier gain attenuating circuit is also provided.
以上仅所述为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.
Claims (10)
- 一种功率放大器增益衰减电路，其特征在于，包括：A power amplifier gain attenuating circuit, comprising:增益衰减单元，接入输入信号、外部提供的驱动信号和偏置电压，并根据该驱动信号、偏置电压对所述输入信号的进行削弱后输出次级输入信号；a gain attenuating unit, which inputs an input signal, an externally supplied driving signal and a bias voltage, and attenuates the input signal according to the driving signal and the bias voltage to output a secondary input signal;放大单元，具有：Amplification unit with:偏置输入端，接入所述偏置电压；Offset input, accessing the bias voltage;信号输入端，接入所述次级输入信号；以及a signal input terminal for accessing the secondary input signal;输出端，输出经增益的输出信号。At the output, the output signal of the gain is output.
- 根据权利要求 1 所述的功率放大器增益衰减电路，其特征在于，所述增益衰减单元包括第一隔直电容、第一电阻、第一功率管、第二功率管、第三功率管，其中，According to claim 1 The power amplifier gain attenuating circuit, wherein the gain attenuating unit comprises a first DC blocking capacitor, a first resistor, a first power tube, a second power tube, and a third power tube, wherein所述第一隔直电容的一端用于接入所述输入信号，另一端输出所述次级输入信号；One end of the first DC blocking capacitor is used to access the input signal, and the other end outputs the secondary input signal;所述第一功率管的基极接入所述驱动信号、发射极接地、集电极与所述第一隔直电容的另一端连接；The base of the first power tube is connected to the driving signal, the emitter is grounded, and the collector is connected to the other end of the first blocking capacitor;所述第三功率管的基极接入偏置电压、集电极接于第一电源、发射极经所述第一电阻与所述第二功率管的发射极连接；所述第二功率管的发射极与本身的基极连接，所述第二功率管的集电极与所述第一隔直电容的另一端连接。The base of the third power tube is connected to the bias voltage, the collector is connected to the first power source, and the emitter is connected to the emitter of the second power tube via the first resistor; the second power tube The emitter is connected to its base, and the collector of the second power tube is connected to the other end of the first DC blocking capacitor.
- 根据权利要求 1 或 2 所述的功率放大器增益衰减电路，其特征在于，所述增益衰减单元为一个或并联的多个。According to claim 1 or 2 The power amplifier gain attenuating circuit is characterized in that the gain attenuating unit is a plurality of one or a parallel.
- 根据权利要求 2 所述的功率放大器增益衰减电路，其特征在于，所述增益衰减单元为并联的多个时，多个所述增益衰减单元中的多个所述第一隔直电容合并为一个隔直电容。According to claim 2 The power amplifier gain attenuating circuit is characterized in that, when the gain attenuating unit is a plurality of parallel, a plurality of the first blocking capacitors of the plurality of the gain attenuating units are combined into one DC blocking capacitor.
- 根据权利要求 1 所述的功率放大器增益衰减电路，其特征在于，所述驱动信号包括高电平和低电平；The power amplifier gain attenuating circuit according to claim 1, wherein said driving signal comprises a high level and a low level;当所述增益衰减单元接入低电平时，所述增益衰减单元截止，未削弱所述输入信号；当所述增益衰减单元接入高电平时，所述增益衰减单元导通，削弱所述输入信号。When the gain attenuating unit is connected to a low level, the gain attenuating unit is turned off, the input signal is not weakened; when the gain attenuating unit is connected to a high level, the gain attenuating unit is turned on, weakening the input signal.
- 根据权利要求 1 或 2 所述的功率放大器增益衰减电路，其特征在于，所述增益衰减单元用于将所述输入信号的进行隔直并拉低电平后，产生所述次级输入信号。According to claim 1 or 2 The power amplifier gain attenuating circuit is characterized in that the gain attenuating unit is configured to generate the secondary input signal after blocking the input signal and pulling a low level.
- 根据权利要求 1 或 2 所述的功率放大器增益衰减电路，其特征在于，所述放大单元包括第一放大器和第二放大器；According to claim 1 or 2 The power amplifier gain attenuating circuit, characterized in that the amplifying unit comprises a first amplifier and a second amplifier;所述第一放大器，具有：The first amplifier has:第一偏置输入端，接入所述偏置电压；a first bias input terminal for accessing the bias voltage;第一信号输入端，接入所述次级输入信号；以及a first signal input terminal for accessing the secondary input signal;第一输出端，输出经第一次增益的初级输出信号；a first output terminal, outputting a primary output signal of a first gain;所述第二放大器，具有：The second amplifier has:第二偏置输入端，接入所述偏置电压；a second bias input terminal for accessing the bias voltage;第二信号输入端，接入所述初级输出信号；以及a second signal input terminal for accessing the primary output signal;第二输出端，输出经第二次增益的所述输出信号。The second output outputs the output signal of the second gain.
- 根据权利要求 7 所述的功率放大器增益衰减电路，其特征在于，所述第一放大器包括第四功率管、第五功率管、第二隔直电容、第二电阻、第一电感；According to claim 7 The power amplifier gain attenuating circuit, wherein the first amplifier comprises a fourth power tube, a fifth power tube, a second DC blocking capacitor, a second resistor, and a first inductor;所述第四功率管的基极作为所述第一偏置输入端，集电极接第一电源，发射极经所述第二电阻与所述第五功率管的基极连接，所述第五功率管的集电极作为所述第一输出端并与所述第一电感的一端连接，所述第一电感的另一端接第二电源，所述第五功率管的发射极接地，所述第二隔直电容的一端作为所述第一信号输入端、另一端与所述第五功率管的基极连接。The base of the fourth power tube serves as the first bias input end, the collector is connected to the first power source, and the emitter is connected to the base of the fifth power tube via the second resistor, the fifth a collector of the power tube is connected to the first output end and connected to one end of the first inductor, and another end of the first inductor is connected to a second power source, and an emitter of the fifth power tube is grounded. One end of the two DC blocking capacitor is connected to the base of the fifth power tube as the first signal input end and the other end.
- 根据权利要求 8 所述的功率放大器增益衰减电路，其特征在于，所述第二放大器包括第六功率管、第七功率管、第三隔直电容、第三电阻、第二电感；According to claim 8 The power amplifier gain attenuating circuit, wherein the second amplifier comprises a sixth power tube, a seventh power tube, a third DC blocking capacitor, a third resistor, and a second inductor;所述第六功率管的基极作为所述第一偏置输入端，集电极接第一电源，发射极经所述第三电阻与所述第七功率管的基极连接，所述第七功率管的集电极作为所述放大单元的输出端并与所述第一电感的一端连接，所述第二电感的另一端接第三电源，所述第七功率管的发射极接地，所述第三隔直电容的一端作为所述第二信号输入端与所述第五功率管的集电极连接，另一端与所述第七功率管的基极连接。The base of the sixth power tube serves as the first bias input end, the collector is connected to the first power source, and the emitter is connected to the base of the seventh power tube via the third resistor, the seventh a collector of the power tube is connected as an output end of the amplifying unit and connected to one end of the first inductor, and another end of the second inductor is connected to a third power source, and an emitter of the seventh power tube is grounded, One end of the third DC blocking capacitor is connected to the collector of the fifth power tube as the second signal input end, and the other end is connected to the base of the seventh power tube.
- 一种功率放大器，其特征在于，包括偏置电压产生电路、驱动信号产生电路以及权利要求 1 至 9 任一项所述的功率放大器增益衰减电路。A power amplifier comprising a bias voltage generating circuit, a driving signal generating circuit, and claims 1 to 9 A power amplifier gain attenuating circuit as claimed in any of the preceding claims.
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| US15/139,087 US9595933B2 (en) | 2013-12-30 | 2016-04-26 | Power amplifier device and circuits |
| US15/418,748 US9887679B2 (en) | 2013-12-30 | 2017-01-29 | Power amplifier and gain switching circuit thereof |
| US15/853,835 US10044334B2 (en) | 2013-12-30 | 2017-12-24 | Power amplifier and gain reduction circuit thereof |
| US15/853,950 US9973164B1 (en) | 2013-12-30 | 2017-12-25 | Power amplifier output power control circuit |
| US15/854,738 US10044335B2 (en) | 2013-12-30 | 2017-12-26 | Multi-mode multi-frequency power amplifier |
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| CN201310746807.5A CN104753483B (en) | 2013-12-30 | 2013-12-30 | Power amplifier and its gain-attenuation control circuitry |
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| PCT/CN2014/093425 Continuation WO2015101146A1 (en) | 2013-12-30 | 2014-12-10 | Output power control circuit of power amplifier |
| PCT/CN2014/093425 Continuation-In-Part WO2015101146A1 (en) | 2013-12-30 | 2014-12-10 | Output power control circuit of power amplifier |
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| CN106374850B (en) * | 2015-07-24 | 2019-05-07 | 江苏林洋能源股份有限公司 | A kind of voltage-controlled continuously adjustable attenuator circuit |
| CN106788298B (en) * | 2015-11-20 | 2019-03-15 | 厦门宇臻集成电路科技有限公司 | A kind of power amplifier gain switching circuit |
| CN110635815B (en) * | 2019-09-09 | 2021-07-30 | 云南康木信科技有限责任公司 | Circuit for automatic attenuation control of front-stage radio frequency input end of medium-short wave receiver |
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| CN101106356A (en) * | 2007-08-01 | 2008-01-16 | 锐迪科无线通信技术（上海）有限公司 | Power amplification circuit and its initialization method and power amplification method |
| CN101784142A (en) * | 2009-01-19 | 2010-07-21 | 原景科技股份有限公司 | Light emitting diode circuit with high light-regulating frequency |
| CN101847973A (en) * | 2010-05-26 | 2010-09-29 | 深圳市力合微电子有限公司 | Automatic gain control circuit for receiving end of power-line carrier communication system |
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