WO2015072036A1

WO2015072036A1 - Inverter control device

Info

Publication number: WO2015072036A1
Application number: PCT/JP2013/081049
Authority: WO
Inventors: 真一古谷; 一文平林
Original assignee: 三菱電機株式会社
Priority date: 2013-11-18
Filing date: 2013-11-18
Publication date: 2015-05-21
Also published as: CN105765837A; JP6160706B2; JPWO2015072036A1; CN105765837B

Abstract

Provided is an inverter control device capable of suppressing the noise and oscillation attributable to current ripples in an electric load. The inverter control device comprises: a two-phase modulation mode setting means (19) having a first determination means (19e) and designating a two-phase modulation mode on the basis of the output frequency (16) of an inverter; and a two-phase modulation processing means (10) for carrying out a two-phase modulation on the basis of a duty command (7) and the two-phase modulation mode. When an odd number is denoted by x, the first determination means (19e) determines whether a frequency of 3x-times the output frequency (16) of the inverter is included in a preset frequency band or not. When it is determined that the 3x-times frequency is included in the frequency band, the two-phase modulation mode setting means (19) designates an upward sliding mode or a downward sliding mode as a two-phase modulation mode. When it is determined that the 3x-times frequency is not included in the frequency band, a two-way sliding mode in which an upward sliding state and a downward sliding state are switched according to the absolute value and polarity of the duty command (7) is designated as the two-phase modulation mode.

Description

Inverter control device

The present invention relates to an inverter control device.

The following Patent Document 1 describes a motor control device including an inverter. This motor control device controls switching of the inverter by two-phase modulation. The motor control device switches between the upper alignment state and the lower alignment state at regular intervals when performing two-phase modulation in the double alignment mode.

Japanese Patent No. 4426433

In the motor control device described in Patent Document 1, noise and vibration are generated due to current pulsation of a motor driven by an inverter.

The present invention has been made to solve the above problems. An object of the present invention is to provide an inverter control device that can suppress noise and vibration caused by current pulsation of an electric load.

The inverter control device according to the present invention includes first determination means, two-phase modulation mode setting means for designating a two-phase modulation mode for driving the inverter based on the output frequency of the inverter, a voltage command, and 2 Two-phase modulation processing means for performing two-phase modulation based on the two-phase modulation mode designated by the phase modulation mode setting means, wherein the first determination means sets x to an odd number, and 3x of the output frequency of the inverter It is determined whether or not the double frequency is included in a preset frequency band, and the two-phase modulation mode setting means increases the mode when it is determined that the frequency band of 3x times the output frequency of the inverter is included in the frequency band. Alternatively, when the downshift mode is designated as the two-phase modulation mode and it is determined that the frequency output 3 × times the inverter output frequency is not included in the frequency band, It is to specify both asked mode switching between top justify state and lower gripping state as a two-phase modulation mode in accordance with the sex.

According to the present invention, noise and vibration caused by current pulsation of an electric load driven by an inverter can be suppressed.

It is a switching circuit diagram of a PWM inverter. It is a figure which shows the change of the duty instruction | command by the two-phase modulation in the top adjustment mode. It is a figure which shows the change of the duty command by the two-phase modulation in the bottoming-up mode. It is a figure which shows the change of the duty instruction | command by the two-phase modulation in the double shift mode. It is a figure for demonstrating the delay of the inverter output voltage pulse by dead time. It is a figure for demonstrating the mechanism in which a ripple component is superimposed on a load current. It is a figure which shows an example of the simulation result in which the current pulsation of a period 3 times the inverter output frequency generate | occur | produces in load current. It is a block diagram of the inverter control apparatus in Embodiment 1 of this invention. It is a figure for demonstrating the dead time compensation in Embodiment 1 of this invention. It is a figure for demonstrating the dead time compensation in Embodiment 1 of this invention. It is a block diagram of the inverter control apparatus in Embodiment 3 of this invention. It is a table | surface for inverter output voltage estimation in Embodiment 3 of this invention. It is a table | surface for inverter output voltage estimation in Embodiment 3 of this invention.

The present invention will be described in detail with reference to the accompanying drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals. The overlapping description will be simplified or omitted as appropriate. Note that the present invention is not limited to the following embodiments.

Embodiment 1 FIG.
The inverter control device is connected to the PWM inverter. The PWM inverter is connected to an electrical load. The electric load is, for example, an AC motor.

FIG. 1 is a switching circuit diagram of a PWM inverter. FIG. 1 shows a switching circuit of a two-level three-phase inverter. The switching circuit is supplied with DC power from the DC bus. Two switching elements are connected in series between the high potential side and the low potential side of the DC bus. The switching circuit includes three pairs of switching elements connected in series. The three pairs of switching elements are connected in parallel. Each switching element pair corresponds to one of the U phase, V phase, and W phase of the electrical load. A free-wheeling diode is connected to each switching element in parallel. The switching element connected to the high potential side of the DC bus is called the upper arm. The switching element connected to the low potential side of the DC bus is called the lower arm. Note that the polarity of the current from the switching circuit to the electric load is positive.

The PWM inverter outputs a voltage in a desired form by switching on and off a plurality of switching elements. The inverter control device generates a switching command to the PWM inverter by PWM (pulse width modulation). For example, when converting DC power to AC power, the inverter control device obtains a duty command from the voltage command and the voltage value of the DC input. The inverter control device generates a switching command based on the comparison result between the duty command and the triangular wave as the carrier. The voltage command indicates a voltage to be output from the PWM inverter. The duty command is a ratio of the pulse width of the switching command. The carrier frequency is sufficiently higher than the frequency of the duty command.

In the switching element of the PWM inverter, conduction loss, switching loss accompanying switching, and the like occur. One control technique for suppressing these losses is two-phase modulation. Two-phase modulation is intended to reduce switching loss by reducing the number of switching operations by operating a voltage command. In the two-phase modulation, the number of times of switching is reduced to 2/3 compared with the three-phase modulation. Hereinafter, a specific method of two-phase modulation is referred to as a two-phase modulation mode.

A plurality of two-phase modulation modes will be described with reference to FIGS. 2 to 4 are diagrams showing changes in duty command due to two-phase modulation. In FIG. 2 to FIG. 4, the description of the carrier waveform is omitted. The PWM inverter is a two-level three-phase inverter.

The inverter control device generates a duty command from the voltage command. The inverter control device generates a switching command based on a comparison result between the duty command and the carrier. The PWM inverter is driven based on a switching command. In the inverter output voltage, a zero voltage vector section and a non-zero voltage vector section appear alternately. At this time, the non-zero voltage vectors across the vertices of the carriers are the same. In the two-phase modulation, this is used to achieve the omission of switching by connecting a non-zero voltage vector. The zero voltage vector section is a section where the inverter output line voltage is zero.

FIG. 2 is a diagram illustrating a change in duty command due to two-phase modulation in the upward mode. FIG. 2 shows a two-phase modulation process in which non-zero voltage vectors are connected at a carrier peak. In this case, the inverter control device fixes the voltage command of the phase that is positive among the three phases and has the maximum absolute value to the maximum constant value. Switching does not occur in the phase where the voltage command is the maximum constant value. The inverter control device slides the remaining two-phase voltage commands in the positive direction while maintaining the line voltage. Hereinafter, changing the voltage command or the duty command of each phase in this way is referred to as “uplifting”. The two-phase modulation mode in which switching is omitted due to the upper adjustment is referred to as “upward adjustment mode”. A phase in which the voltage command is fixed so as not to cause switching is referred to as a “fixed phase”. A phase that is not a stationary phase is called a “non-stationary phase”.

FIG. 3 is a diagram illustrating a change in the duty command due to the two-phase modulation in the lowering mode. FIG. 3 shows a two-phase modulation process in which non-zero voltage vectors are connected at carrier valleys. In this case, the inverter control device fixes the voltage command of the phase that has a negative value and the maximum absolute value among the three phases to a minimum constant value. Switching does not occur in the phase where the voltage command is the minimum constant value. The inverter control device slides the remaining two-phase voltage commands in the negative direction while maintaining the line voltage. Hereinafter, changing the voltage command or duty command of each phase in this way is referred to as “lowering”. A two-phase modulation mode in which switching is omitted due to lowering is referred to as “lowering mode”.

FIG. 4 is a diagram showing a change in duty command due to two-phase modulation in the shift mode. FIG. 4 shows a two-phase modulation process in which the upper and lower adjustment modes are combined. In this case, the inverter control device sequentially selects the phase having the maximum absolute value of the voltage command among the three phases as the fixed phase. When the sign of the voltage command of the phase selected as the stationary phase is positive, the inverter control device performs upswing. The inverter control device performs lowering when the sign of the voltage command of the phase selected as the stationary phase is negative. Hereinafter, the two-phase modulation mode that switches between the upper and lower alignment states and omits switching will be referred to as a “double alignment mode”. It should be noted that switching between the upper and lower alignment states in the double alignment mode can be performed based on the voltage command phase instead of the magnitude and magnitude of the voltage command sign and absolute value.

The switching element of the PWM inverter does not switch on and off instantaneously. Therefore, a dead time is provided in order to prevent a short circuit between the switching element of the upper arm and the switching element of the lower arm. In the dead time section, the switching elements of the upper arm and the lower arm are both turned off. The inverter output voltage in the dead time interval is determined by the polarity of the current. As a result, an error with respect to the voltage command occurs in the inverter output voltage. Compensating for this error is called dead time compensation.

Here, dead time compensation will be described. The inverter control device adds or subtracts the dead time compensation value to the voltage command according to the polarity of the current. The dead time compensation value as a voltage value is calculated by the following equation (1). When the polarity of the current is positive, the inverter control device adds the calculated value of equation (1) to the voltage command. When the polarity of the current is negative, the inverter control device subtracts the calculated value of equation (1) from the voltage command. Td is the dead time length. Vdc is the magnitude of the DC voltage input to the PWM inverter. fc is a carrier frequency.

Due to the dead time compensation, the time average value of the inverter output voltage in the section between the vertices of the carrier coincides with the voltage command. However, the timing at which the non-zero voltage vector section appears shifts due to the dead time. Specifically, the inverter output voltage pulse is delayed by Td / 2 as compared with the case where there is no dead time.

FIG. 5 is a diagram for explaining the delay of the inverter output voltage pulse due to the dead time. The duty command waveform shown in FIG. 5 is obtained by enlarging the extremely short time range of the waveform as shown in FIG.

FIG. 5A shows an inverter output terminal voltage of an ideal PWM inverter having no dead time. In an ideal PWM inverter, the upper arm switching element is turned on under the condition that the duty command exceeds the carrier. While the upper arm switching element is on, a voltage pulse of Vdc is output from the inverter output terminal.

FIG. 5B shows an inverter output terminal voltage when dead time compensation is not performed for a PWM inverter having a dead time. Here, the polarity of the current is positive. When the PWM inverter has a dead time, a delay is inserted into the command to the switching element at the timing of shifting from the off state to the on state. In the dead time section, the switching elements of the upper arm and the lower arm are both turned off. Since the polarity of the current is positive, in the dead time section, the current flows through the free wheel diode in parallel with the lower arm switching element. For this reason, the low potential side voltage of the inverter DC input voltage appears as the inverter output terminal voltage via the freewheeling diode. Therefore, the inverter output terminal voltage is zero in the dead time interval. As a result, the width of the voltage pulse is reduced as compared with FIG.

FIG. 5C shows the inverter output terminal voltage when dead time compensation is performed on a PWM inverter with dead time. The inverter control device performs dead time compensation by converting a dead time compensation value as a voltage value calculated by the equation (1) into a value as a duty command. In FIG. 5C, the width of the voltage pulse is compensated at the timing when the switching element of the upper arm shifts from the off state to the on state by dead time compensation. Further, the width of the voltage pulse is compensated at the timing when the switching element of the upper arm shifts from the on state to the off state. As a result, the width of the voltage pulse coincides with the case of FIG. When attention is paid only to the section from the peak to the valley of the carrier, the width of the voltage pulse is reduced in FIG. 5C than in FIG. When attention is paid only to the section from the trough to the peak of the carrier, the width of the voltage pulse is increased in FIG. 5C than in FIG. However, since the voltage pulse width also increases and decreases in the other phases as well, the line voltage is maintained. As a result, the same inverter output voltage as the voltage command is obtained. However, in FIG. 5C, the generation timing of the voltage pulse is delayed by Td / 2 as compared with FIG. The deviation of the non-zero voltage vector section due to the dead time occurs in the same manner when the two-phase modulation is performed. This is because when the two-phase modulation is performed, switching does not occur in the stationary phase, but the switching timing is delayed in the non-stationary phase.

When power is supplied from the PWM inverter to the electric load, the load current includes a current ripple due to switching. Also, noise may occur with switching. In order to avoid current ripple and noise, the load current sampling timing is often set near the center of the zero voltage vector section. That is, the load current sampling timing is often set to the timing of the top of the carrier.

FIG. 6 is a diagram for explaining a mechanism in which a ripple component is superimposed on a load current. FIG. 6 shows a load current in the case where two-phase modulation is performed in the upward mode. “Average current” in FIG. 6 indicates an average value of the load current.

As shown in FIG. 6, when there is no dead time, the timing of the vertex of the carrier is near the center of the zero voltage vector section or the non-zero voltage vector section. However, when there is a dead time, the timing of the vertex of the carrier deviates from the vicinity of the center of the zero voltage vector section or the non-zero voltage vector section. Thereby, the current sampling performed at the timing of the carrier vertex is performed at a timing relatively shifted from the vicinity of the center of the zero voltage vector section. Furthermore, when performing two-phase modulation, the timing of the top of the carrier is not necessarily within the zero voltage vector interval. In the example of FIG. 6, the timing of the carrier valley is in the zero voltage vector interval, but the timing of the carrier peak is in the non-zero voltage vector interval. As described above, when the two-phase modulation is performed, the current sampling is also performed in the non-zero voltage vector section. Therefore, due to the delay of the voltage pulse generation timing due to the dead time, a relative timing shift from the vicinity of the center of the vector section occurs even in the sampling of the non-zero voltage vector section. For this reason, as shown in FIG. 6, when two-phase modulation is performed, there is a difference between a carrier peak timing and a valley timing, which is a zero voltage vector interval or a non-zero voltage vector interval. Further, the output voltage pulse delay due to the dead time is combined, and the appearance of the current ripple differs between the timing of the peak of the carrier and the timing of the valley, and the current ripple is superimposed on the sampled current value. For example, when current sampling is performed only at the timing of the carrier valley, a current value slightly larger than the average value of the current is sampled as described by the black circle in FIG. Although the above description has been given of the two-phase modulation upshift mode based on FIG. 6, the sampling current value is similarly affected by the current ripple in the two-phase modulation bottom-up mode. However, in the bottom-up mode, a non-zero voltage vector section near the carrier valley appears. Therefore, in the downshift mode, the influence of current ripple is reversed from that in the upshift mode. For example, when current sampling is performed only in the valley of the carrier, a current value slightly smaller than the average value of the current is sampled.

As described above, when current sampling is simply performed at the timing of the peak and valley of the carrier, a difference occurs between the sampling current values of both as shown in FIG. Thereby, for example, when current control of an electric load is performed using a sampling current value, the load current oscillates when the control response is increased. For this reason, the control response in current control cannot be set very high. In order to prevent this problem, current sampling may be performed at the timing of only one of the peak or valley of the carrier.

However, as shown in FIG. 6, when current sampling is performed only in the peak or valley of the carrier, there is a problem that a current pulsation having a period three times the inverter output frequency is generated in the load current. This current pulsation is caused by the difference between the sampling current and the average current being different between the two-phase modulation upshift mode and the downshift mode. Details will be described below.

FIG. 7 is a diagram illustrating an example of a simulation result in which a current pulsation having a period three times the inverter output frequency is generated in the load current. FIG. 7 shows a case where current sampling is performed only at the valley of the carrier. FIG. 7 shows a case where two-phase modulation is performed in the shift mode. Iq is a waveform indicating the load current. The Iq average is a waveform indicating an average current actually flowing through the electric load. The Iq sampling value is a waveform indicating a sampling current value obtained by current sampling.

As shown in FIG. 7, in the two-phase modulation in the double shift mode, the upper shift state and the lower shift state are switched a total of six times every π / 3 during one period of the voltage command. At this time, different ripple components flow into the sampling current every π / 3. As a result, when confirmed on a rotating coordinate synchronized with an alternating load current, a rectangular wave current pulsation having a fundamental wave component having a frequency three times the inverter output frequency is generated in the load current. When the electric load is a motor, torque ripple occurs due to this current pulsation. Torque ripple causes noise and vibration. In particular, when the frequency of the current pulsation matches the resonance frequency of the motor machine load, noise and vibration are noticeable. Since the ripple component is included in the sampling current, it cannot be detected by the inverter control device unless specially devised. For this reason, it is difficult to remove the ripple component. The current pulsation is manifested by switching between the upper and lower states in the two-phase modulation.

When there is a dead time, the sampling current value at the timing of only one of the peak and valley of the carrier includes an error with respect to the average value of the load current. As shown in FIG. 6, in the upward state, the sampling current value at the timing of only the carrier valley is larger than the average value of the load current. In the uplift state, the sampling current value at the timing of only the carrier peak is smaller than the average value of the load current. On the other hand, although not shown in the drawing, the sampling current value at the timing of only the carrier valley is smaller than the average value of the load currents in the lowering state. In the lowering state, the sampling current value at the timing of only the carrier peak is larger than the average value of the load current. For this reason, the Iq sampling value deviates from the Iq average.

FIG. 8 is a configuration diagram of the inverter control device according to Embodiment 1 of the present invention. A PWM inverter (not shown) is connected to the inverter control device. An electrical load (not shown) is connected to the PWM inverter. The inverter control device is configured to perform current control of the electric load. Here, as an example, the electric load is an AC motor.

The inverter control apparatus includes a current command calculation unit 1, a current control unit 3, a first coordinate converter 5, a second coordinate converter 8, a two-phase modulation processing unit 10, a dead time compensation unit 12, a PWM processing unit 14, An integrator 17 and a two-phase modulation mode setting means 19 are provided.

The two-phase modulation mode setting unit 19 includes a current pulsation frequency calculation unit 19a, a prohibited frequency band information recording unit 19c, a first determination unit 19e, a second determination unit 19g, and a power loss calculation unit 19h.

The current command calculation means 1 outputs a current command 2. The detection current 4 is detected from an AC motor that is an electric load. The detection current 4 is an AC signal. The first coordinate converter 5 converts the detected current 4 into a detected current 6 on dq rotation coordinates. The first coordinate converter 5 outputs a detection current 6. The detection current 4 and the detection current 6 correspond to a sampling current.

The current control means 3 performs a current control process so that the current command 2 and the detected current 6 match. The current control means 3 generates a duty command 7 by performing a current control process. The current control means 3 outputs a duty command 7. The duty command 7 indicates ON or OFF of the switching voltage pulse of the PWM inverter. The duty command is converted from the voltage command by the following equation (2). Vd ^* and Vq ^* are voltage commands on dq rotation coordinates. Dd ^* and Dq ^* are duty commands. Vdc is the voltage of the PWM inverter DC input section.

The second coordinate converter 8 converts the duty command 7 into a duty command 9 on stationary coordinates. The duty command 9 has a value in the range of −1 to 1.

The two-phase modulation mode setting means 19 outputs a two-phase modulation mode command 20. The two-phase modulation mode command 20 designates in which two-phase modulation mode the two-phase modulation processing means 10 performs the two-phase modulation. The two-phase modulation processing means 10 performs a two-phase modulation process based on the duty command 9 and the two-phase modulation mode command 20. The two-phase modulation processing means 10 outputs a duty command 11 that has been subjected to two-phase modulation processing.

When the two-phase modulation is performed in the upshift mode, the two-phase modulation processing unit 10 sets a phase having a positive value and a maximum absolute value in the duty command 9 as a fixed phase. The two-phase modulation processing means 10 slides the value of the fixed phase duty command to 1. The two-phase modulation processing means 10 adds the same value as the slide amount with respect to the fixed phase duty command to the non-fixed phase duty command.

When the two-phase modulation is performed in the downshift mode, the two-phase modulation processing unit 10 sets a phase having a negative value and a maximum absolute value in the duty command 9 as a fixed phase. The two-phase modulation processing means 10 slides the value of the fixed phase duty command to -1. The two-phase modulation processing means 10 subtracts the same value as the sliding amount with respect to the fixed phase duty command from the non-fixed phase duty command.

When two-phase modulation is performed in the shift mode, the two-phase modulation processing unit 10 sets the phase having the maximum absolute value in the duty command 9 as a fixed phase. The two-phase modulation processing means 10 performs upper adjustment when the sign of the fixed phase duty command is positive. The two-phase modulation processing means 10 performs lowering when the sign of the fixed phase duty command is negative.

When the electric load is a three-phase AC motor, the duty command 9 has an AC sine wave waveform whose phase is shifted by 2π / 3 as shown in FIG. Therefore, the phase having the maximum absolute value and the polarity of the duty command 9 can be determined from the phase of the duty command 9. That is, the two-phase modulation processing means 10 can also determine the fixed phase based on the phase of the duty command 9.

The dead time compensation means 12 performs dead time compensation for the duty command 11. However, in the stationary phase, no dead time compensation is required because switching is not performed. The dead time compensation means 12 performs dead time compensation according to the current polarity in the non-fixed phase. Since the calculated value of the equation (1) is a voltage value, the dead time compensation means 12 performs dead time compensation using the dead time compensation value converted into a value as a duty command. The dead time compensation value converted into a value as a duty command is calculated by the following equation (3).

The dead time compensation means 12 outputs the duty command 13 after dead time compensation. The PWM processing unit 14 converts the duty command 13 into the switching command 15 by performing comparison with the carrier. The PWM processing means 14 outputs a switching command 15. The PWM inverter is driven based on the switching command 15.

The frequency command 16 corresponds to the inverter output frequency. The frequency command 16 also corresponds to the voltage applied to the AC motor and the frequency of the current flowing through the AC motor. The integrator 17 performs an integration process on the frequency command 16. The frequency command 16 becomes a phase signal 18 by integration processing. The phase signal 18 is used in the first coordinate converter 5 and the second coordinate converter 8. A plurality of methods for acquiring and calculating the frequency command 16 and the phase signal 18 are known depending on the type and control method of the AC motor, but the description thereof is omitted.

Hereinafter, the operation of the two-phase modulation mode setting means 19 will be described. Here, the current sampling is performed at the timing of only the peak or the valley of the carrier.

As shown in FIG. 7, when the two-phase modulation is performed in the shift mode, the sampling current value taken into the inverter control device is constant. However, the load current that actually flows through the AC motor pulsates with the switching between the upper and lower positions. In particular, as shown in FIG. 6, it is remarkable when current sampling is performed at the timing of only the peak or the valley of the carrier. As described above, one of the causes of this current pulsation is the delay of the inverter output voltage pulse due to the dead time. The influence of the delay becomes relatively greater as the amplitude of the inverter output voltage is smaller. For this reason, the smaller the amplitude of the inverter output voltage, the larger the amplitude of the current pulsation. The case where the amplitude of the inverter output voltage is small is, for example, a case where an AC motor that is an electric load is driven at a low speed.

When current sampling is performed at the timing of only the peak or the valley of the carrier and two-phase modulation is performed in the shift mode, the current pulsation has a frequency three times the frequency of the duty command. Since this current pulsation has a rectangular wave shape, it includes a harmonic component. For this reason, the current pulsation includes a component 3x times the inverter output frequency, where x is an odd number.

Based on the frequency command 16, the current pulsation frequency calculation means 19 a calculates a frequency that is 3 × times the inverter output frequency. The current pulsation frequency calculation means 19a outputs the calculated frequency as frequency information 19b. The frequency information 19b is a frequency component of current pulsation that accompanies switching between the up-shift state and the down-shift state in the double shift mode.

The prohibited frequency band information recording means 19c records in advance frequency band information 19d indicating a frequency band that is not desirably included in the load current. The frequency band information 19d is, for example, the resonance frequency of the AC motor and its mechanical load.

The first determination unit 19e determines whether or not the frequency information 19b is included in the frequency band information 19d. The first determination means 19e outputs a two-phase modulation mode command 19f based on the determination result. The two-phase modulation mode command 19f indicates whether or not to perform two-phase modulation in the shift mode.

When the frequency information 19b is not included in the frequency band information 19d, the first determination unit 19e outputs a two-phase modulation mode command 19f that designates the shift mode as the two-phase modulation mode. On the other hand, when the frequency information 19b is included in the frequency band information 19d, the first determination unit 19e outputs a two-phase modulation mode command 19f that does not designate the shift mode as the two-phase modulation mode.

The second determination unit 19g outputs a two-phase modulation mode command 20 based on the two-phase modulation mode command 19f. When the two-phase modulation mode command 19f designates the registration mode as the two-phase modulation mode, the second determination unit 19g similarly gives the two-phase modulation mode command 20 that designates the registration mode as the two-phase modulation mode. Output.

When the two-phase modulation mode command 19f does not designate the shift mode as the two-phase modulation mode, the second determination unit 19g selects either the upper shift mode or the lower shift mode as the two-phase modulation mode. The second determination unit 19g selects either the upshift mode or the downshift mode based on the power loss 19i in each switching element of the PWM inverter. The power loss 19i is output from the power loss calculation means 19h.

Here, the power loss in the switching element of the PWM inverter will be described. For example, when two-phase modulation is performed in the upward mode, the upper arm of the PWM inverter corresponding to the fixed phase is kept on. As a result, a current flows through the switching element of the upper arm, and power loss occurs. At this time, no power loss occurs in the switching element of the lower arm. For this reason, when the two-phase modulation is performed, the power loss in the entire PWM inverter is reduced. However, in the upper and lower positions, power loss is uneven between the switching elements of the upper arm and the lower arm. As a result, the heat generation is biased between the switching elements. Note that the switching element is, for example, an IGBT or an FWD.

When the two-phase modulation mode command 19f switches from the one specifying the shift mode to the one not specifying the shift mode, the second determination unit 19g determines whether the upper shift mode or the lower shift mode 19g is based on the power loss 19i of each switching element. Select one of the shift modes. Specifically, the second determination unit 19g determines which of the switching elements of the PWM inverter the switching element with the maximum power loss 19i belongs to the upper arm group or the lower arm group. When the switching element that maximizes the power loss 19i belongs to the upper arm group, the second determination unit 19g selects the lowering mode. When the switching element that maximizes the power loss 19i belongs to the lower arm group, the second determination unit 19g selects the upward mode. Then, the second determination means 19g outputs a two-phase modulation mode command 20 that designates the selected one as the two-phase modulation mode.

The power loss calculating unit 19h calculates the power loss 19i of each switching element from the duty command 11, the detected current 4, and the like. In the present embodiment, a specific description of the calculation method of the power loss 19i is omitted. A method for calculating the power loss 19i is provided by a power module manufacturer in the form of an application note or the like. The calculation method of the power loss 19i is described in "Transistor technology SPECIAL No. 85 revision * Practical power electronics (P87 to P91)".

The inverter control device in the present embodiment increases the accuracy of dead time compensation processing. Specifically, the dead time compensation unit 12 changes the dead time compensation value represented by the equation (3) based on the two-phase modulation mode command 20.

9 and 10 are diagrams for explaining the dead time compensation in the first embodiment of the present invention. FIG. 9 shows an example in which the duty command is switched from the top-up state to the bottom-up state. FIG. 10 shows an example in which the duty command is switched from the bottom-up state to the top-up state. Here, as an example, FIGS. 9 and 10 show the U phase among the three phases. Hereinafter, with reference to FIG. 9 and FIG.

The U phase shown in FIG. 9 is a non-stationary phase when in the up-aligned state, and is a stationary phase when in the down-aligned state. In other words, the V phase and the W phase are non-stationary phases when in the lowering state. When the state is switched from the upper alignment state to the lower alignment state, the duty command corresponding to the U phase changes from a value between -1 and 1 to -1. At this time, switching occurs because the duty command intersects with the carrier. When the U-phase current polarity is negative, a current flows through the free wheel diode in parallel with the upper arm switching element in the dead time interval. Therefore, the U-phase inverter output terminal voltage in the dead time interval becomes Vdc, and the voltage pulse width increases by Td. This deviation of the inverter output terminal voltage is caused by switching associated with switching between the upper and lower states. Therefore, the deviation of the inverter output terminal voltage cannot be compensated by a process of adding a dead time compensation value to the U-phase duty command as in the normal dead time compensation.

Therefore, the dead time compensation values corresponding to the V phase and the W phase are changed so that the change timings of the V-phase and W-phase inverter output terminal voltages that have become non-fixed phases are delayed by Td. Thereby, although the generation timing of the voltage vector is delayed, the line voltage applied to the AC motor is maintained. Specific processing for the duty command of the V phase and the W phase, which have become non-fixed phases, is performed as follows.

When the V-phase current polarity is negative, the V-phase inverter output terminal voltage in the dead time section is Vdc. That is, the change timing of the V-phase inverter output terminal voltage is automatically delayed by Td halfway due to the dead time. For this reason, dead time compensation is unnecessary in the V phase. In this case, the dead time compensation means 12 changes the dead time compensation value corresponding to the V phase to zero. The same applies to the W phase.

When the V-phase current polarity is positive, the V-phase inverter output terminal voltage in the dead time interval is zero. For this reason, it is necessary to delay the change timing of the V-phase inverter output terminal voltage by Td. The time change rate of the carrier is the slope of the carrier waveform shown in FIG. Since the slope of the carrier waveform is {1-(− 1)} / {1 / (2 · fc)} = 4 · fc, the dead time compensation value is 4 · Td · fc. This value is twice the calculated value of equation (3). That is, the dead time compensation means 12 changes the dead time compensation value corresponding to the V phase to twice the calculated value of equation (3). The same applies to the W phase.

In summary, the inverter control device improves the dead time compensation processing as follows.

[In the case of FIG. 9]
When the carrier valley is switched from the top-down state to the bottom-up state, and the current polarity of the non-fixed phase in the top-up state and the phase that becomes the stationary phase in the bottom-up state is negative.
-If the current polarity of the non-fixed phase in the bottoming-up state is positive, the dead time compensation value corresponding to the non-fixed phase is doubled from the calculated value of equation (3).
・ If the current polarity of the non-stationary phase is negative in the bottom-up state, the dead time compensation value corresponding to the non-stationary phase is set to zero.

[In the case of FIG. 10]
When the carrier peak is switched from the bottom-up state to the top-up state, and the current polarity of the non-stationary phase in the bottom-up state and the phase that becomes the stationary phase in the top-up state is positive.
-If the current polarity of the non-stationary phase in the upward state is positive, the dead time compensation value corresponding to the non-stationary phase is doubled from the calculated value of equation (3).
・ If the current polarity of the non-fixed phase in the up-aligned state is negative, the dead time compensation value corresponding to the non-fixed phase is set to zero.

As described above, the inverter control device according to the present embodiment calculates the frequency component of the rectangular wave-like current pulsation that occurs in association with the switching between the up-shifted state and the down-shifted state. Then, when the frequency component of the current pulsation is included in the pre-recorded frequency band, the inverter control device sets the two-phase modulation mode to the upshift mode or the downshift mode instead of the double shift mode. That is, the occurrence of current pulsation is suppressed by fixing the duty command to the up-shifted state or the down-shifted state. Thereby, excitation of mechanical resonance components such as a motor driven by the PWM inverter can be prevented. As a result, noise and vibration caused by current pulsation can be suppressed.

As described above, the inverter control device according to the present embodiment selects either the upshift mode or the downshift mode as the two-phase modulation mode based on the power loss 19i of each switching element. Thereby, it can prevent that a current burden concentrates on a specific switching element. For this reason, temperature concentration on a specific switching element can be prevented. As a result, destruction of the switching element can be prevented and the life of the power module can be extended.

As described above, the inverter control device in the present embodiment increases the accuracy of the dead time compensation processing based on the two-phase modulation mode command 20. As a result, it is possible to appropriately compensate for a voltage error that occurs due to unintended switching associated with switching between the upper and lower states. As a result, a highly accurate inverter output voltage can be obtained.

As described above, the inverter control device according to the present embodiment selects either the upshift mode or the downshift mode as the two-phase modulation mode based on the power loss 19i of each switching element. However, the same effect can be obtained by selecting the two-phase modulation mode based on the average power loss of the upper arm group and the average power loss of the lower arm group. In this case, the inverter control device compares the average power loss of the upper arm group with the average power loss of the lower arm group. The inverter control device selects the uplift mode when the average value of the power loss of the upper arm group is smaller than the average value of the power loss of the lower arm group. The inverter control device selects the lowering mode when the average power loss of the upper arm group is larger than the average power loss of the lower arm group.

As described above, the inverter control device according to the present embodiment selects either the upshift mode or the downshift mode as the two-phase modulation mode based on the power loss 19i of each switching element. However, the same effect can be obtained by selecting the two-phase modulation mode based on the junction temperature of each switching element. In this case, the inverter control device determines which of the switching elements, the switching element having the maximum junction temperature belongs to the upper arm group or the lower arm group. When the switching element having the maximum junction temperature belongs to the lower arm group, the inverter control device selects the uplift mode. When the switching element having the maximum junction temperature belongs to the upper arm group, the inverter control device selects the lowering mode.

Embodiment 2. FIG.
In the present embodiment, the operation of the second determination means 19g is different from that of the first embodiment. Hereinafter, the difference from the first embodiment will be mainly described.

In the first embodiment, the second determination unit 19g selects either the upper mode or the lower mode as the two-phase modulation mode based on the power loss or the junction temperature of the switching element. However, in the present embodiment, the second determination unit 19g selects either the upshift mode or the downshift mode as the two-phase modulation mode based on the electric energy for each switching element. The amount of power is an integrated value of power loss.

Here, consider a large-capacity PWM inverter that drives a motor that repeats frequent acceleration / deceleration and stoppage. Such a motor is used for hoisting an elevator, for example. Such a motor may be operated at a very low speed including when stopped. For this reason, the current burden of each switching element of the PWM inverter in a long period often becomes non-uniform. In such a case, referring to the electric energy corresponds to referring to the current burden history. In the present embodiment, the two-phase modulation mode is selected based on the amount of power for each switching element so as to alleviate the non-uniformity of the current burden. As a result, fatigue concentration on a specific switching element can be prevented and the life of the power module can be extended.

In addition, a large-capacity PWM inverter has a large main circuit structure on which a power module is mounted. For this reason, the temperature of each switching element may become non-uniform | heterogenous because the thermal resistance of a cooler becomes non-uniform | heterogenous. Since this temperature non-uniformity is derived from the housing structure of the PWM inverter, it may not be resolved even if the current burden of each switching element is made uniform. In such a case, when the two-phase modulation mode is simply selected based on the temperature, the current burden is concentrated on the switching element having a low temperature. The fatigue of the power module depends not only on the absolute value of the temperature but also on the repeated rise and fall of the temperature. For this reason, if the two-phase modulation mode is simply selected based on temperature, fatigue concentrates on a specific switching element. In the present embodiment, the two-phase modulation mode can be selected based on the electric energy for each switching element so as to alleviate the non-uniformity of current burden. As a result, fatigue concentration on a specific switching element can be prevented and the life of the power module can be extended.

When performing control to stop the two-phase modulation shift mode as described in the first embodiment according to conditions, a system having a plurality of mechanical resonance frequencies, such as an elevator, is higher than the shift mode. The time during which the two-phase modulation is performed in the shift mode or the shift mode is relatively long. For this reason, the selection method of the two-phase modulation mode based on the electric energy in the present embodiment is particularly effective in preventing fatigue concentration on a specific switching element.

Embodiment 3 FIG.
FIG. 11 is a configuration diagram of the inverter control device according to the third embodiment of the present invention. Hereinafter, the difference from the first embodiment will be mainly described.

As shown in FIG. 11, in the present embodiment, the inverter control device includes a two-phase modulation mode setting unit 21, an inverter output voltage calculation unit 22, a current compensation value calculation unit 24, and an adder 26.

As described above, a rectangular wave-shaped current pulsation is generated in the load current in accordance with the switching between the upper and lower states. In the present embodiment, the inverter control device estimates the difference between the sampling current value and the average value of the load current. Then, the inverter control device eliminates the influence of the current pulsation by compensating the detected current 6. Therefore, the operation of the two-phase modulation mode setting means 21 simply designates any of the shift mode, the upper shift mode, and the lower shift mode as the two-phase modulation mode.

Hereinafter, a specific compensation method for the detection current 6 will be described. As shown in FIG. 6, the current pulsation is caused by the current ripple by PWM and the sampling timing of the load current. The influence of current ripple is reduced if current sampling is performed near the center of the zero voltage vector section or the non-zero voltage vector section. However, in reality, current pulsation occurs because the non-zero voltage vector section is delayed by Td / 2 due to the dead time. Therefore, a current value at a time point Td / 2 ahead of the sampling timing is predicted. Then, the sampling current value is compensated by the difference value between the sampling current value and the predicted current value. Compensating the sampling current value in this way corresponds to performing current control using the predicted current value.

Here, an IPM is taken as an example of the AC motor. The IPM is an embedded magnet type permanent magnet synchronous motor. The circuit equation of IPM is the following equation (4). Vd and Vq are dq axis voltages. id and iq are dq axis currents. ω is an electrical angular frequency. Ld is a d-axis inductance. Lq is a q-axis inductance. R is a resistance. Φ is an induced voltage constant.

When equation (4) is transformed into a state equation, the following equation (5) is obtained. p is a differential operator.

The right side of equation (5) corresponds to the current differential value of the dq axis. When the right side of equation (5) is multiplied by Td / 2, which is time, the following equation (6) is obtained. idsmp and iqsmp are sampling current values. idsmp and iqsmp correspond to the detection current 6. idcmp and iqcmp are dq axis current compensation values. idcmp and iqcmp correspond to the current compensation signal 25. Vdinv and Vqinv are dq axis voltages.

The current compensation value calculation means 24 calculates a current compensation value by the equation (6) using an electric load model. The current compensation value calculation means 24 outputs a current compensation signal 25. The adder 26 adds the current compensation signal 25 to the detected current 6. The current control means 3 performs a current control process using the compensated detection current 6. Thereby, a current ripple component can be compensated and current pulsation can be suppressed. That is, the adder 26 functions as current compensation means.

Hereinafter, the dq axis voltages Vdinv and Vqinv used for the calculation of the equation (6) will be described. Vdinv and Vqinv are calculated based on the duty command 11 and the two-phase modulation mode command 20 in consideration of PWM.

When current sampling is performed at the timing of only the carrier peak in the bottom-up state, the sampling timing is within the zero voltage vector interval. In this case, the dq axis voltage is zero. In addition, when current sampling is performed at the timing of only the carrier valley in the upward state, the sampling timing is within the zero voltage vector interval. Also in this case, the dq-axis voltage is zero.

In cases other than the above two conditions, the inverter output voltage calculation means 22 estimates the voltage vector output from the PWM inverter in consideration of the PWM. For example, let us consider a case in which current sampling is performed at the timing of only the carrier peak in the upward state. When the U phase is a stationary phase, the switching element of the upper arm of the U phase is turned on. On the other hand, the switching elements of the upper arms of the V phase and the W phase are turned off. At this time, the inverter output voltages Vuinv, Vvinv, and Vwinv are expressed by the following equation (7). When the equation (7) is converted onto the αβ phase which is the stationary two-phase coordinate, the following equation (8) is obtained. Vαinv and Vβinv are inverter output voltages on stationary two-phase coordinates.

12 and 13 are tables for estimating the inverter output voltage in the third embodiment of the present invention. FIG. 12 describes information when current sampling is performed at the timing of only the carrier peak in the upward state. FIG. 13 shows information when current sampling is performed at the timing of only the carrier valley in the bottom-up state. The voltage command phase (U) is a phase in which the U-phase voltage command or the duty command becomes a cos signal. The inverter output voltage coefficient is a coefficient that becomes an inverter output voltage when multiplied by Vdc.

The inverter output voltage calculation means 22 determines the fixed phase when the two-phase modulation is performed based on the duty command 11 and the two-phase modulation mode command 20. And the inverter output voltage calculation means 22 calculates inverter output voltage V (alpha) inv and V (beta) inv based on the information of FIG.12 and FIG.13. Vαinv and Vβinv are converted into voltages Vdinv and Vqinv on the dq rotation coordinates by the following equation (9). Vdinv and Vqinv correspond to the inverter voltage signal 23. The current compensation value calculation means 24 calculates the equation (6) using the calculation result of the equation (9). Note that θ is a signal for coordinate conversion. θ corresponds to the phase signal 18.

As described above, the inverter control device in the present embodiment predicts a current value at a time point that is Td / 2 ahead of the sampling timing. The inverter control device eliminates the influence of the current pulsation by compensating the sampling current value with a difference value between the sampling current value and the predicted current value. Thereby, excitation of mechanical resonance components such as a motor driven by the PWM inverter can be prevented. As a result, noise and vibration caused by current pulsation can be suppressed.

In the first to third embodiments, the case where the present invention is applied to a two-level three-phase inverter is described. However, the present invention may be applied to, for example, a three-level three-phase inverter. In this case, the same effect can be obtained by suppressing the influence of the current pulsation.

The switching element and the diode element may be formed of a wide band gap semiconductor. Wide band gap semiconductors have high voltage resistance and allowable current density. For this reason, a switching element and a diode element can be reduced in size by using a wide band gap semiconductor. By using miniaturized switching elements and diode elements, an inverter control device incorporating these elements can be miniaturized. That is, the inverter control device can be reduced in size by using a switching element and a diode element formed of a wide band gap semiconductor.

As described above, the inverter control device according to the present invention can be used for an inverter that drives an electric load.

1 current command calculation means, 2 current command, 3 current control means, 4, 6 detection current, 5 first coordinate converter, 7, 9, 11, 13 duty command, 8 second coordinate converter, 10 2 phase Modulation processing means, 12 dead time compensation means, 14 PWM processing means, 15 switching command, 16 frequency command, 17 integrator, 18 phase signal, 19 two-phase modulation mode setting means, 19a current pulsation frequency calculation means, 19b frequency information, 19c Prohibited frequency band information recording means, 19d frequency band information, 19e first determination means, 19f, 20 two-phase modulation mode command, 19g second determination means, 19h power loss calculation means, 19i power loss, 21 two-phase modulation Mode setting means, 22 Inverter output voltage calculation means, 23 Inverter voltage signal, 24 Current償値 calculation unit, 25 current compensation signal, 26 an adder

Claims

Two-phase modulation mode setting means for specifying a two-phase modulation mode for driving the inverter based on an output frequency of the inverter;
Two-phase modulation processing means for performing two-phase modulation based on a voltage command and a two-phase modulation mode designated by the two-phase modulation mode setting means;
With
The first determination means determines whether x is an odd number and a frequency that is 3x times the output frequency of the inverter is included in a preset frequency band;
The two-phase modulation mode setting means designates the upshift mode or the downshift mode as the two-phase modulation mode when it is determined that the frequency band of 3 × times the output frequency of the inverter is included in the frequency band, When it is determined that a frequency 3x times the output frequency is not included in the frequency band, a two-phase modulation mode is designated as a two-phase modulation mode that switches between the upper and lower states according to the absolute value and polarity of the voltage command. Inverter control device.
The two-phase modulation mode setting means, when it is determined that a frequency that is 3x times the output frequency of the inverter is included in the frequency band, is based on the power loss in the switching element of the inverter, The inverter control device according to claim 1, which designates as a two-phase modulation mode.
The two-phase modulation mode setting means, when it is determined that a frequency that is 3x times the output frequency of the inverter is included in the frequency band, is based on the temperature of the switching element of the inverter, The inverter control device according to claim 1 specified as a two-phase modulation mode.
If it is determined that the frequency band includes a frequency that is 3 × times the output frequency of the inverter, the two-phase modulation mode setting means may increase the power based on the amount of power accumulated by the power loss for each switching element of the inverter. The inverter control device according to claim 1, wherein the shift mode or the shift mode is designated as a two-phase modulation mode.
An inverter output voltage calculation means for calculating the output voltage of the inverter;
Current compensation value calculation means for calculating a current compensation value based on the output voltage and electric load model calculated by the inverter output voltage calculation means;
Current compensation means for compensating the detected current detected from the electrical load connected to the inverter by adding the current compensation value calculated by the current compensation value calculation means;
Two-phase modulation mode setting means for designating a two-phase modulation mode for driving the inverter;
Two-phase modulation processing means for performing two-phase modulation based on a voltage command and a two-phase modulation mode designated by the two-phase modulation mode setting means;
Inverter control device equipped with.
A dead time compensation means for compensating a voltage error between the output voltage of the inverter and a voltage command;
6. The dead time compensation means changes a dead time compensation value when an upshift state and a downshift state are switched based on a two-phase modulation mode designated by the two-phase modulation mode setting means. The inverter control device according to any one of the above.
The inverter control device according to claim 2 or 3, wherein the switching element is formed of a wide band gap semiconductor.