WO2015055129A1 - 射频识别中的负载调制电路 - Google Patents

射频识别中的负载调制电路 Download PDF

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Publication number
WO2015055129A1
WO2015055129A1 PCT/CN2014/088734 CN2014088734W WO2015055129A1 WO 2015055129 A1 WO2015055129 A1 WO 2015055129A1 CN 2014088734 W CN2014088734 W CN 2014088734W WO 2015055129 A1 WO2015055129 A1 WO 2015055129A1
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Prior art keywords
load modulation
nmos transistor
gate
source
drain
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PCT/CN2014/088734
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English (en)
French (fr)
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傅志军
马和良
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上海华虹集成电路有限责任公司
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Priority to US15/029,413 priority Critical patent/US9665820B2/en
Publication of WO2015055129A1 publication Critical patent/WO2015055129A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/70—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes
    • H04B5/72—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes for local intradevice communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/70—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes
    • H04B5/77—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes for interrogation

Definitions

  • the present invention relates to the field of analog integrated circuit load modulation circuits, and more particularly to a load modulation circuit for radio frequency identification.
  • the RFID card In radio frequency identification, the RFID card needs to couple the analog signal from the card reader, and demodulate the data sent by the card reader through the RF circuit in the card and send it to the digital circuit for processing.
  • the digital circuit returns the processed data to the card reader through the load modulation circuit, which completes the entire communication process.
  • the process of returning data to the card reader is load modulation.
  • the waveform of the load modulation and the depth of the load modulation are not good, which will affect the demodulation of the data by the card reader. Therefore, the load modulation circuit is very important and critical. Should have a better load modulation waveform and a larger load modulation depth.
  • the existing load modulation circuit consists of NMOS transistors MN1 to MN3 and inverter INV1. Composition. Among them, NMOS transistor MN3 is equivalent to a switch, it is turned on when modulation, and is turned off when it is not modulated. DIN is a load modulation signal, which is provided and controlled by digital circuit. NMOS The turn-on and turn-off of transistor MN3 affects the signal on the antenna when the NMOS transistor MN3 When turned on, the signal on the antenna is pulled down to form a groove. One groove signal is the load modulation waveform. These load modulation waveforms carry data and are finally demodulated by the card reader. Inductance L1 in Figure 1, L2, capacitor C1 constitutes a coupling circuit. The input signal IN inductors L1, L2 are coupled to the card end and the load modulation waveform at the card end can also be coupled to the reader side.
  • the advantage of this structure is that it is simple and easy to implement. It works well under small field strength, and the load modulation waveform and load modulation depth are good. The disadvantage is that under the large field strength, the load modulation waveform and the load modulation depth are worse. It is difficult for the card reader to correctly demodulate its data, or it may easily cause the card reader to demodulate errors. If the card reader demodulates an error, the entire communication will fail.
  • the technical problem to be solved by the present invention is to provide a load modulation circuit for radio frequency identification, which can better improve load modulation waveform and load modulation depth under large field strength, improve compatibility of radio frequency identification cards, and ensure radio frequency identification cards and Normal communication between card readers.
  • the load modulation circuit in the radio frequency identification of the present invention includes a first load modulation module connected to the coupling circuit; wherein, the method further includes:
  • a second load modulation module coupled to the coupling circuit; at a set small field strength, the load modulation operation is mainly performed by the first load modulation module, and the second load modulation module applies a load modulation waveform and a load modulation depth
  • the contribution is much smaller than the first load modulation module; as the field strength increases, the contribution of the first load modulation mode to the load modulation waveform and the load modulation depth is gradually reduced; as the field strength increases, the second load modulation module is controlled.
  • the variable voltage is also gradually increased.
  • the contribution of the second load modulation module to the load modulation waveform and the load modulation depth is gradually increased; when the large field strength is set, the load modulation is mainly performed by the first The second load modulation module is completed, and the first load modulation module contributes much less to the load modulation waveform and the load modulation depth than the second load modulation module.
  • the load modulation circuit of the present invention is based on the existing load modulation circuit, and adds a load modulation module, that is, the load modulation module is controlled by a voltage that varies with the field strength.
  • the traditional load modulation circuit works normally.
  • the newly added load modulation module has a smaller control voltage value, and the load modulation tube is smaller, and the effect on load modulation is limited, so the field strength is small.
  • the load modulation of the signal is mainly performed by the existing load modulation module. When the field strength increases, the existing load modulation module still works, but the load modulation waveform and the load modulation depth are not ideal at this time. The contribution to the load modulation waveform and the load modulation depth is gradually reduced as the field strength increases.
  • the load modulation tube since the variable voltage controlled by it increases as the field strength increases, the load modulation tube also gradually turns on as the variable voltage of its control increases, so that the new one is added.
  • the load modulation module also begins to work and contributes to the load modulation waveform and load modulation depth.
  • the workplace strength continues to increase, for example to 7.5A/m
  • the field strength is large, the voltage at both ends of the antenna is also large, and the existing load modulation module is saturated, contributing little to the load modulation waveform and the load modulation depth, and in the newly added load modulation module, its control
  • the voltage is already large, which means that the load modulation tube is fully turned on, and the load modulation waveform and load modulation depth are also ideal. Therefore, under large field strength, the load modulation operation is mainly performed by the newly added load modulation module.
  • the improved load modulation circuit not only can generate better load modulation waveform and larger load modulation depth under small field strength, but also can generate better load modulation waveform and larger load modulation depth under large field strength; It can better improve the load modulation waveform and load modulation depth under large field strength.
  • the compatibility of the RFID card can be greatly improved, so that it is compatible with various card readers, thereby ensuring normal communication between the RFID card and the card reader.
  • Figure 1 is a schematic diagram of a conventional load modulation circuit
  • FIG. 2 is a schematic diagram of an embodiment of a load modulation circuit in the radio frequency identification.
  • the load modulation circuit in the radio frequency identification has two load modulation modules, namely a first load modulation module and a second load modulation module. Both load modulation modules are connected to the coupling circuit.
  • the limiter circuit provides a variable voltage for the second load modulation module VLIM.
  • the variable voltage VLIM changes as the field strength changes. Variable voltage VLIM when working in small field strength The voltage value is lower, and as the field strength increases, the voltage value also increases.
  • the variable voltage VLIM when working at large field strength The voltage value also increases, so that the second load modulation module can be controlled to participate more in load modulation.
  • the coupling circuit is composed of an inductor L1, an inductor L2 and a first capacitor C1.
  • the input signal IN is coupled to the RFID card terminal through the inductor L1 and the inductor L2, and the first capacitor C1 Resonance occurs, resulting in a higher resonant voltage; the carrier signal and the envelope signal are coupled from the reader end to the RFID card end.
  • the demodulation circuit demodulates the corresponding digital signal from the envelope signal and sends it to the digital circuit for processing.
  • the digital processed data also needs to be coupled from the RFID card end to the reader end via a coupling circuit.
  • the data processed by the digital circuit is coupled from the RFID card end to the card reader end in a load modulation manner, that is, the digital circuit controls the control signals of the first load modulation module and the second load modulation module.
  • the voltage value at the DIN terminal is used to implement load modulation.
  • First load modulation module and Figure 1 The existing load modulation circuit has the same structure and participates in load modulation under all field strengths, but contributes less to load modulation under large field strength.
  • the first load modulation module is composed of a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS
  • the transistor MN3 is composed of a first inverter INV1.
  • the gate and drain of the first NMOS transistor MN1 are connected to the ANT1 terminal of the inductor L2 in the coupling circuit, and the second The gate and drain of the NMOS transistor MN2 are connected to the other terminal ANT2 of the inductor L2 in the coupling circuit.
  • the source of the first NMOS transistor MN1 and the second NMOS transistor The source of MN2 is connected to the drain of the third NMOS transistor MN3.
  • the input of the first inverter INV1 inputs a control signal DIN , which is a control signal DIN Provided by digital circuitry.
  • the output of the first inverter INV1 is connected to the gate of the third NMOS transistor MN3, and the source of the third NMOS transistor MN3 is grounded.
  • the second load modulation module is a newly added one-way load modulation module, and its contribution to load modulation is more reflected in the large field strength.
  • the second load modulation module is composed of a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS.
  • the transistor MN6 is composed of a first PMOS transistor MP1, a second inverter INV2, and a third inverter INV3.
  • the drain of the fourth NMOS transistor MN4 is connected to the ANT1 terminal of the inductor L2 in the coupling circuit, fifth The NMOS transistor MN5 is connected to the other end ANT2 of the inductor L2 in the coupling circuit.
  • the source of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 The source is grounded.
  • the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, and the node to which it is connected is denoted as the terminal A.
  • First PMOS transistor MP1 The source input variable voltage VLIM is provided by the limiter circuit.
  • the drain of the first PMOS transistor MP1 and the drain of the sixth NMOS transistor MN6 and the end point Phase A is connected, and the source of the sixth NMOS transistor MN6 is grounded.
  • the input terminal of the second inverter INV2 is connected to the gate of the sixth NMOS transistor MN6, and the control signal DIN is input. .
  • the output of the second inverter INV2 is connected to the input of the third inverter INV3, and the output of the third inverter INV3 is connected to the gate of the first PMOS transistor MP1.
  • the function of the limiting circuit is mainly to ensure that B in Figure 2
  • the voltage of the point is stabilized, and in addition, a variable voltage VLIM is also provided for the second load modulation module in this embodiment.
  • the limiting circuit is composed of a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS.
  • the MN13 is composed of a first resistor R1.
  • the gate and drain of the seventh NMOS transistor MN7 are connected to the ANT1 terminal of the inductor L2 in the coupling circuit, and the eighth NMOS transistor
  • the gate and drain of MN8 are connected to the other terminal ANT2 of inductor L2 in the coupling circuit.
  • the source of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 The source is connected and its connected node is recorded as endpoint B.
  • the source of the ninth NMOS transistor MN9, the source of the twelfth NMOS transistor MN12, and the thirteenth NMOS transistor MN13 The drain is connected to the terminal B.
  • Gate and drain of the ninth NMOS transistor MN9 and the gate of the twelfth NMOS transistor MN12 and the tenth NMOS transistor MN10 The source is connected.
  • the gate and drain of the tenth NMOS transistor MN10 are connected to the source of the eleventh NMOS transistor MN11. Eleventh NMOS transistor MN11 The gate and drain are grounded.
  • the drain of the twelfth NMOS transistor MN12 and one end of the first resistor R1 and the thirteenth NMOS transistor MN13 The gates are connected, and the voltage at the connection node is the variable voltage VLIM.
  • the source of the thirteenth NMOS transistor MN13 is grounded.
  • the voltage at point B rises and is greater than the ninth NMOS transistor MN9
  • the threshold voltages of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are summed, the voltage value of the variable voltage VLIM rises, and the thirteenth NMOS is gradually turned on.
  • the transistor MN13 bleeds off the excess current, and the voltage at point B will decrease, and finally stabilizes at the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, and the eleventh NMOS.
  • the third NMOS transistor MN3 in the first load modulation module Turn on, control the first NMOS transistors MN1 and MN2 Start load modulation.
  • the first load modulation module plays a decisive role, which in itself provides a better load modulation waveform and load modulation depth.
  • the sixth NMOS transistor MN6 when the modulation control signal DIN When the level is low, the sixth NMOS transistor MN6 is first turned off, and the first PMOS transistor MP1 is turned on, and the variable voltage VLIM provided by the limiter circuit is smoothly transmitted to the point A, A
  • the point voltage controls the turn-off and turn-on of the NMOS transistors MN4 and MN5, and the second load modulation module also begins load modulation.
  • the variable voltage VLIM The voltage value is lower, that is, the voltage at point A is lower, so NMOS transistors MN4 and MN5
  • the turn-on is small or has not been turned on, so the second load modulation module contributes less to the load modulation waveform and the load modulation depth.
  • the first load modulation module still works normally, and still can provide a certain degree of load modulation waveform and load modulation depth, but the load modulation waveform and load modulation depth are not ideal at this time, and the load modulation waveform is And the contribution of the load modulation depth gradually decreases as the field strength increases.
  • the second load modulation module increases as the control voltage increases as the field strength increases, and the variable voltage provided by the limiter circuit When VLIM increases, the voltage at point A also increases, that is, NMOS transistors MN4 and MN5 With the gradual turn-on and turn-on, more involved in the load modulation work.
  • the load modulation waveform and the load modulation depth at this time are jointly determined by the two load modulation circuits, and the contribution magnitude varies with the field strength.
  • the field strength is small, the contribution of the second load modulation module is small, the field is strong, and the contribution of the second load modulation module is increased.
  • the load modulation circuit 1 When the work field strength continues to increase, for example, to 7.5 A/m, the voltage value at both ends of the antenna is also large due to the large field strength, and the load modulation circuit 1 It is saturated and contributes little to the load modulation waveform and load modulation depth.
  • the control voltage is already large, that is, the load modulation tube is turned on very well, and the load modulation waveform and the load modulation depth are also ideal. Therefore, under large field strength, the load modulation work is mainly performed by The second load modulation module determines that the contribution of the first load modulation module is small. Therefore, the load modulation circuit of the present invention not only has a good load modulation waveform and load modulation depth at a small field strength, but also a load modulation waveform and a load modulation depth at a medium field strength and a large field strength.
  • the working field strength of RFID cards is generally 1.5A/m to 7.5A/m. .
  • the defined large field strength may vary greatly. Generally, when the field strength is 6A/m or more, it can be considered as a large field strength, or the field strength is 7A/m. The above can be considered as a large field strength.
  • the defined small field strengths may vary widely.
  • the field strength is less than 1.5A/m. It can be considered as a small field strength.

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Abstract

提供一种射频识别中的负载调制电路，所述负载调制电路包括一与耦合电路相连接的第一负载调制模块的第二负载调制模块；在小场强时，负载调制的工作主要由第一负载调制模块完成，第二负载调制模块对负载调制波形和负载调制深度的贡献远小于第一负载调制模块；随着场强的增加，第一负载调制模对负载调制波形和负载调制深度的贡献逐渐减小；随着场强的增加，在可变电压的控制下，第二负载调制模块对负载调制波形和负载调制深度的贡献逐渐增加；在大场强时，负载调制的工作主要由第二负载调制模块完成。所述负载调制电路能够较好地改善大场强下的负载调制波形和负载调制深度，提升射频识别卡片的兼容性，保证射频识别卡片和读卡机之间的正常通讯。

Description

射频识别中的负载调制电路
本发明涉及模拟集成电路负载调制电路领域，特别是涉及一种射频识别中的负载调制电路。
在射频识别中，射频识别卡片需要耦合读卡机发出来的模拟信号，并经卡片中射频电路解调出读卡机发出的数据再送给数字电路处理。数字电路将处理后的数据再经过负载调制电路返回给读卡机，这就完成了整个通讯过程。将数据返回给读卡机的过程就是负载调制，负载调制的波形和负载调制深度不好，会影响读卡机对数据的解调；因此负载调制电路非常重要和关键，在各个场强下都应具有较好的负载调制波形和较大的负载调制深度。
参见图 1 所示，现有的负载调制电路，由 NMOS 晶体管 MN1 ～ MN3 ，反相器 INV1 组成。其中， NMOS 晶体管 MN3 就相当于一个开关，调制的时候就导通，不调制的时候就关闭， DIN 是负载调制信号，由数字电路提供并控制。 NMOS 晶体管 MN3 的导通和关闭会影响着天线上的信号，当 NMOS 晶体管 MN3 导通时，天线上的信号被拉下来，形成一个凹槽，一个一个的凹槽信号就是负载调制波形，这些负载调制波形中带有数据，最后再由读卡机解调出来。图 1 中电感 L1 、 L2 ，电容 C1 组成耦合电路。将输入信号 IN 电感 L1 、 L2 耦合到卡片端，并且也能将卡片端的负载调制波形耦合到读卡机端。
这种结构的优点是简单，容易实现，工作在小场强下，负载调制波形和负载调制深度都还不错；缺点是工作在大场强下，负载调制波形和负载调制深度都变差，很多读卡机都难以正确解调其数据，或者容易导致读卡机解调错误。如果读卡机解调出错，整个通讯也就失败了。
本发明要解决的技术问题是提供一种射频识别中的负载调制电路，能较好的改善大场强下的负载调制波形和负载调制深度，提升射频识别卡片的兼容性，保证射频识别卡片和读卡机之间的正常通讯。
为解决上述技术问题，本发明的射频识别中的负载调制电路，包括一与耦合电路相连接的第一负载调制模块；其中，还包括：
一与所述耦合电路相连接的第二负载调制模块；在设定的小场强时，负载调制的工作主要由第一负载调制模块完成，第二负载调制模块对负载调制波形和负载调制深度的贡献远小于第一负载调制模块；随着场强的增加，第一负载调制模对负载调制波形和负载调制深度的贡献逐渐减小；随着场强的增加，控制第二负载调制模块的可变电压也逐渐增加，在该可变电压的控制下，第二负载调制模块对负载调制波形和负载调制深度的贡献逐渐增加；在设定的大场强时，负载调制的工作主要由第二负载调制模块完成，第一负载调制模块对负载调制波形和负载调制深度的贡献远小于第二负载调制模块。
本发明的负载调制电路，是在现有的负载调制电路基础上，再加一路负载调制模块，即通过一个随场强变化的电压来控制这路负载调制模块。当工作在小场强时，传统的负载调制电路正常工作，新加的负载调制模块由于其控制电压值比较小，负载调制管开启较小，对负载调制的作用比较有限，因此在小场强下，主要由现有的负载调制模块完成信号的负载调制。当工作场强增加时，现有的负载调制模块仍然工作，但是此时的负载调制波形和负载调制深度都不是很理想，对负载调制波形和负载调制深度的贡献随着场强增加而逐渐减小，而在新加的负载调制模块中，由于对其控制的可变电压随着场强增加而增加，负载调制管也随着其控制的可变电压增加而逐渐的开启，于是新加的负载调制模块也开始工作，并对负载调制波形和负载调制深度作出贡献。当工作场强继续增加时，比如到 7.5A/m 时，由于场强很大，天线两端的电压值也很大，现有的负载调制模块已经饱和，对负载调制波形和负载调制深度贡献很小，而在新加的负载调制模块中，其控制电压已经很大，也就是说负载调制管开启的非常充分，负载调制波形和负载调制深度也较理想因此在大场强下，负载调制工作主要由新加的负载调制模块完成。
改进后的负载调制电路不仅在小场强下能产生较好的负载调制波形和较大的负载调制深度，在大场强下也能产生较好的负载调制波形和较大的负载调制深度；能较好的改善大场强下的负载调制波形和负载调制深度。进而能够较大的提升射频识别卡片的兼容性，使得其兼容各种读卡机，从而保证射频识别卡片和读卡机之间的正常通讯。
下面结合附图与具体实施方式对本发明作进一步详细的说明：
图 1 是现有的负载调制电路原理图；
图 2 是所述射频识别中的负载调制电路一实施例原理图。
参见图 2 所示，所述射频识别中的负载调制电路具有两个负载调制模块，即第一负载调制模块和第二负载调制模块。两个负载调制模块均与耦合电路相连接。限幅电路为第二负载调制模块提供一个可变电压 VLIM 。该可变电压 VLIM 会随着场强的变化而变化。当工作在小场强时，可变电压 VLIM 的电压值较低，随着场强的增加，其电压值也随着增加。当工作在大场强时，该可变电压 VLIM 的电压值也随着增大，这样就可控制第二负载调制模块更多的参与负载调制工作。 所述耦合电路由电感 L1 ，电感 L2 和第一电容 C1 组成。第一电容 C1 并联在电感 L2 的两端，输入信号 IN 通过电感 L1 和电感 L2 耦合到射频识别卡片端，并与第一电容 C1 发生谐振，产生较高的谐振电压；同时将载波信号和包络信号从读卡机端耦合到射频识别卡片端。解调电路从包络信号中解调出对应的数字信号，送给数字电路处理。数字电路处理后的数据也需要通过耦合电路将其从射频识别卡片端耦合到读卡机端。数字电路处理后的数据从射频识别卡片端耦合到读卡机端是以负载调制的方式进行的，即数字电路通过控制第一负载调制模块和第二负载调制模块的控制信号 DIN 端的电压值来实现负载调制。
第一负载调制模块与图 1 中现有的负载调制电路结构完全相同，参与所有场强下的负载调制，但是对大场强下的负载调制贡献较小。
第一负载调制模块由第一 NMOS 晶体管 MN1 ，第二 NMOS 晶体管 MN2 ，第三 NMOS 晶体管 MN3 和第一反相器 INV1 组成。
第一 NMOS 晶体管 MN1 的栅极和漏极与耦合电路中电感 L2 的一端 ANT1 端相连接，第二 NMOS 晶体管 MN2 的栅极和漏极与耦合电路中电感 L2 的另一端 ANT2 端相连接。第一 NMOS 晶体管 MN1 的源极与第二 NMOS 晶体管 MN2 的源极和第三 NMOS 晶体管 MN3 的漏极相连接。第一反相器 INV1 的输入端输入控制信号 DIN ，该控制信号 DIN 由数字电路提供。第一反相器 INV1 的输出端与第三 NMOS 晶体管 MN3 的栅极相连接，第三 NMOS 晶体管 MN3 的源极接地。
第二负载调制模块是新增加的一路负载调制模块，它对负载调制的贡献更多的体现在大场强下。
第二负载调制模块由第四 NMOS 晶体管 MN4 ，第五 NMOS 晶体管 MN5 ，第六 NMOS 晶体管 MN6 ，第一 PMOS 晶体管 MP1 ，第二反相器 INV2 和第三反相器 INV3 组成。
第四 NMOS 晶体管 MN4 的漏极与耦合电路中电感 L2 的一端 ANT1 端相连接，第五 NMOS 晶体管 MN5 与耦合电路中电感 L2 的另一端 ANT2 端相连接。第四 NMOS 晶体管 MN4 的源极与第五 NMOS 晶体管 MN5 的源极接地。第四 NMOS 晶体管 MN4 的栅极与第五 NMOS 晶体管 MN5 的栅极相连接，其连接的节点记为端点 A 。第一 PMOS 晶体管 MP1 的源极输入可变电压 VLIM ，该可变电压 VLIM 由限幅电路提供。第一 PMOS 晶体管 MP1 的漏极与第六 NMOS 晶体管 MN6 的漏极与所述端点 A 相连接，第六 NMOS 晶体管 MN6 的源极接地。第二反相器 INV2 的输入端与第六 NMOS 晶体管 MN6 的栅极相连接，并输入控制信号 DIN 。第二反相器 INV2 的输出端与第三反相器 INV3 的输入端相连接，第三反相器 INV3 的输出端与第一 PMOS 晶体管 MP1 的栅极相连接。
所述限幅电路的作用主要是保证图 2 中 B 点的电压稳定，另外在本实施例中还将为第二负载调制模块提供一可变电压 VLIM 。
所述限幅电路由第七 NMOS 晶体管 MN7 ，第八 NMOS 晶体管 MN8 ，第九 NMOS 晶体管 MN9 ，第十 NMOS 晶体管 MN10 ，第十一 NMOS 晶体管 MN11 ，第十二 NMOS 晶体管 MN12 ，第十三 NMOS 晶体管 MN13 和第一电阻 R1 组成。第七 NMOS 晶体管 MN7 的栅极和漏极与耦合电路中电感 L2 的一端 ANT1 端相连接，第八 NMOS 晶体管 MN8 的栅极和漏极与耦合电路中电感 L2 的另一端 ANT2 端相连接。第七 NMOS 晶体管 MN7 的源极与第八 NMOS 晶体管 MN8 的源极相连接，其连接节点记为端点 B 。第九 NMOS 晶体管 MN9 的源极、第十二 NMOS 晶体管 MN12 的源极和第十三 NMOS 晶体管 MN13 的漏极与所述端点 B 相连接。第九 NMOS 晶体管 MN9 的栅极和漏极与第十二 NMOS 晶体管 MN12 的栅极以及第十 NMOS 晶体管 MN10 的源极相连接。第十 NMOS 晶体管 MN10 的栅极和漏极与第十一 NMOS 晶体管 MN11 的源极相连接。第十一 NMOS 晶体管 MN11 的栅极和漏极接地。第十二 NMOS 晶体管 MN12 的漏极与第一电阻 R1 的一端和第十三 NMOS 晶体管 MN13 的栅极相连接，该连接节点的电压即为可变电压 VLIM 。第十三 NMOS 晶体管 MN13 的源极接地。当 B 点电压升高并大于第九 NMOS 晶体管 MN9 、第十 NMOS 晶体管 MN10 和第十一 NMOS 晶体管 MN11 的阈值电压之和时，可变电压 VLIM 的电压值就升高，并逐渐打开第十三 NMOS 晶体管 MN13 泄放多余电流，随之 B 点电压将降低，最后稳定在第九 NMOS 晶体管 MN9 、第十 NMOS 晶体管 MN10 和第十一 NMOS 晶体管 MN11 的阈值电压之和的电压值上。因此，可变电压 VLIM 的电压值是随着场强变化而变化的，场强小，可变电压 VLIM 的电压值就小，场强大，可变电压 VLIM 的电压值就变大。
在小场强时，当调制控制信号 DIN 为低电平时，第一负载调制模块中的第三 NMOS 晶体管 MN3 就导通开启，控制第一 NMOS 晶体管 MN1 和 MN2 开始负载调制。此时，第一负载调制模块起着决定性的作用，它本身就能提供较好的负载调制波形和负载调制深度。而第二负载调制模块中，当调制控制信号 DIN 为低电平时，第六 NMOS 晶体管 MN6 首先被关闭，第一 PMOS 晶体管 MP1 导通，顺利将限幅电路提供的可变电压 VLIM 传输到 A 点， A 点电压就控制着 NMOS 晶体管 MN4 和 MN5 的关闭和导通，于是第二负载调制模块也开始了负载调制。但是由于是小场强，可变电压 VLIM 的电压值较低，也就是说 A 点电压比较低，因此 NMOS 晶体管 MN4 和 MN5 的开启很小，或者还没有开启，所以此时第二负载调制模块对负载调制波形和负载调制深度的贡献较小。
随着工作场强增加，第一负载调制模块仍然正常工作，仍然可以提供一定程度的负载调制波形和负载调制深度，但是此时的负载调制波形和负载调制深度都不是很理想，对负载调制波形和负载调制深度的贡献随着场强增加而逐渐减小。而第二负载调制模块由于其控制电压随着场强增加而增加，当限幅电路提供的可变电压 VLIM 增加时， A 点电压值也增加，也就是说 NMOS 晶体管 MN4 和 MN5 就逐渐的导通和开启，更多的参与了负载调制工作。此时的负载调制波形和负载调制深度由两个负载调制电路共同决定，其贡献大小随着场强的变化而变化。场强小，第二负载调制模块的贡献就小，场强大，第二负载调制模块的贡献就增加。
当工作场强继续增大时，比如到 7.5A/m 时，由于场强很大，天线两端的电压值也很大，负载调制电路 1 已经饱和，对负载调制波形和负载调制深度贡献很小。而在第二负载调制模块中，其控制电压已经很大，也就是说负载调制管开启的非常充分，负载调制波形和负载调制深度也较理想，因此在大场强下，负载调制工作主要由第二负载调制模块决定，第一负载调制模块的贡献较小。因此本发明的负载调制电路不仅在小场强下的负载调制波形和负载调制深度好，中间场强和大场强下的负载调制波形和负载调制深度也很好。
射频识别卡片的工作场强一般是 1.5A/m ～ 7.5A/m 。对于不同类型的射频识别卡片，其定义的大场强可能差别很大，一般情况下当场强为 6A/m 以上时可以认为是大场强，或者当场强为 7A/m 以上时可以认为是大场强。
类似的对于不同类型的射频识别卡片，其定义的小场强也可能差别很大。例如场强小于 1.5A/m 时可以认为是小场强。
虽然本发明利用具体的实施例进行说明，但是对实施例的说明并不限制本发明的范围。本领域内的熟练技术人员通过参考本发明的说明，在不背离本发明的精神和范围的情况下，容易进行各种修改或者可以对实施例进行组合。

Claims (5)

  1. 一种射频识别中的负载调制电路，包括一与耦合电路相连接的第一负载调制模块；其特征在于，还包括：
    一与所述耦合电路相连接的第二负载调制模块；在设定的小场强时，负载调制的工作主要由第一负载调制模块完成，第二负载调制模块对负载调制波形和负载调制深度的贡献远小于第一负载调制模块；随着场强的增加，第一负载调制模对负载调制波形和负载调制深度的贡献逐渐减小；随着场强的增加，控制第二负载调制模块的可变电压也逐渐增加，在该可变电压的控制下，第二负载调制模块对负载调制波形和负载调制深度的贡献逐渐增加；在设定的大场强时，负载调制的工作主要由第二负载调制模块完成，第一负载调制模块对负载调制波形和负载调制深度的贡献远小于第二负载调制模块。
  2. 如权利要求 1 所述的负载调制电路，其特征在于：
    所述耦合电路由第一电感（ L1 ），第二电感（ L2 ）和第一电容（ C1 ）组成；第一电容（ C1 ）并联在第二电感（ L2 ）的两端，输入信号 IN 通过第一电感（ L1 ）和第二电感（ L2 ）耦合到射频识别卡片端，并与第一电容 C1 发生谐振，产生谐振电压；同时将载波信号和包络信号从读卡机端耦合到射频识别卡片端；数字电路处理后的数据也需要通过耦合电路将其从射频识别卡片端耦合到读卡机端。
  3. 如权利要求 1 或 2 所述的负载调制电路，其特征在于：
    所述第一负载调制模块由第一 NMOS 晶体管（ MN1 ），第二 NMOS 晶体管（ MN2 ），第三 NMOS 晶体管（ MN3 ）和第一反相器组成；第一 NMOS 晶体管（ MN1 ）的栅极和漏极与耦合电路中第二电感（ L2 ）的一端（ ANT1 ）端相连接，第二 NMOS 晶体管（ MN2 ）的栅极和漏极与耦合电路中第二电感（ L2 ）的另一端（ ANT2 ）端相连接；第一 NMOS 晶体管（ MN1 ）的源极与第二 NMOS 晶体管（ MN2 ）的源极和第三 NMOS 晶体管（ MN3 ）的漏极相连接；第一反相器（ INV1 ）的输入端输入控制信号 DIN ，该控制信号 DIN 由数字电路提供。第一反相器（ INV1 ）的输出端与第三 NMOS 晶体管（ MN3 ）的栅极相连接，第三 NMOS 晶体管（ MN3 ）的源极接地。
  4. 如权利要求 1 或 2 所述的负载调制电路，其特征在于：
    所述第二负载调制模块由第四 NMOS 晶体管（ MN4 ），第五 NMOS 晶体管（ MN5 ），第六 NMOS 晶体管（ MN6 ），第一 PMOS 晶体管（ MP1 ），第二反相器（ INV2 ）和第三反相器（ INV3 ）组成；
    第四 NMOS 晶体管（ MN4 ）的漏极与耦合电路中第二电感（ L2 ）的一端（ ANT1 ）端相连接，第五 NMOS 晶体管（ MN5 ）与耦合电路中第二电感（ L2 ）的另一端（ ANT2 ）端相连接；第四 NMOS 晶体管（ MN4 ）的源极与第五 NMOS 晶体管（ MN5 ）的源极接地；第四 NMOS 晶体管（ MN4 ）的栅极与第五 NMOS 晶体管（ MN5 ）的栅极相连接，其连接的节点记为端点 A ；第一 PMOS 晶体管（ MP1 ）的源极输入可变电压 VLIM ，该可变电压 VLIM 由限幅电路提供；第一 PMOS 晶体管（ MP1 ）的漏极与第六 NMOS 晶体管（ MN6 ）的漏极与所述端点 A 相连接，第六 NMOS 晶体管（ MN6 ）的源极接地；第二反相器（ INV2 ）的输入端与第六 NMOS 晶体管（ MN6 ）的栅极相连接，并输入控制信号 DIN ；第二反相器（ INV2 ）的输出端与第三反相器（ INV3 ）的输入端相连接，第三反相器（ INV3 ）的输出端与第一 PMOS 晶体管（ MP1 ）的栅极相连接。
  5. 如权利要求 4 所述的负载调制电路，其特征在于：
    所述限幅电路由第七 NMOS 晶体管（ MN7 ），第八 NMOS 晶体管（ MN8 ），第九 NMOS 晶体管（ MN9 ），第十 NMOS 晶体管（ MN10 ），第十一 NMOS 晶体管（ MN11 ），第十二 NMOS 晶体管（ MN12 ），第十三 NMOS 晶体（ MN13 ）和第一电阻（ R1 ）组成；
    第七 NMOS 晶体管（ MN7 ）的栅极和漏极与耦合电路中第二电感（ L2 ）的一端（ ANT1 ）端相连接，第八 NMOS 晶体管（ MN8 ）的栅极和漏极与耦合电路中第二电感（ L2 ）的另一端（ ANT2 ）端相连接；第七 NMOS 晶体管（ MN7 ）的源极与第八 NMOS 晶体管（ MN8 ）的源极相连接，其连接节点记为端点 B ；第九 NMOS 晶体管（ MN9 ）的源极、第十二 NMOS 晶体管（ MN12 ）的源极和第十三 NMOS 晶体管（ MN13 ）的漏极与所述端点 B 相连接；第九 NMOS 晶体管（ MN9 ）的栅极和漏极与第十二 NMOS 晶体管（ MN12 ）的栅极以及第十 NMOS 晶体管（ MN10 ）的源极相连接。第十 NMOS 晶体管（ MN10 ）的的栅极和漏极与第十一 NMOS 晶体管（ MN11 ）的源极相连接；第十一 NMOS 晶体管（ MN11 ）的栅极和漏极接地；第十二 NMOS 晶体管（ MN12 ）的漏极与第一电阻 R1 的一端和第十三 NMOS 晶体管（ MN13 ）的栅极相连接，该连接节点的电压即为可变电压 VLIM ；第十三 NMOS 晶体管（ MN13 ）的源极接地。
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CN113259292A (zh) * 2021-05-28 2021-08-13 卓捷创芯科技（深圳）有限公司 一种差分输入的射频识别标签调幅波包络信号解调电路

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