WO2015043083A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2015043083A1
WO2015043083A1 PCT/CN2013/089157 CN2013089157W WO2015043083A1 WO 2015043083 A1 WO2015043083 A1 WO 2015043083A1 CN 2013089157 W CN2013089157 W CN 2013089157W WO 2015043083 A1 WO2015043083 A1 WO 2015043083A1
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Prior art keywords
light
pixel electrode
emitting structure
array substrate
layer
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English (en)
French (fr)
Inventor
张金中
田宗民
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/371,883 priority Critical patent/US20160141342A1/en
Publication of WO2015043083A1 publication Critical patent/WO2015043083A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/13356—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements
    • G02F1/133565—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements inside the LC elements, i.e. between the cell substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • Embodiments of the present invention relate to the field of liquid crystal display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD is composed of a liquid crystal display panel, a driving circuit, and a backlight module, wherein the liquid crystal display panel is an important part of the TFT-LCD.
  • the liquid crystal display panel is formed by injecting liquid crystal between the array substrate and the color filter substrate, sealing with a sealant around the frame, and then attaching polarizing plates having polarization directions perpendicular to each other on the array substrate and the color filter substrate.
  • FIG. 1 is a plan view of a prior art array substrate
  • FIG. 2 is a cross-sectional view of the array substrate taken along line A-A1 of FIG. As can be seen from FIG. 1 and FIG.
  • the array substrate includes a plurality of pixel units arranged in a matrix, each of the pixel units including a light transmissive area and a non-transmissive area, wherein the dotted line EE, and the dotted line CC, the defined area is a pixel.
  • the light transmissive area of the cell, the dashed line CC, and the dashed line DD, the defined area is the non-transparent area of the pixel unit.
  • the non-transmissive region may include scan lines 101 and data lines 102 that are alternately disposed on the base substrate 100, and thin film transistors 10 arranged in a matrix.
  • the thin film transistor 10 may include a gate electrode 103, a gate insulating layer 104, an active layer 105, a source 106, and a drain 107.
  • the light transmissive area may include a pixel electrode 108.
  • the active layer 105 is formed of an amorphous silicon (a-Si) material
  • the thin film transistor formed of the amorphous silicon material has the advantages of mature technology, low cost, single process, good stability, and the like; however, it is made of amorphous silicon material.
  • the formed thin film transistor has poor characteristics, and the most basic parameters representing the characteristics of the thin film transistor include: carrier mobility, threshold voltage, and sub-threshold amplitude.
  • p-Si polysilicon
  • p-Si polysilicon
  • metal oxide materials thin film transistors formed using metal oxide materials have emerged, in which thin film transistors formed using polysilicon materials have high TFT characteristics and carrier mobility. Higher advantages, but the characteristics of thin film transistors formed using polysilicon materials are unstable, both
  • the thin film transistor formed by the oxide material has the advantages of high characteristics and good uniformity, but the production cost is high and the manufacturing process is complicated.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device, which can increase the aperture ratio of a pixel.
  • An embodiment of the present invention provides an array substrate, the array substrate includes: a plurality of pixel units arranged in a matrix, the pixel unit includes a light transmitting area and a non-light transmitting area, the light transmitting area includes a pixel electrode, and the non-light transmitting area includes a thin film transistor, a scan line, and a data line, wherein the pixel electrode is located above the layer where the thin film transistor is located, and the pixel electrode partially or completely covers the non-transmissive area; the pixel unit further includes a layer disposed above the thin film transistor and insulated from the pixel electrode The light emitting structure is disposed, and the coverage area of the light emitting structure corresponds to the coverage area of the pixel electrode for providing a backlight.
  • the light emitting structure may be connected to the common electrode line and used as a common electrode of the array substrate to further process the manufacturing process, thereby saving production costs.
  • a common electrode may be added to the array substrate, and the common electrode may generate an electric field together with the pixel electrode to drive the liquid crystal layer molecules to deflect.
  • the light emitting structure may include a cathode disposed above the pixel electrode, a luminescent material layer disposed on the cathode, and an anode disposed on the luminescent material layer, wherein the anode may be connected to the common electrode line; or, the illuminating structure may include An anode disposed above the pixel electrode, a layer of luminescent material disposed on the anode, and a cathode disposed above the layer of luminescent material, wherein the anode can be connected Common electrode line.
  • the light emitting structure may be located above the pixel electrode, wherein the light emitting structure is a slit shape, the pixel electrode is a plate shape or a slit shape; or the light emitting structure is located below the pixel electrode, and the light emitting structure is a slit shape or a plate shape.
  • the pixel electrode has a slit shape.
  • the gate insulating layer of the thin film transistor may have a thickness of about 6,000 to 8,000 angstroms, which is about twice the thickness of the gate insulating layer in a general thin film transistor. Increasing the thickness of the gate insulating layer can effectively reduce the coupling capacitance between the gate and the source and the drain of the thin film transistor, thereby reducing the power consumption of the thin film transistor.
  • the array substrate may further include a passivation layer disposed between the layer where the thin film transistor is located and the pixel electrode, so that the pixel electrode can be formed in the upper region of the thin film transistor while protecting the thin film transistor from being corroded;
  • a via hole may also be disposed in the passivation layer such that the pixel electrode is electrically connected to the drain of the thin film transistor through the via hole.
  • the array substrate may further include a second passivation layer disposed between the pixel electrode and the light emitting structure to isolate the pixel electrode from the light emitting structure.
  • the thin film transistor may have a top gate structure or a bottom gate structure.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the embodiment of the present invention further provides a method for fabricating an array substrate, the method may include: a step of forming a data line, a scan line, a pixel electrode, and a step of forming a thin film transistor, wherein the pixel electrode is formed in a light transmissive area of the pixel unit, the film The transistor, the scan line and the data line are formed in a non-transparent area of the pixel unit, wherein the pixel electrode is located above the layer where the thin film transistor is located, and the pixel electrode partially or completely covers the non-transmissive area; the step of forming the light emitting structure, the light emitting structure is located Above the layer where the thin film transistor is located, it is insulated from the pixel electrode, and the coverage area of the light emitting structure corresponds to the coverage area of the pixel electrode for providing a backlight.
  • the step of forming the light emitting structure may include:
  • a pattern including an anode is formed; a pattern including a layer of a luminescent material is formed on the pattern including the anode; and a pattern including a cathode is formed on the pattern including the layer of the luminescent material.
  • the method may further include: forming a passivation layer between the layer where the thin film transistor is located and the pixel electrode, so that a pixel electrode can be formed in an upper region of the thin film transistor, and can also be used to protect the thin film transistor from being corroded .
  • the method may further include: forming a second passivation layer between the pixel electrode and the light emitting structure to isolate the pixel electrode from the light emitting structure.
  • the method may further include: forming a via hole in at least the passivation layer such that the pixel electrode is electrically connected to the drain of the thin film transistor through the via hole.
  • the coverage area of the pixel electrode includes an upper region of the thin film transistor, so that the coverage area of the pixel electrode is larger than that of the pixel electrode in the prior art; and, since the light emitting structure functions as a backlight, Therefore, light is passed through the area corresponding to the pixel electrode above the thin film transistor, and image display can be performed, thereby improving the aperture ratio of the pixel.
  • FIG. 1 is a schematic plan view showing a planar structure of an array substrate in the prior art
  • FIG. 2 is a schematic cross-sectional view of the array substrate taken along line A-A1 of FIG. 1;
  • FIG. 3 is a schematic plan view of the array substrate according to the first embodiment of the present invention;
  • FIG. 4 is a cross-sectional structural view of the array substrate taken along line B-B1 of FIG. 3;
  • FIG. 5 is a cross-sectional structural view of the light-emitting structure of the array substrate provided by the first embodiment;
  • FIG. 7 is a schematic cross-sectional structural view of an array substrate according to a third embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional structural view of a light emitting structure in a fourth embodiment
  • FIG. 9 is a schematic cross-sectional structural view of an array substrate fabricated with a gate
  • 10 is a schematic cross-sectional structural view of an array substrate fabricated with a gate insulating layer; 11 is a schematic cross-sectional view showing an array substrate on which an active layer is formed;
  • FIG. 12 is a schematic cross-sectional structural view of an array substrate fabricated with source and drain electrodes
  • FIG. 13 is a schematic cross-sectional structural view of an array substrate fabricated with a passivation layer
  • FIG. 14 is a schematic cross-sectional structural view of an array substrate fabricated with a pixel electrode
  • 15 is a schematic cross-sectional structural view of an array substrate fabricated with a second passivation layer
  • FIG. 17 is a flow chart showing the fabrication of a thin film transistor of the array substrate provided in the third embodiment.
  • a first embodiment of the present invention provides an array substrate.
  • 3 is a plan view showing the planar structure of the array substrate provided in the first embodiment of the present invention
  • FIG. 4 is a schematic view showing the cross-sectional structure of the array substrate taken along the direction B-B1 in FIG.
  • the array substrate according to the first embodiment may include: a substrate substrate 100, scan lines 101 and data lines 102 disposed on a substrate substrate, and thin film transistors 10 and pixel electrodes arranged in a matrix 108.
  • the thin film transistor 10 may include a gate electrode 103, a gate insulating layer 104, an active layer 105, a source electrode 106, and a drain electrode 107.
  • the array substrate may further include a light emitting structure 301 disposed above the pixel electrode 108 for providing a backlight.
  • the gate electrode 103 may be disposed in the same layer as the scan line 101, both located above the base substrate 100, and the scan line 101 is used to supply a scan signal to the gate electrode 103.
  • the gate electrode 103 and the scan line 101 can be made of the same material, and the materials used are generally chromium (Cr), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), etc. Transparent metals and their alloys.
  • the gate insulating layer 104 may be on the layer where the gate 103 and the scan line 101 are located, covering the gate 103 and the area above the scan line 101 for insulating the gate 103 and the scan line 101 from other layers.
  • the gate insulating layer may be formed using a silicon oxide or silicon nitride material and has a thickness of 6000 to 8000 angstroms, which is about twice the thickness of the gate insulating layer in the prior art. Increasing the thickness of the gate insulating layer 104 can effectively reduce the coupling capacitance between the gate 103 and the source 106 and the drain 107, and reduce the power consumption of the thin film transistor.
  • the active layer 105 may be on the gate insulating layer 104, and the active layer 105 is a film layer structure, and specifically may include a semiconductor material layer 105a and an ohmic contact layer 105b.
  • the layer of semiconductor material 105a can be formed using an indium gallium oxide or other transition metal oxide layer.
  • the semiconductor material layer 105a may also be formed using an amorphous silicon material or a polycrystalline silicon material.
  • the ohmic contact layer 105b may be disposed over the semiconductor material layer 105a and at a position corresponding to the source 106 and the drain 107, and is generally formed using a phosphorus-doped amorphous silicon material.
  • the source 106 and the drain 107 may be disposed in the same layer as the data line 102, both above the layer in which the active layer 105 is located, and made of the same material, and the material used is generally a non-transparent metal material or an alloy thereof.
  • Data line 102 can be electrically coupled to source 106.
  • Source 106 and drain 107 may be located on opposite sides above active layer 105.
  • the pixel electrode 108 may be located above the layer where the data line 102, the source 106, and the drain 107 are located, the coverage area including the upper region of the thin film transistor, and the pixel electrode 108 partially or entirely covering the non-transmissive region.
  • the pixel electrode 108 is generally made of a transparent oxide material such as indium tin oxide, indium oxide or aluminum oxide, and may have a plate shape or a slit shape.
  • the light emitting structure 301 may be disposed in an upper region of the pixel electrode 108 and insulated from the pixel electrode 108.
  • the light emitting structure 301 may be in the shape of a slit for providing a backlight. Meanwhile, the light emitting structure 301 may also serve as a common electrode of the array substrate. It is used to form a horizontal electric field together with the pixel electrode 108, and the liquid crystal molecules that drive the liquid crystal layer are deflected, thereby realizing wide-angle display.
  • the light emitting structure 301 may include: a cathode 3011 disposed above the pixel electrode 108; a luminescent material layer 3012 disposed over the cathode 3011; and an anode 3013 disposed over the luminescent material layer 3012.
  • the anode 3013 can be connected to the common electrode line of the array substrate.
  • the cathode 3011 and the anode 3013 are used to supply a driving voltage to the light emitting structure such that the light emitting structure generates white light.
  • the light emitting structure 301 may further include: an electron transport layer 3014 between the cathode 3011 and the luminescent material layer 3012 for introducing electrons into the luminescent material layer 3012; and a hole transport layer 3015 at the luminescent material layer 3012 and the anode 3013 Between, for introducing holes into the luminescent material layer 3012; a first barrier layer 3016 between the electron transport layer 3014 and the luminescent material layer 3012 for blocking hole transport to the cathode 3011; and a second barrier layer 3017 Located between the hole transport layer 3015 and the luminescent material layer 3012 for blocking electron transport to the anode 3013.
  • the luminescent material layer 3012 may include: an orange phosphor layer 3012a on the first barrier layer 3016; a blue phosphor layer 3012b on the orange phosphor layer 3012a; and a green phosphor layer 3012c on the blue phosphor layer 3012b.
  • electrons are injected from the cathode 3011, holes are injected from the anode 3013, electrons are introduced into the luminescent material layer 3012 through the electron transport layer 3014, and holes are introduced into the luminescent material layer 3012 through the hole transport layer 3015, and electrons are introduced.
  • the holes and the holes are combined in the luminescent material layer 3012 to form singlet excitons and triplet excitons.
  • the energy is photon and heat.
  • the way to release, part of the photons are used as a backlight to provide light for the display of the image.
  • the blue fluorescent layer 3012b when the singlet excitons transition from the excited state to the ground state, blue fluorescence can be emitted; in the orange phosphor layer 3012a and the green phosphor layer 3012c, the triplet excitons are When the ground state transitions to the excited state, green phosphorescence and orange phosphorescence can be emitted, and blue fluorescence is combined with green phosphorescence and orange phosphorescence to form white light.
  • the array substrate may further include a passivation layer 302, and the passivation layer 302 is disposed on the data line.
  • the pixel electrode can be formed over the thin film transistor while protecting the thin film transistor 10 from corrosion.
  • a via hole 303 may be disposed in the passivation layer 302, and the via hole 303 may be disposed at a position corresponding to the drain electrode 107 such that the pixel electrode 108 and the drain electrode 107 may be electrically connected through the via hole 303.
  • the array substrate may further include a second passivation layer 304 disposed above the layer where the pixel electrode 108 is located for isolating the pixel electrode 108 from the light emitting structure 301.
  • the second passivation layer 304 may be formed of a resin material, and the resin material has a lower dielectric constant than the silicon oxide and the silicon nitride material, and the coupling capacitance between the pixel electrode and the light emitting structure can be effectively reduced, thereby further reducing The power consumption of the array substrate; and the use of the resin material makes it easier to form the second passivation layer than the silicon oxide and silicon nitride materials.
  • the above array substrate may have the following driving process:
  • Applying a positive bias voltage on the gate 103 causes the thin film transistor to be turned on, the data signal is transmitted from the source 106 of the thin film transistor to the drain 107 of the thin film transistor, and is transmitted through the via 303 to the pixel electrode 108;
  • a common electrode corresponding to the array substrate is coupled to the pixel electrode 108 located below it to generate an electric field for driving liquid crystal molecules to be deflected, thereby realizing wide-angle display.
  • Figure 6 shows an array substrate in accordance with a second embodiment of the present invention.
  • the structure of the array substrate of the second embodiment may be substantially the same as the structure of the array substrate of the first embodiment, with the difference being
  • the light emitting structure 301 may be disposed under the pixel electrode 108, the light emitting structure 301 may be a plate shape or a slit shape, and the pixel electrode 108 may be a slit shape.
  • the second passivation layer 304 is located on the layer where the thin film transistor is located, the light emitting structure 301 is disposed on the second passivation layer 304, the passivation layer 302 is disposed on the light emitting structure 301, and the pixel electrode 108 is disposed on the passivation layer 302.
  • the pixel electrode 108 is electrically connected to the drain 107 through the via 303', and the via 303' extends through the passivation layer 302 and the second passivation layer 304.
  • Fig. 7 shows an array substrate according to a third embodiment of the present invention.
  • the array substrate according to the third embodiment has substantially the same structure as the array substrate shown in FIG. 4, and the difference is that the array substrate shown in FIG. 4 is an array substrate of a bottom gate structure, and FIG. 7
  • the illustrated array substrate is an array substrate of a top gate structure.
  • the active layer 105 is disposed on the base substrate 100; the source 106, the drain 107, and the data line are disposed in the same layer on the active layer 105; the gate insulating layer 104 is located on the layer where the source 106 and the drain 107 are located.
  • the gate 103 is located on the gate insulating layer 104; in the array substrate shown in FIG.
  • the via 303 penetrates only the passivation layer 302, and is used in the array substrate shown in FIG. 7 to make the drain 107 and the pixel electrode
  • the electrically connected vias 303' extend through the passivation layer 302 and the gate insulating layer 104.
  • the light emitting structure 301 may also be disposed under the pixel electrode 108, and details are not described herein.
  • a fourth embodiment of the present invention provides an array substrate having substantially the same structure as the array substrate shown in FIG. 4, the difference being: the light-emitting structure in the array substrate according to the fourth embodiment has the same structure as that of FIG. The structure of the light-emitting structure in the array substrate is different. Specifically, referring to FIG. 8, in the light emitting structure of the array substrate of the fourth embodiment, the hole transport layer 3015 is disposed on the anode 3013, the second barrier layer 3017 is disposed on the hole transport layer 3015, and the luminescent material layer 3012 is disposed.
  • a first barrier layer 3016 is disposed on the luminescent material layer 3012
  • an electron transport layer 3014 is disposed on the first barrier layer 3016
  • a cathode 3011 is disposed on the electron transport layer 3014.
  • the anode 3013 generally adopts an indium tin oxide/silver/indium tin oxide multi-layer structure
  • the cathode 3011 generally uses a transparent low work function alloy material such as a magnesium-silver alloy or a lithium aluminum alloy.
  • the light emitting structure 301 can also be disposed under the pixel electrode 108, and details are not described herein.
  • a fifth embodiment of the present invention provides an array substrate, and the array substrate and the array substrate shown in FIG. 7 have substantially the same structure, and the difference is that: the light-emitting structure in the array substrate of the fifth embodiment has the same structure as that of FIG. The structure of the light-emitting structure in the array substrate is different, and the specific structure can be seen in FIG. 8. Similarly, in the array substrate provided by the fifth embodiment of the present invention, the light emitting structure 301 can also be disposed. Below the pixel electrode 108, no further details are provided here.
  • the coverage area of the pixel electrode includes an upper region of the thin film transistor, and the light emitting structure is used to provide a backlight. Since the coverage area of the pixel electrode includes the upper region of the thin film transistor, the coverage area of the pixel electrode is larger than that of the pixel electrode in the prior art, and at the same time, since the light emitting structure functions as a backlight, the pixel located above the thin film transistor is made.
  • the light passing through the area corresponding to the electrode is favorable for increasing the aperture ratio of the pixel; in addition, the light emitting structure can also be used as a common electrode of the array substrate, and together with the pixel electrode, generates a horizontal electric field for driving the liquid crystal molecules, thereby realizing a wide angle display.
  • the embodiment of the present invention further provides a method for fabricating an array substrate, the method may include: a step of forming a data line, a scan line, a pixel electrode, and a step of forming a thin film transistor, wherein the pixel electrode is formed in a light transmissive area of the pixel unit, The thin film transistor, the scan line and the data line are formed in a non-transmissive region of the pixel region, wherein the pixel electrode is located above the layer where the thin film transistor is located, the coverage region includes an upper region of the thin film transistor, and the pixel electrode partially or completely covers the non-transmissive region And a step of forming a light-emitting structure, the light-emitting structure is located above the pixel electrode, and is insulated from the pixel electrode, and the coverage area of the light-emitting structure corresponds to the coverage area of the pixel electrode for providing a backlight.
  • the array substrate provided by the first embodiment of the present invention is taken as an example to describe the manufacturing method of the array substrate in detail.
  • a metal thin film is deposited on the base substrate 100, and then processed by a patterning process to form a pattern including a scan line and a gate electrode 103.
  • the material for forming the metal thin film may be Cr, W, Non-transparent metals such as Ti, Ta, Mo, Al, Cu, and alloys thereof.
  • a silicon nitride or silicon oxide layer is deposited over the pattern including the scan lines and the gate electrodes 103 to form a gate insulating layer 104.
  • the step may specifically include: depositing a silicon nitride or silicon oxide layer over the pattern including the scan line and the gate electrode 103, having a thickness of 6000 to 8000 angstroms, which is about twice the thickness of the gate insulating layer in the prior art. Coating a photoresist on the silicon nitride or silicon oxide layer; then removing a portion of the silicon nitride or silicon oxide corresponding to the channel region by exposure, development, etc., so that the gate insulating layer corresponding to the conductive channel region The thickness of the gate insulating layer corresponding to the conductive channel in the prior art is the same, thereby ensuring a high on-state current.
  • a semiconductor material and a phosphorus-doped amorphous silicon material are sequentially deposited on the gate insulating layer 104, and then a pattern including the active layer 105 is formed by a patterning process.
  • the semiconductor material may be a polysilicon semiconductor material, an amorphous silicon semiconductor material, or a metal oxide semiconductor material.
  • a source/drain metal film is formed on the pattern including the active layer 105, and then a pattern including the data line, the source 106, and the drain 107 is formed by a patterning process.
  • a silicon nitride or silicon oxide layer is deposited on the pattern including the data line, the source 106 and the drain 107 to form a passivation layer 302, so that a pixel electrode can be subsequently formed over the thin film transistor. And for protecting the thin film transistor from corrosion; and forming a via 303 in the passivation layer 302 by a patterning process, the via 303 penetrating the passivation layer 302 and corresponding to the position of the drain 107.
  • a layer of indium tin oxide transparent conductive film is deposited on the passivation layer 302 by magnetron sputtering, and a pattern including the pixel electrode 108 is formed by a patterning process.
  • the coverage area of the pixel electrode 108 may include an upper region of the thin film transistor, and the pixel electrode partially or entirely covers the non-transmissive region of the pixel unit. Also, the pixel electrode 108 can be electrically connected to the drain 107 through the via 303.
  • a resin is spin-coated over the pattern including the pixel electrode 108 to form a second passivation layer 304 for isolating the pixel electrode 108 from the light-emitting structure 301.
  • the second passivation layer may also be made of a silicon nitride or silicon oxide material, but the resin material has a relatively low dielectric constant, which can effectively reduce the coupling capacitance between the pixel electrode and the light emitting structure, and further reduce the array substrate.
  • the power consumption, and due to the fluidity of the resin material makes it easier to form the second passivation layer relative to the silicon nitride or silicon oxide material.
  • a highly reflective conductive material, a luminescent material, and a transparent conductive material are sequentially deposited on the second passivation layer 304, and then a pattern including the light-emitting structure 301 is formed by a patterning process.
  • the light emitting structure 301 can be used to provide a backlight, and can also be used as a common electrode of the array substrate, together with the pixel electrode to generate an electric field to drive the liquid crystal molecules to deflect and realize image display.
  • the step of forming the light emitting structure 301 may include: depositing a conductive material having high reflectivity on the passivation layer, and forming a pattern including a cathode by a patterning process; depositing a light emitting material on the pattern including the cathode, and passing through a patterning process Forming a pattern comprising a layer of luminescent material; depositing a transparent conductive material on the pattern comprising the layer of luminescent material, and forming a pattern comprising the anode by a patterning process.
  • the array substrate having the structure shown in Fig. 4 provided by the first embodiment of the present invention is formed.
  • the method for fabricating the array substrate in which the light emitting structure is disposed under the pixel electrode according to the second embodiment of the present invention may be substantially the same as the method for fabricating the array substrate provided by the first embodiment of the present invention, with the difference that, referring to FIG.
  • the square of the array substrate provided by the second embodiment of the present invention is fabricated.
  • the law can include:
  • a resin is spin-coated on the pattern including the data line, source 106 and drain 107 to form a second passivation layer 304 for isolating the thin film transistor from the light emitting structure 301;
  • a high reflectivity conductive material, a luminescent material, and a transparent conductive material are sequentially deposited on the second passivation layer 304, and then a pattern including the light emitting structure 301 is formed by a patterning process;
  • the pixel electrode 108 is electrically connected to the drain 107 through the via 303', and the via 303' extends through the passivation layer 302 and the second passivation layer 304.
  • the array substrate having the structure shown in Fig. 6 provided by the second embodiment of the present invention is formed.
  • the second passivation layer, the light emitting structure, the passivation layer and the pixel electrode are sequentially formed after forming the thin film transistor, and specific reference may be made.
  • a method of fabricating the array substrate according to the second embodiment is sequentially formed after forming the thin film transistor.
  • the method for fabricating the array substrate according to the third embodiment of the present invention is similar to the method for fabricating the array substrate according to the first embodiment of the present invention, except that referring to FIG. 17, the array substrate according to the third embodiment is fabricated.
  • the step of forming a thin film transistor may include:
  • An amorphous silicon semiconductor material layer 105a and a phosphorus-doped amorphous silicon material layer are deposited on the base substrate 100.
  • a source/drain metal film is formed on the pattern including the active layer 105, and then a pattern including the data line, the source 106, and the drain 107 is formed by a patterning process;
  • a metal thin film is deposited on the gate insulating layer 104, and then patterned by a patterning process to form a pattern including a scan line and a gate electrode 103.
  • the material for forming the metal thin film may be Cr, W, Ti, Ta, Mo, Al, Cu. Non-transparent metals and their alloys.
  • the method for fabricating the array substrate according to the fourth embodiment of the present invention is similar to the method for fabricating the array substrate of the first embodiment of the present invention, except that when the array substrate of the fourth embodiment is fabricated, the light-emitting structure is formed.
  • the step may include: depositing a conductive layer having a high reflectance on the passivation layer a material, and forming a pattern including an anode by a patterning process; depositing a luminescent material on the pattern including the anode, and forming a pattern including the luminescent material layer by a patterning process; depositing a transparent conductive material on the pattern including the luminescent material layer, and patterning
  • the process forms a pattern comprising a cathode.
  • the method for fabricating the array substrate according to the fifth embodiment of the present invention is similar to the method for fabricating the array substrate of the third embodiment of the present invention, except that when the array substrate of the fifth embodiment is fabricated, the light-emitting structure is formed.
  • the steps may be the same as the steps of forming the light-emitting structure when the array substrate of the fourth embodiment is fabricated.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like;
  • the photolithography process refers to a process of forming a pattern using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the embodiment of the present invention.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the coverage area of the pixel electrode includes the upper region of the thin film transistor, the coverage area of the pixel electrode is larger than that of the pixel electrode in the prior art, and
  • the light-emitting structure acts as a backlight, so that light is passed through the area corresponding to the pixel electrode above the thin film transistor, and image display can be performed, which is advantageous for increasing the aperture ratio of the pixel.

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Abstract

提供一种阵列基板及其制作方法和显示装置。该阵列基板包括衬底基板（100）、在衬底基板（100）上交叉布置的扫描线（101）、数据线（102）以及由扫描线（101）和数据线（102）划分出的呈矩阵排列的像素单元，像素单元内设置有薄膜晶体管（10）、像素电极（108）和发光结构（301），像素电极（108）位于薄膜晶体管（10）所在的层的上方，像素电极（108）的覆盖区域包括薄膜晶体管（10）的上方区域；发光结构（301）设置在薄膜晶体管（10）所在的层的上方，其覆盖区域与像素电极（108）的覆盖区域相对应。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明的实施例涉及液晶显示技术领域， 具体地， 涉及一种阵列基板及 其制作方法和显示装置。 背景技术
薄月莫晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )具有体积小、 功耗低、无辐射等特点， 近年来得到了迅速地发展， 在当前的平板显示器市场中占据了主导地位。
TFT-LCD由液晶显示面板、驱动电路以及背光模组组成，其中液晶显示 面板是 TFT-LCD的重要部分。 液晶显示面板是通过在阵列基板和彩膜基板 之间注入液晶， 四周用封框胶密封， 然后在阵列基板和彩膜基板上分别贴覆 偏振方向相互垂直的偏振片等过程形成的。 参见图 1和图 2, 图 1为现有技 术中的阵列基板的平面结构图， 图 2为沿图 1中的 A-A1方向的阵列基板的 剖面结构示意图。 从图 1和图 2中可以看出， 阵列基板包括多个呈矩阵排列 的像素单元， 每个像素单元包括透光区域和非透光区域， 其中虚线 EE，与虚 线 CC，所界定区域为像素单元的透光区域， 虚线 CC，与虚线 DD，所界定区域 为像素单元的非透光区域。 非透光区域可以包括在衬底基板 100上交叉设置 的扫描线 101和数据线 102、 以及呈矩阵式排列的薄膜晶体管 10。 薄膜晶体 管 10可以包括栅极 103、 栅绝缘层 104、 有源层 105、 源极 106和漏极 107。 透光区域可以包括像素电极 108。
通常有源层 105采用非晶硅（a-Si )材料形成， 由非晶硅材料形成的薄 膜晶体管具有技术成熟、 成本低、 工艺筒单、 稳定性好等优点； 但是， 由非 晶硅材料形成的薄膜晶体管特性较差， 其中最基本的代表薄膜晶体管特性的 参数包括： 载流子迁移率、 阈值电压和阈下振幅。 随着显示技术的发展， 出 现了采用多晶硅（p-Si )材料形成的薄膜晶体管和采用金属氧化物材料形成 的薄膜晶体管， 其中采用多晶硅材料形成的薄膜晶体管具有 TFT特性高、 载 流子迁移率高等优点， 但采用多晶硅材料形成的薄膜晶体管特性不稳定、 均 一性差；采用氧化物材料形成的薄膜晶体管具有特性较高、均一性好等优点， 但是生成成本高， 制作工艺复杂。
随着高开口率、 高分辨率等发展趋势的需要， 目前已有多种技术可以用 于实现较高的分辨率， 如低温多晶硅薄膜晶体管技术、 半导体氧化物薄膜晶 体管技术、 降低栅极线、 源极线和漏极线宽度的细化技术， 但是开口率的改 善情况并不理想， 其中开口率是指除去每一像素的周边电路区域和薄膜晶体 管区域后的光线通过部分的面积与每一像素整体的面积之间的比例。 随着有 机发光二极管技术（Organic Light-Emitting Diode, OLED ) 的发展， OLED 被用于提高像素的开口率， 但是 OLED是电流驱动器件， 需要较高的载流子 迁移率， 只有应用低温多晶硅技术驱动 OLED才能获得较高的开口率， 但是 由于低温多晶硅中存在均一性差、 工艺复杂、 良品率低等问题， 使得应用低 温多晶硅技术驱动 OLED的方案仍无法很好地解决开口率低的问题。 发明内容
本发明的实施例提供了一种阵列基板及其制作方法和显示装置， 可以增 大像素的开口率。
本发明的实施例提供了一种阵列基板， 该阵列基板包括： 多个呈矩阵排 列的像素单元， 像素单元包括透光区域和非透光区域， 透光区域包括像素电 极， 非透光区域包括薄膜晶体管、 扫描线和数据线， 其中像素电极位于薄膜 晶体管所在的层的上方， 且像素电极部分或全部覆盖非透光区域； 像素单元 还包括设置在薄膜晶体管所在的层上方且与像素电极绝缘设置的发光结构， 发光结构的覆盖区域与像素电极的覆盖区域相对应， 用于提供背光源。
在实施例中， 发光结构可以与公共电极线连接， 用作阵列基板的公共电 极， 从而进一步筒化制作工艺， 节约生产成本。 此外， 阵列基板中还可以增 设一公共电极， 该公共电极可以和像素电极一起产生电场以驱动液晶层分子 发生偏转。
在实施例中， 发光结构可以包括设置在像素电极上方的阴极、 设置在阴 极上的发光材料层、 以及设置在发光材料层上的阳极， 其中阳极可以连接公 共电极线； 或者， 发光结构可以包括设置在像素电极上方的阳极、 设置在阳 极上的发光材料层、 以及设置在发光材料层上方的阴极， 其中阳极可以连接 公共电极线。由于发光结构中设置有两个电极用于驱动发光材料层进行发光， 消除了发光结构对具有较高载流子迁移率的薄膜晶体管的依赖， 解决了载流 子迁移率较低的薄膜晶体管不能用于制作高开口率和高分辨率显示器的问 题。
在实施例中， 发光结构可以位于像素电极的上方， 其中发光结构为狭缝 状， 像素电极为板状或狭缝状； 或者发光结构位于像素电极的下方， 发光结 构为狭缝状或板状， 像素电极为狭缝状。 通过以上结构， 可以在发光结构与 像素电极之间形成水平电场， 驱动液晶层的液晶分子发生偏转， 进而实现图 像的显示。
在实施例中， 薄膜晶体管的栅绝缘层可以具有约 6000~8000埃的厚度， 该厚度约为一般薄膜晶体管中的栅绝缘层的厚度的两倍。 增大栅绝缘层的厚 度可以有效减小薄膜晶体管的栅极与源极、 漏极之间的耦合电容， 从而降低 薄膜晶体管的功耗。
在实施例中， 阵列基板还可以包括设置在薄膜晶体管所在的层与像素电 极之间的钝化层， 使得可以在薄膜晶体管的上方区域形成像素电极， 同时用 于保护薄膜晶体管不被腐蚀； 此外， 钝化层中还可以设置有过孔， 使得像素 电极通过该过孔与薄膜晶体管的漏极电连接。
在实施例中， 阵列基板还可以包括设置在像素电极与发光结构之间的第 二钝化层， 使像素电极与发光结构进行隔离。
在实施例中， 薄膜晶体管可以具有顶栅结构或底栅结构。
本发明的实施例还提供一种显示装置， 包括上述阵列基板。
本发明的实施例还提供一种阵列基板的制作方法， 该方法可以包括： 形 成数据线、 扫描线、 像素电极的步骤和形成薄膜晶体管的步骤， 像素电极形 成在像素单元的透光区域， 薄膜晶体管、 扫描线和数据线形成在像素单元的 非透光区域， 其中像素电极位于薄膜晶体管所在的层的上方， 且像素电极部 分或全部覆盖非透光区域； 形成发光结构的步骤， 发光结构位于薄膜晶体管 所在的层的上方， 与像素电极绝缘设置， 发光结构的覆盖区域与像素电极的 覆盖区域相对应， 用于提供背光源。
在实施例中， 形成发光结构的步骤可以包括：
形成包括阴极的图形；在包括阴极的图形上形成包括发光材料层的图形； 在包括发光材料层的图形上形成包括阳极的图形；
或者， 形成包括阳极的图形； 在包括阳极的图形上形成包括发光材料层 的图形； 在包括发光材料层的图形上形成包括阴极的图形。 消除了发光结构对具有较高载流子迁移率的薄膜晶体管的依赖， 解决了载流 子迁移率较低的薄膜晶体管不能用于制作高开口率和高分辨率显示器的问 题。
在实施例中， 所述方法还可以包括： 在薄膜晶体管所在的层与像素电极 之间形成钝化层， 使得可以在薄膜晶体管的上方区域形成像素电极， 还可以 用于保护薄膜晶体管不被腐蚀。
在实施例中， 所述方法还可以包括： 在像素电极与发光结构之间形成第 二钝化层， 以将像素电极与发光结构进行隔离。
在实施例中， 所述方法还可以包括： 至少在钝化层中形成过孔， 使得像 素电极通过该过孔与薄膜晶体管的漏极电连接。
在以上阵列基板及其制作方法中， 像素电极的覆盖区域包括薄膜晶体管 的上方区域， 因此像素电极的覆盖区域较现有技术中像素电极的覆盖区域增 大； 同时， 由于发光结构充当背光源， 所以使得位于薄膜晶体管上方的像素 电极所对应的区域内有光线通过，可以进行图像显示，提高了像素的开口率。 附图说明
图 1为现有技术中的一种阵列基板的平面结构示意图；
图 2为沿图 1中的 A-A1方向截取的阵列基板的剖面结构示意图； 图 3为本发明第一实施例提供的阵列基板的平面结构示意图；
图 4为沿图 3中的 B-B1方向截取的阵列基板的剖面结构示意图； 图 5为第一实施例提供的阵列基板中的发光结构的剖面结构示意图; 图 6为本发明第二实施例提供的阵列基板的剖面结构示意图；
图 7为本发明第三实施例提供的阵列基板的剖面结构示意图；
图 8为第四实施例中的发光结构的剖面结构示意图；
图 9为完成栅极制作的阵列基板的剖面结构示意图；
图 10为完成栅绝缘层制作的阵列基板的剖面结构示意图； 图 11为完成有源层制作的阵列基板的剖面结构示意图；
图 12为完成源极和漏极制作的阵列基板的剖面结构示意图；
图 13为完成钝化层制作的阵列基板的剖面结构示意图；
图 14为完成像素电极制作的阵列基板的剖面结构示意图；
图 15为完成第二钝化层制作的阵列基板的剖面结构示意图；
图 16为制作第二实施例提供的阵列基板的流程示意图； 以及
图 17为制作第三实施例提供的阵列基板的薄膜晶体管的流程示意图。 具体实施方式 下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本发明的第一实施例提供了一种阵列基板。 图 3为本发明第一实施例提 供的阵列基板的平面结构示意图， 图 4为沿图 3中 B-B1方向截取的阵列基 板的剖面结构的示意图。 参照图 3和图 4, 根据第一实施例的阵列基板可以 包括： 衬底基板 100, 在衬底基板上交叉设置的扫描线 101和数据线 102、 以 及呈矩阵排列的薄膜晶体管 10和像素电极 108。 薄膜晶体管 10可以包括： 栅极 103、 栅绝缘层 104、 有源层 105、 源极 106和漏极 107。 阵列基板还可 以包括设置在像素电极 108上方的发光结构 301 , 发光结构 301用于提供背 光源。
具体地， 栅极 103可以与扫描线 101同层设置， 均位于衬底基板 100的 上方， 扫描线 101用于向栅极 103提供扫描信号。 栅极 103和扫描线 101可 以采用相同的材料制作， 所用的材料一般为铬（Cr )、 钨（W )、 钛（Ti )、 钼 ( Mo ), 铝（Al )、 铜 （Cu )等非透明金属及其合金。
栅绝缘层 104可以位于栅极 103与扫描线 101所在的层上，覆盖栅极 103 和扫描线 101之上的区域， 用于使栅极 103和扫描线 101与其它的层绝缘。 栅绝缘层可以采用采用硅氧化物或硅氮化物材料形成， 且其厚度为 6000-8000埃， 约为现有技术中的栅绝缘层厚度的两倍。 增大栅绝缘层 104 的厚度可以有效减小栅极 103与源极 106和漏极 107之间的耦合电容， 降低 薄膜晶体管的功耗。 有源层 105可以位于栅绝缘层 104上， 有源层 105为膜层结构， 具体可 以包括半导体材料层 105a和欧姆接触层 105b。 在某些实施例中， 半导体材 料层 105a可以采用铟镓辞氧化物或其他过渡金属氧化层形成。此外，半导体 材料层 105a还可以采用非晶硅材料或多晶硅材料形成。 欧姆接触层 105b可 以设置在半导体材料层 105a上方且在与源极 106、 漏极 107相对应的位置， 一般采用磷掺杂非晶硅材料形成。
源极 106和漏极 107可以与数据线 102同层设置， 均位于有源层 105所 在的层的上方， 且采用相同的材料制作， 所用的材料一般为非透明的金属材 料或其合金。 数据线 102可以与源极 106电连接。 源极 106和漏极 107可以 位于有源层 105上方的相对两侧。
像素电极 108可以位于数据线 102、 源极 106和漏极 107所在的层的上 方区域， 其覆盖区域包括薄膜晶体管的上方区域， 像素电极 108部分或全部 覆盖非透光区域。 像素电极 108—般采用铟锡氧化物、 铟辞氧化物或铝辞氧 化物等透明氧化物材料制作， 其形状可以为板状或狭缝状。
发光结构 301可以位于像素电极 108的上方区域， 且与像素电极 108绝 缘设置，发光结构 301可以为狭缝状， 用于提供背光源； 同时，发光结构 301 还可以用作阵列基板的公共电极， 用于与像素电极 108—起形成水平电场， 驱动液晶层的液晶分子发生偏转， 从而实现广角显示。
参见图 5 , 发光结构 301可以包括： 阴极 3011 , 设置在像素电极 108上 方； 发光材料层 3012, 设置在阴极 3011上方； 以及阳极 3013 , 设置在发光 材料层 3012上方的。 阳极 3013可以连接阵列基板的公共电极线。 阴极 3011 和阳极 3013用于向发光结构提供给驱动电压， 使得发光结构产生白光。
此外， 发光结构 301还可以包括： 电子传输层 3014, 位于阴极 3011与 发光材料层 3012之间，用于将电子导入到发光材料层 3012;空穴传输层 3015, 位于发光材料层 3012与阳极 3013之间，用于将空穴导入到发光材料层 3012; 第一阻挡层 3016, 位于电子传输层 3014与发光材料层 3012之间， 用于阻挡 空穴传输到阴极 3011 ; 以及第二阻挡层 3017, 位于空穴传输层 3015与发光 材料层 3012之间， 用于阻挡电子传输到阳极 3013。
发光材料层 3012可以包括： 橙色磷光层 3012a, 位于第一阻挡层 3016 上； 蓝色荧光层 3012b, 位于橙色磷光层 3012a上； 以及绿色磷光层 3012c, 位于蓝色荧光层 3012b上。 当发光结构工作时， 从阴极 3011注入电子， 从阳极 3013注入空穴， 电 子通过电子传输层 3014导入到发光材料层 3012 中， 空穴通过空穴传输层 3015导入到发光材料层 3012中， 电子和空穴在发光材料层 3012中复合， 形 成单重态激子和三重态激子， 在单重态激子和三重态激子由激发态向基态跃 迁的过程中，其能量以光子和热能的方式释放，其中部分光子被用作背光源， 为实现图像的显示提供光线。 具体地， 在蓝色荧光层 3012b中， 单重态的激 子由激发态向基态跃迁时， 可以发出蓝色的荧光； 在橙色磷光层 3012a和绿 色磷光层 3012c中， 三重态的激子由基态向激发态跃迁时， 可以发出绿色磷 光和橙色磷光， 蓝色荧光与绿色磷光、 橙色磷光复合， 从而形成白光。
进一步地， 阵列基板还可以包括钝化层 302, 钝化层 302设置在数据线
102、源极 106和漏极 107所在的层的上方，覆盖薄膜晶体管 10的上方区域， 使得可以在薄膜晶体管的上方形成像素电极， 同时用于保护薄膜晶体管 10 不被腐蚀。
此外， 钝化层 302中还可以设置有过孔 303 , 过孔 303可以设置在与漏 极 107相对应的位置， 使得像素电极 108和漏极 107可以通过过孔 303电连 接。
进一步地， 阵列基板还可以包括第二钝化层 304, 第二钝化层 304设置 在像素电极 108所在的层的上方，用于将像素电极 108与发光结构 301隔离。 第二钝化层 304可以采用树脂材料形成， 相对于硅氧化物和硅氮化物材料， 树脂材料具有较低的介电常数， 可以有效减小像素电极和发光结构之间的耦 合电容， 进一步降低该阵列基板的功耗； 并且与硅氧化物和硅氮化物材料相 比， 使用树脂材料更易于形成第二钝化层。
上述阵列基板可以具有如下的驱动过程：
在栅极 103上施加正偏压， 使得薄膜晶体管导通， 数据信号从薄膜晶体 管的源极 106传输到薄膜晶体管的漏极 107, 并通过过孔 303传输到像素电 极 108;
对发光结构 301施加电压， 使其产生白光；
发光结构 301通电后， 相当于该阵列基板的公共电极， 与位于其下方的 像素电极 108耦合，产生用于驱动液晶分子偏转的电场，从而实现广角显示。
图 6示出根据本发明第二实施的阵列基板。 参见图 6, 第二实施例的阵 列基板的结构可以与第一实施例的阵列基板的结构基本上相同， 不同之处在 于：在第二实施例提供的阵列基板中，发光结构 301可以设置在像素电极 108 的下方， 发光结构 301可以为板状或狭缝状， 像素电极 108可以为狭缝状。 具体地， 第二钝化层 304位于薄膜晶体管所在的层上， 发光结构 301设置在 第二钝化层 304上， 钝化层 302设置在发光结构 301上， 像素电极 108设置 在钝化层 302上， 像素电极 108通过过孔 303'与漏极 107电连接， 过孔 303' 贯穿钝化层 302和第二钝化层 304。
图 7示出根据本发明第三实施例的阵列基板。 参见图 7, 根据第三实施 例的阵列基板和图 4所示的阵列基板的结构基本上相同， 区别之处在于： 图 4所示的阵列基板为底栅结构的阵列基板， 而图 7所示的阵列基板为顶栅结 构的阵列基板。 具体地， 有源层 105位于衬底基板 100上； 源极 106、 漏极 107和数据线同层设置， 在有源层 105上； 栅绝缘层 104位于源极 106和漏 极 107所在的层上； 栅极 103位于栅绝缘层 104上； 在图 4所示的阵列基板 中过孔 303只贯穿钝化层 302,而在图 7所示的阵列基板中用于使得漏极 107 和像素电极 108电连接的过孔 303'贯穿钝化层 302和栅绝缘层 104。
需指出的是， 对于本发明第三实施例提供的阵列基板， 发光结构 301也 可以设置在像素电极 108的下方， 此处不再赘述。
本发明的第四实施例提供了一种阵列基板， 该阵列基板和图 4所示的阵 列基板的结构基本相同， 区别在于： 根据第四实施例的阵列基板中的发光结 构具有与图 4所示的阵列基板中的发光结构不同的结构。 具体地， 参见图 8, 在第四实施例的阵列基板的发光结构中， 空穴传输层 3015设置在阳极 3013 上，第二阻挡层 3017设置在空穴传输层 3015上，发光材料层 3012设置在第 二阻挡层 3017上，第一阻挡层 3016设置在发光材料层 3012上， 电子传输层 3014设置在第一阻挡层 3016上， 阴极 3011设置在电子传输层 3014上。 阳 极 3013—般采用氧化铟锡 /银 /氧化铟锡多膜层结构， 阴极 3011—般采用镁 银合金、 锂铝合金等透明的低功函数合金材料。
同理， 对于本发明第四实施例提供的阵列基板， 发光结构 301也可以设 置在像素电极 108的下方， 此处不再赘述。
本发明的第五实施例提供了一种阵列基板， 该阵列基板和图 7所示的阵 列基板的结构基本上相同， 区别在于： 第五实施例的阵列基板中的发光结构 具有与图 7所示的阵列基板中的发光结构不同的结构， 具体结构可以参见图 8。 同理， 在本发明第五实施例提供的阵列基板中，发光结构 301也可以设置 在像素电极 108的下方， 此处不再赘述。
在上述第一至第五实施例提供的阵列基板中， 像素电极的覆盖区域包括 薄膜晶体管的上方区域， 发光结构用于提供背光源。 由于像素电极的覆盖区 域包括薄膜晶体管的上方区域， 因此像素电极的覆盖区域较现有技术中像素 电极的覆盖区域增大， 同时， 由于发光结构充当背光源， 因此， 使得位于薄 膜晶体管上方的像素电极所对应的区域内有光线通过， 有利于提高像素的开 口率； 此外， 发光结构还可以用作阵列基板的公共电极， 与像素电极一起产 生用于驱动液晶分子的水平电场， 从而实现了广角显示。
本发明的实施例还提供一种阵列基板的制作方法， 该方法可以包括： 形 成数据线、 扫描线、 像素电极的步骤和形成薄膜晶体管的步骤， 其中像素电 极形成在像素单元的透光区域， 薄膜晶体管、 扫描线和数据线形成在像素区 域的非透光区域， 其中像素电极位于薄膜晶体管所在的层的上方， 其覆盖区 域包括薄膜晶体管的上方区域， 像素电极部分或全部覆盖非透光区域； 形成 发光结构的步骤， 发光结构位于像素电极的上方， 与像素电极绝缘设置， 发 光结构的覆盖区域与像素电极的覆盖区域相对应， 用于提供背光源。
下面以本发明第一实施例提供的阵列基板为例， 详细介绍实际制作工艺 中， 阵列基板的制作方法可以具体包括：
第一步， 参见图 9, 在衬底基板 100上沉积一层金属薄膜， 然后通过构 图工艺处理， 形成包括扫描线和栅极 103的图形， 用于形成金属薄膜的材料 可以为 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等非透明金属及其合金。
第二步， 参见图 10, 在包括扫描线和栅极 103的图形的上方沉积硅氮化 物或硅氧化物层， 形成栅绝缘层 104。
该步骤可以具体包括： 在包括扫描线和栅极 103的图形的上方沉积硅氮 化物或硅氧化物层， 其厚度为 6000~8000埃， 约为现有技术中的栅绝缘层厚 度的 2倍； 在硅氮化物或硅氧化物层上涂覆光刻胶； 然后经过曝光， 显影等 工艺， 去除沟道区域对应的部分硅氮化物或硅氧化物， 使得导电沟道区域对 应的栅绝缘层的厚度与现有技术中的导电沟道对应的栅绝缘层的厚度相同， 从而保证了较高的开态电流。
第三步， 参见图 11 , 在栅绝缘层 104上依次沉积半导体材料和磷掺杂非 晶硅材料， 然后通过构图工艺形成包括有源层 105的图形。 半导体材料可以 为多晶硅半导体材料、 非晶硅半导体材料或者金属氧化物半导体材料。 第四步， 参见图 12, 在包括有源层 105的图形上形成源漏金属薄膜， 然 后通过构图工艺， 形成包括数据线、 源极 106和漏极 107的图形。
第五步， 参见图 13 , 在包括数据线、 源极 106和漏极 107的图形上沉积 硅氮化物或硅氧化物层以形成钝化层 302, 使得可以随后在薄膜晶体管的上 方形成像素电极并用于保护薄膜晶体管不被腐蚀； 以及利用构图工艺在该钝 化层 302中形成过孔 303 , 过孔 303贯穿钝化层 302并与漏极 107的位置相 对应。
第六步， 参见图 14, 在钝化层 302的上方使用磁控溅射法沉积一层氧化 铟锡透明导电薄膜， 并通过构图工艺形成包括像素电极 108的图形。 像素电 极 108的覆盖区域可以包括薄膜晶体管的上方区域， 且像素电极部分或全部 覆盖像素单元的非透光区域。 并且， 像素电极 108可以通过过孔 303与漏极 107电连接。
第七步， 参见图 15 , 在包括像素电极 108的图形的上方旋涂树脂， 形成 第二钝化层 304, 用于将像素电极 108与发光结构 301进行隔离。 第二钝化 层还可以采用硅氮化物或硅氧化物材料制作， 但是树脂材料具有较低的相对 介电系数， 可以有效减小像素电极和发光结构之间的耦合电容， 进一步降低 该阵列基板的功耗， 且由于树脂材料具有流动性， 相对于硅氮化物或硅氧化 物材料更容易形成第二钝化层。
第八步， 参见图 4, 在第二钝化层 304上依次沉积高反射率的导电材料、 发光材料和透明导电材料，然后通过构图工艺形成包括发光结构 301的图形。 发光结构 301可以用于提供背光源， 同时还可以用作阵列基板的公共电极， 与像素电极一起产生电场以驱动液晶分子发生偏转， 实现图像显示。具体地， 形成发光结构 301的步骤可以包括： 在钝化层上沉积具有高反射率的导电材 料， 并通过构图工艺形成包括阴极的图形； 在包括阴极的图形上沉积发光材 料， 并通过构图工艺形成包括发光材料层的图形； 在包括发光材料层的图形 上沉积透明导电材料， 并通过构图工艺形成包括阳极的图形。
经过上述步骤， 即形成本发明第一实施例提供的具有如图 4所示的结构 的阵列基板。
对于本发明第二实施提供的其中发光结构设置在像素电极下方的阵列基 板， 其制作方法可以与制作本发明第一实施例提供的阵列基板的方法基本相 同， 不同之处在于， 参见图 16, 制作本发明第二实施例提供的阵列基板的方 法可以包括：
在包括数据线、 源极 106和漏极 107的图形上旋涂树脂以形成第二钝化 层 304, 用于将薄膜晶体管与发光结构 301进行隔离；
在第二钝化层 304上依次沉积高反射率的导电材料、 发光材料和透明导 电材料， 然后通过构图工艺形成包括发光结构 301的图形；
在包括发光结构 301的图形上沉积硅氮化物或硅氧化物层以形成钝化层
302;
在钝化层 302上使用磁控溅射法沉积一层氧化铟锡透明导电薄膜， 并通 过构图工艺形成包括像素电极 108的图形， 像素电极 108的覆盖区域可以包 括薄膜晶体的上方区域； 并且， 像素电极 108通过过孔 303'与漏极 107电连 接， 过孔 303 '贯穿钝化层 302和第二钝化层 304。
经过上述步骤， 即形成本发明第二实施例提供的具有如图 6所示的结构 的阵列基板。
需指出的是， 对于本发明中的其中发光结构设置在像素电极下方的阵列 基板， 均是在形成薄膜晶体管之后依次形成第二钝化层、 发光结构、 钝化层 和像素电极， 具体可以参考制作根据第二实施例的阵列基板的方法。
对于根据本发明第三实施例的阵列基板， 其制作方法与制作根据本发明 第一实施例的阵列基板的方法类似， 不同之处在于， 参见图 17, 在制作根据 第三实施例的阵列基板时， 形成薄膜晶体管的步骤可以包括：
在衬底基板 100上沉积非晶硅半导体材料层 105a和磷掺杂非晶硅材料层
105b, 然后通过构图工艺形成包括有源层 105的图形；
在包括有源层 105的图形上形成源漏金属薄膜， 然后通过构图工艺形成 包括数据线、 源极 106和漏极 107的图形；
在包括数据线、 源极 106和漏极 107的图形上沉积硅氮化物或硅氧化物 材料以形成栅绝缘层 104；
在栅绝缘层 104上沉积一层金属薄膜， 然后通过构图工艺处理形成包括 扫描线和栅极 103的图形， 用于形成金属薄膜的材料可以为 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等非透明金属及其合金。
对于根据本发明第四实施例的阵列基板， 其制作方法与制作本发明第一 实施例的阵列基板的方法类似， 不同之处在于， 在制作第四实施例的阵列基 板时， 形成发光结构的步骤可以包括： 在钝化层上沉积具有高反射率的导电 材料， 并通过构图工艺形成包括阳极的图形； 在包括阳极的图形上沉积发光 材料， 并通过构图工艺形成包括发光材料层的图形； 在包括发光材料层的图 形上沉积透明导电材料， 并通过构图工艺形成包括阴极的图形。
对于根据本发明第五实施例的阵列基板， 其制作方法与制作本发明第三 实施例的阵列基板的方法类似， 不同之处在于， 在制作第五实施例的阵列基 板时， 形成发光结构的步骤可以与在制作第四实施例的阵列基板时形成发光 结构的步骤相同。
需指出的是， 在本发明的实施例中， 构图工艺可以只包括光刻工艺， 或 者包括光刻工艺以及刻蚀步骤， 同时还可以包括打印、 喷墨等其他用于形成 预定图形的工艺； 光刻工艺是指包括成膜、 曝光、 显影等工艺过程的利用光 刻胶、 掩模板、 曝光机等形成图形的工艺。 可以根据本发明的实施例中所形 成的结构选择相应的构图工艺。
本发明的实施例还提供一种显示装置，该显示装置包括上述的阵列基板。 综上， 在本发明的实施例提供的阵列基板中， 由于像素电极的覆盖区域 包括薄膜晶体管的上方区域， 因此像素电极的覆盖区域较现有技术中像素电 极的覆盖区域增大， 同时， 由于发光结构充当背光源， 因此使得位于薄膜晶 体管上方的像素电极所对应的区域内有光线通过， 可以进行图像显示， 有利 于提高像素的开口率； 同时， 由于发光结构中设置有两个电极， 因此该发光 结构的驱动不依赖于薄膜晶体管的特性， 因此解决了非晶硅材料不能用于制 作高分辨率和高开口率显示器的问题。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权利要求书
1、一种阵列基板， 包括多个呈矩阵排列的像素单元， 所述像素单元包括 透光区域和非透光区域， 所述透光区域包括像素电极， 所述非透光区域包括 薄膜晶体管、 扫描线和数据线，
其中所述像素电极位于所述薄膜晶体管所在的层的上方， 并且所述像素 电极部分或全部覆盖所述非透光区域；
其中所述像素单元还包括设置在所述薄膜晶体管所在的层上方且与所述 像素电极绝缘设置的发光结构， 所述发光结构的覆盖区域与所述像素电极的 覆盖区域相对应， 所述发光结构用于提供背光源。
2、如权利要求 1所述的阵列基板，其中所述发光结构与公共电极线连接 以用作所述阵列基板的公共电极。
3、如权利要求 2所述的阵列基板， 其中所述发光结构包括阴极、设置在 所述阴极上的发光材料层、 以及设置在所述发光材料层上的阳极， 其中所述 阳极连接到所述公共电极线；
或者所述发光结构包括阳极、 设置在所述阳极上的发光材料层、 以及设 置在所述发光材料层上的阴极， 其中所述阳极连接到所述公共电极线。
4、如权利要求 1-3中任一项所述的阵列基板， 其中所述发光结构位于所 述像素电极的上方，所述发光结构为狭缝状，所述像素电极为板状或狭缝状； 或者， 所述发光结构位于所述像素电极的下方， 所述发光结构为狭缝状 或板状， 所述像素电极为狭缝状。
5、如权利要求 1-4中任一项所述的阵列基板， 其中所述薄膜晶体管的栅 绝缘层具有 6000~8000埃的厚度。
6、如权利要求 1-5中任一项所述的阵列基板，还包括设置在所述薄膜晶 体管所在的层与所述像素电极之间的钝化层。
7、如权利要求 1至 6中任一项所述的阵列基板，还包括设置在所述像素 电极与所述发光结构之间的第二钝化层。
8、如权利要求 6所述的阵列基板，其中过孔至少形成在所述钝化层中以 将所述像素电极连接到所述薄膜晶体管的漏电极。
9、如权利要求 1-8中任一项所述的阵列基板， 其中所述薄膜晶体管具有 顶栅结构或底栅结构。
10、 一种显示装置， 包括权利要求 1-9中任一项所述的阵列基板。
11、 一种阵列基板的制作方法， 包括：
形成数据线、 扫描线、 像素电极的步骤和形成薄膜晶体管的步骤， 其中 所述像素电极形成在像素单元的透光区域， 所述薄膜晶体管、 扫描线和数据 线形成在所述像素单元的非透光区域， 其中所述像素电极位于所述薄膜晶体 管所在的层的上方， 且所述像素电极部分或全部覆盖所述非透光区域； 以及 形成发光结构的步骤， 所述发光结构位于所述薄膜晶体管所在的层的上 方， 与所述像素电极绝缘设置， 所述发光结构的覆盖区域与所述像素电极的 覆盖区域相对应。
12、 如权利要求 11所述的方法， 其中形成所述发光结构的步骤包括： 形成包括阴极的图形、在包括阴极的图形上形成包括发光材料层的图形、 以及在包括发光材料层的图形上形成包括阳极的图形；
或者， 形成包括阳极的图形、 在包括阳极的图形上形成包括发光材料层 的图形、 以及在包括发光材料层的图形上形成包括阴极的图形。
13、 如权利要求 11或 12所述的方法， 其中所述发光结构位于所述像素 电极的上方， 所述发光结构为狭缝状， 所述像素电极为板状或狭缝状；
或者， 所述发光结构位于所述像素电极的下方， 所述发光结构为狭缝状 或板状， 所述像素电极为狭缝状。
14、 如权利要求 11-13中任一项所述的方法， 还包括：
在所述薄膜晶体管所在的层与所述像素电极之间形成钝化层。
15、 如权利要求 11-14中任一项所述的方法， 还包括：
在所述像素电极与所述发光结构之间形成第二钝化层。
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