WO2015042814A1

WO2015042814A1 - Wideband injection locked frequency multipliers, oscillators and dividers using higher order lc resonant tank

Info

Publication number: WO2015042814A1
Application number: PCT/CN2013/084237
Authority: WO
Inventors: Li ALVIN; Wu Liang; Luong HOWARD CAM; Luo XUN
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2013-09-25
Filing date: 2013-09-25
Publication date: 2015-04-02

Abstract

The present invention provides an injection locked frequency multiplier. The injection locked frequency multiplier comprises: an input stage, configured to receive an input signal having a first frequency, and generate a harmonic current; a resonant tank, configured to receive the generated harmonic current and flatten a phase response over a frequency band; and an output stage, configured to provide an output signal having a second frequency. The second frequency is a multiple of the first frequency. The resonant tank may be a high order resonant tank.

Description

Wideband injection locked frequency multipliers, oscillators and dividers using higher order LC resonant tank

FIELD OF THE INVENTION

The present invention relates to a wideband injection locked frequency multipliers, oscillators and dividers.

BACKGROUND OF THE INVENTION

In prior art, Injection locked frequency multipliers, which include frequency doublers and triplers, are the key blocks that enable the superior phase noise performance of sub-harmonically injection-locked Phase locked loop (PLL) architectures at mm-wave frequencies compared to direct synthesis architectures. Fundamental voltage controlled oscillator (VCO) architectures, as shown in Fig. 1, at millimetre wave (mm-wave) frequencies are inferior because the VCO's phase noise deviates from the theoretical phase noise vs. frequency relationship of

dB vertical separation when operating at angular frequencies oi and co₂, given identical power consumption and resonator quality factor (Q). This is attributed to the lower tank quality factor, layout parasitics and power consumption constraints at such high frequencies in integrated CMOS technologies.

For injection-locked PLL architectures, as shown in Fig. 2, this is not a problem because the output phase noise is determined by the Injection locked frequency tripler (ILFT)'s injection signal generated by the low frequency PLL through injection locking rather than the ILFT's free running phase noise.

Due to the typically narrow locking range of conventional frequency multipliers, Process-voltage-temperature (PVT) variations and modeling inaccuracies at mm-wave frequencies, frequency calibration to align the multiplier's operating frequency to the injected signal's harmonic is necessary to ensure locking, and thus phase noise tracking, is achieved. This frequency alignment is usually implemented using an additional PLL for each multiplier as shown in Fig 2. This turns out to be very costly in terms of extra chip area, increased routing complexity, and additional loading and parasitic capacitance especially when implemented at high frequencies.

To address this problem, the invented circuit technique enables ultra-wide locking ranges in injection locked oscillators (ILO), injection locked frequency multipliers (ILFM) and injection locked frequency dividers (ILFD). As illustrated in Fig. 3, the use of wideband frequency multipliers eliminates the need for the costly frequency alignment circuitry in mm-wave synthesizers. Additionally, this technique enables the use of injection locked PLL architecture for wideband mm- wave applications and standards.

At high frequencies, the conventional LC-based frequency multiplier is widely used for it's low power consumption despite suffering from very narrow locking range. Unfortunately, a wide locking range is often necessary to ensure both robust operations under PVT frequency variations and to cover multiband or wideband standards. Therefore, recent works have focused on widening the locking range. The schematic of a conventional 2^nd order LC-type injection locked frequency multiplier and it's corresponding behavioral model is shown in Fig. 4.

The 2^nd order LC-based resonant tank is centered at ω₀. For a frequency tripler, cog « 3co_in , while for a frequency doubler, ω₀ « 2ω_ίη , and for an injection locked oscillator, ω₀ » co_in . The cross coupled pair M₃ and M generate a negative feedback loop to ensure start-up and self-oscillation of the frequency multiplier at coo when there is no input signal. Given sinusoidal input signals (1), injection currents with fundamental and harmonic components (2) are generated from the nonlinearities of Mi and M₂ and injected into the resonant tank.

cos(co + e) 0) n

m = k₀ + k, - v + k₂ ^■ v_m ² _j + k₃ + -v³ +^■■■■ +k_n · v; inj (2)

If the harmonic component of the injected current is large enough and close enough to co₀, the multiplier output signal will lock to the input signal. When locked, the output phase noise will track the input signal up to an offset equal to the locking range, co_L.

Document D4 (W. Liang et. al., entitled "A 4-path 42.8-to-49.5GHz LO generation with automatic phase tuning for 60GHz phased-array receivers," ISSCC Dig. Tech. Papers, pp.270-272, Feb. 2012) discloses an injection locked frequency multiplier, as shown in Fig. 5(a)-5(c) and Fig. 6(b). The locking range of the frequency multiplier can be determined by the phasor diagram in conjunction with the magnitude and phase lots of the resonant tank shown in Fig. 5.

The locking range is approximated mathematically by Adler's equation (3) for 2^nd order LC based frequency oscillators, of which both frequency multipliers and frequency dividers are a subset. From the equation (3), it is therefore desirable to maximize the —— ratio for a wide locking range. In the conventional frequency

^ osc tripler, this —— ratio depends on the injection devices' non-linearity to generate the

^ osc third harmonic current, 3eo_jnJ . Although the equation (3) seems to also indicate minimizing I_osc would lead to a wider locking range, this is slightly misleading as it would reduce the output amplitude until the lower limit is reached. This lower limit is determined by the tank Q necessary to ensure start up conditions are satisfied.

A low frequency method to achieve wideband is to use SCA and varactors to tune coo, however, this method is not effective at mm-wave frequencies for two reasons. Firstly, the small amount of resonant capacitance in the LC tank is mostly allocated to active devices and unavoidable parasitics leaving very little to SCA and varactors which constrains the tuning/locking range. Secondly, as the output frequency increases, the quality factor of the resonant tank decreasesm which leads to small output amplitudes. To minimize this, it is necessary to maximize the inductance value for a given operating frequency at the expense of capacitance leading to smaller frequency tuning elements.

In D4, the non-linearity based input stage is replaced with a more efficient mixer based input stage shown in Fig. 6b to further enhance the — ratio and locking

^ osc

range. The inductor placed between ground and the source of the two input devices, node CM, resonates with the parasitic capacitance to present a high impedance at 2ω. The common mode second harmonic voltage then mixes with the input signals through Ml and M2 to generate the enhanced third harmonic injection current.

Document D2 (Wei L. Chan, entitled "A 56-65 GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2739-2746, Dec. 2008) discloses an injection locked frequency multiplier core, as shown in Fig. 6(a). The locking range is widened by focusing on improving the —— ratio in conjunction with degenerating the Q of the LC tank

^ osc

using a resistors Ri and R₂ for a flatter phase response around the 0° crossing frequency. The i<w, current component injected to the resonant tank, Ij_nj, is enhanced by biasing the injection devices, V , at the boundary of sub-threshold region for class-B operation which increases it's nonlinearity.

Document D5 (G. Mangraviti, et al., entitled "A 52-66GHz Subharmonically Injection locked quadrature oscillator with 10GHz locking range in 40nm LP CMOS," IEEE RFIC Symp., pp.309-312, June 2012) discloses an alternative approach of an injection locked frequency multiplier, as shown in Fig. 7, which proposes to obtain a flat phase response at ω₀ over a wide frequency range by using a 4^th order transformer based resonant tank. By achieving a flat 0° phase response, a wide locking range can be achieved without the need for a large injection current I,_nj.

While D5 claims a locking range of 10GHz from 52-66GHz due to a flat phase response at 0°, their presented phase noise plot indicated otherwise. When frequency locked, the output phase noise tracks the input phase noise theoretically by

20 log 10 up to an offset of COL after which the phase noise curve returns to the

ILFM's self-oscillation phase noise according to the study on injection locking of prior art. From Fig. 9, the presented frequency tripler only tracks the input by 9.5dB up to approximately 50 kHz offset. This indicates that the claimed wide locking range is not achieved through their claimed technique.

Document D6 (Reynolds et al., entitled "Frequency multipliers using multi-phase oscillation," United States Patent no. US 7,825,741 B2, Nov. 2, 2012) discloses another existing frequency tripler, which employs multiple phases to control separate devices for injecting fundamental currents into the 2^nd order LC resonant tank as shown in Fig. 8. This push-push-push method does not use a negative gm cell to compensate for the tank loss of the resonant LC tank, and is therefore not a type of injection locked oscillator but rather an amplifier. However, a large output amplitude is still possible as it benefits from using the typically large ki conversion gain of the input devices in equation (2). This type of frequency multiplier depends on the resistive degeneration of the LC tank to achieve a wide output frequency range which trades off with the achievable output amplitude. Compared to the invented frequency multipliers, this method does not achieve a wider output frequency range.

SUMMARY OF THE INVENTION

In first aspect, the present invention provides an injection locked frequency multiplier, comprising: an input stage, configured to receive an input signal having a first frequency, and generate a harmonic current; a resonant tank, configured to receive the generated harmonic current and flatten a phase response over a frequency band; and an output stage, configured to provide an output signal having a second frequency; wherein the second frequency is a multiple of the first frequency. In second aspect, the present invention provides an injection- locked frequency multiplier, comprising: an input stage; an output stage; and a 4^th or 6^th order LC resonant tank, configured to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle between the total vector sum of currents injected into the resonant tank and an output signal over a wide frequency band to achieve a wide locking range.

In third aspect, the present invention provides an injection-locked frequency divider, comprising: an input stage; an output stage; and a 4^th or 6^th order LC resonant tank, configured to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle between the total vector sum of currents injected into the resonant tank and an output signal over a wide frequency band to achieve a wide locking range.

In fourth aspect, the present invention provides an injection-locked oscillator, comprising: an input stage; an output stage; and a 4^th order LC resonant tank, configured to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle between the total vector sum of currents being injected into the resonant tank and an output signal over a wide frequency band to achieve a wide locking range.

In fifth aspect, the present invention provides a sub-harmonically injected PLL frequency synthesizer system, comprising:

a phase/frequency detector (PFD);

a charge pump (CP);

a low-pass filter (LPF);

a voltage controlled oscillator (VCO);

a divider chain; and

a wideband frequency multiplier chain; wherein the wideband frequency multiplier chain comprises the injection locked frequency multiplier of the first aspect.

The sub-harmonically injected PLL frequency synthesizer system may further comprises at least one of the injection-locked frequency multiplier of the second aspect, the injection-locked frequency divider of the third aspect, and the injection-locked oscillator of the fourth aspect.

BREIF DESCRIPTION OF THE DRAWINGS

Fig. 1 shows a fundamental mm-wave PLL in prior art;

Fig. 2 shows a sub-harmonically injection-locked PLL using narrowband frequency multipliers in prior art;

Fig. 3 shows a sub-harmonically injection-locked PLL using wideband frequency multipliers in prior art;

Fig. 4 shows a conventional injection locked oscillator;

Fig. 5(a) shows a conventional ILFM model; Fig. 5(b) shows a phasor diagram of the ILFM model; and Fig. 5(c) shows 2^nd order LC tank magnitude and phase response of the ILFM model; Fig. 6(a) shows an injection locked frequency multiplier core in prior art; and Fig. 6(b) shows another injection locked frequency multiplier core in prior art;

Fig. 7 shows an injection locked frequency multiplier in prior art;

Fig. 8 shows an injection locked frequency tripler in prior art;

Fig. 9 shows a phase noise of ILFM shown in Fig. 7 under injection supposedly showing wide band locking;

Fig. 10 shows a schematic of an injection locked frequency doubler with 6^th order LC tank of a first embodiment of the present invention;

Fig. 11 shows a schematic of an injection locked frequency tripler with 4^th order LC tank of a second embodiment of the present invention;

Fig. 12 shows a schematic of an injection locked frequency tripler with 6^th order LC tank of a third embodiment of the present invention;

Fig. 13(a) shows an ILFM model with higher order LC tank and corresponding phasor diagram; and Fig. 13(b) shows a magnitude and phase response of 2nd, 4th and 6th order LC resonant tanks;

Fig. 14(a) shows three 2^nd order LC tanks; and Fig. 14(b) shows six 3^rd order LC tanks;

Fig. 15(a) shows efficient 3rd harmonic generation based on push-push mixing; Fig. 15(b) shows a conventional input stage; and Fig. 15(c) shows a graph of the simulated 3coj_nj differential current;

Fig. 16 shows a sub-harmonically injected PLL frequency synthesizer utilizing wideband frequency multiplier chain;

Fig. 17 shows a fabricated sub-harmonically injection locked PLL with wideband injection locked frequency synthesizers;

Fig. 18 shows phase noise plots of ILFM chain at different frequencies;

Fig. 19 shows a phase noise of closed loop VCO driving ILFM chain;

Fig. 20 (a) shows 4^th order transformer based LC tank model and Fig. 20 (b) shows 6^th order transformer based LC tank model;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

According to embodiments of the present invention, wideband injection locked frequency multipliers with higher-order LC tanks and efficient injection stages are proposed to achieve ultra- wide locking range. Figs. 10, 11, and 12 show two I-Q frequency triplers with 4^th and 6^th order LC tanks and a differential frequency doubler, respectively. Similar to the conventional injection locked oscillators previously discussed, M₅ and M shown in Fig. 10 and 11 form a cross coupled pair to ensure start-up of the ILFM's self-oscillation. For quadrature generation, M₇ and M₈ shown in Fig. 12 provide I-Q coupling in parallel with the cross coupled pair. Each circuit shown in Figs 10-12 also has an input stage to generate harmonic currents injected to the resonant tank. Each of the circuits shown in Figs 11-12 includes two symmetrical parts, i.e. a left part and a right part. Vinj represents an input voltage and Vo represents an output voltage. The frequency doubler shown in Fig. 10 utilizes the same higher order LC tank characteristics described for the frequency triplers to achieve a wide locking range. However, the input stage is based on push-push pairs Mi, M₂ and M₃, M₄ to generate the large injection current at 2co_inj . Since there are no mixing devices, this input stage does not recover quadrature injection currents from the quadrature input resulting in a loss of output phases. The frequency doubler is thus only capable of quadrature-in differential-out operations. As shown in Fig. 10, the left-upper part and the right-upper part include three independent resonant circuits. Each resonant circuit corresponds to a resonant point. The wideband effect can be achieved by adjusting coupling coefficients between inductors.

The basic working principles of the enhanced locking range for the three embodiments may be explained though a general model shown in Fig. 13a. The corresponding magnitude and phase response of 2^nd, 4^th and 6^th order LC resonant tanks are shown in Fig. 13b. The phase plot in particular shows the phase difference, in degrees, between injecting a current I_totai and the output voltage at different frequencies while the phasor diagram illustrates the maximum phase I_totai can have with respect to V_out given the magnitudes of I_osc and Ij_nj .

For locking to be possible at an output frequency of N^■ ω_ί■ within the desired locking range, the gain and phase conditions for steady state oscillation must first be met. From the gain condition, the resonant tank's amplitude response (Fig. 13b) at

N - (o_jnj must be large enough to ensure the loop gain is greater than 1. This is controlled by the cross coupled pair and IQ coupling transistor sizing along with lose- To satisfy the phase condition, the phase φ between I_totai with V_out must be large enough to compensate for the phase shift Θ of the resonant tank at N■ (o_mj such that the total phase around the loop is 2π. The maximum phase shift (p_max that Itotai can compensate for can be found by representing I_totai in a phasor diagram (Fig. 13 a) as the vector sum of the self-oscillation current I_osc and the injected current. The phase clearly shows that by increasing Ij_nj or decreasing I_osc would lead to a larger <p_max.

By looking at the phase responses of a 2^nd, 4^th, and 6^th-order resonant tanks, as shown in Fig. 13b, the frequency range where |9|<|(p_max| can be identified as the range where the phase condition can be satisfied. In order to achieve a wide locking range, it is therefore desirable to both maximize the achievable phase angle between I_totai with Vout by increasing the Ii„j Iosc ratio and to minimize the phase shift across the resonant tank over the desired frequency range by using higher-order LC tanks. The wider frequency band due to the 4^th and 6^th order tank's rippled response near 0° is significantly wider than that offered by the 2^nd order LC tank. Furthermore, it is not necessary to have a flat 0° phase response as long as the ripple stays within |(p_max|.

In the case where multiple frequencies satisfy the gain and phase conditions, the steady-state output frequency tends to favor the frequency with a larger loop gain. To avoid a strong self-oscillation at an undesirable frequency and to ensure that the ILFM tracks the injection frequency when higher-order resonators are used, it is best to design the resonant tank such that the amplitude variation across the locking range is minimized and to increase the injection current so that it is large enough to compensate for the loop gain difference at fj_nj and the other possible resonant frequencies.

Although the embodiments shown in Figs. 10, 11 and 12 show the application of transformers to implement the higher order LC tank, other configurations may also enhance the locking range as long as the discussed magnitude and phase characteristics are satisfied. Figure 14 illustrates some, but not all, of the other 2^nd and 3^rd order resonant tank configurations.

To maximize |(p_max| and thus locking range, for a fixed power consumption, it is important to maximize the harmonic generation efficiency of the injection stage. Thus, a highly efficient input generation stage based on push-push mixing, shown in Fig.

15a, is used in the frequency triplers Fig. 11 and 12. A large 2co_mj voltage is created at the common node CM using a push-push pair biased at boarder of sub-threshold region and driven by the in-phase input signal at a>_mj . The upper differential pair mixes the 2co_inj tone with the quadrature input signal at finj to generate a differential injection current at 3co_mj which is injected into the resonant tank. This injection stage is suitable for quadrature-in-quadrature-out frequency triplers, as the quadrature injection currents can be generated by swapping the in-phase input signals driving the push-push pair with the quadrature input signals driving the mixing pair as shown in

Fig. 11. Compared to the conventional case where 3a>_inj is generated from the differential pair nonlinearity (Fig. 15b) (see D2), simulations show that our enhanced input stage improves the 3 o_inj current from 0.14mA to 1.24mA for the same power with a 400mV input swing at

The simulated 3a?_inJ differential current is plotted in Fig. 15c for various phase differences between the "Iinj" and "Qinj" input signals. The plot shows that the push-push and mixing input signals should be 90° apart to maximize the conversion efficiency and is quite robust even with phase delays of ±20°. Unfortunately, the input stage also generates an injection current at

2a>_in: due to the input device's nonlinearities. If a frequency tripler's locking range is too wide, a strong injection current at 2a>_inj may cause false locking when trying to lock 3o)_mj to the top portion of the locking range. To address this, an additional

2a)_mj current steering path is used to cancel the 2oo_mj tone before it reaches the resonant tank as shown in Fig. 12. For narrower locking ranges the resonant tank naturally filters out the 2co_inj tone. A cascade device is also placed in the injection stage current path to increase the impedance seen by the resonant tank.

To demonstrate the wideband injection locked frequency multipliers of the embodiments, the three ILFMs shown in Figures 10, 11 and 12 are designed and fabricated in a 65nm CMOS process (V_th__n ⁼ 0-4 V) with 9 metal layers as shown in Fig. 17. The ILFMs are implemented as part of a frequency multiplier chain used in a sub-harmonically injected PLL frequency synthesizer system shown in Fig. 16 which is designed for multiple wireless backhaul transceivers. ILFM1 is a narrowband frequency multiplier with a large switch capacitor array to obtain a wide tuning/locking range.

The locking range and phase noise tracking properties of injection locking are demonstrated by using ILFM1 as a free running signal source to lock the rest of the frequency multiplier chain. ILFM2 may be that of Fig. 12 and measure a locking range of 66.4% from 8.9GHz to 17.75GHz while consuming 23.3 mW. ILFM3 may be that of Fig. 10 and measure a locking range of 53.1% from 20.6GHz to 35.5GHz while consuming 21.8 mW. ILFM4 may be the differential version of Fig. 11 and measure a locking range of 34.8% from 33.9GHz to 48.2GHz while consuming 16.8 mW. The phase noise plots at different output frequencies (min., mid. and max. of each band) are shown in Fig. 18. The pink curve (lowest) is the signal source ILFM1, while the blue (middle) is locked output signal from ILFM2. The yellow curves (upper) in (a), (b), and (c) are the ILFM chain's output signal from ILFM3 and while (d), (e), and (f) are from ILFM4. From about 100kHz offset until the spectrum analyzer's noise floor is reached, all plots show the phase noise tracking their respective inputs by approximately 20 log 10 It is important to note that in the region above -60dB, the measured phase noise saturates due to limitations in the spectrum analyzer.

When used as part of the sub-harmonically injected frequency synthesizer, the phase noise tracking is also observed to be close the theoretical 20 log as shown in Fig. 19. Due to the better phase noise performance of the signal source (closed loop PLL using the VCO), the phase noise saturation observed in the open loop cases are no longer present. Each plot in Fig. 19 shows four curves. The lowest curve corresponds to the output from the PLL and is used to injection lock the multiplier chain. The highest curve is the output of the frequency multiplier chain either from ILFM3 or ILFM4 depending on the output frequency. For the 38 GHz and 42GHz output frequency plots, the flattening of the curve is due to the noise floor of the measurement equipment.

As previously mentioned, the use of higher order LC tanks to flatten the phase response around 0° within ±|(p_max| over a wide frequency band to enlarge the locking range can be applied to injection locked multipliers, injection locked oscillators and injection locked dividers in general. The technique may also be used in miller type dividers, oscillators and multipliers. The method to achieve the described magnitude and phase response is not restricted to transformer implementations as there are other LC configurations shown in Fig. 13 that are capable of achieving the same results. Different harmonic generation stages, such as but not limited to those described in prior art, may also be used in conjunction with the higher order LC tanks to achieve wide locking ranges as long as they provide a sufficiently large injection current at the frequency of interest such that |(p_max| is larger than the LC tank's phase Θ response within the desired locking range. An alternate variation may include adding a tunable delay within the feedback path such that the flat or rippled phase response no longer centered around 0°.

According to an embodiment of the present invention, an injection-locked frequency multiplier using 4^th or 6^th order LC resonant tank comprises: a 4^th or 6^th order LC resonant tank, which is used in an injection frequency multiplier to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle icpmax between the total vector sum of currents being injected into the resonant tank and the output signal V_out over a wide frequency band to achieve a wide locking range.

According to another embodiment of the present invention, an injection-locked frequency divider using 4^th or 6^th order LC resonant tank comprises: a 4^th or 6^th order LC resonant tank, which is used in an injection frequency divider or miller divider to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle ±(p_max between the total vector sum of currents being injected into the resonant tank and the output signal V_out over a wide frequency band to achieve a wide locking range.

According to further embodiment of the present invention, an injection-locked oscillator using 4^th or 6^th order LC resonant tank comprises: a 4^th order LC resonant tank, which is used in an injection locked oscillator to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle ±(p_max between the total vector sum of currents being injected into the resonant tank and the output signal Vout over a wide frequency band to achieve a wide locking range.

According to further embodiment of the present invention, a quadrature-in differential-out enhanced 3^rd harmonic current generation comprises: a push-push differential pair driven by in-phase differential input signals generating a strong single-phase tone at twice the input frequency 2ω_Ιη/ . A separate "mixing" differential pair driven by quadrature-phase input signals mixes with the common-mode 2ω_ι mj tone at their source node to generate differential output currents at the drain of this differential pair.

According to further embodiment of the present invention, a quadrature-in quadrature-out enhanced 3^rd harmonic current generation comprises: two 3^rd harmonic current generation stage as described above which is used to generate quadrature output currents at three times the input signal frequency 3co_in} . . Compared to the in-phase output currents generated by the configuration as described above, the quadrature-phase output currents are generated by switching the input signals of the push-push differential pair with the mixing differential pair.

According to further embodiment of the present invention, a sub-harmonically injection-locked frequency synthesizer uses wideband frequency multipliers, dividers or injection locked oscillators as described above to avoid the need for frequency calibration loops for frequency alignment. The use of above described wideband blocks to achieve phase noise tracking of

between injection and output signals.

According to the embodiments of the present invention, the mm-wave wideband injection locked frequency multiplier is based on conventional injection locked oscillators but it employs a 4^th or 6^th order transformer based LC resonant tank to flatten the phase response to less than ± )_max ⁰ over a wide frequency range, where it can be compensated by the total injected current ai's phase shift θ°. Furthermore, a highly efficient quadrature-in-quadrature-out 3 ^rd harmonic generation stage is proposed based on push-push mixing to maximize the ratio and thus both θ°

osc

and locking range as well. The two designs together allow for a very wide frequency locking range at mm-wave frequencies where the output phase noise tracks the input close to the theoretical limit of ince the phase response need not be

perfectly flat over the frequency band. Several prototype injection locked frequency multipliers (both tripler and doubler) have been successfully demonstrated as part of a sub-harmonically injected phase locked loop in TSMC 65nm CMOS process. The embodiments of the present invention will also work in other processes and technology nodes.

According to the embodiments of the present invention, the wideband injection locking technique enables a wide locking range at mm-wave frequencies for ILOs, ILFDs and ILFMs that significantly exceeds the locking range achieved in prior art. When used in injection locked PLL architectures, costly frequency alignment circuitry is no longer required to ensure robust phase noise tracking. The proposed technique also enables wide mm-wave output frequency range to be achieved which is desirable for wideband standards but difficult to realize using fundamental mm-wave oscillators. Contrary to D5, the demonstrated output phase noise tracks the input by

20 log 10 for the entire measured offset band within the locking range <X>L as expected by the injection locked theory studied in D3 which is a key indicator of frequency locking. Furthermore, a much wider locking range than all prior art is demonstrated to cover wide band applications as well as PVT variations.

An alternative approach to obtain a wide locking range is to flatten or ripple the resonant tank's phase response around 0° over a wide frequency range using higher order LC tanks. The model of an ILFM utilizing a higher order LC tank is shown in Fig. 13 along with its corresponding phasor diagram. Similar to the 2^nd order LC tank case, for locking to be possible at an output frequency

the gain and phase conditions for steady state oscillation (7) must first be satisfied.

I ^G m ^Z tan k 1= ¹

(7) G_m ^z,_ank = 2τοΊ,η≡0,1,2 · -

It is thus necessary to find the input impedance of the higher order resonant tank, Ztank- Although a wide variety of higher order resonant tanks exist and can be used, we will focus on the 4^th and 6^th order transformer based configurations as shown in Fig. 20, as they are easily implemented without the need for significantly extra area compared to a 2^nd order LC tank. The input impedance of a 4^th order transformer based LC tank can be derived as equation (8). (8)

Ζ(ω) =

Which simplifies to equation (9) for the lossless case as R_cl,R_C2,R_LI,R_L2 -» 0 where

Similarly, the input impedance for a 6 order transformer based LC tank is given by equation (10) where the mutual inductances are given

M_l3 = k_l3^L,L₃ , and M_l2 = k_l2^L,L₂ for the coupling factors k_]2, k]₃, and k₂₃ between the three coils. Additionally, the three stand-alone peak impedances are characterized

and RLC, = r

transformer can be expressed as:

+ R, Cl [(sL_l+R_Ll (s²M² ₃-RLC₂RLC₃)+s²(M² ₂RLC_i+M² ₃RLC₂ -2sM_nM_uM_2i)] s² [M₃RL + M₂RLC₃ + M² ₃RLC₂ - 2sM_L2M_UM_2I]- RLC,^■ RLC₂ ^■ RLC,

Equation (10) can be simplified to equation (11) for the lossless case where as

1 1

R_CI>R_C2>^R _C3'^R _LI>R_L2> _L3→0 where ω, =^■ ,ω₃ =

By equating the argument of the 4 and 6 order tank impedances (8) and (10) to the maximum compensable phase shift (p_max (5), a complicated mathematical expression for the new locking range can be determined. However, a more intuitive method to visualize the locking range, and whether equation (2) has been satisfied, is to plot the magnitude and phase response of the 4^th or 6^th order LC tank along with |Zmin| for start-up conditions and (p_max for phase conditions as shown in Fig. 1.

To satisfy the gain condition, the resonant tank's amplitude response at co_out must be large enough to ensure start-up given a self-oscillation current i_osc through the -gm cell. To satisfy the phase condition, the phase φ between i_totai and i_osc must be large enough to compensate for the phase shift Θ introduced by the resonant tank at co_out such that the total phase around the loop is 2π. The maximum phase shift _max that itotai can compensate for can be found by representing itotai in a phasor diagram as the vector sum of the self-oscillation current i_osc and the injected current ij_nj at cOjnj-N co_in and occurs when i_totai is 90° with ij_nj. The frequency range over which |θ| < |4>_max| can be identified as the range where the phase condition can be satisfied. In order to achieve a wide locking range, it is therefore desirable to not only maximize the phase angle between i_totai with v_out by increasing the imj/iosc ratio, but also minimize the phase shift across the resonant tank over the desired frequency range by using higher-order LC tanks. In the case where multiple frequencies satisfy the gain and phase conditions, the steady-state output frequency tends to favor the frequency with a larger loop gain. To avoid a strong self-oscillation at an undesirable frequency and to ensure that the ILFM tracks the injection frequency when higher-order resonators are used, it is recommended to design the resonant tank such that the amplitude variation across the locking range is minimized and to increase the injection current so that it is large enough to compensate for the loop gain difference at coj_nj and the other possible resonant frequencies.

Design of 4^th and 6^th order transformer based resonant LC tank

The 4^th and 6^th order transformer based LC tanks are designed to achieve the desired magnitude and phase response described below for a wide locking range and sufficient output amplitude. Although we cannot intuitively see the effects of varying various parameter directly from the magnitude and phase equations derived from impedance expressions (8) and (10) due to their complexity, it is useful to describe the trends by plotting the equations for various parameter trade-offs to achieve the desired magnitude and phase response, simultaneously.

A. 4^th order transformer-based LC tank

Fig. 20(a) shows the schematic of a 4^th order transformer-based LC tank; and its impedance is given by equations (8) and (9) for the lossy and low loss cases respectively.

where ω_ι - , ^ and ω₂ = , ^ . As the tank Q is lowered, a phase ripple near

V L_jC_j J L₂C₂

0° is formed between in ω_\ and co₂. Therefore, the peak and zero crossing frequencies, can be set by the LC products in (O i and co₂ for a given coupling coefficient k to determine the center frequency where the phase ripple occurs. After fixing coi and co₂, the coupling coefficient can be tuned to trade off the minimum magnitude with the ripple's frequency range. A lower k will result in a narrower ripple frequency range and flatter phase response while the magnitude response's minimum impedance increases and peak-to-null variation decreases.

To increase the minimum impedance without changing the phase response, Li can be increased while Cj is decreased by the same factor while keeping ooi, QLI and Qci fixed. It can be seen that minimizing d is desirable in order to maximize the output amplitude; however, this will also increase the output impedance variation across the locking range.

To achieve a wide locking range, the phase should ripple around 0°. To achieve this, the phase response can be shifted up or down without changing its shape through several different methods.

The values of L₂ and C₂ can be freely traded off by the same factor to keep co₂ constant. If QL₂ and Qc₂ are also constant, then both the magnitude and phase response will not change. This can be useful during implementation if there are layout or technology constraints associated with achievable Q factors, inductance or capacitance values. Varying the quality factor of the secondary tank through by changing the L₂ to RL₂ ratio or C₂ to Rc₂ ratio will determine the ripple amplitude and frequency range in addition to the magnitude response's minimum impedance and peak-to-null variation.

B. 6^th order transformer-based LC tank

Fig. 20(b) shows the schematic model of a 6^th order transformer-based LC tank; and its impedance is described by equations (10) and (11) under lossy and low loss conditions respectively. A phase ripple around 0° from 20GHz to 33 GHz with a magnitude peak-to-null variation from 205Ω to 132Ω is achieved within the locking range. Similar to the low loss 4 order tank case, the three poles frequencies are primarily set by ω_ι along with the

ipling factors k[₂, k[₃, and k₂₃ according to equation (14).

Assuming low loss conditions, the three peaks and zero crossings in the magnitude and phase plot respectively are predominately defined by coi_, ω₂ and ω₃ corresponding to the middle, low and high frequency peaks respectively. As the Q associated with each peak decreases, the peak magnitudes are reduced while the slope of the 0° phase crossing also decreases. The resulting phase ripple is approximately centered around ω_\ with a frequency range lying somewhere between the lower frequency pole co₂ and the higher pole co₃.

For a given lower peak frequency co_2; fixed by the L₂*C₂ product, decreasing L₂ while increasing C₂ results in no changes in the magnitude or phase response as long as QL₂ and Qc₂ are kept constant. Decreasing the Q of the secondary tank by altering the L₂ to RL2 ratio or C₂ to Rc₂ ratio, however, will result in a reduced null-to-lower-peak magnitude difference. In addition, the ripple in the phase response flattens out resulting in a narrower locking range.

Likewise, a trade off in the L₃xC₃ product, which defines the higher peak frequency, will not change the magnitude of phase response as long as Q_L3 and Qc₃ are kept constant. Decreasing the Q of the tertiary tank will result in a similar reduction in the null-to-higher-peak magnitude difference and flattening of the phase ripple.

For Lj xCi product, decreasing Cj at the expense of an increased Li when Qci and QLI are fixed will result in the magnitude response shifting up vertically while the phase response does not change. It is therefore desirable to minimize Q to maximize the output amplitude. On the other hand, either Q, Li or RLI can be increased/decreased to shift the phase response down/up without affecting it's shape which is useful to center the phase ripple around 0°. Deciding to change C_{l s} Li or RLI however, depends on which of the peaks (upper or lower) magnitudes will be affected. Increasing C] without changing Ret will drastically lower the higher frequency peak's magnitude.

During implementation, the capacitance of both the 4^th and 6^th order LC tank should be taken into account the parasitic capacitance of the active devices such as the cross coupled pair and injection stages in addition to. parasitics contributed by routing and loading. The inductance and coupling of the 6 order LC tank is implemented using a triple coil transformer. Since k)₂ and k₁₃ are relatively stronger than k₂₃, Li is placed in the middle of L₂ and L₃. To tune the coupling factors, track interleaving is used to increase the coupling factor between two coils while a short circuit ring is used to shield coils from each other to decrease the coupling factor between coils within the ring and coils outside the ring.

Claims

1. An injection locked frequency multiplier, comprising:

an input stage, configured to receive an input signal having a first frequency, and generate a harmonic current;

a resonant tank, configured to receive the generated harmonic current and flatten a phase response over a frequency band; and

an output stage, configured to provide an output signal having a second frequency;

wherein the second frequency is a multiple of the first frequency.

2. The injection locked frequency multiplier of claim 1, wherein the resonant tank is a high order resonant tank.

3. The injection locked frequency multiplier of claim 2, wherein the high order resonant tank comprises at least 4^th or 6^th order LC resonant tank.

4. The injection locked frequency multiplier of claim 1, wherein the resonant tank is further configured to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle between the total vector sum of currents injected into the resonant tank.

5. The injection locked frequency multiplier of claim 1, wherein the input stage is a quadrature-in-differential-out enhanced 3 ^rd harmonic current generation stage, comprising:

a push-push differential pair, configured to be driven by in-phase differential input signals, and generate a strong single-phase tone at twice the first frequency; and a separate mixing differential pair, configured to be driven by quadrature-phase input signals, mix with the common-mode tone, and generate differential output currents.

6. The injection locked frequency multiplier of claim 1, wherein the input stage is a quadrature-in-quadrature-out enhanced 3^rd harmonic current generation stage, comprising:

two quadrature-in-differential-out enhanced 3 ^rd harmonic current generation stages, configured to generate quadrature output currents at three times the first frequency.

7. The injection locked frequency multiplier of claim 1, wherein the injection locked frequency multiplier is an injection locked frequency doubler or an injection locked frequency tripler.

8. An injection- locked frequency multiplier, comprising:

an input stage, configured to receive an input signal; an output stage, configured to output the frequency multiplied signal; and a 4^th or 6^th order LC resonant tank, configured to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle between the total vector sum of currents injected into the resonant tank and an output signal over a wide frequency band to achieve a wide locking range.

9. An injection-locked frequency divider, comprising:

an input stage, configured to receive an input signal;

an output stage, configured to output the frequency divided signal; and a 4^th or 6^th order LC resonant tank, configured to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle between the total vector sum of currents injected into the resonant tank and an output signal over a wide frequency band to achieve a wide locking range.

10. An injection-locked oscillator, comprising:

an input stage, configured to receive an input signal;

an output stage, configured to output an oscillating signal; and

a 4^th order LC resonant tank, configured to obtain a flat or rippled phase response around 0° within the maximum achievable phase angle between the total vector sum of currents being injected into the resonant tank and an output signal over a wide frequency band to achieve a wide locking range.

11. A sub-harmonically injected PLL frequency synthesizer system, comprising: a phase/frequency detector (PFD);

a charge pump (CP);

a low-pass filter (LPF);

a voltage controlled oscillator (VCO);

a divider chain; and

a wideband frequency multiplier chain; wherein the wideband frequency multiplier chain comprises the injection locked frequency multiplier of claim 1.

12. The sub-harmonically injected PLL frequency synthesizer system, further comprising:

at least one of the injection-locked frequency multiplier of claim 8, the injection- locked frequency divider of claim 9, and the injection-locked oscillator of claim 10.