CN110729998B - Broadband injection locking frequency divider based on distributed injection and transformer - Google Patents
Broadband injection locking frequency divider based on distributed injection and transformer Download PDFInfo
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Abstract
The invention discloses a broadband injection locking frequency divider based on distributed injection and a transformer, which comprises a frequency divider body and a frequency divider body, wherein the frequency divider body is provided with a power supply circuit, a power supply circuit and a power supply circuit, and the power supply circuit is connected with the power supply circuit: the power supply comprises a first cross-coupling tube, a second cross-coupling tube, a first nMOS injection tube, a first pMOS injection tube, a second nMOS injection tube, a second pMOS injection tube, a current source tube, a pMOS output tube, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, a first output buffer, a second output buffer, a first transformer and a second transformer, wherein the first transformer comprises a first primary coil, a first secondary coil, a first tertiary coil, a first transformer capacitor, and the second transformer comprises a second primary coil, a second secondary coil, a second tertiary coil and a second transformer capacitor. The invention can realize a wider locking range, achieves better overall performance in the aspects of phase noise, power consumption, output power and the like, and has better application prospect.
Description
Technical Field
The invention relates to the field of microwave engineering, in particular to a broadband injection locking frequency divider based on distributed injection and a transformer.
Background
The frequency divider, which is one of the key modules in a phase locked loop system, will have a direct impact on the quality of the signal source and the overall performance of the transceiver system. While realizing the frequency division function, we have to comprehensively consider the performance indexes of the frequency divider, such as the locking range, the power consumption, the phase noise, the output power, the chip area and the like. The frequency divider can be classified into a static frequency divider, a renewable frequency divider, and an injection locking frequency divider. Among them, injection locked frequency dividers are receiving continuous attention because of their high operating frequency and low power consumption. In a phase locked loop system, the locked range of the injection locked frequency divider needs to cover the output frequency range of the voltage controlled oscillator. To avoid the effects of process variations, ensuring good performance of the pll system, achieving a wide locking range becomes a major challenge in designing injection locked dividers.
Currently, a variety of techniques that can extend the lock range have been applied to the design of injection locked frequency dividers. In 2013, yue Chao and Howard C.Luong proposed a frequency tracking method, which can increase the injection efficiency of the injection tube and improve the locking range [1]. In 2016, sheng Lyang Jang et al used a third order cavity to reduce the quality factor of the divider cavity and thereby increase the locking range [2]. In 2017, alireza Imani and hostein hashimi proposed a distributed injection method, and the energy injected by multiple nodes is utilized to make the frequency divider complete the frequency division function at more resonance points, so as to improve the bandwidth [3]. However, the existing method has limited lifting effect on the locking range, and cannot achieve the optimal compromise between various indexes, so that the strict requirements of the system on the injection locking frequency divider cannot be met.
Therefore, how to better extend the locking range has become a critical issue in injection locked frequency divider design.
[ reference ] to
[1]Y.Chao and H.C.Luong,“Analysis and Design of a 2.9-mW 53.4–79.4-GHz Frequency-Tracking Injection-Locked Frequency Divider in 65-nm CMOS,”IEEE J.Solid-State Circuits,vol.48,no.10,pp.2403–2418,Oct.2013.
[2]S.L.Jang et al.“Triple-Resonance RLC-Tank Divide-By-2Injection-Locked Frequency Divider”,Electronics Letters,vol.52,no.8,pp.624-626,April 2016.
[3]Alireza Imani and Hossein Hashemi,“Distributed Injection-Locked Frequency Dividers”,IEEE J.Solid-State Circuits.vol.52.no.8.pp.2083-2093.August 2017.
Disclosure of Invention
Based on the requirements, the invention provides a broadband injection locking frequency divider based on distributed injection and a transformer, which can realize a wider locking range, achieves better overall performance in the aspects of phase noise, power consumption, output power and the like, and has better application prospect.
The aim of the invention is achieved by the following technical scheme.
The invention relates to a broadband injection locking frequency divider based on a distributed injection and transformer, which comprises a first transformer and a second transformer, wherein one end of a first primary coil of the first transformer is grounded, and the other end of the first primary coil of the first transformer is connected with the input end of a first output buffer; one end of a first secondary coil of the first transformer is connected with a voltage source, and the other end of the first secondary coil is connected with a first tertiary coil and is respectively connected with drains of a second nMOS injection tube and a second pMOS injection tube; one end of a first tertiary coil of the first transformer is connected with a first secondary coil, and the other end of the first tertiary coil is respectively connected with a first cross-coupling tube drain electrode, a second cross-coupling tube grid electrode, a first nMOS injection tube drain electrode and a first pMOS injection tube drain electrode;
one end of a second primary coil of the second transformer is grounded, and the other end of the second primary coil of the second transformer is connected with the input end of a second output buffer; one end of a second secondary coil of the second transformer is connected with a voltage source, and the other end of the second secondary coil is connected with a second tertiary coil and is respectively connected with sources of a second nMOS injection tube and a second pMOS injection tube; one end of a second tertiary coil of the second transformer is connected with a second secondary coil, and the other end of the second tertiary coil is respectively connected with a grid electrode of a first cross coupling tube, a drain electrode of the second cross coupling tube, a source electrode of an nMOS injection tube and a source electrode of a first pMOS injection tube;
the source electrode of the first cross coupling tube and the source electrode of the second cross coupling tube are both connected with the drain electrode of the current source tube, the source electrode of the current source tube is grounded, and the grid electrode of the current source tube inputs control voltage; the grid electrode of the first nMOS injection tube is connected with the negative end of the input signal through a third transmission line; the grid electrode of the second nMOS injection tube is connected with the negative end of the input signal through a fourth transmission line and a third transmission line in sequence; the grid electrode of the first pMOS injection tube is connected with the forward end of the input signal through a first transmission line; and the grid electrode of the second pMOS injection tube is connected with the forward end of the input signal through a second transmission line and a first transmission line in sequence.
The first output buffer and the second output buffer have the same circuit structure and comprise a pMOS output tube, the source electrode of the pMOS output tube is grounded, the grid electrode is used as the input end of the output buffer, and the drain electrode is respectively connected with an inductor, a harmonic short-circuit capacitor and an output capacitor; one end of the inductor is connected with the drain electrode of the pMOS output tube, the other end of the inductor is respectively connected with the bypass capacitor and the voltage source, one end of the bypass capacitor is connected with the inductor, and the other end of the bypass capacitor is grounded; one end of the harmonic short-circuit capacitor is connected with the drain electrode of the pMOS output tube, and the other end of the harmonic short-circuit capacitor is grounded; one end of the output capacitor is connected with the drain electrode of the pMOS output tube, and the other end of the output capacitor is used as the output end of the output buffer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
(1) The topology of the present invention utilizes distributed injection to create multiple segments of interdigitated locking ranges at multiple resonance points, creating an overall wide locking range effect. In addition, the locking range is further expanded by the four-order resonant cavity.
(2) The topology of the invention adopts the peaking inductance technology, so that the impedance peak value of the resonant cavity at the resonance point is increased, and the power consumption of the circuit is reduced. And by optimizing parameters of elements such as a transformer, an injection pipe, a cross coupling pipe and the like, the high-performance power-saving device can achieve good overall performance in the aspects of power consumption, output power and the like.
(3) The invention has simple topological structure and is convenient for integration.
Drawings
FIG. 1 is a schematic diagram of a wideband injection locked frequency divider based on a distributed injection and transformer in accordance with the present invention;
FIG. 2 is a schematic diagram of an output buffer;
FIG. 3 is a schematic diagram of the simulation results of the output sensitivity curve.
Reference numerals: m is M 1 Cross-coupled tube I, M 2 No. two cross-coupling tube M 3 First nMOS injection tube, M 4 First pMOS injection tube, M 5 No. two nMOS injection tube, M 6 Second pMOS injection tube, M 7 Current source tube M 8 pMOS output tube, TL 1 First transmission line, TL 2 Transmission line No. two, TL 3 Transmission line No. three, TL 4 Transmission line number four, L 1 Primary coil I, L 2 A first secondary coil L 3 Third-stage coil I, L 4 Second primary coil, L 5 Second secondary coil, L 6 Second third-stage coil, C t1 First transformer capacitor, C t2 No. two transformer capacitors, buffer No. 1 output Buffer, buffer No. 2 output Buffer, L b Inductance, C 1 Bypass capacitor C 2 Harmonic short-circuit capacitor C out And an output capacitance.
Detailed Description
In order to more clearly illustrate the technical scheme of the invention, the invention is further described below with reference to the accompanying drawings.
The invention provides a broadband injection locking frequency divider based on distributed injection and a transformer. The topology consists of cross-coupled pair transistors, transformers and output buffers. The topology adopts a distributed differential injection mode, enhances injection current and injection efficiency, adopts a high-order transformer as a resonant cavity, effectively increases the locking range of the frequency divider, reduces the number of control voltages and simplifies operation under the condition of tuning without using a variable capacitor tube. Meanwhile, the design of the high-order transformer combines the peaking inductance technology, so that the power consumption of the circuit is reduced. In addition, the structure of the traditional buffer is improved, the harmonic suppression capability is enhanced, and a wider locking range is maintained.
The injection locked frequency divider of the LC structure can be expressed by equation (1) as a relation between its locking range and circuit parameters.
Wherein Q is the quality factor of the resonant cavity, f center Is the self-resonant frequency of the frequency divider, eta is the injection efficiency of the injection tube, I inj To inject current, I osc Is the direct current of the frequency divider circuit. It can be seen that in order to expand the locking range of the divider, it is desirable to increase the injection efficiency η and decrease the resonator quality factor Q. However, in order to ensure the gain condition of the frequency divider, the Q value needs to be large enough, otherwise the circuit power consumption will be greatly increased. The topology provided by the invention can effectively improve the injection efficiency eta of the injection pipe, and can achieve better overall performance of the frequency divider by selecting a proper resonant cavity quality factor Q.
As shown in fig. 1, the wideband injection locking frequency divider based on distributed injection and transformer of the present invention comprises a first transformer and a second transformer, wherein the first transformer comprises a first primary coil L 1 First secondary coil L 2 Third-stage coil L 3 Transformer capacitor C t1 ，C t1 The two ends of the first transformer capacitor are respectively connected to the first primary coil L 1 Both ends; the second transformer comprises a second primary coil L 4 Secondary coil L 5 Third-stage coil L 6 Capacitor C of transformer II t2 No. two voltage transformationCapacitor C t2 Two ends are respectively connected to the primary coil L 4 Two ends.
Primary winding L of the primary transformer 1 One end is grounded, and the other end is connected with the input end of the first output Buffer 1; a primary secondary coil L of the primary transformer 2 One end and a voltage source V DD Is connected with a third-stage coil L at the other end 3 Is connected with a second nMOS injection tube M 5 And a second pMOS injection tube M 6 A drain electrode of (2); third-stage coil L of the first transformer 3 One end and a first secondary coil L 2 The other ends are respectively connected with a first cross coupling pipe M 1 Drain electrode, no. two cross-coupled tube M 2 Grid, nMOS injection tube M 3 Drain, first pMOS injection tube M 4 And a drain electrode.
No. two primary coil L of No. two transformers 4 One end is grounded, and the other end is connected with the input end of the second output Buffer 2. Secondary coil L of transformer II 5 One end and a voltage source V DD The other end is connected with a second third-stage coil 6 Is connected with a second nMOS injection tube M 5 And a second pMOS injection tube M 6 Is a source of (c). Second third-stage coil L of second transformer 3 One end and a second secondary coil L 5 The other ends are respectively connected with a first cross coupling pipe M 1 Grid, no. two cross-coupling tube M 2 Drain, nMOS injection tube M 3 Source, pMOS injection tube M 4 And a source electrode.
The first cross-coupling pipe M 1 Source and No. two cross-coupled tubes M 2 Sources are all connected with a current source pipe M 7 Drain electrode, the current source tube M 7 The source electrode is grounded, the current source tube M 7 The control voltage V outside the grid input chip B . The first nMOS injection tube M 3 The grid is connected with TL through a transmission line III 3 Connected with the negative terminal V of the input signal inj -. The second nMOS injection tube M 5 The grid electrode sequentially passes through a fourth transmission line TL 4 Transmission line TL 3 Connection and transmissionGo into negative terminal V of signal inj -. The first pMOS injection tube M 4 The grid electrode passing through a first transmission line TL 1 Connected with the positive terminal V of the input signal inj +. The second pMOS injection tube M 6 The grid electrode sequentially passes through a transmission line TL No. two 2 Transmission line TL 1 Connected with the positive terminal V of the input signal inj +。
As shown in FIG. 2, the first output Buffer1 and the second output Buffer2 have the same circuit structure and each include a pMOS output tube M 8 The pMOS output tube M 8 The source electrode is grounded, the grid electrode is used as the input end of the output buffer, and the drain electrodes are respectively connected with the inductor L b Harmonic short-circuit capacitor C 2 Output capacitance C out . The inductance L b One end is connected with the pMOS output tube M 8 The other ends of the drain electrodes are respectively connected with a bypass capacitor C 1 And a voltage source V DD The bypass capacitor C 1 One end is connected with an inductance L b The other end is grounded. The harmonic short-circuit capacitor C 2 One end is connected with the pMOS output tube M 8 And the other end of the drain electrode is grounded. The output capacitor C out One end is connected with the pMOS output tube M 8 And the other end of the drain electrode is used as an output end of the output buffer.
First cross coupling pipe M 1 Source and No. two cross-coupled tubes M 2 And when the frequency divider is conducted, negative resistance is provided for the frequency divider circuit, and loss of the resonant cavity is compensated. First nMOS injection tube M 3 First pMOS injection tube M 4 nMOS injection tube M No. two 5 pMOS injection tube M No. two 6 The frequency divider is equivalent to a frequency mixer, and mixes the injected frequency doubling signal with a fundamental frequency feedback signal, so as to obtain fundamental frequency output and complete the frequency division function. First nMOS injection tube M of this topology 3 First pMOS injection tube M 4 And No. two nMOS injection pipes M 5 pMOS injection tube M No. two 6 Two pairs of injection tubes for interconnecting the source and drain electrodes of the nMOS and the pMOS respectively. The differential injection is realized, the transconductance is enhanced, the injection efficiency is improved, the size of the total parasitic capacitance is reduced, and the locking range of the frequency divider is improved. The transformer adopts a mode of combining coaxial coupling and vertical coupling, so that parasitic electricity of the transformer is reducedHold and let L at the same time 1 L 2 L 3 、L 4 L 5 L 6 The coupling coefficients between the two are almost equal. First transformer capacitor C t1 And transformer capacitor C t2 For adjusting parameters of the transformer. And finally, the output signal is output to the next-stage frequency divider by the input end of the transformer, which is coupled to the buffer.
The frequency divider provided by the invention adopts the fourth-order resonant cavity, reduces the phase shift of the resonant cavity, and is more beneficial to meeting the phase condition of injection locking. The slope of the phase response curve of the traditional second-order LC resonant cavity is larger at the central frequency point, so that the phase shift of the resonant cavity in a wider frequency band is overlarge, and the phase shift compensation provided by the injection tube is difficult, so that the locking range of the frequency divider is reduced. Although the impedance of the second-order LC resonant cavity is larger at the center frequency point, the gain condition can be fully met, the steeper phase response curve can not meet the phase condition in a wider bandwidth, and the whole locking range is narrower. To improve this situation, this topology employs a fourth-order LC cavity to effectively extend the locking range. The impedance of the fourth-order LC resonant cavity presents two adjacent peaks, the phase response of the fourth-order LC resonant cavity presents a corrugated gentle curve near 0 degrees, and the gain condition and the phase condition of the injection locking of the frequency divider can be met within a wider bandwidth.
To further extend the locking range, this topology employs a distributed injection approach, increasing the locking range by increasing iinj. The traditional injection locking frequency divider has only one resonance point, the injection current is irrelevant to frequency, and the locking range is limited. The distributed injection method can enhance the injection current, and can enable the frequency divider to meet the vibration starting condition at a plurality of resonance points, so that the locking range and the injection power required by the frequency divider are improved. The magnitude of the injection current of the distributed injection is related to the frequency omega, and when the frequency is larger than the first resonance point, the injection current is gradually increased and is larger than that of the conventional structure. The injection level number and the locking range show a proportional relation, but the topology selects two-stage distributed injection due to the consideration of the chip area, so that a wider locking range can be achieved. By careful selection of the injection tube M 3 ～M 6 Dimension and L of (2) 2 、L 3 The two-stage injection current is superimposed in the forward direction. Therefore, the injection current in the frequency band above the self-resonant frequency of the frequency divider is enhanced, the energy injected into the frequency divider is effectively enhanced, the highest frequency division frequency is improved, and the locking range is enlarged.
Besides distributed injection, the topology also adopts a differential injection mode, adopts the mode of interconnecting an nMOS source electrode and a pMOS drain electrode, enhances the transconductance of an injection tube, increases the injection current, reduces the size of the total parasitic capacitance, and improves the locking range of the frequency divider. Meanwhile, the differential injection tube is convenient to connect with the differential output of the VCO.
The output buffer of the invention adopts a harmonic suppression technology. The injection locked frequency divider acts as a first stage frequency divider of the phase locked loop, and the fundamental wave of the output signal should be greater than its harmonic wave. In the output buffer shown in fig. 2, the inductance L b And bypass capacitor C 1 For biasing the pMOS output tube M8. To filter out harmonics, L b The inductance value of (a) tends to be large, otherwise the harmonic size will be larger than the fundamental wave, resulting in poor signal quality and narrowing of the locking range. But L is b Occupies an excessive chip area. Therefore, the invention reintroduces the harmonic short-circuit capacitor C into the bias network 2 The bias network becomes AC ground for the second harmonic and the third harmonic, thereby achieving the effect of restraining the harmonic. Through simulation comparison, the buffer structure can improve the power ratio of fundamental wave and second harmonic by 10.91dB.
As shown in FIG. 3, simulation verifies that the invention can reach a locking range of 22.8-36.3GHz (45.7%) under the injection power of 0dBm, and the power consumption is 3.54mW, so that a wider locking range and better overall performance are achieved.
Although the function and operation of the present invention has been described above with reference to the accompanying drawings, the present invention is not limited to the above-described specific functions and operations, but the above-described specific embodiments are merely illustrative, not restrictive, and many forms can be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the appended claims, which are included in the protection of the present invention.
Claims (2)
1. A broadband injection locking frequency divider based on distributed injection and transformers comprises a first transformer and a second transformer, and is characterized in that a first primary coil (L 1 ) One end is grounded, and the other end is connected with the input end of the first output Buffer (Buffer 1); a primary secondary winding (L of the primary transformer 2 ) One end is connected with a voltage source (V DD ) Is connected with a third-stage coil (L) 3 ) Is connected with a second nMOS injection tube (M 5 ) And pMOS injection tube No. two (M) 6 ) A drain electrode of (2); a third-stage coil (L) 3 ) One end and a first secondary coil (L) 2 ) Is connected with the other end of the first cross-coupled tube (M) 1 ) Drain, no. two cross-coupled tube (M) 2 ) Grid, nMOS injection tube number one (M) 3 ) Drain, first pMOS injection tube (M) 4 ) A drain electrode;
the primary winding (L) 4 ) One end is grounded, and the other end is connected with the input end of a second output Buffer (Buffer 2); the secondary winding (L) 5 ) One end is connected with a voltage source (V DD ) And a second tertiary coil (L) 6 ) Is connected with a second nMOS injection tube (M 5 ) And pMOS injection tube No. two (M) 6 ) A source of (a); the second tertiary coil (L of the second transformer 6 ) One end and the second secondary coil (L) 5 ) Is connected with the other end of the first cross-coupled tube (M) 1 ) Grid, no. two cross coupling tube (M) 2 ) Drain, nMOS injection tube (M) 3 ) Source, first pMOS injection tube (M) 4 ) A source electrode;
the cross-coupled tube number one (M 1 ) Source and No. two cross-coupled tube (M) 2 ) Sources are all connected with current source tube (M) 7 ) Drain, current source tube (M 7 ) The source electrode is grounded, the current source tube (M 7 ) The gate input control voltage (V B ) The method comprises the steps of carrying out a first treatment on the surface of the The first nMOS injection tube (M 3 ) The gate is connected via a transmission line No. three (TL 3 ) Connecting the negative side of the input signal (V inj (-) -; the second nMOS injection tube (M 5 ) The grid electrode sequentially passes through a fourth transmission line (TL 4 ) Transmission line number Three (TL) 3 ) Connecting the negative side of the input signal (V inj (-) -; the first pMOS injection tube (M 4 ) The gate is connected to the first transmission line (TL 1 ) Is connected to the input signal forward terminal (V inj (+) is carried out; the second pMOS injection tube (M 6 ) The grid electrode sequentially passes through a second transmission line (TL 2 ) Transmission line number one (TL) 1 ) Is connected to the input signal forward terminal (V inj +)。
2. The wideband injection locked frequency divider based on distributed injection and transformer as claimed in claim 1, wherein the first output Buffer (Buffer 1) and the second output Buffer (Buffer 2) have the same circuit structure and each include a pMOS output tube (M 8 ) Said pMOS output tube (M 8 ) The source electrode is grounded, the grid electrode is used as the input end of the output buffer, and the drain electrodes are respectively connected with the inductor (L b ) Harmonic short-circuit capacitor (C) 2 ) Output capacitance (C) out ) The method comprises the steps of carrying out a first treatment on the surface of the Said inductance (L b ) One end is connected with a pMOS output tube (M) 8 ) The other ends of the drain electrodes are respectively connected with a bypass capacitor (C 1 ) And a voltage source (V) DD ) The bypass capacitance (C 1 ) One end connecting inductance (L) b ) The other end is grounded; the harmonic short-circuit capacitor (C 2 ) One end is connected with a pMOS output tube (M) 8 ) A drain electrode, the other end of which is grounded; the output capacitance (C out ) One end is connected with a pMOS output tube (M) 8 ) And the other end of the drain electrode is used as an output end of the output buffer.
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| WO2014026029A1 (en) * | 2012-08-09 | 2014-02-13 | Qualcomm Incorporated | Tunable injection locked dividers with enhanced locking range |
| CN103607201A (en) * | 2013-11-27 | 2014-02-26 | 中国科学院微电子研究所 | Injection locking frequency divider with wide locking range |
| WO2015042814A1 (en) * | 2013-09-25 | 2015-04-02 | Huawei Technologies Co., Ltd. | Wideband injection locked frequency multipliers, oscillators and dividers using higher order lc resonant tank |
| JP2016208156A (en) * | 2015-04-17 | 2016-12-08 | 株式会社半導体理工学研究センター | Oscillation circuit and phase lock loop |
| CN106487382A (en) * | 2016-10-13 | 2017-03-08 | 天津大学 | A kind of injection locking frequency divider of multimode frequency dividing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7154349B2 (en) * | 2004-08-11 | 2006-12-26 | Qualcomm, Incorporated | Coupled-inductor multi-band VCO |
| TWI431943B (en) * | 2010-07-20 | 2014-03-21 | Ind Tech Res Inst | Injection-locked frequency divider |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014026029A1 (en) * | 2012-08-09 | 2014-02-13 | Qualcomm Incorporated | Tunable injection locked dividers with enhanced locking range |
| WO2015042814A1 (en) * | 2013-09-25 | 2015-04-02 | Huawei Technologies Co., Ltd. | Wideband injection locked frequency multipliers, oscillators and dividers using higher order lc resonant tank |
| CN103607201A (en) * | 2013-11-27 | 2014-02-26 | 中国科学院微电子研究所 | Injection locking frequency divider with wide locking range |
| JP2016208156A (en) * | 2015-04-17 | 2016-12-08 | 株式会社半導体理工学研究センター | Oscillation circuit and phase lock loop |
| CN106487382A (en) * | 2016-10-13 | 2017-03-08 | 天津大学 | A kind of injection locking frequency divider of multimode frequency dividing |
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