WO2015040658A1

WO2015040658A1 - Information processing method, information processing device, memory controller, and memory

Info

Publication number: WO2015040658A1
Application number: PCT/JP2013/005598
Authority: WO
Inventors: 早坂　和美; 雅紀日下田
Original assignee: 富士通株式会社
Priority date: 2013-09-20
Filing date: 2013-09-20
Publication date: 2015-03-26
Also published as: JPWO2015040658A1; JP6075456B2

Abstract

The objective of the disclosed technology is to provide a method able to suppress erroneous operation of an information processing device on the basis of erroneous data and erroneous data reading even in the case that there has been a failure in the writing of data to memory. In the disclosed method, data to which a logical address has been imparted is written to a predetermined physical address of memory, and when the writing of data has not been carried out normally, a first flag is generated indicating that writing was not carried out normally and is stored associated with the logical address. By means of the first flag, it is possible for the fact that there is an error in data to which a specific logical address has been imparted to remain as a record. As a result, it is possible to prevent a computation processing node from reading erroneous data.

Description

Information processing method, information processing apparatus, memory controller, and memory

The present disclosure relates to an information processing method, an information processing device memory controller, and a memory.

The information processing apparatus includes an arithmetic processing node that performs data processing, and a memory that is connected to the arithmetic processing node via a bus and stores data. The arithmetic processing node reads out data stored in the memory and performs necessary arithmetic processing. The arithmetic processing node stores data obtained as a result of the arithmetic processing in the memory. An information processing apparatus may have a plurality of arithmetic processing nodes. The first arithmetic processing node of the plurality of arithmetic processing nodes stores data in a specific area of the memory, and another second arithmetic processing node of the plurality of arithmetic processing nodes is the data stored by the first arithmetic processing node. May be read from the memory for processing.

As a memory for storing data, for example, a flash memory which is a kind of nonvolatile memory is known. The flash memory stores data by holding the charge injected into the charge storage film. Even if the arithmetic processing node makes a write request to the memory and performs a data write process to the memory, the data may not be correctly written to the memory. For example, when the memory is the above flash memory, a write error such as the amount of charge injected into the charge storage film does not reach a predetermined amount may occur. When a data write error occurs, erroneous data is stored in the memory.

In the writing of data to the flash memory, when writing to a specific address fails, a prior art is known in which the same data is written to another address (for example, see Patent Document 1).

JP 2004-133777 A

When data writing to the memory fails, if the arithmetic processing node makes a read request for the data written to the memory thereafter, erroneous data stored in the memory will be read. If processing based on the read erroneous data is performed at the arithmetic processing node, it may cause a malfunction of the information processing apparatus. If the information processing apparatus has a plurality of operation processing nodes, the first operation processing node itself writes the data after the first operation processing node of the plurality of operation processing nodes writes the data. This can occur in both cases where data is read and when a second arithmetic processing node different from the first arithmetic processing node reads data.

The prior art expects that when data writing to a certain address fails, normal writing is performed by changing the write target address and performing writing again. However, in the prior art, there is a means for preventing erroneous data from being read when the data is not normally written even if the address is changed to another address, and eventually the erroneous data is written in the memory. There is no disclosure.

The technique disclosed in the present application is intended to provide a method capable of suppressing erroneous data reading and malfunctioning of an information processing apparatus based on erroneous data even when data writing to a memory fails.

Write data with a logical address to a given physical address in the memory, and if the data is not written correctly, generate a flag indicating that the data was not written correctly Store in association with the logical address.

By providing a flag indicating that writing to the memory has not been performed normally in association with the logical address, it is possible to leave a record that there is an error in the data with the specific logical address. Thereby, it is possible to prevent the arithmetic processing node from reading erroneous data. In addition, it is possible to suppress information processing based on the read erroneous data.

It is a figure which shows the hardware constitutions of the information processing apparatus in an Example. It is a figure explaining the page of the flash memory in an Example. It is a figure which shows the logical address management table and physical address management table in an Example. It is a figure which shows the logical address management table and physical address management table in an Example. It is a functional block diagram of the processor which the arithmetic processing node in an Example has. It is a figure which shows the description format of the request | requirement in an Example. It is a figure which shows the information stored in the memory in an Example. It is a functional block diagram of the processor which the memory controller in an Example has. 1 is a circuit block diagram of a flash memory in an embodiment. It is a figure which shows the flow of a process between the arithmetic processing node in a Example, a memory controller, and a memory. It is a figure which shows the flow of a process between the arithmetic processing node in a Example, a memory controller, and a memory. It is a write-processing flowchart figure of the processor which the memory controller in an Example has. It is a read-out process flowchart figure of the processor which the memory controller in an Example has. It is a figure which shows the logical address management table in 2nd Example. It is a figure which shows the flow of a process between the arithmetic processing node in 2nd Example, a memory controller, and memory. It is a write-processing flowchart figure of the processor which the memory controller in 2nd Example has. It is a figure which shows the logical address management table in 3rd Example. It is a write-processing flowchart figure of the processor which the memory controller in 3rd Example has. It is a figure which shows the logical address management table in 4th Example. It is a figure which shows the flow of a process between the arithmetic processing node in 4th Example, a memory controller, and memory. It is a read-out process flowchart figure of the processor which the memory controller in 4th Example has. It is a write-processing flowchart figure of the processor which the memory controller in 4th Example has.

<First embodiment>
FIG. 1 is a hardware configuration diagram of an information processing apparatus 1 in the embodiment. The information processing apparatus 1 includes a first arithmetic processing node 100, a second arithmetic processing node 200, a memory controller 300, a flash memory 400, and a bus 500. The first processing node 100 includes a processor 110, a memory 130, and a network interface card (hereinafter, NIC) 150. The processor 110 and the memory 130 are connected to each other, and the processor 110 can access the memory 130. Similar to the first arithmetic processing node 100, the second arithmetic processing node 200 includes a processor 210, a memory 230, and a NIC 250. The processor 210 and the memory 230 are connected to each other, and the processor 210 can access the memory 230. The memory controller 300 includes a processor 310, a memory 330, and a NIC 350. The processor 310 and the memory 330 are connected to each other, and the processor 310 can access the memory 330. The

processors

110, 210, and 310 are, for example, CPU chips, and the

memories

130, 230, and 330 are, for example, DRAM chips. The first arithmetic processing node 100, the second arithmetic processing node 200, and the memory controller 300 are connected to each other by a bus 500. The flash memory 400 is connected to the bus 500 via the memory controller 300.

The first arithmetic processing node 100 and the second arithmetic processing node 200 can write data to the flash memory 400 via the memory controller 300. The first arithmetic processing node 100 and the second arithmetic processing node 200 can read data from the flash memory 400 via the memory controller 300. In addition, the second arithmetic processing node 200 can read out the data written in the flash memory 400 by the first arithmetic processing node 100 and perform arithmetic processing. The present embodiment shows an information processing apparatus 1 including two arithmetic processing nodes, a first arithmetic processing node 100 and a second arithmetic processing node 200, as arithmetic processing nodes that can access the flash memory 400 via the memory controller 300. It was. However, the number of arithmetic processing nodes included in the information processing apparatus 1 is not limited to this, and the information processing apparatus 1 only needs to include at least one arithmetic processing node.

FIG. 2 is a diagram for explaining a unit of an area where writing, reading, and erasing can be performed in the flash memory 400 in the embodiment. The flash memory 400 writes and reads data in units called pages including a plurality of storage elements. The flash memory 400 erases data in units called blocks including a plurality of pages. 2, each of P # 0000, P # 0001,... P # 00MN corresponds to one page. Also, P # 0000 to P # 000N constitute one block.

When writing data to a specific page of the flash memory 400, if data is already stored in the page, new data cannot be overwritten on the stored data. This is due to the principle that the storage element of the flash memory 400 writes data by performing charge injection or charge extraction with respect to the charge holding film between the gate electrode and the channel region. Therefore, when writing certain data to page P # 0000, for example, it is necessary to first check whether data is already stored in page P # 0000. If data is not yet stored on page P # 0000, data is written to page P # 0000. If data is already stored in page P # 0000, another empty page is extracted and data is written. Further, when data is already stored in page P # 0000 and the already stored data is updated with new write data, processing is performed according to the following procedure.

First, prepare the data to be newly written. Then, the data stored in page P # 0000 is read. Next, the read data and newly written data are merged to create update data. Then, a page where data has not been written is searched. For example, when page P # 0001 is selected as a page where data is not written, update data is written to page P # 0001.

Next, the logical address and physical address used in this specification and the correspondence between them will be described. In the information processing apparatus 1 shown in FIG. 1, a case where the first arithmetic processing node 100 writes data X to the flash memory 400 will be described as an example. The first processing node 100 makes a write request to the memory controller 300 and transmits write data X. At this time, the first arithmetic processing node 100 attaches an identifier that can be recognized by the first arithmetic processing node 100 and the second arithmetic processing node 200 to the data. This identifier is called a logical address. Here, the logical address is described as L # 00xx. The memory controller 300 stores the received data X in any page of the flash memory 400. For example, when data is not yet written on page P # 0000, data X can be written on page P # 0000. On the other hand, if data has already been written to page P # 0000, data X is written to another empty page, for example P # 0001. If data has already been written to page P # 0001, data X is written to another page. That is, the page in which the data X is stored in the flash memory 400 differs depending on the empty state of the page in the flash memory 400 at that time. Here, pages P # 0000 and P # 0001 on which data X is actually written are called physical addresses. After the data X is written to any page of the flash memory 400, the first arithmetic processing node 100 or the second arithmetic processing node 200 accesses the flash memory 400 in order to read the data X. In this case, the first arithmetic processing node 100 or the second arithmetic processing node 200 designates the logical address L # 00xx used for storing and makes a read request. In order for the memory controller 300 to correctly respond to the request, it is necessary to store to which page in the flash memory 400 the data X specified by the logical address L # 00xx was written. In this specification, a table that records which physical address a logical address corresponds to is called a logical address management table.

FIG. 3A is a diagram illustrating an example of a logical address management table in the embodiment. The logical address management table shown in FIG. 3A includes a logical address, a physical address corresponding to the logical address, an L-Valid value, and an L-Error value.

The L-Valid value is a flag indicating whether data with a logical address is stored in the corresponding physical address. In FIG. 3A, the L-Valid value “1” corresponding to the logical address L # 0003 indicates that the data with the logical address L # 0003 is stored in the page of the corresponding physical address P # 0001. Indicates that In FIG. 3A, the L-Valid value corresponding to the logical address L # 0000 is “0”. In this case, the data with the logical address L # 0000 is not stored in the page of the physical address P # 0011. That is, in the logical address management table, it seems that the logical address L # 0000 and the physical address P # 0011 are associated with each other, but the data to which the logical address L # 0000 is actually attached is the physical address P # 0011. Is not stored in the page.

The L-Error value is a flag indicating whether or not the data with the logical address is correctly written in the flash memory 400. In the example shown in FIG. 3A, if the L-Error value is “0”, it means that the data specified by the logical address is correctly stored in the flash memory 400. On the other hand, if the L-Error value is “1”, it means that the data specified by the logical address is not correctly stored in the flash memory 400, that is, the written data includes an error.

In addition to the logical address management table, it is necessary to record whether the page of each physical address in the flash memory 400 is in a state where some data is stored or whether the data is erased. is there. A table in which the page status of each physical address is recorded is called a physical address management table. FIG. 3B is a diagram illustrating an example of a physical address management table in the embodiment. The physical address management table shown in FIG. 3B includes a physical address, a P-Valid value, and a P-Error value.

The P-Valid value is a flag indicating whether any data is written in the page of the corresponding physical address. For example, “0” that is the P-Valid value corresponding to the page of the physical address P # 0011 means that data is not written in the page of the physical address P # 0011. Further, “1” which is a P-Valid value corresponding to the page of the physical address P # 0001 means that some data is written to the page of the physical address P # 0001.

The P-Error value is a flag indicating that some device failure has occurred in the storage element of the corresponding physical address page. The device failure of the memory element is, for example, a case where the charge retention capability of the charge retention film of the flash memory 400 is deteriorated. In FIG. 3B, “1” which is the value of P-Error corresponding to the page of the physical address P # 0014 indicates that there is some trouble in at least a part of the storage element included in the page of the physical address P # 0014. It means that there is. By recording the P-Error value in this way, it is possible to recognize that this page has some physical defect, and it is possible to control such that writing to this page will not be performed in the future. Become.

Here, the difference in technical significance between the L-Error value described in the logical address management table and the P-Error value described in the physical address management table will be described. The P-Error value is an identifier associated with a physical address, and indicates that some trouble has occurred in the storage element of the corresponding physical address page, and data cannot be correctly written to the page of the physical address. It is. On the other hand, the L-Error value is an identifier associated with the logical address, and indicates that the data with the corresponding logical address was not correctly written. The correspondence between the logical address and the physical address is not constant, and can be changed by, for example, garbage collection described later. Therefore, the P-Error value associated with the physical address cannot continuously record that the data with a certain logical address was not correctly written. On the other hand, the L-Error value is an identifier assigned corresponding to the logical address. Therefore, even if the correspondence relationship between the logical address and the physical address is changed, it can be continuously recorded that the writing of data with a certain logical address was not performed correctly. By using this L-Error value, it is possible to improve the efficiency of data processing of the entire information processing apparatus 1 or to suppress malfunction of information processing. In this specification, L-Error is also called a write error flag.

Next, how to use the logical address management table and the physical address management table and how to update the contents of each table when writing data will be described. Assume that the logical address management table and the physical address management table have the contents shown in FIGS. 3A and 3B, respectively, at the time of receiving the data write request. As a first example, an example will be described in which the first arithmetic processing node 100 makes a write request for data A with the logical address L # 0000. According to the logical address management table of FIG. 3A, since the L-Valid value of the logical address L # 0000 is “0”, it can be seen that the current write is not a data update but a new data write. . It can also be seen that the logical address L # 0000 is associated with the physical address P # 0011. According to the physical address management table of FIG. 3B, the P-Valid value of the physical address P # 0011 is “0”. That is, it can be seen that no data is written in the page of the physical address P # 0011 associated with the logical address L # 0000. In this case, data A is written in the page of physical address P # 0011. Then, “1” is written in the L-Valid field corresponding to the logical address L # 0000. Further, “1” is written in the P-Valid field corresponding to the physical address P # 0011.

As a second example, an example will be described in which the first arithmetic processing node 100 makes a write request for data B to which a logical address L # 0002 is attached. According to the logical address management table of FIG. 3A, since the L-Valid value of the logical address L # 0002 is “0”, it can be seen that the current write is not a data update but a new data write. . It can also be seen that the logical address L # 0002 is associated with the physical address P # 0006. According to the physical address management table of FIG. 3B, since the P-Valid value of the physical address P # 0006 is “1”, some data has already been written to the page of the physical address P # 0006. I understand that In this case, another page to which data has not yet been written, for example, the page of the physical address P # 0011 is specified as the write page. Then, data B is written to the physical address P # 0011, and the physical address corresponding to the logical address L # 0002 is rewritten from P # 0006 to P # 0011 in the logical address management table. Also, the L-Valid value corresponding to the logical address L # 0002 in the logical address management table is set to “1”. Further, the P-Valid value corresponding to the physical address P # 0011 in the physical address management table is set to “1”.

As a third example, an example will be described in which the first arithmetic processing node 100 makes a write request for data C with the logical address L # 0003. According to the logical address management table of FIG. 3A, since the L-Valid value of the logical address L # 0003 is “1”, it can be seen that the current write is not a new data write but a data update. . It can also be seen that the logical address L # 0003 is associated with the physical address P # 0001. In this case, the data stored at the physical address P # 0001 is read and merged with the data C, and the merged data is written to another page. As another page, for example, the merged data is written in the page of the physical address P # 0011. In the logical address management table, the physical address corresponding to the logical address L # 0003 is rewritten from P # 0001 to P # 0011. In the physical address management table, the P-Valid value corresponding to the physical address P # 0011 is rewritten to “1”. In this third example, the physical address P # 0001 in which the pre-update data is stored is not associated with the logical address L # 0003 while retaining the pre-update data, and the first calculation process is performed. The page cannot be accessed from the node 100 or the second arithmetic processing node 200. This means that the memory area that can actually be used is reduced. In this way, by performing garbage collection on the area that can no longer be accessed, it can be made an area that can be accessed for writing and reading again. Garbage collection is a writable area in which a page in which valid data is written in a block to be erased is moved to another block, and the block to be erased is erased without including a page in which valid data is written. It means the work to increase.

As a fourth example, an example in which the first arithmetic processing node 100 makes a write request for data D with the logical address L # 0001 will be described. According to the logical address management table of FIG. 3A, since the L-Valid value of the logical address L # 0001 is “0”, it can be seen that the current write is not a data update but a new data write. . It can also be seen that the logical address L # 0001 is associated with the physical address P # 0023. According to the physical address management table of FIG. 3B, the P-Valid value of the physical address P # 0023 is “0”. That is, it can be seen that no data is written to the physical address P # 0023 associated with the logical address L # 0001. In this case, data D is written at physical address P # 0023. At this time, it is assumed that the data writing is not normally performed and the data D is not correctly written to the page of the physical address P # 0023. In this case, the following operations are performed.

First, since data was written to the physical address P # 0023, the P-Valid value is set to “1” to indicate that this page is not in the erased state. Also, the P-Error value is set to “1” to indicate that there is a possibility that there is any device failure in the physical address P # 0023. In order to indicate that the logical address L # 0001 is associated with the physical address 0023, the L-Valid value is set to “1”. Further, in order to indicate that the data with the logical address L # 0001 is stored in the flash memory 400 in an error state, the L-Error value is set to “1”. The contents of the logical address management table and physical address management table after such rewriting are shown in FIG. 4 (A) and FIG. 4 (B).

As described above, data is written using the logical address management table and physical address management table, and the contents of the logical address management table and physical address management table are rewritten.

FIG. 5 is a functional block diagram of the processor 110 included in the first arithmetic processing node 100 in the embodiment. The processor 110 implements the function of each block shown in FIG. 5 by executing processing based on a predetermined program stored in the memory 130, the flash memory 400, or the memory of another arithmetic processing node. The processor 110 transmits / receives data and / or various notifications to / from the request issuing unit 111 that issues an access request to the flash memory 400 to the memory controller 300, the memory controller 300, and the second processing node 200. It functions as a transmission / reception unit 112, a recovery processing unit 113 that performs recovery processing when data writing to the flash memory 400 fails, and a memory control unit 114 that controls the memory 130. However, not all of the functions shown in FIG. Some functions may be realized by a processor other than the processor 110 or a dedicated integrated circuit. The processor 210 included in the second processing node 200 realizes the same function as the processor 110 by executing processing based on a predetermined program stored in the memory 230, the flash memory 400, or the memory of another processing node. .

FIG. 6 is a diagram illustrating an example of a description format of a request issued from the first arithmetic processing node 100 or the second arithmetic processing node 200 in the present embodiment. The request description format includes a “request issuer ID” indicating the request issuer, a “request ID” for identifying the request identity, a “command” indicating the request content, and a “node” indicating the request destination. “Address” and “logical address” for designating the logical address of the data are included.

FIG. 7 is a diagram illustrating information included in the memory 330 included in the memory controller 300 according to the embodiment. The memory 330 stores a logical address management table 331 and a physical address management table 332. The memory 330 is also used as a data buffer for temporarily storing data written to the flash memory 400.

FIG. 8 is a functional block diagram of the processor 310 included in the memory controller 300 in the embodiment. The processor 310 implements the function of each block illustrated in FIG. 8 by executing processing based on a predetermined program stored in the memory 330, the flash memory 400, or the memory of another arithmetic processing node. The processor 310 includes a table management unit 311 that decodes and changes the logical address management table 331 and the physical address management table 332, and a lock control unit that restricts access to other requests while the memory controller 300 is processing the request. 312, a notification unit 313 that performs various notifications to the first arithmetic processing node 100 and the second arithmetic processing node 200, a memory control unit 314 that controls the memory 330, a data reading unit 315 that reads data from the flash memory 400, and a flash A data writing unit 316 that writes data to the memory 400, a confirmation unit 317 that confirms whether writing to the flash memory 400 has been completed correctly, a rewriting unit 318 that performs rewriting control to the flash memory 400, and data transmission As the data transmission unit 319 To function. However, not all of the functions shown in FIG. Some functions may be realized by a processor other than the processor 310 or a dedicated integrated circuit.

FIG. 9 is a circuit block diagram of the flash memory 400 in the embodiment. The flash memory 400 includes a memory cell array 410 in which storage elements are arranged, a write / read circuit 420 that writes data to and reads data from the storage elements included in the memory cell array 410, and a write buffer 430 that stores write data. And a comparator 440 and a status register 450. The flash memory 400 may include an error correction circuit 460, although not essential. When an error correction circuit is used in this embodiment, the error correction circuit may be mounted on the flash memory 400 or the memory controller 300.

When writing data to the flash memory 400, the write data is first held in the write buffer 430. Then, the write / read circuit 420 performs a write process on the storage elements in the memory cell array 410 based on the data in the write buffer 430. Thereafter, the comparator 440 compares the data written in the storage element with the data held in the write buffer 430. As a result of the comparison by the comparator 440, when both data match, information indicating that the writing has been normally performed is recorded in the status register 450. If the data written in the storage element and the data held in the write buffer 430 do not match, information indicating that the writing has not been normally performed is recorded in the status register 450. When the flash memory 400 has the error correction circuit 460, the error correction additional bits are written into the memory cell array 410 together with the write data. Even if there is an error in the written data, the error-corrected data is read if the error can be corrected using the additional bit for error correction. In the present embodiment, even when there is an error in the write data, if the error can be corrected by the error correction circuit 460, information indicating that the writing has been normally completed may be written in the status register 450. . In this case, when there is a write error that cannot be corrected by the error correction circuit 460, information indicating that the writing has not been normally performed is written in the status register 450. Alternatively, if there is an error in the write data, even if the error can be corrected by the error correction circuit 460, information indicating that the writing has not been normally performed may be written in the status register 450. In this specification, “normally writing has not been performed” means that “there is some error in the written data regardless of whether error correction is possible or impossible” and “error correction is impossible”. It is used to include both cases where an error is present in the write data.

FIG. 10 is a diagram illustrating a process flow among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400. First, in process 601, the first arithmetic processing node 100 makes a data write request to the memory controller 300. In process 602, the first arithmetic processing node 100 transmits write data to the memory controller 300. It is assumed that the write data is assigned a logical address L # 00xx. In process 603, the NIC 350 transfers the write request to the processor 310. In process 604, the NIC 350 temporarily stores write data in the memory 330. In process 605, the NIC 350 notifies the first arithmetic processing node 100 of a request receipt notification. Although the request reception notification is not essential in this embodiment, the first arithmetic processing node 100 performs other work by transmitting the request reception notification before the actual writing to the flash memory 400 is completed. Is possible. Since writing data to the flash memory 400 requires time for writing data to the DRAM or SRAM, such a request reception notification is effective for improving the processing efficiency of the first processing node 100. . In process 606, when the received data write request is an update of data already stored in the flash memory 400, the processor 310 reads data already stored from the flash memory 400. In process 607, data is read from the flash memory 400. In process 608, the write data stored in the memory 330 and the data read from the flash memory 400 are merged to create data to be written to the flash memory 400. In process 609, the processor 310 writes data to the flash memory 400. In process 610, the processor 310 confirms whether or not the writing to the flash memory 400 has been normally completed. In process 611, the flash memory 400 notifies the processor 310 of the contents of the status register 450 in response to the completion confirmation. In the example shown in FIG. 10, a normal end notification indicating that data writing has ended normally is sent to the processor 310, and the processor 310 ends the write process.

In process 612, the second operation processing node 200 transmits a read request designating the same logical address L # 00xx as the one requested by the first operation processing node 100 in step 601 to the memory controller 300. . In process 613, the NIC 350 transfers the read request to the processor 310. The processor 310 suspends the processing for the read request received from the second arithmetic processing node 200 until the processing for the write request received from the first arithmetic processing node 100 is completed. After the process for the write request is completed, the processor 310 performs a read process on the flash memory 400 in process 614. In process 615, the processor 310 receives data from the flash memory 400. In processes 616 and 617, the processor 310 transmits data to the second arithmetic processing node 200 via the NIC 350.

FIG. 10 shows processing when data has already been written to the physical address corresponding to the logical address L # 00xx. However, when data is not written to the physical address corresponding to the logical address L # 00xx, the processing 606 and processing 607 are not performed, and the write data is directly written to the corresponding physical address. FIG. 10 shows an example in which a read request is received from the second arithmetic processing node 200 during the processing for the write request received from the first arithmetic processing node 100. However, the read request from the second arithmetic processing node 200 may be received by the memory controller 300 after the processing for the write request received from the first arithmetic processing node 100 is completed.

FIG. 11 is a diagram showing another example of the flow of processing among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400. The processes having the same contents as those shown in FIG. 10 are denoted by the same reference numerals, and the description thereof is omitted.

FIG. 11 illustrates a case where a write error has occurred in writing data to the flash memory 400. In the process 700, the flash memory 400 notifies the processor 310 of an abnormal end notification. Here, the processor 310 may perform a rewrite process. The rewrite process is a process for writing the same data into the flash memory 400 again when the writing is not normally completed. Details of the rewriting process will be described later. If the writing does not end normally even after performing the rewriting process, the processor 310 receives an abnormal end notification from the flash memory 400 again.

Upon receiving the abnormal termination notification from the flash memory 400, the processor 310 notifies the first arithmetic processing node 100 that is the source of the write request via the NIC 350 in processing 701 and processing 702. When the processor 310 receives an abnormal end notification from the flash memory 400, the processor 310 generates a write error flag by setting the L-Error value of the logical address management table 331 to "1". In processing 703 and processing 704, the processor 310 notifies a request non-acceptance notification to the read request received from the second arithmetic processing node 200 via the NIC 350. Data is not read in response to a read request received from the second arithmetic processing node 200. Thereby, it is possible to prevent erroneous data from being transmitted to the second arithmetic processing node 200.

Here, the rewriting process performed by the processor 310 will be described. The rewrite process is performed before a write error notification is issued in response to a request from the first arithmetic processing node 100 when the writing is not normally completed. When performing the rewrite process, the processor 310 sets the P-Error value of the physical address that has been written first to “1” and stores it in the physical address management table 332. Then, the processor 310 searches the physical address management table 332 for a page whose P-Valid is “0”, that is, a page in which no data is written. Data is similarly written to the retrieved new page. If data is normally written by the rewrite process, the logical address management table 331 is rewritten so that the physical address of the new page corresponds to the logical address. In this case, the L-Error value of the logical address is “0” indicating that the writing has been performed normally, and no write error notification is issued. The rewrite process may limit the number of times rewrite is performed. For example, if the rewrite count limit is set to two, if data is not normally written to the flash memory 400 even after two rewrites, the rewrite process is terminated. The L-Error value of the logical address is “1” indicating that writing has not been performed normally. Note that the rewrite process by the processor 310 is not essential in this embodiment, and a write error notification may be transmitted to the first arithmetic processing node 100 in response to the failure of the first write.

FIG. 12 is a diagram illustrating a processing flow of the processor 310 when a data write request is received in the embodiment. The process of FIG. 12 is started by process 1100. In processing 1101, the lock control unit 312 locks the accessed logical address. When another request is made to the corresponding logical address in the locked state, the other request is temporarily stored in the memory 330, for example. In processing 1102, the table management unit 311 accesses the logical address management table 331 stored in the memory 330. In processing 1103, the table management unit 311 determines whether or not the value of L-Error described in the logical address management table 331 is “0”. When it is determined in process 1103 that the value of L-Error is not “0”, in process 1115, the notification unit 313 sends a request non-acceptance notification to the operation processing node that issued the data write request. If it is determined in process 1103 that the L-Error value is “0”, the table management unit 311 in process 1104 indicates that the L-Valid value described in the logical address management table 331 is “0”. It is determined whether or not. If it is determined in process 1104 that the value of L-Valid is “0”, the process proceeds to process 1108. If it is determined in process 1104 that the value of L-Valid is not “0”, the table management unit 311 extracts a physical address corresponding to the logical address based on the logical address management table 331 in process 1105. In processing 1106, the data reading unit 315 reads the data written in the extracted physical address. In process 1107, the memory control unit 314 merges the read data and the write data stored in the memory 330 to create update write data. In processing 1108, the table management unit 311 accesses the physical address management table 332 stored in the memory 330 and selects a physical address for writing data. In processing 1109, the data writing unit 316 writes the write data or the update write data to the selected physical address. In processing 1110, the confirmation unit 317 accesses the status register 450 of the flash memory 400 and determines whether or not the data writing is successful. If it is determined in the process 1110 that the data writing has succeeded, the table management unit 311 records “0” in the L-Error of the logical address management table 331 in the process 1111. If it is determined in process 1110 that data writing has failed, in process 1112, the rewrite unit 318 determines whether or not the number of rewrites exceeds the set value. If it is determined in process 1112 that the rewrite count does not exceed the set value, the process returns to process 1108. If it is determined in process 1112 that the number of rewrites exceeds the set value, the table management unit 311 records “1” in L-Error of the logical address management table 331 in process 1113. In processing 1114, the notification unit 313 notifies the write request issuer of a write error notification. In process 1116, the lock control unit 312 releases the lock for the other request, and the process 1117 ends.

FIG. 13 is a diagram illustrating a processing flow of the processor 310 when a data read request is received in the embodiment. The process of FIG. 13 is started by process 1200. In processing 1201, the table management unit 311 accesses the logical address management table 331 stored in the memory 330. In processing 1202, the table management unit 311 determines whether or not the value of L-Error described in the logical address management table 331 is “0”. When it is determined in process 1202 that the value of L-Error is not “0”, in process 1206, the notification unit 313 issues a request rejection notification to the issuer of the data read request.

If it is determined in process 1202 that the value of L-Error is “0”, the table management unit 311 in process 1203 uses the physical address corresponding to the logical address included in the read request based on the logical address management table 331. To extract. In processing 1204, the data reading unit 315 reads data from the corresponding physical address. In process 1205, the data transmission unit 319 transmits the read data to the issuer of the read request, and ends the process 1207.

As described above, in this embodiment, when the writing is not normally performed in the processing of the write request received from the first arithmetic processing node 100, the L-Error value “1” that is the write error flag is set to the logical value. Stored in association with the address. As a result, when a read request is made for the same logical address, the memory controller 300 can recognize that an error exists in the data specified by the logical address. In addition, the memory controller 300 notifies the fact that there is an error in the data without causing the read request issuer to read and transmit the incorrect data, thereby suppressing malfunction of the information processing apparatus 1. .

Here, as shown in processing 1115 of FIG. 12, when the value of L-Error is “1”, a request rejection notification is notified in response to a data write request, and data writing is not performed. Explain the significance. For example, it is assumed that the first arithmetic processing node 100 requests the memory controller 300 to write data and the data writing fails. In this case, the memory controller 300 transmits a write error notification to the first arithmetic processing node 100. Upon receiving the write error notification, the first arithmetic processing node 100 can take various measures. For example, the memory controller 300 may be requested again to write the same data as the recovery process. Here, it is assumed that a data write request, that is, a data update request is made by designating the same logical address from the second arithmetic processing node 200 before this request is made again. It is assumed that the memory controller 300 receives a write request from the second arithmetic processing node 200, writes data, and succeeds in writing. In this case, the data in the flash memory 400 is correctly updated by a write request from the second arithmetic processing node 200. However, after that, when data is written in response to a request from the first arithmetic processing node 100 again, the old data is written back. In order to prevent such a problem, in the present embodiment, the memory controller 300 sends a request non-acceptance notification without responding to the request not only when the received request is a read request but also when it is a write request. To notify.

<Second embodiment>
The second embodiment is based on the contents of the first embodiment, and further adds processing when a re-request for writing is made by the first arithmetic processing node 100.

The first arithmetic processing node 100 that has received the write error notification from the memory controller 300 can perform a rewrite request for writing the same data into the memory 400 as error state recovery processing. Specifically, the recovery processing unit 113 illustrated in FIG. 5 instructs the request issuing unit 111 to issue a write request again. The request issuing unit 111 issues a write rerequest along the predetermined description format shown in FIG. Processing of the memory controller 300 in response to this write re-request will be described with reference to FIGS.

FIG. 14 is a diagram showing an example of a logical address management table in the second embodiment. A request issuer ID is recorded in addition to the contents of the logical address management table shown in FIG. The request issuer ID is an ID that identifies the issuer of the write request that the memory controller 300 has received most recently. As shown in FIG. 6, this request issuer ID is included as information in the write request sent from the processing node. The memory controller 300 that has received the previous write request stores the request issuer ID included in the write request and the logical address in the logical address management table 331 in association with each other.

FIG. 15 is a diagram illustrating another example of the flow of processing among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400 in the second embodiment. The same processes as those in FIGS. 10 and 11 are denoted by the same reference numerals, and description thereof is omitted.

In process 702, the first arithmetic processing node 100 receives a write error notification from the memory controller 300. In process 801, the first arithmetic processing node 100 issues a write re-request. In process 802, the first arithmetic processing node 100 transmits write data to the memory controller 300. In process 803, the NIC 350 transfers the write rerequest to the processor 310. In step 804, the NIC 350 transfers the write data to the memory 330 and stores it. In process 805, the NIC 350 sends a request receipt notification to the first processing node 100 that is the issuer of the write request. On the other hand, the processor 310 confirms that the issuer ID of the write rerequest is the same as the issuer ID of the previously written request, and performs processing for the write rerequest. Specifically, the processor 310 reads data from the flash memory 400 in processing 806 and processing 807, writes data to the flash memory 400 in processing 808 and processing 809, and confirms completion of processing in the flash memory 400 in processing 810. In step 811, a normal end notification is received from the flash memory 400. Note that if the writing cannot be performed normally even if writing is performed in response to the re-request for writing, the memory controller 300 receives an abnormal end notification in step 811 instead of the normal end notification.

In the first embodiment, when the L-Error value is “1”, the memory controller 300 that has received the write request notifies a request acceptance notice to the issuer of the write request without responding to the write request. Therefore, even if the first arithmetic processing node 100 that has received the write error notification makes a re-request for writing as a recovery process, the memory controller 300 does not accept the re-request and the re-write process is not performed. On the other hand, in the second embodiment, the memory controller 300 stores the request issuer ID in the logical address management table 331 when there is a write request. After that, the memory controller 300 that has received the write request, even if the L-Error value is “1”, the issuer ID stored in the logical address management table 331 matches the issuer ID of the write request. Exceptionally accepts write requests. Thereby, the first arithmetic processing node 100 can perform rewriting as the recovery processing.

FIG. 16 is a diagram showing a processing flow of the processor 310 when a data write request is received in the second embodiment. The same processing contents as those shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In processing 1103, if the table management unit 311 determines that the value of L-Error is not “0”, the processing proceeds to processing 1301. In processing 1301, the table management unit 311 determines whether the request issuer ID included in the write request matches the request issuer ID stored in the logical address management table 331. If it is determined in process 1301 that both request issuer IDs match, the process proceeds to process 1104, where write processing is performed. If it is determined in process 1301 that the two request issuer IDs do not match, the notification unit 313 issues a request rejection notice to the issuer of the write request in process 1115.

<Third embodiment>
Similar to the second embodiment, the third embodiment is based on the contents of the first embodiment and includes a rewrite process by the first arithmetic processing node 100. In the second embodiment, the request issuer ID is used to identify that the request received by the memory controller 300 is a write re-request by the processing node that has received the write error notification. In the third embodiment, the request ID is used to identify that the write request received by the memory controller 300 is a write re-request by the processing node that has received the write error notification.

FIG. 17 shows an example of a logical address management table in the third embodiment. A request ID is recorded in addition to the contents of the logical address management table shown in FIG. The request ID is an ID indicating the identity of the content of the latest write request received by the memory controller 300. As shown in FIG. 6, this request ID is included as information in the write request sent from the arithmetic processing node. The memory controller 300 that has received the previous write request stores the request ID and logical address included in the write request in association with each other in the logical address management table. When the first arithmetic processing node 100 makes a write request for the recovery process again, the recovery processing unit 114 shown in FIG. 5 receives the write request with the same request ID as the request ID attached to the previous write request. The reissue is instructed to the request issuing unit 111. The request issuing unit 111 transmits a write rerequest to the memory controller. The memory controller 300 that has received the write re-request confirms the logical address management table 331. Even if the value of L-Error is “1”, if the request ID attached to the write re-request matches the request ID stored in the logical address management table 331, the memory controller 300 writes Accept the request. Thereby, the first arithmetic processing node 100 can perform rewriting as the recovery processing.

FIG. 18 is a diagram showing a processing flow of the processor 310 in the third embodiment. Components having the same processing contents as the processing flow of the processor 310 shown in FIGS. 12 and 16 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

If the table management unit 311 determines in the processing 1103 that the value of L-Error is not “0”, the processing proceeds to a processing 1401. In process 1401, the table management unit 311 determines whether or not the request ID included in the write request matches the request ID stored in the logical address management table 331. If it is determined in process 1401 that both request IDs match, the process proceeds to process 1104, and a write process is performed. If it is determined in process 1401 that the request IDs do not match, the notification unit 313 issues a request non-acceptance notification to the issuer of the write request in process 1115.

<Fourth embodiment>
The fourth embodiment is based on the contents of the second embodiment or the third embodiment, and the processing of the memory controller 300 when data is normally written in the memory 400 by rewriting by the first processing node 100. It discloses about.

For example, in the second embodiment, the second operation processing node 200 that has received the request non-acceptance notification in the process 704 cannot receive the desired data, and the process stagnates. Further, the second arithmetic processing node 200 does not have a means for recognizing whether or not the write error state has been eliminated by the re-request for writing by the first arithmetic processing node 100. Therefore, it is not possible to recognize when the read request should be attempted again. Therefore, in the fourth embodiment, when the writing to the write re-request of the first arithmetic processing node 100 is normally completed, the recovery is a notification that the data has been normally written to the second arithmetic processing node 200. Notification of completion will be sent. By this notification, the second arithmetic processing node 200 can recognize that it is possible to make a read re-request for the read request that has received the request non-acceptance notification, and can read desired data from the memory 400. It becomes possible.

FIG. 19 shows an example of a logical address management table in the fourth embodiment. In addition to the contents of the logical address management table shown in FIG. 14, the read request performance of each arithmetic processing node included in the information processing apparatus 1 is recorded. The read request record records that each arithmetic processing node makes a read request for the logical address in a state where the L-Error value of the specific logical address is “1”. In other words, it means that the arithmetic processing node whose read request record is recorded in the logical address management table 331 has received a request non-acceptance notification for the read request in the past. In FIG. 19, it is recorded that the second arithmetic processing node 200 makes a read request to the logical address L # 0001.

FIG. 20 is a diagram illustrating another example of the processing flow among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400 in the fourth embodiment. The same processes as those in FIGS. 10, 11 and 15 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In step 803, the processor 310 that has received a re-write request from the first arithmetic processing node 100 performs a write process on the flash memory 400 in steps 806 to 809. Further, the processor 310 confirms completion of the flash memory 400 in process 810 and receives a normal end notification from the flash memory 400 in process 811. Thereafter, the processor 310 notifies the second arithmetic processing node 200 via the NIC 350 of a recovery completion notification indicating that the data in the flash memory 400 has become normal in processing 901 and processing 902.

FIG. 21 is a diagram showing a processing flow of the processor 310 of the memory controller 300 that has received a read request in the fourth embodiment. Components having the same processing contents as the processing flow of the processor 310 shown in FIG. 13 are given the same reference numerals, and description thereof will be omitted as appropriate.

If the table management unit 311 determines in the processing 1202 that the value of the L-Error is “0”, the processing proceeds to a processing 1203 and a reading process is performed. If the table management unit 311 determines in step 1202 that the value of L-Error is not “0”, the process proceeds to step 1501. In processing 1501, the table management unit 311 records “1” in the read request record of the logical address management table. In step 1206, the notification unit 313 issues a request rejection notification to the data read request issuer.

FIG. 22 is a diagram showing a processing flow of the processor 310 that has received a write request in the fourth embodiment. Components having the same processing contents as the processing flow of the processor 310 shown in FIGS. 12, 16, and 18 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In step 1111, the table management unit 311 records “0” in the L-Error value of the logical address management table 331, and then in step 1601, the table management unit 311 determines whether there is a read request record in the logical address management table 311. . If it is determined in process 1601 that there is no record of the read request, the process proceeds to process 1116. When it is determined in the process 1601 that there is a record of the read request, the notification unit 313 notifies the recovery processing completion notification to the arithmetic processing node that has made the read request in the process 1602. With this notification, for example, in FIG. 20, the second processing node 200 that has received the request rejection notification for the read request can recognize that the data has been correctly stored in the flash memory 400. The second arithmetic processing node 200 can perform processing such as re-requesting reading as necessary.

In the processing 1301 of FIG. 22, the table management unit 311 determines whether the request issuer ID matches, but as a modification, the table management unit 311 determines whether the request ID matches as in the processing 1401 of FIG. May be.

As described above, according to the technology disclosed in this specification, by providing a flag indicating that writing to the memory is not normally performed in association with a logical address, there is an error in data with a specific logical address. It can be recorded as a record. This can prevent the arithmetic processing node from reading erroneous data. In addition, it is possible to suppress information processing based on the read erroneous data. Further, by storing the request issuer ID or the request ID in the logical address management table, the arithmetic processing node that has received the write error notification can make a write re-request. Further, by storing the presence / absence of the read request record in the logical address management table, it is possible to notify the arithmetic processing node that has not received the read request that the writing has been normally performed.

In the present disclosure, the memory whose writing and reading are controlled by the memory controller 300 is not limited to the flash memory. A management table that describes the correspondence between logical addresses and physical addresses or a memory that can be controlled for writing and reading based on information having the same contents as the management table is applicable to the present invention.

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 100 1st arithmetic processing node 200 2nd arithmetic processing node 300 Memory controller 400 Flash memory 500

Bus

110, 210, 310

Processor

130, 230, 330 Memory 150, 250, 350 NIC
DESCRIPTION OF SYMBOLS 111 Request issuing part 112 Transmission / reception part 113 Recovery processing part 114 Memory control part 311 Table management part 312 Lock control part 313 Notification part 314 Memory control part 315 Data reading part 316 Data writing part 317 Confirmation part 318 Rewriting part 319 Data transmission part 331 Logical address management table 332 Physical address management table 410 Memory cell array 420 Write / read circuit 430 Write buffer 440 Comparator 450 Status register 460 Error correction circuit

Claims

A first computing node requesting a memory controller to write data to a memory with a first logical address; and
The memory controller writing the data to the first physical address of the memory;
The memory controller includes a step of generating a first flag indicating that the data has not been written normally and storing the first flag in association with the first logical address.
The memory controller receiving a request to read the data designating the first logical address from a second processing node;
The memory controller recognizing the first flag associated with a first logical address;
The memory controller not reading the data and notifying the second operation processing node of a first notification indicating that the data writing has not been normally performed;
The information processing method according to claim 1, further comprising:
The memory controller notifying the first arithmetic processing node of a second notification indicating that the data writing has not been normally performed;
After the first notification is made to the second operation processing node, the first operation processing node rewrites the data to the memory;
The memory controller erasing the first flag when the data is normally written to the memory by the rewriting; and
The memory controller notifying the second operation processing node of a third notification indicating that the data has been normally written;
The information processing method according to claim 2, further comprising:
The information processing method according to any one of claims 1 to 3, wherein the memory is a flash memory.
The said memory controller produces | generates the 2nd flag which shows that there is a device defect in the said 1st physical address, when the writing of the said data is not performed normally. Information processing method according to item.
When the data writing is not normally performed, the data is written to the second physical address of the memory, and when the data is normally written to the second physical address, the second physical address is written. 6. The information processing method according to claim 1, wherein a logical address management table indicating that one logical address corresponds to the second physical address is created.
Memory,
A first operation processing node that makes a write request to the memory for data with a first logical address;
The write request is received, the data is written to the first physical address of the memory, a first flag is generated indicating that the data was not normally written, and the first flag is An information processing apparatus comprising: a memory controller that stores the first logical address in association with the first logical address.
The memory controller receives a read request designating the first logical address from a second arithmetic processing node, recognizes the first flag associated with the first logical address, and does not perform a read process for the read request. The information processing apparatus according to claim 7, further comprising: notifying the second arithmetic processing node of a first notification indicating that the data writing has not been normally performed.
The memory controller notifies the first arithmetic processing node of a second notification indicating that the writing of the data has not been normally performed;
When the data is normally written to the memory by rewriting the data by the first arithmetic processing node, the memory controller erases the first flag, and the first data is normally written. The information processing apparatus according to claim 8, wherein a third notification indicating that the second arithmetic processing node is notified.
The information processing apparatus according to any one of claims 7 to 9, wherein the memory is a flash memory.
11. The information processing apparatus according to claim 7, wherein the memory controller generates a second flag indicating that there is a device failure in the first physical address.
After the writing of the data to the first physical address fails, the memory controller writes the first data to the second physical address of the memory, and the writing to the second physical address is performed normally. The information processing apparatus according to any one of claims 7 to 11, wherein if an error occurs, a logical address management table indicating that the first logical address corresponds to the second physical address is created.
A memory controller for processing a data write request to a first memory received from a first arithmetic processing node,
The memory controller is
A processor and a second memory;
The processor receives a request from the first arithmetic processing node to write data with a first logical address to the first memory, and writes the data to the first physical address of the first memory. And a first flag indicating that the data writing has not been normally performed is stored in the second memory in association with the first logical address.
When the processor receives a read request designating the first logical address from a second arithmetic processing node, the processor reads the first flag from the second memory, and performs the read process for the read request without performing the read process. 14. The memory controller according to claim 13, wherein a first notification indicating that data has not been normally written is notified to the second arithmetic processing node.
The processor notifies the first operation processing node of a second notification indicating that the data writing has not been performed normally, and the data is rewritten by the first operation processing node. When the data is normally written to the first memory, the processor erases the first flag and notifies the second arithmetic processing node of a third notification indicating that the data has been normally written. The memory controller according to claim 14.
16. The memory controller according to claim 13, wherein the first memory is a flash memory.
The memory controller according to any one of claims 13 to 16, wherein the processor generates a second flag indicating that the first physical address has a device failure.
After the writing of the data to the first physical address fails, the processor writes the data to the second physical address of the first memory, and the writing to the second physical address is normally performed. The memory controller according to any one of claims 13 to 17, wherein if it is performed, a conversion table is generated to indicate that the first logical address corresponds to the second physical address.
A memory in which write control is performed by a memory controller that receives a data write request with a first logical address from a first arithmetic processing node,
The memory is
A storage element;
A status register for storing that the data has not been normally written to the storage element, and the status register is a first register indicating that the data has not been normally written to the memory controller. A memory that stores a flag in association with the first logical address.
The memory of claim 19, wherein the memory is a flash memory.