WO2015040658A1 - Procédé de traitement d'informations, dispositif de traitement d'informations, contrôleur de mémoire et mémoire - Google Patents

Procédé de traitement d'informations, dispositif de traitement d'informations, contrôleur de mémoire et mémoire Download PDF

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WO2015040658A1
WO2015040658A1 PCT/JP2013/005598 JP2013005598W WO2015040658A1 WO 2015040658 A1 WO2015040658 A1 WO 2015040658A1 JP 2013005598 W JP2013005598 W JP 2013005598W WO 2015040658 A1 WO2015040658 A1 WO 2015040658A1
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data
memory
logical address
processing node
memory controller
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PCT/JP2013/005598
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English (en)
Japanese (ja)
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早坂　和美
雅紀 日下田
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富士通株式会社
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Priority to JP2015537435A priority Critical patent/JP6075456B2/ja
Priority to PCT/JP2013/005598 priority patent/WO2015040658A1/fr
Publication of WO2015040658A1 publication Critical patent/WO2015040658A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance

Definitions

  • the present disclosure relates to an information processing method, an information processing device memory controller, and a memory.
  • the information processing apparatus includes an arithmetic processing node that performs data processing, and a memory that is connected to the arithmetic processing node via a bus and stores data.
  • the arithmetic processing node reads out data stored in the memory and performs necessary arithmetic processing.
  • the arithmetic processing node stores data obtained as a result of the arithmetic processing in the memory.
  • An information processing apparatus may have a plurality of arithmetic processing nodes.
  • the first arithmetic processing node of the plurality of arithmetic processing nodes stores data in a specific area of the memory
  • another second arithmetic processing node of the plurality of arithmetic processing nodes is the data stored by the first arithmetic processing node. May be read from the memory for processing.
  • a flash memory which is a kind of nonvolatile memory is known.
  • the flash memory stores data by holding the charge injected into the charge storage film. Even if the arithmetic processing node makes a write request to the memory and performs a data write process to the memory, the data may not be correctly written to the memory. For example, when the memory is the above flash memory, a write error such as the amount of charge injected into the charge storage film does not reach a predetermined amount may occur. When a data write error occurs, erroneous data is stored in the memory.
  • the arithmetic processing node When data writing to the memory fails, if the arithmetic processing node makes a read request for the data written to the memory thereafter, erroneous data stored in the memory will be read. If processing based on the read erroneous data is performed at the arithmetic processing node, it may cause a malfunction of the information processing apparatus. If the information processing apparatus has a plurality of operation processing nodes, the first operation processing node itself writes the data after the first operation processing node of the plurality of operation processing nodes writes the data. This can occur in both cases where data is read and when a second arithmetic processing node different from the first arithmetic processing node reads data.
  • the technique disclosed in the present application is intended to provide a method capable of suppressing erroneous data reading and malfunctioning of an information processing apparatus based on erroneous data even when data writing to a memory fails.
  • FIG. 1 is a hardware configuration diagram of an information processing apparatus 1 in the embodiment.
  • the information processing apparatus 1 includes a first arithmetic processing node 100, a second arithmetic processing node 200, a memory controller 300, a flash memory 400, and a bus 500.
  • the first processing node 100 includes a processor 110, a memory 130, and a network interface card (hereinafter, NIC) 150.
  • the processor 110 and the memory 130 are connected to each other, and the processor 110 can access the memory 130.
  • the second arithmetic processing node 200 includes a processor 210, a memory 230, and a NIC 250.
  • the processor 210 and the memory 230 are connected to each other, and the processor 210 can access the memory 230.
  • the memory controller 300 includes a processor 310, a memory 330, and a NIC 350.
  • the processor 310 and the memory 330 are connected to each other, and the processor 310 can access the memory 330.
  • the processors 110, 210, and 310 are, for example, CPU chips, and the memories 130, 230, and 330 are, for example, DRAM chips.
  • the first arithmetic processing node 100, the second arithmetic processing node 200, and the memory controller 300 are connected to each other by a bus 500.
  • the flash memory 400 is connected to the bus 500 via the memory controller 300.
  • the first arithmetic processing node 100 and the second arithmetic processing node 200 can write data to the flash memory 400 via the memory controller 300.
  • the first arithmetic processing node 100 and the second arithmetic processing node 200 can read data from the flash memory 400 via the memory controller 300.
  • the second arithmetic processing node 200 can read out the data written in the flash memory 400 by the first arithmetic processing node 100 and perform arithmetic processing.
  • the present embodiment shows an information processing apparatus 1 including two arithmetic processing nodes, a first arithmetic processing node 100 and a second arithmetic processing node 200, as arithmetic processing nodes that can access the flash memory 400 via the memory controller 300. It was. However, the number of arithmetic processing nodes included in the information processing apparatus 1 is not limited to this, and the information processing apparatus 1 only needs to include at least one arithmetic processing node.
  • FIG. 2 is a diagram for explaining a unit of an area where writing, reading, and erasing can be performed in the flash memory 400 in the embodiment.
  • the flash memory 400 writes and reads data in units called pages including a plurality of storage elements.
  • the flash memory 400 erases data in units called blocks including a plurality of pages. 2, each of P # 0000, P # 0001,... P # 00MN corresponds to one page. Also, P # 0000 to P # 000N constitute one block.
  • the first arithmetic processing node 100 writes data X to the flash memory 400
  • the first processing node 100 makes a write request to the memory controller 300 and transmits write data X.
  • the first arithmetic processing node 100 attaches an identifier that can be recognized by the first arithmetic processing node 100 and the second arithmetic processing node 200 to the data.
  • This identifier is called a logical address.
  • the logical address is described as L # 00xx.
  • the memory controller 300 stores the received data X in any page of the flash memory 400.
  • the first arithmetic processing node 100 or the second arithmetic processing node 200 accesses the flash memory 400 in order to read the data X.
  • the first arithmetic processing node 100 or the second arithmetic processing node 200 designates the logical address L # 00xx used for storing and makes a read request.
  • L # 00xx used for storing and makes a read request.
  • a table that records which physical address a logical address corresponds to is called a logical address management table.
  • FIG. 3A is a diagram illustrating an example of a logical address management table in the embodiment.
  • the logical address management table shown in FIG. 3A includes a logical address, a physical address corresponding to the logical address, an L-Valid value, and an L-Error value.
  • the L-Valid value is a flag indicating whether data with a logical address is stored in the corresponding physical address.
  • the L-Valid value “1” corresponding to the logical address L # 0003 indicates that the data with the logical address L # 0003 is stored in the page of the corresponding physical address P # 0001.
  • the L-Valid value corresponding to the logical address L # 0000 is “0”. In this case, the data with the logical address L # 0000 is not stored in the page of the physical address P # 0011.
  • the L-Error value is a flag indicating whether or not the data with the logical address is correctly written in the flash memory 400. In the example shown in FIG. 3A, if the L-Error value is “0”, it means that the data specified by the logical address is correctly stored in the flash memory 400. On the other hand, if the L-Error value is “1”, it means that the data specified by the logical address is not correctly stored in the flash memory 400, that is, the written data includes an error.
  • FIG. 3B is a diagram illustrating an example of a physical address management table in the embodiment.
  • the physical address management table shown in FIG. 3B includes a physical address, a P-Valid value, and a P-Error value.
  • the P-Valid value is a flag indicating whether any data is written in the page of the corresponding physical address. For example, “0” that is the P-Valid value corresponding to the page of the physical address P # 0011 means that data is not written in the page of the physical address P # 0011. Further, “1” which is a P-Valid value corresponding to the page of the physical address P # 0001 means that some data is written to the page of the physical address P # 0001.
  • the P-Error value is a flag indicating that some device failure has occurred in the storage element of the corresponding physical address page.
  • the device failure of the memory element is, for example, a case where the charge retention capability of the charge retention film of the flash memory 400 is deteriorated.
  • “1” which is the value of P-Error corresponding to the page of the physical address P # 0014 indicates that there is some trouble in at least a part of the storage element included in the page of the physical address P # 0014. It means that there is.
  • the P-Error value is an identifier associated with a physical address, and indicates that some trouble has occurred in the storage element of the corresponding physical address page, and data cannot be correctly written to the page of the physical address. It is.
  • the L-Error value is an identifier associated with the logical address, and indicates that the data with the corresponding logical address was not correctly written.
  • the correspondence between the logical address and the physical address is not constant, and can be changed by, for example, garbage collection described later.
  • the P-Error value associated with the physical address cannot continuously record that the data with a certain logical address was not correctly written.
  • the L-Error value is an identifier assigned corresponding to the logical address. Therefore, even if the correspondence relationship between the logical address and the physical address is changed, it can be continuously recorded that the writing of data with a certain logical address was not performed correctly.
  • L-Error is also called a write error flag.
  • the logical address management table and the physical address management table have the contents shown in FIGS. 3A and 3B, respectively, at the time of receiving the data write request.
  • the first arithmetic processing node 100 makes a write request for data A with the logical address L # 0000.
  • the L-Valid value of the logical address L # 0000 is “0”, it can be seen that the current write is not a data update but a new data write. .
  • the logical address L # 0000 is associated with the physical address P # 0011.
  • the P-Valid value of the physical address P # 0011 is “0”. That is, it can be seen that no data is written in the page of the physical address P # 0011 associated with the logical address L # 0000. In this case, data A is written in the page of physical address P # 0011. Then, “1” is written in the L-Valid field corresponding to the logical address L # 0000. Further, “1” is written in the P-Valid field corresponding to the physical address P # 0011.
  • the first arithmetic processing node 100 makes a write request for data B to which a logical address L # 0002 is attached.
  • the logical address management table of FIG. 3A since the L-Valid value of the logical address L # 0002 is “0”, it can be seen that the current write is not a data update but a new data write. . It can also be seen that the logical address L # 0002 is associated with the physical address P # 0006. According to the physical address management table of FIG. 3B, since the P-Valid value of the physical address P # 0006 is “1”, some data has already been written to the page of the physical address P # 0006.
  • the first arithmetic processing node 100 makes a write request for data C with the logical address L # 0003.
  • the L-Valid value of the logical address L # 0003 is “1”
  • the current write is not a new data write but a data update.
  • the logical address L # 0003 is associated with the physical address P # 0001.
  • the data stored at the physical address P # 0001 is read and merged with the data C, and the merged data is written to another page.
  • the merged data is written in the page of the physical address P # 0011.
  • the physical address corresponding to the logical address L # 0003 is rewritten from P # 0001 to P # 0011.
  • the P-Valid value corresponding to the physical address P # 0011 is rewritten to “1”.
  • the physical address P # 0001 in which the pre-update data is stored is not associated with the logical address L # 0003 while retaining the pre-update data, and the first calculation process is performed. The page cannot be accessed from the node 100 or the second arithmetic processing node 200. This means that the memory area that can actually be used is reduced.
  • Garbage collection is a writable area in which a page in which valid data is written in a block to be erased is moved to another block, and the block to be erased is erased without including a page in which valid data is written. It means the work to increase.
  • the first arithmetic processing node 100 makes a write request for data D with the logical address L # 0001
  • the logical address management table of FIG. 3A since the L-Valid value of the logical address L # 0001 is “0”, it can be seen that the current write is not a data update but a new data write. . It can also be seen that the logical address L # 0001 is associated with the physical address P # 0023. According to the physical address management table of FIG. 3B, the P-Valid value of the physical address P # 0023 is “0”. That is, it can be seen that no data is written to the physical address P # 0023 associated with the logical address L # 0001. In this case, data D is written at physical address P # 0023. At this time, it is assumed that the data writing is not normally performed and the data D is not correctly written to the page of the physical address P # 0023. In this case, the following operations are performed.
  • the P-Valid value is set to “1” to indicate that this page is not in the erased state.
  • the P-Error value is set to “1” to indicate that there is a possibility that there is any device failure in the physical address P # 0023.
  • the L-Valid value is set to “1”.
  • the L-Error value is set to “1”.
  • FIG. 5 is a functional block diagram of the processor 110 included in the first arithmetic processing node 100 in the embodiment.
  • the processor 110 implements the function of each block shown in FIG. 5 by executing processing based on a predetermined program stored in the memory 130, the flash memory 400, or the memory of another arithmetic processing node.
  • the processor 110 transmits / receives data and / or various notifications to / from the request issuing unit 111 that issues an access request to the flash memory 400 to the memory controller 300, the memory controller 300, and the second processing node 200. It functions as a transmission / reception unit 112, a recovery processing unit 113 that performs recovery processing when data writing to the flash memory 400 fails, and a memory control unit 114 that controls the memory 130.
  • the processor 210 included in the second processing node 200 realizes the same function as the processor 110 by executing processing based on a predetermined program stored in the memory 230, the flash memory 400, or the memory of another processing node. .
  • FIG. 6 is a diagram illustrating an example of a description format of a request issued from the first arithmetic processing node 100 or the second arithmetic processing node 200 in the present embodiment.
  • the request description format includes a “request issuer ID” indicating the request issuer, a “request ID” for identifying the request identity, a “command” indicating the request content, and a “node” indicating the request destination. “Address” and “logical address” for designating the logical address of the data are included.
  • FIG. 7 is a diagram illustrating information included in the memory 330 included in the memory controller 300 according to the embodiment.
  • the memory 330 stores a logical address management table 331 and a physical address management table 332.
  • the memory 330 is also used as a data buffer for temporarily storing data written to the flash memory 400.
  • FIG. 8 is a functional block diagram of the processor 310 included in the memory controller 300 in the embodiment.
  • the processor 310 implements the function of each block illustrated in FIG. 8 by executing processing based on a predetermined program stored in the memory 330, the flash memory 400, or the memory of another arithmetic processing node.
  • the processor 310 includes a table management unit 311 that decodes and changes the logical address management table 331 and the physical address management table 332, and a lock control unit that restricts access to other requests while the memory controller 300 is processing the request.
  • a notification unit 313 that performs various notifications to the first arithmetic processing node 100 and the second arithmetic processing node 200
  • a memory control unit 314 that controls the memory 330
  • a data reading unit 315 that reads data from the flash memory 400
  • a flash A data writing unit 316 that writes data to the memory 400
  • a confirmation unit 317 that confirms whether writing to the flash memory 400 has been completed correctly
  • a rewriting unit 318 that performs rewriting control to the flash memory 400
  • data transmission As the data transmission unit 319
  • Some functions may be realized by a processor other than the processor 310 or a dedicated integrated circuit.
  • FIG. 9 is a circuit block diagram of the flash memory 400 in the embodiment.
  • the flash memory 400 includes a memory cell array 410 in which storage elements are arranged, a write / read circuit 420 that writes data to and reads data from the storage elements included in the memory cell array 410, and a write buffer 430 that stores write data. And a comparator 440 and a status register 450.
  • the flash memory 400 may include an error correction circuit 460, although not essential. When an error correction circuit is used in this embodiment, the error correction circuit may be mounted on the flash memory 400 or the memory controller 300.
  • the write data is first held in the write buffer 430. Then, the write / read circuit 420 performs a write process on the storage elements in the memory cell array 410 based on the data in the write buffer 430. Thereafter, the comparator 440 compares the data written in the storage element with the data held in the write buffer 430. As a result of the comparison by the comparator 440, when both data match, information indicating that the writing has been normally performed is recorded in the status register 450. If the data written in the storage element and the data held in the write buffer 430 do not match, information indicating that the writing has not been normally performed is recorded in the status register 450.
  • the error correction additional bits are written into the memory cell array 410 together with the write data. Even if there is an error in the written data, the error-corrected data is read if the error can be corrected using the additional bit for error correction. In the present embodiment, even when there is an error in the write data, if the error can be corrected by the error correction circuit 460, information indicating that the writing has been normally completed may be written in the status register 450. . In this case, when there is a write error that cannot be corrected by the error correction circuit 460, information indicating that the writing has not been normally performed is written in the status register 450.
  • FIG. 10 is a diagram illustrating a process flow among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400.
  • the first arithmetic processing node 100 makes a data write request to the memory controller 300.
  • the first arithmetic processing node 100 transmits write data to the memory controller 300. It is assumed that the write data is assigned a logical address L # 00xx.
  • the NIC 350 transfers the write request to the processor 310.
  • the NIC 350 temporarily stores write data in the memory 330.
  • the NIC 350 notifies the first arithmetic processing node 100 of a request receipt notification.
  • the first arithmetic processing node 100 performs other work by transmitting the request reception notification before the actual writing to the flash memory 400 is completed. Is possible. Since writing data to the flash memory 400 requires time for writing data to the DRAM or SRAM, such a request reception notification is effective for improving the processing efficiency of the first processing node 100. .
  • the processor 310 reads data already stored from the flash memory 400.
  • data is read from the flash memory 400.
  • the write data stored in the memory 330 and the data read from the flash memory 400 are merged to create data to be written to the flash memory 400.
  • the processor 310 writes data to the flash memory 400.
  • the processor 310 confirms whether or not the writing to the flash memory 400 has been normally completed.
  • the flash memory 400 notifies the processor 310 of the contents of the status register 450 in response to the completion confirmation.
  • a normal end notification indicating that data writing has ended normally is sent to the processor 310, and the processor 310 ends the write process.
  • the second operation processing node 200 transmits a read request designating the same logical address L # 00xx as the one requested by the first operation processing node 100 in step 601 to the memory controller 300. .
  • the NIC 350 transfers the read request to the processor 310.
  • the processor 310 suspends the processing for the read request received from the second arithmetic processing node 200 until the processing for the write request received from the first arithmetic processing node 100 is completed.
  • the processor 310 performs a read process on the flash memory 400 in process 614.
  • the processor 310 receives data from the flash memory 400.
  • the processor 310 transmits data to the second arithmetic processing node 200 via the NIC 350.
  • FIG. 10 shows processing when data has already been written to the physical address corresponding to the logical address L # 00xx. However, when data is not written to the physical address corresponding to the logical address L # 00xx, the processing 606 and processing 607 are not performed, and the write data is directly written to the corresponding physical address.
  • FIG. 10 shows an example in which a read request is received from the second arithmetic processing node 200 during the processing for the write request received from the first arithmetic processing node 100. However, the read request from the second arithmetic processing node 200 may be received by the memory controller 300 after the processing for the write request received from the first arithmetic processing node 100 is completed.
  • FIG. 11 is a diagram showing another example of the flow of processing among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400.
  • the processes having the same contents as those shown in FIG. 10 are denoted by the same reference numerals, and the description thereof is omitted.
  • FIG. 11 illustrates a case where a write error has occurred in writing data to the flash memory 400.
  • the flash memory 400 notifies the processor 310 of an abnormal end notification.
  • the processor 310 may perform a rewrite process.
  • the rewrite process is a process for writing the same data into the flash memory 400 again when the writing is not normally completed. Details of the rewriting process will be described later. If the writing does not end normally even after performing the rewriting process, the processor 310 receives an abnormal end notification from the flash memory 400 again.
  • the processor 310 Upon receiving the abnormal termination notification from the flash memory 400, the processor 310 notifies the first arithmetic processing node 100 that is the source of the write request via the NIC 350 in processing 701 and processing 702.
  • the processor 310 receives an abnormal end notification from the flash memory 400, the processor 310 generates a write error flag by setting the L-Error value of the logical address management table 331 to "1".
  • the processor 310 notifies a request non-acceptance notification to the read request received from the second arithmetic processing node 200 via the NIC 350. Data is not read in response to a read request received from the second arithmetic processing node 200. Thereby, it is possible to prevent erroneous data from being transmitted to the second arithmetic processing node 200.
  • the rewrite process is performed before a write error notification is issued in response to a request from the first arithmetic processing node 100 when the writing is not normally completed.
  • the processor 310 sets the P-Error value of the physical address that has been written first to “1” and stores it in the physical address management table 332. Then, the processor 310 searches the physical address management table 332 for a page whose P-Valid is “0”, that is, a page in which no data is written. Data is similarly written to the retrieved new page.
  • the logical address management table 331 is rewritten so that the physical address of the new page corresponds to the logical address.
  • the L-Error value of the logical address is “0” indicating that the writing has been performed normally, and no write error notification is issued.
  • the rewrite process may limit the number of times rewrite is performed. For example, if the rewrite count limit is set to two, if data is not normally written to the flash memory 400 even after two rewrites, the rewrite process is terminated.
  • the L-Error value of the logical address is “1” indicating that writing has not been performed normally. Note that the rewrite process by the processor 310 is not essential in this embodiment, and a write error notification may be transmitted to the first arithmetic processing node 100 in response to the failure of the first write.
  • FIG. 12 is a diagram illustrating a processing flow of the processor 310 when a data write request is received in the embodiment.
  • the process of FIG. 12 is started by process 1100.
  • the lock control unit 312 locks the accessed logical address.
  • the table management unit 311 accesses the logical address management table 331 stored in the memory 330.
  • the table management unit 311 determines whether or not the value of L-Error described in the logical address management table 331 is “0”.
  • the notification unit 313 sends a request non-acceptance notification to the operation processing node that issued the data write request. If it is determined in process 1103 that the L-Error value is “0”, the table management unit 311 in process 1104 indicates that the L-Valid value described in the logical address management table 331 is “0”. It is determined whether or not. If it is determined in process 1104 that the value of L-Valid is “0”, the process proceeds to process 1108.
  • the table management unit 311 extracts a physical address corresponding to the logical address based on the logical address management table 331 in process 1105.
  • the data reading unit 315 reads the data written in the extracted physical address.
  • the memory control unit 314 merges the read data and the write data stored in the memory 330 to create update write data.
  • the table management unit 311 accesses the physical address management table 332 stored in the memory 330 and selects a physical address for writing data.
  • the data writing unit 316 writes the write data or the update write data to the selected physical address.
  • the confirmation unit 317 accesses the status register 450 of the flash memory 400 and determines whether or not the data writing is successful. If it is determined in the process 1110 that the data writing has succeeded, the table management unit 311 records “0” in the L-Error of the logical address management table 331 in the process 1111. If it is determined in process 1110 that data writing has failed, in process 1112, the rewrite unit 318 determines whether or not the number of rewrites exceeds the set value. If it is determined in process 1112 that the rewrite count does not exceed the set value, the process returns to process 1108.
  • the table management unit 311 records “1” in L-Error of the logical address management table 331 in process 1113.
  • the notification unit 313 notifies the write request issuer of a write error notification.
  • the lock control unit 312 releases the lock for the other request, and the process 1117 ends.
  • FIG. 13 is a diagram illustrating a processing flow of the processor 310 when a data read request is received in the embodiment.
  • the process of FIG. 13 is started by process 1200.
  • the table management unit 311 accesses the logical address management table 331 stored in the memory 330.
  • the table management unit 311 determines whether or not the value of L-Error described in the logical address management table 331 is “0”.
  • the notification unit 313 issues a request rejection notification to the issuer of the data read request.
  • the table management unit 311 in process 1203 uses the physical address corresponding to the logical address included in the read request based on the logical address management table 331. To extract.
  • the data reading unit 315 reads data from the corresponding physical address.
  • the data transmission unit 319 transmits the read data to the issuer of the read request, and ends the process 1207.
  • the L-Error value “1” that is the write error flag is set to the logical value. Stored in association with the address.
  • the memory controller 300 can recognize that an error exists in the data specified by the logical address.
  • the memory controller 300 notifies the fact that there is an error in the data without causing the read request issuer to read and transmit the incorrect data, thereby suppressing malfunction of the information processing apparatus 1. .
  • a request rejection notification is notified in response to a data write request, and data writing is not performed.
  • the memory controller 300 transmits a write error notification to the first arithmetic processing node 100.
  • the first arithmetic processing node 100 can take various measures. For example, the memory controller 300 may be requested again to write the same data as the recovery process.
  • a data write request that is, a data update request is made by designating the same logical address from the second arithmetic processing node 200 before this request is made again.
  • the memory controller 300 receives a write request from the second arithmetic processing node 200, writes data, and succeeds in writing.
  • the data in the flash memory 400 is correctly updated by a write request from the second arithmetic processing node 200.
  • the memory controller 300 sends a request non-acceptance notification without responding to the request not only when the received request is a read request but also when it is a write request. To notify.
  • the second embodiment is based on the contents of the first embodiment, and further adds processing when a re-request for writing is made by the first arithmetic processing node 100.
  • the first arithmetic processing node 100 that has received the write error notification from the memory controller 300 can perform a rewrite request for writing the same data into the memory 400 as error state recovery processing.
  • the recovery processing unit 113 illustrated in FIG. 5 instructs the request issuing unit 111 to issue a write request again.
  • the request issuing unit 111 issues a write rerequest along the predetermined description format shown in FIG. Processing of the memory controller 300 in response to this write re-request will be described with reference to FIGS.
  • FIG. 14 is a diagram showing an example of a logical address management table in the second embodiment.
  • a request issuer ID is recorded in addition to the contents of the logical address management table shown in FIG.
  • the request issuer ID is an ID that identifies the issuer of the write request that the memory controller 300 has received most recently. As shown in FIG. 6, this request issuer ID is included as information in the write request sent from the processing node.
  • the memory controller 300 that has received the previous write request stores the request issuer ID included in the write request and the logical address in the logical address management table 331 in association with each other.
  • FIG. 15 is a diagram illustrating another example of the flow of processing among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400 in the second embodiment.
  • the same processes as those in FIGS. 10 and 11 are denoted by the same reference numerals, and description thereof is omitted.
  • the first arithmetic processing node 100 receives a write error notification from the memory controller 300.
  • the first arithmetic processing node 100 issues a write re-request.
  • the first arithmetic processing node 100 transmits write data to the memory controller 300.
  • the NIC 350 transfers the write rerequest to the processor 310.
  • the NIC 350 transfers the write data to the memory 330 and stores it.
  • the NIC 350 sends a request receipt notification to the first processing node 100 that is the issuer of the write request.
  • the processor 310 confirms that the issuer ID of the write rerequest is the same as the issuer ID of the previously written request, and performs processing for the write rerequest. Specifically, the processor 310 reads data from the flash memory 400 in processing 806 and processing 807, writes data to the flash memory 400 in processing 808 and processing 809, and confirms completion of processing in the flash memory 400 in processing 810. In step 811, a normal end notification is received from the flash memory 400. Note that if the writing cannot be performed normally even if writing is performed in response to the re-request for writing, the memory controller 300 receives an abnormal end notification in step 811 instead of the normal end notification.
  • the memory controller 300 when the L-Error value is “1”, the memory controller 300 that has received the write request notifies a request acceptance notice to the issuer of the write request without responding to the write request. Therefore, even if the first arithmetic processing node 100 that has received the write error notification makes a re-request for writing as a recovery process, the memory controller 300 does not accept the re-request and the re-write process is not performed.
  • the memory controller 300 stores the request issuer ID in the logical address management table 331 when there is a write request.
  • the memory controller 300 that has received the write request, even if the L-Error value is “1”, the issuer ID stored in the logical address management table 331 matches the issuer ID of the write request. Exceptionally accepts write requests. Thereby, the first arithmetic processing node 100 can perform rewriting as the recovery processing.
  • FIG. 16 is a diagram showing a processing flow of the processor 310 when a data write request is received in the second embodiment.
  • the same processing contents as those shown in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • processing 1103 if the table management unit 311 determines that the value of L-Error is not “0”, the processing proceeds to processing 1301.
  • the table management unit 311 determines whether the request issuer ID included in the write request matches the request issuer ID stored in the logical address management table 331. If it is determined in process 1301 that both request issuer IDs match, the process proceeds to process 1104, where write processing is performed. If it is determined in process 1301 that the two request issuer IDs do not match, the notification unit 313 issues a request rejection notice to the issuer of the write request in process 1115.
  • the third embodiment is based on the contents of the first embodiment and includes a rewrite process by the first arithmetic processing node 100.
  • the request issuer ID is used to identify that the request received by the memory controller 300 is a write re-request by the processing node that has received the write error notification.
  • the request ID is used to identify that the write request received by the memory controller 300 is a write re-request by the processing node that has received the write error notification.
  • FIG. 17 shows an example of a logical address management table in the third embodiment.
  • a request ID is recorded in addition to the contents of the logical address management table shown in FIG.
  • the request ID is an ID indicating the identity of the content of the latest write request received by the memory controller 300. As shown in FIG. 6, this request ID is included as information in the write request sent from the arithmetic processing node.
  • the memory controller 300 that has received the previous write request stores the request ID and logical address included in the write request in association with each other in the logical address management table.
  • the recovery processing unit 114 shown in FIG. 5 receives the write request with the same request ID as the request ID attached to the previous write request.
  • the reissue is instructed to the request issuing unit 111.
  • the request issuing unit 111 transmits a write rerequest to the memory controller.
  • the memory controller 300 that has received the write re-request confirms the logical address management table 331. Even if the value of L-Error is “1”, if the request ID attached to the write re-request matches the request ID stored in the logical address management table 331, the memory controller 300 writes Accept the request. Thereby, the first arithmetic processing node 100 can perform rewriting as the recovery processing.
  • FIG. 18 is a diagram showing a processing flow of the processor 310 in the third embodiment. Components having the same processing contents as the processing flow of the processor 310 shown in FIGS. 12 and 16 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the table management unit 311 determines in the processing 1103 that the value of L-Error is not “0”, the processing proceeds to a processing 1401.
  • the table management unit 311 determines whether or not the request ID included in the write request matches the request ID stored in the logical address management table 331. If it is determined in process 1401 that both request IDs match, the process proceeds to process 1104, and a write process is performed. If it is determined in process 1401 that the request IDs do not match, the notification unit 313 issues a request non-acceptance notification to the issuer of the write request in process 1115.
  • the fourth embodiment is based on the contents of the second embodiment or the third embodiment, and the processing of the memory controller 300 when data is normally written in the memory 400 by rewriting by the first processing node 100. It discloses about.
  • the second operation processing node 200 that has received the request non-acceptance notification in the process 704 cannot receive the desired data, and the process stagnates. Further, the second arithmetic processing node 200 does not have a means for recognizing whether or not the write error state has been eliminated by the re-request for writing by the first arithmetic processing node 100. Therefore, it is not possible to recognize when the read request should be attempted again. Therefore, in the fourth embodiment, when the writing to the write re-request of the first arithmetic processing node 100 is normally completed, the recovery is a notification that the data has been normally written to the second arithmetic processing node 200. Notification of completion will be sent. By this notification, the second arithmetic processing node 200 can recognize that it is possible to make a read re-request for the read request that has received the request non-acceptance notification, and can read desired data from the memory 400. It becomes possible.
  • FIG. 19 shows an example of a logical address management table in the fourth embodiment.
  • the read request record records that each arithmetic processing node makes a read request for the logical address in a state where the L-Error value of the specific logical address is “1”. In other words, it means that the arithmetic processing node whose read request record is recorded in the logical address management table 331 has received a request non-acceptance notification for the read request in the past.
  • the second arithmetic processing node 200 makes a read request to the logical address L # 0001.
  • FIG. 20 is a diagram illustrating another example of the processing flow among the first arithmetic processing node 100, the second arithmetic processing node 200, the memory controller 300, and the flash memory 400 in the fourth embodiment.
  • the same processes as those in FIGS. 10, 11 and 15 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • step 803 the processor 310 that has received a re-write request from the first arithmetic processing node 100 performs a write process on the flash memory 400 in steps 806 to 809. Further, the processor 310 confirms completion of the flash memory 400 in process 810 and receives a normal end notification from the flash memory 400 in process 811. Thereafter, the processor 310 notifies the second arithmetic processing node 200 via the NIC 350 of a recovery completion notification indicating that the data in the flash memory 400 has become normal in processing 901 and processing 902.
  • FIG. 21 is a diagram showing a processing flow of the processor 310 of the memory controller 300 that has received a read request in the fourth embodiment.
  • Components having the same processing contents as the processing flow of the processor 310 shown in FIG. 13 are given the same reference numerals, and description thereof will be omitted as appropriate.
  • the processing proceeds to a processing 1203 and a reading process is performed. If the table management unit 311 determines in step 1202 that the value of L-Error is not “0”, the process proceeds to step 1501. In processing 1501, the table management unit 311 records “1” in the read request record of the logical address management table. In step 1206, the notification unit 313 issues a request rejection notification to the data read request issuer.
  • FIG. 22 is a diagram showing a processing flow of the processor 310 that has received a write request in the fourth embodiment.
  • Components having the same processing contents as the processing flow of the processor 310 shown in FIGS. 12, 16, and 18 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • step 1111 the table management unit 311 records “0” in the L-Error value of the logical address management table 331, and then in step 1601, the table management unit 311 determines whether there is a read request record in the logical address management table 311. . If it is determined in process 1601 that there is no record of the read request, the process proceeds to process 1116. When it is determined in the process 1601 that there is a record of the read request, the notification unit 313 notifies the recovery processing completion notification to the arithmetic processing node that has made the read request in the process 1602. With this notification, for example, in FIG. 20, the second processing node 200 that has received the request rejection notification for the read request can recognize that the data has been correctly stored in the flash memory 400. The second arithmetic processing node 200 can perform processing such as re-requesting reading as necessary.
  • the table management unit 311 determines whether the request issuer ID matches, but as a modification, the table management unit 311 determines whether the request ID matches as in the processing 1401 of FIG. May be.
  • the memory whose writing and reading are controlled by the memory controller 300 is not limited to the flash memory.
  • a management table that describes the correspondence between logical addresses and physical addresses or a memory that can be controlled for writing and reading based on information having the same contents as the management table is applicable to the present invention.

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Abstract

La technologie ci-décrite vise à proposer un procédé pouvant éviter le fonctionnement erroné d'un dispositif de traitement d'informations à cause de données erronées et de la lecture de données erronées, même lorsque l'écriture des données en mémoire a échoué. Dans ledit procédé, des données auxquelles une adresse logique a été attribuée sont écrites à une adresse physique prédéfinie de la mémoire, et lorsque l'écriture des données n'a pas été réalisée normalement, un premier fanion est généré pour indiquer que l'écriture n'a pas été réalisée normalement, et il est mémorisé en association avec l'adresse logique. Au moyen du premier fanion, il est possible qu'une erreur dans les données auxquelles une adresse logique spécifique a été attribuée reste enregistrée. En conséquence, il est possible d'éviter qu'un nœud de calcul lise des données erronées.
PCT/JP2013/005598 2013-09-20 2013-09-20 Procédé de traitement d'informations, dispositif de traitement d'informations, contrôleur de mémoire et mémoire WO2015040658A1 (fr)

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PCT/JP2013/005598 WO2015040658A1 (fr) 2013-09-20 2013-09-20 Procédé de traitement d'informations, dispositif de traitement d'informations, contrôleur de mémoire et mémoire

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006085342A (ja) * 2004-09-15 2006-03-30 Sony Corp メモリ制御装置、メモリ制御方法、プログラム
JP2007148965A (ja) * 2005-11-30 2007-06-14 Oki Electric Ind Co Ltd フラッシュディスク装置のエラーブロック管理方法及び装置
JP2009301264A (ja) * 2008-06-12 2009-12-24 Mitsubishi Electric Corp Ｎａｎｄ型フラッシュメモリアクセス装置及びｎａｎｄ型フラッシュメモリアクセスプログラム及び記録媒体
JP2011181155A (ja) * 2010-03-03 2011-09-15 Toshiba Corp 不揮発性半導体記憶装置及びメモリシステム
US20120144249A1 (en) * 2010-12-03 2012-06-07 International Business Machines Corporation Program Disturb Error Logging and Correction for Flash Memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006085342A (ja) * 2004-09-15 2006-03-30 Sony Corp メモリ制御装置、メモリ制御方法、プログラム
JP2007148965A (ja) * 2005-11-30 2007-06-14 Oki Electric Ind Co Ltd フラッシュディスク装置のエラーブロック管理方法及び装置
JP2009301264A (ja) * 2008-06-12 2009-12-24 Mitsubishi Electric Corp Ｎａｎｄ型フラッシュメモリアクセス装置及びｎａｎｄ型フラッシュメモリアクセスプログラム及び記録媒体
JP2011181155A (ja) * 2010-03-03 2011-09-15 Toshiba Corp 不揮発性半導体記憶装置及びメモリシステム
US20120144249A1 (en) * 2010-12-03 2012-06-07 International Business Machines Corporation Program Disturb Error Logging and Correction for Flash Memory

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