KR20140101626A

KR20140101626A - Data processing method of solid state drive

Info

Publication number: KR20140101626A
Application number: KR1020130015012A
Authority: KR
Inventors: 권민철
Original assignee: 삼성전자주식회사
Priority date: 2013-02-12
Filing date: 2013-02-12
Publication date: 2014-08-20

Abstract

The present invention relates to a semiconductor memory device and, more particularly, to a method for processing the data of a solid state drive. According to the embodiment of the present invention, provided is a method for efficiently programming data with a cache-off method by securing the reliability of the data.

Description

Technical Field [0001] The present invention relates to a data processing method for a solid state drive,

The present invention relates to a semiconductor memory device, and more particularly, to a data processing method of a solid state drive (SSD).

Recently, devices using nonvolatile memory are increasing. For example, an MP3 player, a digital camera, a mobile phone, a camcorder, a flash card, and a solid state drive (SSD) use nonvolatile memory as a storage device.

The SSD, which is one of data storage devices using a memory device, is a data storage device in which all the storage media are composed of memory devices. The SSD can be used as a hard disk drive using a host interface such as PATA or SATA which is used in existing data storage devices. The SSD has no mechanical drive, has more stability and durability than conventional hard disk drives, has the advantages of very high access speed and low power consumption.

It is an object of the present invention to provide an SSD using a write cache in which, when data is stored by a cache-off method, meta data is not separately programmed in a flash memory for each page, And a method of efficiently programming data by a cache-off method.

According to an aspect of the present invention, there is provided a data processing method for a solid state drive, the method including receiving first data including a first logical page address and first user data from a host, Program the first data and a logical page address corresponding to a page area programmed prior to the first page area in the first page area; and receiving from the host a second logical page address and a second user data The method comprising: receiving second data comprising a first page address and a second page address, and assigning the second data to a second page area, programming the second data and the first logical page address into the second page area, After programming in the page area, And sending the response to the host.

The method may further include the steps of: receiving a write command of data for a page area from a host; programming the data including user data and spare data in the page area; reading the data programmed in the page area to read the spare data Determining whether or not an uncorrectable error exists in the spare data, and transmitting, if the uncorrectable error does not exist in the spare data, a storage completion response to the page area to the host, .

The method includes the steps of: receiving a write command of data for a page area from a host; confirming integrity of a block to which the data is to be programmed; performing mirror mirroring or spare validation Programming the data including user data and spare data in the page area in at least one of the following two methods: transmitting a storage completion response to the page area to the host;

According to the embodiment of the present invention as described above, it is possible to secure the reliability of data without programming the meta data for each page in the flash memory separately in the SSD using the write cache, -off < / RTI > method.

1 is a block diagram showing a basic configuration of a system using an SSD according to the present invention.
2 is a flowchart showing a data processing method of a cache-on / off method.
3 is a flowchart showing a program process of a cache-off scheme.
4 is a diagram illustrating a write operation of the flash memory according to the first embodiment of the present invention.
5 is a flowchart showing a data processing method of a cache-off method according to the first embodiment of the present invention.
FIG. 6 is a flowchart illustrating a data processing method of a cache-off method according to the second embodiment of the present invention.
7 is a flowchart showing a data processing method of a cache-off method according to the third embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

Hereinafter, a solid state drive (SSD) will be used as an example of a storage device or an electronic device for explaining the features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. Further, the present invention may be implemented or applied through other embodiments. In addition, the detailed description may be modified or changed in accordance with the aspects and applications without departing substantially from the scope, technical ideas and other objects of the present invention.

1 is a block diagram showing a basic configuration of a system using an SSD according to the present invention. Referring to FIG. 1, a system 100 using an SSD 120 as a storage device stores data through exchange of data between the host 110 and the SSD 120. The SSD 120 includes a controller 121 and a flash memory 122. The controller 121 receives data from the host 110 and stores the data in the flash memory 122. [ The SSD 120 is mounted on the system 100 including the host 110 and used. The host 110 stores data in a cache-on / off manner according to the type of data.

2 is a flowchart showing a data processing method of a cache-on / off method. Referring to FIG. 2 (a), when data is processed in a cache-on manner, the controller 120 receives a write command together with data from the host 110. Upon receipt of the command, the controller 120 temporarily stores the data in the buffer. Buffer usually uses volatile memory such as DRAM. Then, the controller 120 sends a storage completion response to the host 110. Thereafter, the controller 120 writes data stored in a buffer in the flash memory 130 (Write). Therefore, the cache-on method is also referred to as an asynchronous write method.

Referring to FIG. 2 (b), when data is processed in a cache-off manner, the controller 120 receives a write command with the data from the host 110. Upon receiving the command, the controller 120 stores data in a buffer and writes data to the flash memory 130. When the write is completed, the controller 120 sends a storage completion response to the host 110. Therefore, the cache-off method is also referred to as a synchronous write method.

The flash memory performs read and write operations in units of pages (pages), and performs erase operations in block units. Software called the Flash Translation Layer (FTL) is used to overcome these shortcomings. Among the main functions of the flash translation layer (FTL) is an address mapping function. A physical page corresponding to a logical page is connected by address mapping. Spare data including logical page address (LPN) information when a write operation is performed on a page is stored together with user data including information.

Flash memory using the Shadow Program method programs the LSB page (Page) and then MSB page (Page). Therefore, if the power is turned off while programming the MSB page (page), an error may also occur in the LSB page (page) connected to the MSB page (page). In this case, the controller generally ensures the reliability of the data according to the flush-based data protection scheme. Therefore, only the data up to the point of storing the data in the buffer in the flash memory is guaranteed by the flush operation. Also, if a sudden loss of power causes the logical page address (LPN) information to be lost, the controller uses a Data Protection Scheme that discards the data and rolls it back to the previous data.

However, if the cache-off method is used, the data that has been sent to the host once the storage completion response must be guaranteed to be reliable. Thus, in the case of the cache-off method, the controller additionally performs a process of separately storing meta data in the flash memory in preparation for an error of the spare data.

3 is a flowchart showing a program process of a cache-off scheme. Referring to FIG. 3, in step S110, a controller that receives a write command from a host programs data into a new page (page).

In step S120, the controller programs the meta data of the new page (page) separately in the flash memory. This is because the data sent to the host as a response to completion must be reliable.

In step S130, the controller transmits a storage completion response to the host after the new page (page) meta data is stored in the flash memory. In this way, the reliability of the data sent from the cache-off method to the host is confirmed.

However, this method is degraded due to the time required to program the meta data of the new page (page) in the flash memory. Therefore, the performance of the cache-off method will be improved if the time for separately programming the meta data for each page can be reduced. Thus, a method for reducing the time required for separately programming meta data will be described below. The following description is based on the premise that no error occurs in the connected LSB page (Paired LSB Page) even if there is a sudden power supply interruption during the program of the MSB page (page). Therefore, in case of an SSD using a shadow program method, there is a method of programming only the LSB page (page) or a method of skipping the MSB offset of the data already notified of the completion response to the host Should be used together. Therefore, it must be ensured that there is no error in the connected LSB page (Paired LSB Page) due to abrupt power supply interruption during the program of the MSB page (page).

4 is a diagram illustrating a write operation of the flash memory according to the first embodiment of the present invention. Flash memory programs data in page units. The flash memory programs the data in pages in order from page 0 (page 0). Generally, one logical page address (LPN) information corresponding to one user data is stored in one page. If an uncorrectable error occurs in the logical page address (LPN) information, the data of the page (page) is lost. As shown in FIG. 3, in the case of the cache-off method, the controller programs the new page and stores the meta data including the logical page address (LPN) information in the flash memory separately Send a save complete response to the host.

Referring to FIG. 4, the present invention proposes a method of securing data reliability by omitting the process of storing such meta data in a flash memory separately. The controller programs the user data, the current logical page address (Current LPN) and the logical page address of the previous page (PreviousWrite LPN) together in a new page (page). For example, user data n (User Data n), logical page address n-1 (LPN n-1), and logical page address n (LPN n) are programmed together in page n (Page n). Next, the user data n + 1 (User Data n + 1), the logical page address n (LPN n), and the logical page address n + 1 (LPN n + 1) Programmed. After the page n + 1 (Page n + 1) is programmed, the storage completion response of page n (Page n) is notified to the host. Then, even if an uncorrectable error occurs in the logical page address n (LPN n) in the page n (Page n), the logical page address n (LPN n) information is recovered from the page n + 1 can do. However, since page 0 (Page 0) does not have the logical page address of the previous page, the gauging data and logical page address 0 (LPN 0) are programmed. Since the probability of an error occurring at the same time in a page written consecutively is low, the logical page address (LPN) information can be restored through a page before and after the page when an error occurs in one page. Thus, the reliability of the data can be secured without storing the meta data in the flash memory every time a new page is programmed. This method is defined as Spare Mirroring.

5 is a flowchart showing a data processing method of a cache-off method according to the first embodiment of the present invention. Referring to FIG. 5, the Spare Mirroring method includes programming two logical page addresses (LPN) per page without programming meta data separately into the flash memory to secure data reliability Method.

In step S210, the controller receives a write command for page n (page n) together with data from the host. Where n is an integer greater than or equal to zero. n is incremented by one from zero. The controller that receives the write command stores the data in a buffer.

In step S220, the controller determines whether n is zero. If n is 0, the process moves to step S240. If n is not 0, the process moves to step S230.

If n is not 0 in step S230, the controller writes the user data n, the logical page address n-1 (LPN n-1), and the logical page address n (LPN n) in the page n (Page n) Lt; / RTI > The controller sends a store completion response to page n (Page n) after programming page n + 1 (Page n + 1) without sending a store completion response to the host immediately after programming page n (Page n). This ensures the reliability of the page (page) where the storage completion response is notified to the host when an error occurs.

In step S240, if n is 0, the controller programs user data 0 (User Data 0), garbage data, and logical page data 0 (LPN 0) on page 0 (page 0). Then, the process moves to step S250. A save complete response to page 0 (page 0) is sent after page 1 (Page 1) has been programmed.

In step S250, the controller receives a write command for page n + 1 (page n + 1) together with data from the host. The controller that receives the write command stores the data in a buffer.

In step S260, the controller writes user data n + 1 (User data n + 1), logical page address n (LPN n), and logical page address n + 1 (LPN n + 1) on page n + 1 ). If n is 0 in step S220, page 1 (page 1) is programmed in step S260.

In step S270, the controller sends a storage completion response to page n (page n) to the host. The reason for sending a store completion response for page n (Page n) after page n + 1 (Page n + 1) has been programmed is that logical page address n (LPN n) must be programmed up to page n + 1 (Page n + As well as the possibility of recovery.

The Spare Mirroring method stores two logical page address (LPN) information in one page, thereby reducing the time required to program the meta data separately in the flash memory per page, Cache-off method can be improved.

FIG. 6 is a flowchart illustrating a data processing method of a cache-off method according to the second embodiment of the present invention. Referring to FIG. 6, the controller does not separately program meta data in the flash memory for each page. The controller reads the page immediately after programming a new page and verifies spare data containing logical page address (LPN) information. If there is no uncorrectable error in the spare data, the controller sends a save complete response to the host. We will define this method as Spare Verifying. Spare data in the Spare Verifying method includes only the logical page address (LPN) of the current page.

In step S310, the controller receives a write command for a new page (page) together with data from the host. When a controller receives a write command, it first stores the data in a buffer.

In step S320, the controller programs user data and spare data on a new page (page). After programming a new page (page), the controller does not program meta data into flash memory separately.

In step S330, the controller directly reads the new page (page) programmed. The controller checks whether there is an uncorrectable error in the Spare data of the new page (page). Instead of programming the meta data separately, it is possible to reduce the operation time of the cache-off method by reading the new page (page) and checking the spare data. This is because the time for reading a page in the flash memory is shorter than the time for programming a page.

In step S340, the controller determines whether there is an uncorrectable error in the spare data. If there is no uncorrectable error, the process proceeds to step S360. If there is an uncorrectable error, the process proceeds to step S350.

In step S350, if there is an uncorrectable error, the controller performs a program failure (Program Fail). The controller changes the currently active block to another physical block. In step S320, the controller reprograms the program failed data to a new page of a new active block.

In step S360, if there is no uncorrectable error, the controller sends a save completion response to a new page (page) to the host that received the write command.

The above-mentioned Spare Verifying method reads the programmed page (page) instead of programming the meta data separately from the cache memory in the cache-off method, and confirms the error of the spare data . The time to read a page in flash memory is shorter than the time to program a page. Therefore, the Spare Verifying method can improve the performance of the cache-off method.

7 is a flowchart showing a data processing method of a cache-off method according to the third embodiment of the present invention. The Spare Mirroring method and the Spare Verifying method shown in FIGS. 5 and 6 are based on the assumption that the probability of uncorrectable errors occurring in consecutive pages in the same block is extremely low . However, there is a possibility that an uncorrectable error may occur in a continuous page (page) in a block due to a weak erase operation due to a subsequent erase operation. Therefore, referring to FIG. 7, the controller checks whether it is a weak block and programs it in a different method.

In step S410, the controller receives a write command for a new page (page) together with data from the host. The controller stores the received data in a buffer.

In step S420, the controller checks the integrity of the active block currently being programmed. For example, there is a method of counting the number of erase operations and counting the number of erase operations as a weak block when the number of erase operations exceeds the reference number.

In step S430, if the current active block is not a weak block, the process moves to step S460. If the current active block is a weak block, the process proceeds to step S440.

In step S440, if the current active block is a weak block, the controller programs a new page in a general cache-off manner. The controller programs the User data and Spare data into a new page.

In step S450, the controller stores the meta data of the new page (page) separately in the flash memory to ensure the reliability of the data. Even though the operation time is longer, in the case of a weak block, there is a possibility of an uncorrectable error in a consecutive page.

In step S460, if the current active block is not a weak block, the controller inserts a new page (Spare Mirroring) or Spare Verifying ) Program the data. This is because it is unlikely that an uncorrectable error will occur in successive pages (page) unless it is a weak block.

In step S470, the controller sends a storage completion response to a new page (page) in which the program is completed to the host.

In the above, we have seen that the current active block is programmed in different ways depending on whether it is a weak block or not. In the case of a weak block, an uncorrectable error may occur in successive pages in a block. In the case of a weak block, the controller stores the meta data separately in the flash memory. If it is not a weak block, the operation time can be reduced through a method of sparing mirroring or spare verifying. In this way, both efficiency and reliability can be satisfied in a cache-off scheme.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100: System that uses SSD as a storage device
110: Host
120: SSD
121: Controller of SSD
122: Flash memory of SSD

Claims

Receiving first data including a first logical page address and first user data from a host and allocating the first data to a first page area;
Programming the first data and a logical page address corresponding to a page area programmed prior to the first page area in the first page area;
Receiving second data including a second logical page address and second user data from the host and allocating the second data to a second page area;
Programming the second data and the first logical page address in the second page area; And
And transmitting a storage completion response for the first page area to the host after programming the second page area.

The method according to claim 1,
Wherein when the first page area is the first page area programmed in the block, the first data and the gabbage data are programmed in the first page area, A method for processing data in a state drive.

Receiving a write command of data for a page area from a host;
Programming the data including user data and spare data in the page area;
Reading the data programmed in the page area to identify the spare data;
Determining whether or not an uncorrectable error exists in the spare data; And
And if the uncorrectable error does not exist in the spare data, transmitting a storage completion response to the page area to the host.

The method of claim 3,
Wherein the step of determining whether or not the uncorrectable error exists includes the step of, when there is an uncorrectable error in the spare data, the program operation for the page area is processed as a failure.

5. The method of claim 4,
And program the data for the page area processed by the program failure in a page area of another block.

Receiving a write command of data for a page area from a host;
Confirming the integrity of the block to which the data is to be programmed;
Programming the data including user data and spare data in the page area using at least one of a spare mirroring method or a spare verifying method when the block is defective; And
And transmitting a storage completion response for the page area to the host.

The method according to claim 6,
And programing the data in the page area and then programming the metadata for the page area separately in the flash memory if the block is not integrity in the step of programming the page area.

The method according to claim 6,
Wherein the step of determining integrity of the block determines that the integrity of the block is determined to be defective when the number of erase times of the block is equal to or less than a reference number.