JP2015049722A - Microcomputer and block control method of non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer that can efficiently control data for which writing is unsuccessfully performed when it stores a plurality of data in a non-volatile memory while updating them.SOLUTION: A low voltage detection circuit 8 outputs a low voltage detection signal when it detects a voltage reduction of a flash power 7 to a level at which writing to a flash memory cannot be performed. A non-volatile under-writing flag memory 9 W is provided where an under-writing flag is set by the low voltage detection signal. A CPU2 starts writing an ID and data in a block of a flash memory 4 after shifting to a status where the flag can be set by a control logic 10 W. Afterward, the control logic 10 W shifts to a status where the flag cannot be set. When a reset is cancelled, the CPU2 reads out the under-writing flag memory 9 W, and disables the final ID and data for which writing was performed when the flag is set, before deleting the flag memory 9 W.

Description

  The present invention relates to a microcomputer incorporating a nonvolatile memory having a plurality of blocks of a predetermined size, which is a unit capable of erasing data collectively, and a block management method for the nonvolatile memory.

  In recent years, a microcomputer incorporating a flash memory which is a kind of nonvolatile semiconductor memory has been used. For example, the flash memory can be used for storing a user program used by a CPU (Central Processing Unit) of the microcomputer, Used for writing and storing various data. Here, the flash memory can be written for each word, but erasing needs to be performed in batches in units of blocks of a plurality of words.

When the number of block erase increases, the life of the flash memory is shortened. Therefore, a technique has been proposed in which erasure is not performed as much as possible when data stored in the flash memory is updated. For example, Patent Document 1 discloses a technique for managing data in units of IDs and adding only updated data to reduce the number of erasures.

  Here, if a reset occurs due to, for example, a momentary power interruption during the writing of data to the flash memory, there arises a problem that the written data becomes an incorrect value or the retention cannot be maintained for a long time. For example, by arranging a large-capacity capacitor, a measure for maintaining a writable voltage even if an instantaneous interruption occurs can be considered. However, there is a demerit of increasing the cost and size of the product, and it is difficult to adopt it in practice.

  Some flash memories have a blank check function and a verify function. If these functions are used, the above problem can be dealt with. However, flash memory that does not have the function has another countermeasure. Necessary. For example, as shown in FIG. 11, a check area in which a predetermined value is written before starting writing of each data and a check area in which a predetermined value is written after writing ID and data are provided. It can be considered to determine whether or not the writing is properly performed by checking whether or not a predetermined value is written in each of these check areas.

  Further, in Patent Document 2, when a power interruption occurs during writing of a program to the flash memory, an auxiliary memory such as an EEPROM stores a flag, a position where the writing is interrupted, a program type, etc. A technique is disclosed in which, when the computer is restarted, the information in the EEPROM is read and writing is resumed from the position where it was interrupted.

JP 2004-164493 A JP 2010-9165 A

  However, in the method shown in FIG. 11, two check areas are required for one ID and data (data record), and the storage area is eroded by them, so that the use efficiency of the flash memory is lowered. Further, in the technique of Patent Document 2, since a write target is a program, it is necessary to store a lot of information corresponding to the program in the EEPROM. If the object to be written is a plurality of types of data, it cannot be applied immediately, and necessary and efficient information cannot be stored.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a microcomputer capable of efficiently managing data that has failed to be written when a plurality of data is stored in a nonvolatile memory while being updated, and a nonvolatile memory. A block management method for a random memory is provided.

  According to the microcomputer of the first aspect, the low voltage detection circuit outputs a low voltage detection signal when detecting that the power supply voltage has dropped to a level at which writing to the nonvolatile memory becomes impossible. In addition, a non-writing flag memory in which a writing flag is set by a low voltage detection signal is provided. The flash memory may be a 1-bit storage element.

  Then, when writing to the write target block, the write processing means writes the ID and data to the block after the flag is set by the control logic. Thereafter, the control logic makes the flag unsettable. When the reset is released, the writing check means reads the writing flag memory, and when the writing flag is set, invalidates the ID and data that was written last, and then writes. Erase the flag memory (flag reset).

  With this configuration, the writing flag is set when the power supply voltage drops while writing to a certain block. Then, when the reset is released, the write check means can check based on whether or not the writing flag is set. If the flag is set, the ID and data that was last written is written. Disable.

  Here, the identification of “ID and data that was last written” can be identified by referring to the status area indicating the validity of the block. If writing is performed in ascending order of addresses, a record in which data having a value different from the erased data value is stored in descending order from the maximum address of the block may be searched. Therefore, if a writing flag memory that is a 1-bit storage element is prepared, a write check can be performed, so that the storage area of the nonvolatile memory can be used efficiently.

  According to the microcomputer of the fourth aspect, the writing flag memory and the control logic are provided corresponding to each block provided in the nonvolatile memory. In other words, even when only one writing flag memory is prepared for the non-volatile memory, if the status area is referred to as described in claim 1, the data record that has been written last is stored. Can be identified. However, it cannot be denied that the writing and erasing of the status area itself may have failed due to a decrease in power supply voltage. Therefore, if the writing flag memory and the control logic are provided corresponding to each block, the writing check can be performed more reliably.

  According to another aspect of the microcomputer of the present invention, there is provided a nonvolatile erasing flag memory in which an erasing flag is set by a low voltage detection signal. When erasing the block, the erasure processing unit erases the block after setting the flag in a state where the flag can be set by the control logic, and then sets the flag in a state where the flag cannot be set by the control logic. When the reset is released, the erasure check means reads the erasing flag memory, and when the erasing flag is set, the erasure check means is scheduled to be the next to be written after the last written block. The erased flag memory is erased after that block is erased.

  With this configuration, an erasing flag is set when the power supply voltage drops while erasing a certain block, so the erasure check means checks whether the erasing flag is set when the reset is released. Can be checked. And since the block to be erased is the one to be written next to the block that was last written, the block can be identified by referring to the status area, and the block that was incompletely erased is completely Can be deleted.

  According to the microcomputer of the eleventh aspect, first, the erasure check unit performs the erasure check, and then the write check unit performs the write check. With this configuration, the possibility of erroneously determining a block that has failed to be erased due to a decrease in power supply voltage as a valid block is reduced as much as possible by performing an erase check first. After that, by searching the data record that has been written last for the block determined to be valid, it is possible to efficiently process without searching all the blocks.

The flowchart which is 1st Embodiment and shows the process which CPU performs after reset cancellation | release Flow chart showing the writing process to the block of the flash memory A flowchart showing the erase processing of a block of the flash memory Functional block diagram showing the configuration of the microcomputer The figure which shows each block and flag memory in flash memory The figure which shows the structure of the control logic corresponding to each flag memory The figure which shows an example of the address map of the head block in flash memory Diagram showing an example of block management When an area for determining validity / invalidity is assigned to each data record, (a) shows the first embodiment, and (b) shows an example of the prior art. FIG. 1 equivalent view showing the second embodiment Diagram explaining the prior art

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 9. As shown in FIG. 4, the microcomputer 1 includes a CPU 2 (writing processing means, writing checking means, erasing processing means, erasing checking means), a flash memory (FLASH) for program storage 3, and a flash memory 4 for data storage ( A nonvolatile semiconductor memory), a RAM (Random Access Memory) 5, a peripheral circuit 6, a flash power supply 7, and a low voltage detection circuit 8 are provided. The CPU 2 has the function of a memory controller that controls data writing and rewriting (updating) of the flash memory 4, erasing of blocks, switching of blocks to be written, and the like by reading and executing program data from the flash memory 3. Yes.

  The RAM 5 is a main memory of the CPU 2, and is used as a work area for temporarily storing data, calculation results of the CPU 2, and the like when data is written or rewritten. The flash memory 4 includes a memory cell divided into a plurality of blocks as a storage unit. Then, the ID indicating the type of data and the data are written as a set of records.

  The flash power supply 7 transforms and stabilizes the power supplied from the outside and supplies it to the flash memories 3 and 4. The low voltage detection circuit 8 outputs a low voltage detection signal to the flash memory 4 when the flash power supply voltage decreases and falls below a writable level (for example, 14 V). The determination threshold is set to 10 V, for example. The flash memory 4 includes a flag memory 9 (W, E) and a control logic 10 (W, E). The low voltage detection signal is used to write (set a flag) to the flag memory 9 via the control logic 10.

  As shown in FIG. 5, the flash memory 4 includes a plurality of blocks 4B (1), 4B (2),. The capacity of one block is, for example, about 2 kbytes. A 1-bit writing flag memory 9W and an erasing memory flag 9E are arranged for each block 4B. These flag memories 9 are nonvolatile memories like the flash memory 4. However, the writable voltage of the flag memory 9 is set lower than the writable voltage of a normal memory cell of the flash memory 4, and is about 8V, for example.

  Data writing (flag setting) to the flag flag 9W being written and the memory flag 9E being erased is performed via the control logic 10 (W, E) as shown in FIG. The control logic 10 includes an AND gate 10a and a register 10b. A low voltage detection signal is supplied to one input terminal of the AND gate 10a, and the output terminal of the register 10b is connected to the other input terminal.

  When data “1, 0” is written in the predetermined areas set in the flash memory 4 in the registers 10Wb and 10Eb, the data values are held. That is, if a high-level low voltage detection signal is output while “1” is held in the registers 10Wb and 10Eb (start of writing and erasing), the writing flag memory 9W and the erasing memory flag 9E respectively. A flag is set. On the other hand, while “0” is held in the registers 10Wb and 10Eb, the flag is not set in the flag memories 9W and 9E.

  An address for writing to the register 10b of the control logic 10 (W, E) and an address for resetting the flag of the flag memory 9 (W, E) are arranged at the head of each block 4B. For example, as shown in FIG. 7, if one data record is 16 bytes, the address area is from 0x0000 to 0x001F (first part). However, only the first three bytes are actually used. For example, 0x0000 is assigned to the writing flag memory 9W, and the next 0x0001 is assigned to the erasing flag memory 9E.

For example, the following functions are assigned to each bit of the address 0x0000 (first byte).
Bit 0: Reading / reset of flag in writing flag memory 9W
1: Data “1/0” is written to the register 10b, and bits 2 to 7 are not used. Further, the same functions as described above are assigned to bits 0 and 1 of the address 0x0001 (second byte) corresponding to the erasing flag memory 9E.

  The address 0x0002 (third byte) is used as a status area. This status area is generally used in a usage pattern in which updated data is sequentially added to each block as in the present embodiment, and a block 4B (valid block) in which data is currently written. Therefore, a predetermined value (for example, “55”, “AA”, etc.) is written when data is first written in the new block 4B after being erased. As described above, if the capacity of each block 4B is 2 kbytes, the start address of the next block is 0x0400, and the start address of the next block is 0x0800.

  Next, the operation of this embodiment will be described with reference to FIGS. 1 to 3 and FIGS. As shown in FIG. 2, when the CPU 2 writes a data record in the write target block 4B of the flash memory 4, "1" is written and set in the register 10Wb (S1), and ID and data are respectively set in the write target address. Write (S2, S3). Then, “0” is written to the register 10Wb to be cleared (S4). The processing shown in FIG. 2 corresponds to the writing processing means.

  As shown in FIG. 3, when the CPU 2 erases the block 4B to be erased from the flash memory 4, "1" is written and set in the register 10Eb (S11) and erased (S12). Next, “0” is written to the register 10Eb to clear it (S13). Therefore, during the execution of steps S2 and S3, or step S12, if the voltage of the flash power supply 7 drops and a voltage drop detection signal is output due to, for example, a momentary interruption of the power supply, writing to the flag memories 9W and 9E is in progress. Flag and erasing flag are set. The process shown in FIG. 3 corresponds to an erasure processing unit.

  As shown in FIG. 1, when the power is restored and the reset is released, the CPU 2 reads the erasing flag memory 9E of each block (S21). If the erasing flag memory 9E does not have the erasing flag set (no write, S22: NO), the process proceeds to step S25 to determine a valid block (described later). On the other hand, if the erasing flag is set (S22: YES), the block 4B is erased (S23), and the erasing flag memory 9E is reset (erased) (S24). Steps S21 to S24 correspond to the erasure check means.

  In the subsequent valid block determination in step S25, the above-described status area is checked, and the processing in the subsequent step S26 is performed on the “write valid” block 4B. FIG. 8 shows an example. There are four types of data, ID0 to ID3, and when they are updated, data is written in the empty area of the block 4B being written. For example, when there is no free space in block 4B (1), writing is performed after erasing block 4B (2) (at this time, a predetermined value is written in the status area of block 4B (2)). It is ID1 data that was last written in 4B (1).

  Therefore, with respect to the data of other IDs 0, 2, and 3, the data written in the past is picked up and then transferred to the head area of the block 4B (2). It is the data of ID3 that was last written when the free area of the block 4B (2) is exhausted. Therefore, when writing is performed after erasing block 4B (3) next time, the latest data of ID0 to ID3 is transferred to the head area of block 4B (2). If the number of blocks is “3” as shown in FIG. 8, when there is no more free space in the block 4B (3), the next block 4B (1) is erased and writing is performed.

  Refer to FIG. 1 again. In step S26, the CPU 2 reads the valid flag memory 9W of the valid block 4B and determines whether or not the flag is set (S27). If the flag is not set (NO), the process proceeds to step S30 to wait for a request for write / erase processing. On the other hand, if the flag is set in step S27 (YES), the last data record written in the block 4B is searched.

  In general, since data is written in ascending order of addresses, a record having a data value different from the erased data value (all “F”) is searched in descending order from the maximum address of the block 4B. Identify the last data record. Since it is presumed that the power supply voltage has dropped during the writing of the final data record and the writing has become incomplete, the data record is invalidated (S28). Then, the writing flag memory 9W is reset (erased) (S29), and the process proceeds to step S30. Steps S25 to S29 correspond to write check means.

  In order to determine the validity / invalidity of data for each data record, for example, as shown in FIG. 9A, an invalidation flag area (Invalid) is provided for each data record. In step S28, for example, a data value “0” is written in the invalidation flag area of the corresponding data record. The storage area for data and the like is eroded accordingly, which is also the case with the prior art shown in FIG.

  As described above, according to the present embodiment, in the microcomputer 1, when the low voltage detection circuit 8 detects that the voltage of the flash power supply 7 has dropped to a level at which writing to the flash memory 4 becomes impossible, the low voltage detection circuit 8 A detection signal is output. Further, a non-writing flag memory 9W in which a writing flag is set by a low voltage detection signal is provided. Then, when writing to the block 4B to be written, the CPU 2 writes the ID and data to the block 4B after the control logic 10W makes the flag settable.

  After that, the flag cannot be set by the control logic 10W. When the reset is released, the CPU 2 reads the writing flag memory 9W. If the flag is set, the CPU 2 invalidates the last written ID and data, and then the flag memory 10W. Erase.

  Similarly, for erasing the block 4B, a nonvolatile erasing flag memory 9E is provided, and when erasing the block 4B, the CPU 2 erases after the control logic 10E sets the erasing flag in a state that can be set, Thereafter, the erasing flag cannot be set by the control logic 10E. When the reset is released, the erasing flag memory 9E is read, and when the erasing flag is set, the block that was scheduled to be written next to the last written block is erased. Thereafter, the erasing flag memory 9E is erased.

  Therefore, if the flag memories 10W and 10E, which are 1-bit storage elements, are prepared for each block 4B, the write check and the erase check can be performed, so that the storage area of the flash memory 4 can be used efficiently. In addition, since the flag memory 9 and the control logic 10 are provided corresponding to each block 4B included in the flash memory 4, even when the writing and erasing itself into the status area by the CPU 2 has failed due to a decrease in the power supply voltage, Write check and erase check can be performed more reliably.

  Since the flag memory 9 and the control logic 10 are arranged inside the flash memory 4, the nonvolatile flag memory 9 can be manufactured as a single device in the same process as the flash memory 4. In addition, since the access addresses to the flag memory 9 and the control logic 10 are addresses in the same area as the flash memory 4, it is easy to access and control them.

  Further, since the address for accessing the flag memory 9 and the control logic 10 is set at the head of the address assigned to the flash memory 4, when accessing these bits, the MSB side bit corresponding to the number of blocks 4B is used. You can easily access by simply specifying. In addition, the CPU 2 first performs an erasure check and then performs a write check. As a result, the possibility of erroneously determining 4B as a valid block 4B for a block that has failed to be erased due to a decrease in power supply voltage is reduced as much as possible. Then, with respect to the block 4B that is determined to be valid thereafter, the data record that has been written last is searched, so that the processing can be efficiently performed without searching all the blocks 4B.

(Second Embodiment)
Hereinafter, a second embodiment will be described with reference to FIG. In addition, the same code | symbol is attached | subjected to the same part as 1st Embodiment, description is abbreviate | omitted, and a different part is demonstrated below. In the first embodiment, the flag memory 9 (W, E) and the control logic 10 (W, E) are individually provided corresponding to each block 4B. However, in the second embodiment, a flag is provided for the flash memory 4. Only one set of the memory 9 (W, E) and the control logic 10 (W, E) is provided. Therefore, even if a write failure or erasure failure occurs in any one of the plurality of blocks 4B due to the voltage drop of the flash power supply 7, a flag is set in the common flag memory 9.

  In this case, as shown in FIG. 10, when the CPU 2 determines “YES” in step S22, the CPU 2 checks the status area of each block 4B, and identifies the block 4B in which writing was valid before reset release (S31). ). Since the block 4B that has been erased last is the block 4B to be written next to the valid block 4B before reset release, the block 4B that has failed to be erased can be identified. In subsequent step S23 ', the block 4B specified in step S31 is erased.

  On the other hand, the write check is exactly the same as in the first embodiment. That is, if the valid block 4B is identified in step S25 and the writing flag is set, it is the identified valid block 4B that failed to be written. Therefore, the code is invalidated with the final data in the block 4B (S28).

  Here, differences between the first and second embodiments will be described. The second embodiment has an advantage that the required hardware size is reduced because only one set of flag memory 9 (W, E) and control logic 10 (W, E) is provided for the flash memory 4. The block 4B that has failed to be erased or written can be identified in substantially the same manner as in the first embodiment by using the status area.

  However, it cannot be denied that the CPU 2 is writing to the status area and that the voltage drop of the flash power supply 7 has occurred and the writing has failed. Therefore, as in the first embodiment, if the flag memory 9 (W, E) and the control logic 10 (W, E) are provided corresponding to each block 4B, erasing or writing is possible without depending on the status area. It is possible to reliably identify the block 4B that has failed.

  That is, in the write check of the first embodiment, the valid block 4B is specified with reference to the status area in step S25. However, it is not always necessary to refer to the status area, and even if only the flag memory 9W of each block 4B is referred to from the beginning, it is possible to identify the block 4B in which writing has failed.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The capacity of the block 4B is not limited to 2 kbytes.
The address for accessing the flag memory 9 and the control logic 10 is not necessarily arranged at the head of the address of the block 4B.
The flag memory 9 and the control logic 10 may be arranged outside the flash memory 4 as devices independent of the flash memory 4.

The erasing process and the erasure check process performed by providing the erasing flag memory 9E and the control logic 10E may be performed as necessary.
A writable voltage, a threshold voltage for detecting a low voltage, and the like may be appropriately changed according to individual designs.
The present invention is not limited to a flash memory and can be applied to any rewritable nonvolatile memory.

  In the drawings, 1 is a microcomputer, 2 is a CPU (write processing means, write check means, erase processing means, erase check means), 4 is a flash memory (nonvolatile memory), 4B is a block, 7 is a power supply for flash, 8 Is a low voltage detection circuit, 9W is a writing flag memory, and 10W is a control logic.

Claims (16)

Non-volatile memory having a plurality of blocks (4B) of a predetermined size, which is a unit capable of erasing data collectively, and storing a plurality of updated types of data written in an empty area together with an ID indicating the type A microcomputer (1) incorporating (4),
A low voltage detection circuit (8) that outputs a low voltage detection signal when detecting that the power supply voltage has dropped to a level at which writing to the nonvolatile memory becomes impossible;
A non-writing flag memory (9W) in which a writing flag is set by the low voltage detection signal;
Control logic (10 W) for controlling whether or not the writing flag is set to the writing flag memory;
A status area provided corresponding to each block of the non-volatile memory and indicating a block where data is currently written, and a predetermined area to which a predetermined value is written,
When writing to a block to be written, the flag can be set by the control logic, and then the ID and data are written to the block, and then the flag cannot be set by the control logic. Write processing means (2)
When the reset is released, the writing flag memory is read, and if the writing flag is set, the ID and data that were written last are invalidated, and then the writing flag memory is erased. A microcomputer comprising write check means (2).   2. The microcomputer according to claim 1, wherein the writing flag memory and the control logic are arranged inside the nonvolatile memory.   3. The microcomputer according to claim 2, wherein an address for accessing the writing flag memory and the control logic is set at a head portion of an address assigned to the nonvolatile memory.   The microcomputer according to any one of claims 1 to 3, wherein the writing flag memory and the control logic are provided corresponding to each block included in the nonvolatile memory.   4. The reference to claim 1 or 2, wherein an address for accessing the flag memory during writing and the control logic corresponding to each block is set at a head portion of an address assigned to each block. The microcomputer as described. A non-erasing flag memory (9E) in which an erasing flag is set by the low voltage detection signal;
Control logic (10E) for controlling whether or not the erasing flag is set to the erasing flag memory;
When erasing a block to be erased, the control logic enables the flag to be set and then erases the block, and then the control logic disables the flag to be set. 2) and
When the reset is released, the erasing flag memory is read, and if the erasing flag is set, the block that was scheduled to be written next to the last written block is erased. The microcomputer according to any one of claims 1 to 5, further comprising an erasure check means (2) for erasing the erasure flag memory thereafter.   7. The microcomputer according to claim 6, wherein the erasing flag memory and a control logic corresponding to the flag memory are arranged in the nonvolatile memory.   8. The microcomputer according to claim 7, wherein an address for accessing the erasing flag memory and the control logic is set at a head portion of an address assigned to the nonvolatile memory.   8. The microcomputer according to claim 6, wherein the erasing flag memory and a control logic corresponding to the flag memory are provided corresponding to each block included in the nonvolatile memory.   10. The microcomputer according to claim 9, wherein an address for accessing the erasing flag memory and the control logic corresponding to each block is set at a head portion of an address assigned to each block.   11. The microcomputer according to claim 6, wherein an erase check is first performed by the erase check unit, and then a write check is performed by the write check unit. Non-volatile memory block management in which a plurality of blocks of a predetermined size, which is a unit capable of erasing data collectively, are stored and a plurality of types of updated data are written and stored in an empty area together with an ID indicating the type A method,
In a status area provided corresponding to each block of the non-volatile memory, a predetermined value is written to indicate a block in which data is currently written,
When writing to a block to be written, a low output is output to the nonvolatile writing flag memory when it is detected that the power supply voltage has dropped to a level at which writing to the nonvolatile memory becomes impossible. After enabling the setting of the flag during writing by the voltage detection signal, ID and data are written to the block, and then the flag cannot be set,
When the reset is released, the writing flag memory is read, and if the writing flag is set, the ID and data that were written last are invalidated, and then the writing flag memory is erased. A block management method for a nonvolatile memory. The writing flag memory is provided corresponding to each block included in the nonvolatile memory,
13. The non-volatile memory block management according to claim 12, wherein when the reset is released, the in-writing flag memory corresponding to each block is read to determine whether or not the in-writing flag is set. Method. When erasing a block to be erased, the non-erasing flag memory is enabled to set the erasing flag by the low voltage detection signal, and then the block is erased, and then the flag cannot be set. In a state
When the reset is released, the erasing flag memory is read, and if the erasing flag is set, the block that was scheduled to be written next to the last written block is erased. 14. The nonvolatile memory block management method according to claim 12, wherein the erasing flag memory is erased thereafter. The erasing flag memory is provided corresponding to each block included in the nonvolatile memory,
15. The block management of a non-volatile memory according to claim 14, wherein when the reset is released, each of the erasing flag memories corresponding to each block is read to determine whether or not the erasing flag is set. Method. First, determine if the erasing flag is set,
16. The non-volatile memory block management method according to claim 14, wherein it is determined whether or not a writing flag is set.

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