WO2015024329A1 - 阵列基板行驱动单元、阵列基板行驱动电路及显示装置 - Google Patents

阵列基板行驱动单元、阵列基板行驱动电路及显示装置 Download PDF

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Publication number
WO2015024329A1
WO2015024329A1 PCT/CN2013/088684 CN2013088684W WO2015024329A1 WO 2015024329 A1 WO2015024329 A1 WO 2015024329A1 CN 2013088684 W CN2013088684 W CN 2013088684W WO 2015024329 A1 WO2015024329 A1 WO 2015024329A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
row
array substrate
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/088684
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English (en)
French (fr)
Inventor
郑义
王智勇
张郑欣
于尧
时凌云
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/388,500 priority Critical patent/US10002560B2/en
Publication of WO2015024329A1 publication Critical patent/WO2015024329A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present invention relates to display technologies, and in particular, to a GOA (gate drive on Array) unit, an array substrate drive circuit, and a display device.
  • GOA gate drive on Array
  • GOA technology is a technology that integrates a liquid crystal display gate driver circuit (TFT Driver IC) on an array (Array) substrate, and has the following advantages: (1) Integrating a gate driving circuit on an array substrate, which can effectively reduce production. Cost and power consumption; (2) Eliminate the bonding yield process, which can improve product yield and productivity; (3) Eliminate the gate IC bonding area and make the display panel (Panel) has a symmetrical structure and can realize a narrow frame of the display panel.
  • TFT Driver IC liquid crystal display gate driver circuit
  • the present invention provides a GOA unit, a GOA circuit, and a display device for the deficiencies of the prior art, which can effectively reduce the abnormality of the gate drive signal output due to the multilayer overlap of the traces, and the existence of overlap points. Electrostatic discharge problems caused by large pressure differences.
  • An embodiment of the present invention provides an array substrate row driving unit, and the array substrate row driving unit includes:
  • control module configured to output a clock signal under the control of a gate driving signal or a starting input signal of the row row substrate driving unit of the previous row;
  • An output module coupled to the control, for outputting a high voltage signal as a gate drive signal of the row under the control of a clock signal output by the control module, and under the control of a clock signal output by the control module , outputting a low voltage signal;
  • a reset module connected to the output module, for driving the gate of the row of the substrate row in the next row
  • the gate drive signal of the current stage is reset under the control of the pole drive signal.
  • the control module includes a first thin film transistor
  • the output module includes: a second thin film transistor and a third thin film transistor
  • the reset module includes a fourth thin film transistor; wherein, the first thin film transistor The gate is connected to the gate driving signal output end or the initial input signal of the row substrate driving unit of the upper row; the first electrode of the first thin film transistor is connected to the clock signal input end; and the second thin film transistor is connected to the second thin film transistor a pole is respectively connected to a gate of the second thin film transistor and a gate of the third thin film transistor;
  • a first pole of the second thin film transistor is connected to a high level output terminal;
  • a second pole of the second thin film transistor is respectively connected to a second pole of the third thin film transistor and a gate driving signal output end of the row ;
  • a second pole of the third thin film transistor is respectively connected to a low level output terminal and a first pole of the fourth thin film transistor;
  • the gate of the fourth thin film transistor is connected to the output end of the gate driving signal of the array driving unit of the next row; the second electrode of the fourth thin film transistor is connected to the output terminal of the gate driving signal of the row.
  • the first thin film transistor, the second thin film transistor, and the fourth thin film transistor of the first row of array substrate row driving units are N-type thin film transistors; and the third thin film transistor is a P-type thin film transistor.
  • the first thin film transistor and the third thin film transistor of the odd row array substrate row driving unit are P-type thin film transistors; the second thin film transistor and the fourth thin film transistor The thin film transistor is an N-type thin film transistor;
  • the first thin film transistor and the second thin film transistor of the even row array substrate row driving unit are P-type thin film transistors; and the third thin film transistor and the fourth thin film transistor are N-type thin film transistors.
  • An embodiment of the present invention further provides an array substrate row driving circuit, wherein the array substrate row driving circuit includes one or more of the foregoing array substrate row driving units;
  • each row of array substrate row driving units is connected with the gate signal output ends of the row of array substrate row driving units;
  • the reset terminals of each row of array substrate row driving units are connected to the gate signal output terminals of the next row of array substrate row driving units.
  • the embodiment of the invention further provides a display device comprising the array substrate row driving circuit of the invention.
  • the GOA unit, the GOA circuit and the display device provided by the embodiments of the present invention have the following beneficial effects fruit:
  • the GOA unit adopts four thin film transistors, and the original GOA unit is compressed, which reduces the wiring of the circuit board, and effectively reduces the problem of abnormal output of the gate driving signal caused by the multilayer overlapping of the traces; Due to the reduction of the overlap point, the problem of electrostatic discharge due to a large pressure difference between the overlapping points is effectively reduced.
  • FIG. 1 is a schematic block diagram showing the structure of a GOA unit according to a first embodiment of the present invention
  • FIG. 2 is a circuit diagram of a GOA unit according to a second embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a GOA unit according to a third embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a GOA unit according to a fourth embodiment of the present invention.
  • FIG. 5 is a schematic circuit diagram of a GOA unit according to a fifth embodiment of the present invention.
  • FIG. 6 is a timing diagram of signals of a GOA unit in operation according to a fifth embodiment of the present invention
  • FIG. 7 is a circuit diagram of a GOA unit according to a sixth embodiment of the present invention.
  • FIG. 8 is a timing diagram of signals of a GOA unit in operation according to a sixth embodiment of the present invention. detailed description
  • the GOA unit includes: a control module 11, an output module 12, and a reset module 13.
  • control module 11 is connected to the output module 12 for outputting the clock signal CLK to the output module 12 under the control of the gate driving signal or the initial input signal of the row substrate driving row driver unit.
  • the output module 12 is configured to output the high voltage signal VGH as the gate drive signal of the row under the control of the clock signal; and output the low voltage signal VGL under the control of the clock signal.
  • the reset module 13 is respectively connected to the gate driving signal of the next row of the array substrate row driving unit and the output terminal of the row gate driving signal, and is used for controlling the gate of the current level under the control of the gate driving signal of the row driving unit of the next row of the substrate substrate The drive signal is reset.
  • the gate driving signal of the row driving row of the upper row of the array substrate is G(n-1)
  • the gate driving signal of the row is G(n)
  • the gate driving signal of the row driving unit of the array of the next row is G. ( n+1 ).
  • FIG. 2 is a circuit diagram of a GOA unit of a second embodiment of the present invention.
  • the second implementation The GOA unit provided by the example is based on the GOA unit provided by the first embodiment, and is the first row G0A unit; in the second embodiment, the control module 11 includes the first thin film transistor M1, and the output module 12 includes the second thin film transistor M2 and The third thin film transistor M3, the reset module 13 includes a fourth thin film transistor M4.
  • the gate of the first thin film transistor M1 is connected to the signal input terminal INPUT; the first pole of the first thin film transistor M1 is connected to the clock signal input terminal CLK; the second pole of the first thin film transistor M1 is respectively and the second The gate of the thin film transistor M2 is connected to the gate of the third thin film transistor M3.
  • the first pole of the second thin film transistor M2 is connected to the high level signal terminal VGH; the second pole of the second thin film transistor M2 is respectively connected to the first pole of the third thin film transistor M3 and the gate driving signal output terminal G of the row (1) )connection.
  • the second electrode of the third thin film transistor M3 is connected to the low level signal terminal VGL and the first electrode of the fourth thin film transistor M4, respectively.
  • the gate of the fourth thin film transistor M4 is connected to the reset terminal RESET; the second electrode of the fourth thin film transistor M4 is connected to the gate drive signal output terminal G(1) of the row.
  • the reset terminal RESET is connected to the output terminal of the gate driving signal of the next row of array substrate driving units, that is, the reset terminals RESET of the first row of array substrate row driving units are connected to G(2).
  • the first thin film transistor, the second thin film transistor, and the fourth thin film transistor are N-type thin film transistors; and the third thin film transistor is a P-type thin film transistor.
  • the first and second electrodes of the thin film transistor of this embodiment may be the source or drain of the thin film transistor.
  • FIG. 3 is a circuit diagram of a GOA unit in accordance with a third embodiment of the present invention.
  • the array substrate driving unit of the GOA is based on the GOA unit provided in the first embodiment, and is an even-line GOA unit.
  • the control module 11 includes a first thin film transistor M1
  • the output module 12 includes: a second thin film transistor M2 and a third thin film transistor M3, and the reset module 13 includes a fourth thin film transistor M4.
  • the gate of the first thin film transistor M1 is connected to the output terminal G ( n-1 ) of the gate driving signal of the upper row of the array substrate driving unit; the first pole of the first thin film transistor M1 and the clock signal input The terminal CLK is connected; the second electrode of the first thin film transistor M1 is connected to the gate of the second thin film transistor M2 and the gate of the third thin film transistor M3, respectively.
  • the first pole of the second thin film transistor M2 is connected to the high level signal terminal VGH; the second pole of the second thin film transistor M2 is respectively connected to the first pole of the third thin film transistor M3 and the gate driving signal output terminal G of the row ( n ) Connection.
  • the second electrode of the third thin film transistor M3 is connected to the low level signal terminal VGL and the first electrode of the fourth thin film transistor M4, respectively.
  • the gate of the fourth thin film transistor M4 is connected to the reset terminal RESET; the second electrode of the fourth thin film transistor M4 is connected to the gate drive signal output terminal G(n) of the row.
  • the reset terminal RESET is connected to the output terminal of the gate driving signal of the next row of array substrate driving units, that is, the reset terminal RESET is connected to G(n+1).
  • the first thin film transistor and the second thin film transistor are P-type thin film transistors; the third thin film transistor and the fourth thin film transistor are N-type thin film transistors.
  • the first and second electrodes of the thin film transistor of this embodiment may be the source or drain of the thin film transistor.
  • FIG. 4 is a circuit diagram of a GOA unit in accordance with a third embodiment of the present invention.
  • the GOA unit provided by the fourth embodiment is based on the GOA unit provided in the first embodiment, and is an odd-line GOA unit other than the first line.
  • the control module 11 includes a first thin film transistor M1
  • the output module 12 includes: a second thin film transistor M2 and a third thin film transistor M3, and the reset module 13 includes a fourth thin film transistor M4.
  • the gate of the first thin film transistor M1 is connected to the output terminal G ( n-1 ) of the gate driving signal of the upper row of the array substrate driving unit; the first pole of the first thin film transistor M1 and the clock signal input a terminal CLK is connected; a second electrode of the first thin film transistor M1 is respectively connected to a gate of the second thin film transistor M2 and a gate of the third thin film transistor M3;
  • the first pole of the second thin film transistor M2 is connected to the high level signal terminal VGH; the second pole of the second thin film transistor M2 is respectively connected to the first pole of the third thin film transistor M3 and the gate driving signal output terminal G of the row )
  • the second electrode of the third thin film transistor M3 is connected to the low level signal terminal VGL and the first electrode of the fourth thin film transistor M4, respectively.
  • the gate of the fourth thin film transistor M4 is connected to the reset terminal RESET; the second electrode of the fourth thin film transistor M4 is connected to the gate drive signal output terminal G(n) of the row;
  • the reset terminal RESET is connected to the output terminal of the gate drive signal of the next row of array substrate driving units, that is, the reset terminal RESET is connected to G (n+1).
  • the first thin film transistor M1 and the third thin film transistor M3 are P-type thin film transistors; the second thin film transistor M2 and the fourth thin film transistor M4 are N-type thin film transistors.
  • the first and second electrodes of the thin film transistor of this embodiment may be the source or the drain of the thin film transistor.
  • FIG. 5 is a circuit diagram of a GOA unit according to a fifth embodiment of the present invention. As shown in FIG. 5, the circuit includes a first row and a second row of GOA units; in the fifth embodiment, the first row and the second row of GOA units respectively include: a control module 11, an output module 12, and a reset module 13.
  • control module 11 of the first row of array substrate row driving units includes a first thin film transistor M1
  • the output module 12 includes a second thin film transistor M2 and a third thin film transistor M3, and the reset module 13 includes a fourth thin film transistor M4;
  • the control module 11 of the row array substrate row driving unit includes a fifth thin film transistor M5, the output module 12 includes a sixth thin film transistor M6 and a seventh thin film transistor M7, and the reset module 13 includes an eighth thin film transistor M8.
  • the gate of the first thin film transistor M1 is connected to the signal input terminal INPUT; the first electrode of the first thin film transistor M1 is connected to the clock signal input terminal CLK; the second pole of the first thin film transistor M1 is respectively The gate of the second thin film transistor M2 is connected to the gate of the third thin film transistor M3; the first electrode of the second thin film transistor M2 is connected to the high level signal terminal VGH; and the second electrode of the second thin film transistor M2 is respectively connected to the third thin film.
  • a first pole of the transistor M3 is connected to the gate drive signal output terminal G(1) of the row;
  • the second pole of the third thin film transistor M3 is respectively connected to the low level signal terminal VGL and the first pole of the fourth thin film transistor M4;
  • the gate of the fourth thin film transistor M4 is connected to the second row gate driving signal output terminal G ( 2 ); the second electrode of the fourth thin film transistor M4 is connected to the first row gate driving signal output terminal G ( 1 );
  • a gate of the fifth thin film transistor M5 is connected to the first row of gate drive signal output terminals G(1); a first electrode of the fifth thin film transistor M5 is connected to the clock signal input terminal CLK; and a second electrode of the fifth thin film transistor M5 Connected to the gate of the sixth thin film transistor M6 and the gate of the seventh thin film transistor M7, respectively; the first pole of the sixth thin film transistor M6 is connected to the high level signal terminal VGH; and the second pole of the sixth thin film transistor M6 is respectively a first pole of the seventh thin film transistor M7 and a second row of gate drive signal output terminals G ( 2 ) are connected;
  • the second pole of the seventh thin film transistor M7 is respectively connected to the low level signal terminal VGL and the first pole of the eighth thin film transistor M8;
  • the gate of the eighth thin film transistor M8 is connected to the reset terminal RESET, the reset terminal RESET is connected to the third row gate drive signal output terminal G(3); the second and second row gate drive signals of the eighth thin film transistor M8
  • the output G ( 2 ) is connected.
  • the first thin film transistor M1, the second thin film transistor M2, the fourth thin film transistor M4, the seventh thin film transistor M7, and the eighth thin film transistor M8 are N-type thin film transistors; the third thin film transistor M3, the fifth thin film transistor M5, The sixth thin film transistor M6 is a P-type thin film transistor.
  • the first and second electrodes of the thin film transistor of this embodiment may be the source or drain of the thin film transistor.
  • Fig. 6 is a timing chart showing the signals of the array substrate row driving unit in operation according to the fifth embodiment of the present invention. According to the timing chart shown in FIG. 6, taking the first row of array substrate row driving units as an example, the operation process of the array substrate row driving unit is divided into an output signal phase tl and a reset phase t2.
  • the input INPUT is at a high level. Since the first thin film transistor M1 is an N-type thin film transistor, M1 is turned on, and the clock signal CLK is at the same high level, because the second thin film transistor M2 is N-type.
  • the thin film transistor, the third thin film transistor M3 is a P-type thin film transistor, then M2 is turned on, M3 is still turned off, and G(l) outputs a high level;
  • the clock signal CLK is at a low level
  • the second thin film transistor M2 is turned off
  • the third thin film transistor M3 is turned on, at which time the output terminal G(1) outputs a low level due to the output terminal G(l) and
  • the gate of the fifth thin film transistor M5 is connected, and the fifth thin film transistor M5 and the sixth thin film transistor M6 are P-type thin film transistors, M5 is turned on, and since the clock signal CLK is at a low level at this time, M6 is turned on,
  • the output terminal G ( 2 ) outputs a high level; since G ( 2 ) is connected to the gate of the fourth thin film transistor M4, and M4 is an N-type thin film transistor, M4 is turned on, and the output terminal G ( l ) is kept low. Level, thus completing the reset operation of the output G ( l ).
  • FIG. 7 is a circuit diagram of a row driving unit of an array substrate according to a sixth embodiment of the present invention. As shown in Fig. 7, the circuit includes a 2nth row, a 2n+1th row, and a 2n+2th row array substrate row driving unit.
  • the 2nth row, the 2n+1th row, and the 2n+2th row array substrate row driving unit respectively include: a control module 11, an output module 12, and a reset module 13.
  • the control module 11 of the 2n-row array substrate row driving unit includes a first thin film transistor M1, the output module 12 includes: a second thin film transistor M2 and a third thin film transistor M3, and the reset module 13 includes a fourth thin film transistor M4;
  • the control module 11 of the +1 row array substrate row driving unit includes a fifth thin film transistor M5, and the output module 12 includes: a sixth thin film transistor M6 and a seventh thin film transistor M7, and the reset module 13 includes an eighth thin film transistor M8; 2n+2
  • the control module 11 of the row array substrate row driving unit includes a ninth thin film transistor M9, and the output module 12 includes: a tenth thin film transistor M10 and an eleventh thin film transistor Mil, and the reset module 13 includes a twelfth thin film transistor M12.
  • the gate of the first thin film transistor M1 and the output signal of the upper row of gate driving signals G ( 2n - l ) is connected; the first electrode of the first thin film transistor M1 is connected to the clock signal input terminal CLK; the second electrode of the first thin film transistor M1 is respectively connected to the gate of the second thin film transistor M2 and the third thin film transistor M3 Gate connection
  • the first pole of the second thin film transistor M2 is connected to the high level output terminal VGH; the second pole of the second thin film transistor M2 is respectively connected to the first pole of the third thin film transistor M3 and the gate driving signal output terminal G of the row (2n) )
  • the second pole of the third thin film transistor M3 is respectively connected to the low level output terminal VGL and the first pole of the fourth thin film transistor M4;
  • the gate of the fourth thin film transistor M4 is connected to the gate driving signal output terminal G ( 2n + l ) of the next row; the second electrode of the fourth thin film transistor M4 is connected to the gate driving signal output terminal G ( n ) of the row;
  • the gate of the fifth thin film transistor M5 is connected to the gate driving signal output terminal G ( 2n ) of the upper row; the first electrode of the fifth thin film transistor M5 is connected to the clock signal input terminal CLK; and the second electrode of the fifth thin film transistor M5 is respectively Connected to the gate of the sixth thin film transistor M6 and the gate of the seventh thin film transistor M7;
  • the first pole of the sixth thin film transistor M6 is connected to the high level output terminal VGH; the second pole of the sixth thin film transistor M6 is respectively connected to the first pole of the seventh thin film transistor M7 and the gate driving signal output terminal G of the row (2n) +l ) connection;
  • the second pole of the seventh thin film transistor M7 is respectively connected to the low level output terminal VGL and the first pole of the eighth thin film transistor M8;
  • the gate of the eighth thin film transistor M8 is connected to the gate driving signal output terminal G ( 2n+2 ) of the next row; the second electrode of the eighth thin film transistor M8 and the gate driving signal output terminal G ( 2+1 ) of the row Connecting; the gate of the ninth thin film transistor M9 is connected to the gate driving signal output terminal G ( 2n+1 ) of the upper row; the first electrode of the ninth thin film transistor M9 is connected to the clock signal input terminal CLK; the ninth thin film transistor M9 is The second pole is respectively connected to the gate of the tenth thin film transistor M10 and the gate of the eleventh thin film transistor Mil;
  • the first pole of the tenth thin film transistor M10 is connected to the high level output terminal VGH; the second pole of the tenth thin film transistor M10 is respectively connected to the first pole of the eleventh thin film transistor Mil and the gate driving signal output terminal G of the current row ( 2n+2) connection;
  • the second pole of the eleventh thin film transistor Mil is connected to the low level output terminal VGL and the first pole of the twelfth thin film transistor M12, respectively;
  • the gate of the twelfth thin film transistor M12 is connected to the gate drive signal output terminal G ( 2n+3 ) of the next row
  • the second electrode of the twelfth thin film transistor M12 is connected to the row gate driving signal output terminal G (2+2) of the row.
  • the first thin film transistor M1, the second thin film transistor M2, the fifth thin film transistor M5, the seventh thin film transistor M7, the ninth thin film transistor M9, and the tenth thin film transistor M10 are P-type thin film transistors;
  • the third thin film transistor M3, The fourth thin film transistor M4, the sixth thin film transistor M6, the eighth thin film transistor M8, the eleventh thin film transistor M11, and the twelfth thin film transistor M12 are N-type thin film transistors.
  • Fig. 8 is a timing chart showing the signals of the array substrate row driving unit in operation according to the sixth embodiment of the present invention.
  • the operation process of the array substrate row driving unit is divided into the t1, t2, and t3 phases, the t1 phase is the output signal phase of the 2nth row array substrate row driving unit; the t2 phase is the 2n+1 row array.
  • the output signal phase of the substrate row driving unit; the t3 phase is the output signal phase of the 2n+2 row array substrate row driving unit; correspondingly, each row of the array substrate row driving output signal phase is the upper row of the array substrate row driving unit Reset phase.
  • the second thin film transistor M2 is turned off, and the third thin film transistor M3 is turned on, at which time G ( 2n ) outputs a low level, since G ( 2n ) and the fifth thin film transistor M5
  • the gate is connected, and M5 is a P-type thin film transistor, then M5 is turned on, and since CLK is at a high level at this time, and the sixth thin film transistor M6 is an N-type thin film transistor, the seventh thin film transistor M7 is a P-type thin film transistor.
  • M6 is turned on, M7 is turned off, G (2n+l) is output high; since G (2n+l) is connected to the gate of the fourth thin film transistor M4, and M4 is an N-type thin film transistor, M4 is Pass, keep G ( 2n ) output low, thus complete the reset operation of G ( 2n );
  • the clock signal CLK is low, then M6 is off, M7 is on, then G( 2n+l
  • the output is low, since G ( 2n + l ) is connected to the gate of the ninth thin film transistor M9, and M9 is a P-type thin film transistor, M9 is turned on, and since CLK is at a low level, the tenth thin film
  • the transistor M10 is a P-type thin film transistor, and the eleventh thin film transistor Mil is an N-type thin film transistor, and the M9 is M10 is off, G ( 2n+2 ) is output high; since G ( 2n+2 ) is connected to the gate of the eighth thin film transistor M
  • each row of array substrate row driving units is connected with the gate signal output ends of the row of array substrate row driving units;
  • the reset terminals of each row of array substrate row driving units are connected to the gate signal output terminals of the next row of array substrate row driving units.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any display product or component.

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Abstract

一种阵列基板行驱动（GOA）单元，阵列基板行驱动（GOA）电路及显示装置。该阵列基板行驱动（GOA）单元包括：控制模块（11），用于在上一行阵列基板行驱动单元的栅极驱动信号（G（n-1））或起始输入信号的控制下输出时钟信号（CLK）；输出模块（12），与所述控制模块（11）连接，用于在所述控制模块（11）输出的时钟信号（CLK）的控制下，将高电压信号（VGH）输出作为本行栅极驱动信号（G（n））；以及在所述控制模块（11）输出的时钟信号（CLK）的控制下，将低压信号（VGL）进行输出；复位模块（13），与所述输出模块（12）相连，用于在下一行阵列基板行驱动单元的栅极驱动信号（G（n+1））的控制下，对本行栅极驱动信号（G（n））进行复位。该阵列基板行驱动（GOA）单元，阵列基板行驱动（GOA）电路及显示装置，减少了由于走线多层交叠导致的栅极驱动信号输出异常，以及交迭点之间存在较大压差引起的静电释放问题。

Description

阵列基板行驱动单元、 阵列基板行驱动电路及显示装置 技术领域
本发明涉及显示技术，具体涉及一种阵列基板行驱动（GOA, Gate Drive on Array )单元、 阵列基板行驱动电路及显示装置。 背景技术
GOA技术是一种将液晶显示器栅极驱动电路（ Gate Driver IC )集成在阵列 ( Array )基板上的技术， 具有以下优点： （ 1 )将栅极驱动电路集成在阵列基板 上， 能有效降低生产成本和功耗； （2 )省去绑定（bonding ) 良率工艺， 能使产 品良率和产能得到提升； ( 3 )省去栅极驱动电路绑定（ gate IC bonding ) 区域， 使显示面板（panel )具有对称结构， 能实现显示面板的窄边框化。
但是，现有的 GOA技术采用数量较多的薄膜场效应晶体管（ TFT , Thin Film Transistor ), 导致线路板走线存在多层交叠， 从而会引起以下问题： （1 )工艺波 动易导致 GOA 内部寄生电容耦合变化， 导致栅极输出异常； （2 ) 由于交迭点 数量多，使得交迭点之间存在较大压差，容易引起静电释放（ESD, Electro-Static Discharge )。 发明内容
有鉴于此， 本发明针对现有技术的不足提供一种 GOA单元、 GOA电路及 显示装置， 能够有效减少由于走线多层交叠导致的栅极驱动信号输出异常， 以 及交迭点之间存在较大压差引起的静电释放问题。
本发明的技术方案可以这样实现：
本发明实施例提供了一种阵列基板行驱动单元， 所述阵列基板行驱动单元 包括：
控制模块， 用于在上一行阵列基板行驱动单元的栅极驱动信号或起始输入 信号的控制下输出时钟信号；
输出模块， 与所述控制连接， 用于在所述控制模块输出的时钟信号的控制 下， 将高电压信号输出作为本行栅极驱动信号， 以及在所述控制模块输出的时 钟信号的控制下， 将低电压信号进行输出；
复位模块， 与所述输出模块连接， 用于在下一行阵列基板行驱动单元的栅 极驱动信号的控制下， 对所述本级栅极驱动信号进行复位。
上述实施例中， 所述控制模块包括第一薄膜晶体管， 所述输出模块包括： 第二薄膜晶体管和第三薄膜晶体管， 所述复位模块包括第四薄膜晶体管； 其中， 所述第一薄膜晶体管的栅极与上一行阵列基板行驱动单元的栅极驱动信号 输出端或起始输入信号连接； 所述第一薄膜晶体管的第一极与时钟信号输入端 连接； 所述第一薄膜晶体管的第二极分别与所述第二薄膜晶体管的栅极和第三 薄膜晶体管的栅极连接；
所述第二薄膜晶体管的第一极与高电平输出端连接； 所述第二薄膜晶体管 的第二极分别与所述第三薄膜晶体管的第二极和本行栅极驱动信号输出端连 接；
所述第三薄膜晶体管的第二极分别与低电平输出端和所述第四薄膜晶体管 的第一极连接；
所述第四薄膜晶体管的栅极与下一行阵列基板驱动单元的栅极驱动信号的 输出端连接； 所述第四薄膜晶体管的第二极与本行栅极驱动信号输出端连接。
上述实施例中， 第一行阵列基板行驱动单元的所述第一薄膜晶体管、 第二 薄膜晶体管和第四薄膜晶体管为 N型薄膜晶体管； 所述第三薄膜晶体管为 P型 薄膜晶体管。
上述实施例中， 除第一行阵列基板行驱动单元外， 奇数行阵列基板行驱动 单元的所述第一薄膜晶体管和第三薄膜晶体管为 P型薄膜晶体管； 所述第二薄 膜晶体管和第四薄膜晶体管为 N型薄膜晶体管；
偶数行阵列基板行驱动单元的所述第一薄膜晶体管和第二薄膜晶体管为 P 型薄膜晶体管； 所述第三薄膜晶体管和第四薄膜晶体管为 N型薄膜晶体管。
本发明实施例还提供了一种阵列基板行驱动电路， 所述阵列基板行驱动电 路包括一个以上前述的阵列基板行驱动单元；
除第一行阵列基板行驱动单元外， 每一行阵列基板行驱动单元的信号输入 端均与上一行阵列基板行驱动单元的栅极信号输出端连接；
除最后一行的阵列基板行驱动单元外， 每一行阵列基板行驱动单元的复位 端均与下一行阵列基板行驱动单元的栅极信号输出端连接。
本发明实施例还提供了一种显示装置， 所述显示装置包括本发明所述的阵 列基板行驱动电路。
本发明实施例提供的 GOA单元、 GOA电路及显示装置， 具有以下有益效 果：
所述 GOA单元采用四个薄膜晶体管， 筒化了原有的 GOA单元， 减少了线 路板走线， 有效的减少了由于走线多层交叠导致的栅极驱动信号输出异常的问 题； 另外， 由于交迭点的减少， 又有效地减少了由于交迭点之间存在较大压差 引起的静电释放的问题。 附图说明
图 1为本发明第一实施例的 GOA单元的结构示意框图；
图 2为本发明第二实施例的 GOA单元的电路示意图；
图 3为本发明第三实施例的 GOA单元的电路示意图；
图 4为本发明第四实施例的 GOA单元的电路示意图；
图 5为本发明第五实施例的 GOA单元的电路示意图；
图 6为本发明第五实施例的 GOA单元在工作时各信号的时序示意图； 图 7为本发明第六实施例的 GOA单元的电路示意图；
图 8为本发明第六实施例的 GOA单元在工作时各信号的时序示意图。 具体实施方式
下面结合附图对本发明具体实施例作进一步详细的说明。
图 1为本发明第一实施例的 GOA单元的结构框图。如图 1所示，所述 GOA 单元包括： 控制模块 11、 输出模块 12和复位模块 13。
在本实施例中， 控制模块 11与输出模块 12连接， 用于在上一行阵列基板 行驱动单元的栅极驱动信号或起始输入信号的控制下将时钟信号 CLK输出给 输出模块 12。
输出模块 12用于在时钟信号的控制下， 将高电压信号 VGH输出作为本行 栅极驱动信号； 以及在时钟信号的控制下， 将低电压信号 VGL进行输出。
复位模块 13 分别与下一行阵列基板行驱动单元的栅极驱动信号和本行栅 极驱动信号输出端连接， 用于在下一行阵列基板行驱动单元的栅极驱动信号的 控制下， 对本级栅极驱动信号进行复位。
图 1 中， 上一行阵列基板行驱动单元的栅极驱动信号为 G ( n-1 ), 本行栅 极驱动信号为 G ( n ), 下一行阵列基板行驱动单元的栅极驱动信号为 G ( n+1 )。
图 2为本发明第二实施例的 GOA单元的电路图。 如图 2所示， 第二实施 例提供的 GOA单元基于第一实施例提供的 GOA单元， 并且为第一行 G0A单 元； 在第二实施例中， 控制模块 11 包括第一薄膜晶体管 Ml , 输出模块 12包 括第二薄膜晶体管 M2和第三薄膜晶体管 M3, 复位模块 13包括第四薄膜晶体 管 M4。
本实施例中， 第一薄膜晶体管 Ml的栅极与信号输入端 INPUT连接； 第一 薄膜晶体管 Ml的第一极与时钟信号输入端 CLK连接； 第一薄膜晶体管 Ml的 第二极分别与第二薄膜晶体管 M2的栅极和第三薄膜晶体管 M3的栅极连接。
第二薄膜晶体管 M2的第一极与高电平信号端 VGH连接；第二薄膜晶体管 M2的第二极分别与第三薄膜晶体管 M3的第一极和本行栅极驱动信号输出端 G ( 1 )连接。
第三薄膜晶体管 M3的第二极分别与低电平信号端 VGL和第四薄膜晶体管 M4的第一极连接。
第四薄膜晶体管 M4的栅极与复位端 RESET连接； 第四薄膜晶体管 M4的 第二极与本行栅极驱动信号输出端 G ( 1 )连接。
复位端 RESET与下一行阵列基板驱动单元的栅极驱动信号的输出端连接， 即第一行阵列基板行驱动单元的复位端 RESET与 G ( 2 )连接。
作为举例， 第一薄膜晶体管、 第二薄膜晶体管和第四薄膜晶体管为 N型薄 膜晶体管； 第三薄膜晶体管为 P型薄膜晶体管。
本实施例的薄膜晶体管的第一极和第二极可以是薄膜晶体管的源极或漏 极。
图 3为本发明第三实施例的 GOA单元的电路图。 如图 3所示， GOA的阵 列基板行驱动单元基于第一实施例提供的 GOA单元，并且为偶数行 GOA单元。 在第三实施例中， 控制模块 11 包括第一薄膜晶体管 Ml , 输出模块 12包括： 第二薄膜晶体管 M2和第三薄膜晶体管 M3, 复位模块 13包括第四薄膜晶体管 M4。
在本实施例中， 第一薄膜晶体管 Ml的栅极与上一行阵列基板驱动单元的 栅极驱动信号的输出端 G ( n-1 )连接； 第一薄膜晶体管 Ml的第一极与时钟信 号输入端 CLK连接； 第一薄膜晶体管 Ml的第二极分别与第二薄膜晶体管 M2 的栅极和第三薄膜晶体管 M3的栅极连接。
第二薄膜晶体管 M2的第一极与高电平信号端 VGH连接；第二薄膜晶体管 M2的第二极分别与第三薄膜晶体管 M3的第一极和本行栅极驱动信号输出端 G ( n )连接。
第三薄膜晶体管 M3的第二极分别与低电平信号端 VGL和第四薄膜晶体管 M4的第一极连接。
第四薄膜晶体管 M4的栅极与复位端 RESET连接； 第四薄膜晶体管 M4的 第二极与本行栅极驱动信号输出端 G ( n )连接。
本实施例中，复位端 RESET与下一行阵列基板驱动单元的栅极驱动信号的 输出端连接， 即复位端 RESET与 G ( n+1 )连接。
作为举例， 第一薄膜晶体管和第二薄膜晶体管为 P型薄膜晶体管； 第三薄 膜晶体管和第四薄膜晶体管为 N型薄膜晶体管。
本实施例的薄膜晶体管的第一极和第二极可以是薄膜晶体管的源极或漏 极。
图 4为本发明第三实施例的 GOA单元的电路图。 如图 4所示， 第四实施 例提供的 GOA单元基于第一实施例提供的 GOA单元，并且为除第一行外的奇 数行 GOA单元。 在第四实施例中， 控制模块 11 包括第一薄膜晶体管 Ml , 输 出模块 12包括： 第二薄膜晶体管 M2和第三薄膜晶体管 M3, 复位模块 13包括 第四薄膜晶体管 M4。
在本实施例中， 第一薄膜晶体管 Ml的栅极与上一行阵列基板驱动单元的 栅极驱动信号的输出端 G ( n-1 )连接； 第一薄膜晶体管 Ml的第一极与时钟信 号输入端 CLK连接； 第一薄膜晶体管 Ml的第二极分别与第二薄膜晶体管 M2 的栅极和第三薄膜晶体管 M3的栅极连接；
第二薄膜晶体管 M2的第一极与高电平信号端 VGH连接；第二薄膜晶体管 M2的第二极分别与第三薄膜晶体管 M3的第一极和本行栅极驱动信号输出端 G ( n )连接；
第三薄膜晶体管 M3的第二极分别与低电平信号端 VGL和第四薄膜晶体管 M4的第一极连接。
第四薄膜晶体管 M4的栅极与复位端 RESET连接； 第四薄膜晶体管 M4的 第二极与本行栅极驱动信号输出端 G ( n )连接；
复位端 RESET与下一行阵列基板驱动单元的栅极驱动信号的输出端连接， 即复位端 RESET与 G ( n+1 )连接。
作为举例，第一薄膜晶体管 Ml和第三薄膜晶体管 M3为 P型薄膜晶体管； 第二薄膜晶体管 M2和第四薄膜晶体管 M4为 N型薄膜晶体管。 本实施例的薄膜晶体管的第一极和第二极可以是薄膜晶体管的源极或漏 极。
图 5为本发明第五实施例的 GOA单元的电路示意图。 如图 5所示， 该电 路包括第一行和第二行 GOA单元； 在第五实施例中， 第一行和第二行 GOA单 元分别包括： 控制模块 11、 输出模块 12和复位模块 13。 此处， 第一行阵列基 板行驱动单元的控制模块 11 包括第一薄膜晶体管 Ml , 输出模块 12包括第二 薄膜晶体管 M2和第三薄膜晶体管 M3, 复位模块 13包括第四薄膜晶体管 M4; 第二行阵列基板行驱动单元的控制模块 11包括第五薄膜晶体管 M5 , 输出模块 12包括第六薄膜晶体管 M6和第七薄膜晶体管 M7, 复位模块 13包括第八薄膜 晶体管 M8。
在本实施例中， 第一薄膜晶体管 Ml的栅极与信号输入端 INPUT连接； 第 一薄膜晶体管 Ml的第一极与时钟信号输入端 CLK连接； 第一薄膜晶体管 Ml 的第二极分别与第二薄膜晶体管 M2的栅极和第三薄膜晶体管 M3的栅极连接； 第二薄膜晶体管 M2的第一极与高电平信号端 VGH连接；第二薄膜晶体管 M2的第二极分别与第三薄膜晶体管 M3的第一极和本行栅极驱动信号输出端 G ( 1 )连接；
第三薄膜晶体管 M3的第二极分别与低电平信号端 VGL和第四薄膜晶体管 M4的第一极连接；
第四薄膜晶体管 M4的栅极与第二行栅极驱动信号输出端 G ( 2 )连接； 第 四薄膜晶体管 M4的第二极与第一行栅极驱动信号输出端 G ( 1 )连接；
第五薄膜晶体管 M5的栅极与第一行栅极驱动信号输出端 G ( 1 )连接； 第 五薄膜晶体管 M5的第一极与时钟信号输入端 CLK连接； 第五薄膜晶体管 M5 的第二极分别与第六薄膜晶体管 M6的栅极和第七薄膜晶体管 M7的栅极连接； 第六薄膜晶体管 M6的第一极与高电平信号端 VGH连接；第六薄膜晶体管 M6 的第二极分别与第七薄膜晶体管 M7 的第一极和第二行栅极驱动信号输出 端 G ( 2 )连接；
第七薄膜晶体管 M7的第二极分别与低电平信号端 VGL和第八薄膜晶体管 M8的第一极连接；
第八薄膜晶体管 M8的栅极与复位端 RESET连接， 复位端 RESET与第三 行栅极驱动信号输出端 G ( 3 )连接； 第八薄膜晶体管 M8的第二极与第二行栅 极驱动信号输出端 G ( 2 )连接。 作为举例， 第一薄膜晶体管 Ml、 第二薄膜晶体管 M2、 第四薄膜晶体管 M4、 第七薄膜晶体管 M7、 第八薄膜晶体管 M8为 N型薄膜晶体管； 第三薄膜 晶体管 M3、 第五薄膜晶体管 M5、 第六薄膜晶体管 M6为 P型薄膜晶体管。
本实施例的薄膜晶体管的第一极和第二极可以是薄膜晶体管的源极或漏 极。
图 6为本发明第五实施例的阵列基板行驱动单元在工作时各信号的时序示 意图。 根据图 6所示的时序图， 以第一行阵列基板行驱动单元为例， 将阵列基 板行驱动单元的工作过程分为输出信号阶段 tl和复位阶段 t2。
在输出信号阶段 tl , 输入 INPUT为高电平， 由于第一薄膜晶体管 Ml为 N 型薄膜晶体管， 则 Ml导通， 此时时钟信号 CLK同为高电平， 由于第二薄膜晶 体管 M2为 N型薄膜晶体管， 第三薄膜晶体管 M3为 P型薄膜晶体管， 则 M2 导通， M3依旧关闭， 此时 G ( l )输出高电平；
在复位阶段 t2, 时钟信号 CLK为低电平， 则第二薄膜晶体管 M2关闭， 第 三薄膜晶体管 M3导通， 此时输出端 G ( 1 )输出低电平， 由于输出端 G ( l ) 与第五薄膜晶体管 M5的栅极连接， 且第五薄膜晶体管 M5和第六薄膜晶体管 M6为 P型薄膜晶体管， M5导通， 并且由于此时时钟信号 CLK为低电平， 则 M6导通， 此时输出端 G ( 2 )输出高电平； 由于 G ( 2 )与第四薄膜晶体管 M4 的栅极连接， 且 M4为 N型薄膜晶体管， 则 M4导通， 保持输出端 G ( l )输出 低电平， 从而完成对输出端 G ( l ) 的复位操作。
图 7为本发明第六实施例的阵列基板行驱动单元的电路示意图。 如图 7所 示， 该电路包括第 2n行、 第 2n+l行和第 2n+2行阵列基板行驱动单元。 在第 六实施例中， 第 2n行、 第 2n+l行和第 2n+2行阵列基板行驱动单元分别包括： 控制模块 11、 输出模块 12和复位模块 13。 其中， 第 2n行阵列基板行驱动单元 的控制模块 11 包括第一薄膜晶体管 Ml , 输出模块 12包括： 第二薄膜晶体管 M2和第三薄膜晶体管 M3, 复位模块 13包括第四薄膜晶体管 M4; 第 2n+l行 阵列基板行驱动单元的控制模块 11 包括第五薄膜晶体管 M5, 输出模块 12包 括： 第六薄膜晶体管 M6和第七薄膜晶体管 M7, 复位模块 13包括第八薄膜晶 体管 M8; 第 2n+2行阵列基板行驱动单元的控制模块 11 包括第九薄膜晶体管 M9, 输出模块 12包括： 第十薄膜晶体管 M10和第十一薄膜晶体管 Mil , 复位 模块 13包括第十二薄膜晶体管 M12。
在本实施例中， 第一薄膜晶体管 Ml的栅极与上一行栅极驱动信号输出端 G ( 2n-l )连接； 第一薄膜晶体管 Ml的第一极与时钟信号输入端 CLK连接； 第一薄膜晶体管 Ml的第二极分别与第二薄膜晶体管 M2的栅极和第三薄膜晶 体管 M3的栅极连接；
第二薄膜晶体管 M2的第一极与高电平输出端 VGH连接；第二薄膜晶体管 M2的第二极分别与第三薄膜晶体管 M3的第一极和本行栅极驱动信号输出端 G ( 2n )连接；
第三薄膜晶体管 M3的第二极分别与低电平输出端 VGL和第四薄膜晶体管 M4的第一极连接；
第四薄膜晶体管 M4的栅极与下一行栅极驱动信号输出端 G ( 2n+l )连接； 第四薄膜晶体管 M4的第二极与本行栅极驱动信号输出端 G ( n )连接；
第五薄膜晶体管 M5的栅极与上一行栅极驱动信号输出端 G ( 2n )连接； 第五薄膜晶体管 M5 的第一极与时钟信号输入端 CLK连接； 第五薄膜晶体管 M5的第二极分别与第六薄膜晶体管 M6的栅极和第七薄膜晶体管 M7的栅极连 接；
第六薄膜晶体管 M6的第一极与高电平输出端 VGH连接；第六薄膜晶体管 M6的第二极分别与第七薄膜晶体管 M7的第一极和本行栅极驱动信号输出端 G ( 2n+l )连接；
第七薄膜晶体管 M7的第二极分别与低电平输出端 VGL和第八薄膜晶体管 M8的第一极连接；
第八薄膜晶体管 M8的栅极与下一行栅极驱动信号输出端 G ( 2n+2 )连接； 第八薄膜晶体管 M8的第二极与本行行栅极驱动信号输出端 G ( 2+1 )连接； 第九薄膜晶体管 M9的栅极与上一行栅极驱动信号输出端 G ( 2n+l )连接； 第九薄膜晶体管 M9 的第一极与时钟信号输入端 CLK连接； 第九薄膜晶体管 M9的第二极分别与第十薄膜晶体管 M10的栅极和第十一薄膜晶体管 Mil的栅 极连接；
第十薄膜晶体管 M10的第一极与高电平输出端 VGH连接； 第十薄膜晶体 管 M10的第二极分别与第十一薄膜晶体管 Mil的第一极和本行栅极驱动信号 输出端 G ( 2n+2 )连接；
第十一薄膜晶体管 Mil的第二极分别与低电平输出端 VGL和第十二薄膜 晶体管 M12的第一极连接；
第十二薄膜晶体管 M12的栅极与下一行栅极驱动信号输出端 G ( 2n+3 )连 接； 第十二薄膜晶体管 M12的第二极与本行行栅极驱动信号输出端 G ( 2+2 ) 连接。
作为举例， 第一薄膜晶体管 Ml、 第二薄膜晶体管 M2、 第五薄膜晶体管 M5、 第七薄膜晶体管 M7、 第九薄膜晶体管 M9、 第十薄膜晶体管 M10为 P型 薄膜晶体管； 第三薄膜晶体管 M3、 第四薄膜晶体管 M4、 第六薄膜晶体管 M6、 第八薄膜晶体管 M8、 第十一薄膜晶体管 Mll、 第十二薄膜晶体管 M12为 N型 薄膜晶体管。
图 8为本发明第六实施例的阵列基板行驱动单元在工作时各信号的时序示 意图。 根据图 6的时序图， 将阵列基板行驱动单元的工作过程分为 tl、 t2和 t3 阶段， tl阶段为第 2n行阵列基板行驱动单元的输出信号阶段； t2阶段为第 2n+l 行阵列基板行驱动单元的输出信号阶段; t3阶段为第 2n+2行阵列基板行驱动单 元的输出信号阶段； 相应地， 每一行阵列基板行驱动的输出信号阶段均为上一 行阵列基板行驱动单元的复位阶段。
在 tl阶段， 由于 G ( 2n-l ) 为低电平， 且第一薄膜晶体管 Ml为 P型薄膜 晶体管， 则 Ml导通， 此时时钟 CLK同为低电平， 由于第二薄膜晶体管 M2为 P型薄膜晶体管， 第三薄膜晶体管 M3为 N型薄膜晶体管， 则 M2导通， M3依 旧关闭， 此时 G ( 2n )输出高电平；
在 t2阶段， 时钟仪器 CLK为高电平， 则第二薄膜晶体管 M2关闭， 第三 薄膜晶体管 M3导通， 此时 G ( 2n )输出低电平， 由于 G ( 2n )与第五薄膜晶 体管 M5的栅极连接， 且 M5为 P型薄膜晶体管， 则 M5导通， 并且由于此时 CLK为高电平， 且第六薄膜晶体管 M6为 N型薄膜晶体管， 第七薄膜晶体管 M7为 P型薄膜晶体管， 因此， M6导通， M7关闭， G ( 2n+l )输出高电平； 由于 G ( 2n+l )与第四薄膜晶体管 M4的栅极连接， 且 M4为 N型薄膜晶体管， 则 M4导通， 保持 G ( 2n )输出低电平， 从而完成对 G ( 2n ) 的复位操作； 在 t3阶段，时钟信号 CLK为低电平，则 M6关闭， M7导通，此时 G( 2n+l ) 输出低电平， 由于 G ( 2n+l )与第九薄膜晶体管 M9的栅极连接， 且 M9为 P 型薄膜晶体管， 则 M9导通， 并且由于此时 CLK为低电平， 第十薄膜晶体管 M10为 P型薄膜晶体管， 第十一薄膜晶体管 Mil为 N型薄膜晶体管， 则 M9 导通， M10关闭， G ( 2n+2 )输出高电平； 由于 G ( 2n+2 )与第八薄膜晶体管 M8的栅极连接， 且 M8为 N型薄膜晶体管， 则 M8导通， 保持 G ( 2n+l )输 出低电平， 从而完成对 G ( 2n+l ) 的复位操作。 基于上述阵列基板行驱动单元， 本发明实施例还提供了一种阵列基板行驱 动电路， 包括一个以上上述阵列基板行驱动单元； 并且，
除第一行阵列基板行驱动单元外， 每一行阵列基板行驱动单元的信号输入 端均与上一行阵列基板行驱动单元的栅极信号输出端连接；
除最后一行的阵列基板行驱动单元外， 每一行阵列基板行驱动单元的复位 端均与下一行阵列基板行驱动单元的栅极信号输出端连接。
在此还记载了按照本发明实施例的一种显示装置， 该显示装置包括上述显 示面板。 该显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液 晶显示器、 数码相框、 手机、 平板电脑等任何具有显示功能的产品或部件。
以上所述， 仅为本发明的示例性实施例而已， 并非用于限定本发明的保护 范围。 凡在本发明的精神和范围之内所作的任何修改、 等同替换和改进等， 均 包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1、 一种阵列基板行驱动单元， 包括：
控制模块， 用于在上一行阵列基板行驱动单元的栅极驱动信号或起始输入 信号的控制下输出时钟信号；
输出模块， 与所述控制连接， 用于在所述控制模块输出的时钟信号的控制 下， 将高电压信号输出作为本行栅极驱动信号， 以及在所述控制模块输出的时 钟信号的控制下， 将低电压信号进行输出；
复位模块， 与所述输出模块连接， 用于在下一行阵列基板行驱动单元的栅 极驱动信号的控制下， 对所述本级栅极驱动信号进行复位。
2、 根据权利要求 1所述的阵列基板行驱动单元， 其中， 所述控制模块包括 第一薄膜晶体管， 所述输出模块包括： 第二薄膜晶体管和第三薄膜晶体管， 所 述复位模块包括第四薄膜晶体管； 其中，
所述第一薄膜晶体管的栅极与上一行阵列基板行驱动单元的栅极驱动信号 输出端或起始输入信号连接， 所述第一薄膜晶体管的第一极与时钟信号输入端 连接， 所述第一薄膜晶体管的第二极分别与所述第二薄膜晶体管的栅极和第三 薄膜晶体管的栅极连接；
所述第二薄膜晶体管的第一极与高电平输出端连接， 所述第二薄膜晶体管 的第二极分别与所述第三薄膜晶体管的第二极和本行栅极驱动信号输出端连 接；
所述第三薄膜晶体管的第二极分别与低电平输出端和所述第四薄膜晶体管 的第一极连接；
所述第四薄膜晶体管的栅极与下一行阵列基板驱动单元的栅极驱动信号的 输出端连接， 所述第四薄膜晶体管的第二极与本行栅极驱动信号输出端连接。
3、 根据权利要求 2所述的阵列基板行驱动单元， 其中，
第一行阵列基板行驱动单元的所述第一薄膜晶体管、 第二薄膜晶体管和第 四薄膜晶体管为 N型薄膜晶体管， 所述第三薄膜晶体管为 P型薄膜晶体管。
4、 根据权利要求 3所述的阵列基板行驱动单元， 其中，
除第一行阵列基板行驱动单元外， 奇数行阵列基板行驱动单元的所述第一 薄膜晶体管和第三薄膜晶体管为 P型薄膜晶体管， 所述第二薄膜晶体管和第四 薄膜晶体管为 N型薄膜晶体管； 偶数行阵列基板行驱动单元的所述第一薄膜晶体管和第二薄膜晶体管为 P 型薄膜晶体管， 所述第三薄膜晶体管和第四薄膜晶体管为 N型薄膜晶体管。
5、一种阵列基板行驱动电路， 所述阵列基板行驱动电路包括一个以上如权 利要求 1至 4任一项所述的阵列基板行驱动单元；
除第一行阵列基板行驱动单元外， 每一行阵列基板行驱动单元的信号输入 端均与上一行阵列基板行驱动单元的栅极信号输出端连接；
除最后一行的阵列基板行驱动单元外， 每一行阵列基板行驱动单元的复位 端均与下一行阵列基板行驱动单元的栅极信号输出端连接。
6、 一种显示装置， 其中， 所述显示装置包括如权利要求 5所述的阵列基板 行驱动电路。
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