WO2015016007A1 - Display device and method for driving same - Google Patents

Display device and method for driving same Download PDF

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Publication number
WO2015016007A1
WO2015016007A1 PCT/JP2014/068012 JP2014068012W WO2015016007A1 WO 2015016007 A1 WO2015016007 A1 WO 2015016007A1 JP 2014068012 W JP2014068012 W JP 2014068012W WO 2015016007 A1 WO2015016007 A1 WO 2015016007A1
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WIPO (PCT)
Prior art keywords
voltage
display device
terminal
transistor
transistors
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PCT/JP2014/068012
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French (fr)
Japanese (ja)
Inventor
成継 山中
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シャープ株式会社
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Publication of WO2015016007A1 publication Critical patent/WO2015016007A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display

Definitions

  • the present invention relates to a display device and a driving method thereof, and more particularly, to a display device that displays a plurality of subframes in one frame period and a driving method thereof.
  • organic EL Electro Luminescence
  • the organic EL display device includes a plurality of pixel circuits arranged two-dimensionally.
  • a typical pixel circuit of an organic EL display device includes one organic EL element and one drive transistor.
  • the organic EL element is a light emitting element that emits light with a luminance corresponding to the amount of current passing therethrough.
  • the drive transistor is provided in series with the organic EL element, and controls the amount of current flowing through the organic EL element.
  • a field sequential color display device performs color display by displaying a plurality of subframes in one frame period.
  • the backlight emission color is switched to red, green, and blue every subframe period, and 3 subframes (red, green, and blue are supported per frame period) Liquid crystal display devices that display subframes) are known.
  • Patent Documents 1 and 2 describe a field sequential color organic EL display device.
  • the display device described in Patent Document 1 displays three subframes in one frame period.
  • FIG. 18 is a circuit diagram of a pixel matrix of the display device described in FIG.
  • Each pixel circuit includes an organic EL element OLEDr that emits red light, an organic EL element OLEDg that emits green light, and an organic EL element OLEDb that emits blue light.
  • the light emission signal lines E1r, E2r, E3r are selected in the first subframe period, the light emission signal lines E1g, E2g, E3g are selected in the second subframe period, and the light emission signal lines E1b, E2b, E3b are selected in the third subframe period. Is selected.
  • color display can be performed by switching the color of the pixel for each pixel and for each subframe.
  • the circuit amount and the layout area can be reduced by controlling the luminance of a plurality of organic EL elements using one driving transistor.
  • Patent Document 3 describes an organic EL display device including a pixel circuit including a plurality of drive transistors.
  • FIG. 19 is a block diagram of the pixel circuit described in FIG. 19 includes a first semiconductor element 91 in which an output current characteristic with respect to an input variable as a gradation signal exhibits a saturation characteristic, and a second semiconductor in which an output current characteristic with respect to the input variable as a gradation signal exhibits a linear characteristic.
  • An element 92 and a light emitting element 93 are included.
  • the first current path that outputs the current I1 determined by the first semiconductor element 91 and the second current path that outputs the current I2 determined by the second semiconductor element 92 merge to emit light. It is connected to the current path of the element 93. According to the organic EL display device including the pixel circuit 90, it is possible to generate higher peak luminance while sufficiently ensuring a voltage range for performing gradation display within a predetermined driver output range.
  • each organic EL element emits light only in one subframe period. For this reason, the length of the light emission period of each organic EL element is 1 / k (k is one frame period) as compared with an organic EL display device that is not a field sequential color system (hereinafter referred to as a general organic EL display device). The number of subframes displayed). Therefore, if the other conditions are the same, the luminance of the pixel of the field sequential color organic EL display device is 1 / k compared to a general organic EL display device.
  • the luminance of the organic EL element is proportional to the square of the data voltage written in the pixel circuit. For this reason, in the field sequential color organic EL display device, in order to make the maximum luminance of the pixel the same as that of a general organic EL display device, the amplitude of the data voltage is ⁇ compared with that of a general organic EL display device. It is necessary to make k times or more. For example, when three subframes are displayed in one frame period, the amplitude of the data voltage needs to be ⁇ 3 times or more as compared with a general organic EL display device.
  • the field sequential color organic EL display device has a problem that the power consumption of the data line driving circuit increases when the amplitude of the data voltage is increased in order to increase the maximum luminance of the pixel. This problem becomes more prominent in an organic EL display device having a function of making the luminance of a pixel higher than the maximum luminance in gradation display.
  • an object of the present invention is to provide a field sequential color display device in which the maximum luminance of a pixel is increased without increasing the power consumption of a driving circuit.
  • a first aspect of the present invention is a display device that displays a plurality of subframes in one frame period, A display unit including a plurality of pixel circuits arranged two-dimensionally; A drive circuit that performs writing and light emission control on the plurality of pixel circuits in each sub-frame period, The pixel circuit includes: A plurality of light emitting elements that emit light in different colors; A first drive transistor that applies a first power supply voltage to one conduction terminal and outputs a current corresponding to the voltage of the control terminal; A second power supply voltage is applied to one conduction terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and a second drive transistor that outputs a current according to the voltage of the control terminal; A selection circuit for switching which of the plurality of light emitting elements allows the current output from the first and second drive transistors to flow; The first drive transistor operates in a saturation region when the voltage at the control terminal is within a predetermined range, and the second drive transistor is within a first range where the voltage at the control terminal
  • the voltage in the first range is a voltage used in gradation display
  • the voltage in the second range is a voltage corresponding to a luminance higher than the maximum luminance in gradation display.
  • control terminals of the first and second driving transistors are connected to the same node.
  • the pixel circuit includes an input transistor that supplies a data voltage output from the drive circuit to control terminals of the first and second drive transistors, and a capacitive element that holds a voltage of the control terminal of the first and second drive transistors. And further comprising.
  • the capacitive element is provided between a control terminal of the first and second drive transistors and one conduction terminal of the first drive transistor.
  • a sixth aspect of the present invention is the fourth aspect of the present invention,
  • the capacitive element is provided between a control terminal of the first and second drive transistors and the other conduction terminal.
  • the capacitive element is provided between a control terminal and a control line of the first and second drive transistors.
  • control terminals of the first and second drive transistors are configured to be able to apply different voltages.
  • the selection circuit includes a plurality of light emission control transistors each having a control terminal provided between the other conduction terminal of the first and second drive transistors and the plurality of light emitting elements and connected to a light emission control line. It is characterized by including.
  • the display unit further includes a plurality of scanning lines, a plurality of data lines, and a plurality of light emission control lines
  • the driving circuit applies a data voltage corresponding to a video signal to the plurality of data lines in each line period of each subframe period, and a scanning line driving circuit that sequentially selects the plurality of scanning lines in each subframe period.
  • An eleventh aspect of the present invention includes a plurality of pixel circuits, a plurality of scanning lines, a plurality of data lines, and a plurality of light emission control lines arranged two-dimensionally, and a plurality of sub-circuits in one frame period.
  • a driving method of a display device for displaying a frame Sequentially selecting the plurality of scan lines in each subframe period; Applying a data voltage corresponding to a video signal to each of the plurality of data lines in each line period of each subframe period; Driving the plurality of light emission control lines in each subframe period,
  • the pixel circuit includes a plurality of light emitting elements that emit light of different colors, a first drive transistor that outputs a current corresponding to a voltage of a control terminal by applying a first power supply voltage to one conduction terminal, and one conduction A second power supply voltage is applied to the terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and the second drive transistor outputs a current corresponding to the voltage of the control terminal;
  • the first drive transistor operates in a saturation region when the voltage at the control terminal is within a predetermined range, and the second drive transistor is within a first
  • the second drive transistor that operates in the saturation region or the linear region according to the voltage of the control terminal is provided.
  • the maximum luminance of the pixel can be increased by increasing the current flowing through the light emitting element without increasing the amplitude of the data voltage output from the driver circuit. Therefore, in the field sequential color display device, the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit.
  • the first and second drive transistors operate in the saturation region during gradation display, and the first drive transistor is saturated when the luminance is higher than the maximum luminance in gradation display.
  • the second driving transistor operates in a linear region. In this way, the operation of the second driving transistor can be switched to make the luminance of the pixel higher than the maximum luminance in gradation display.
  • the third aspect of the present invention by applying the same voltage to the control terminals of the first and second drive transistors, it is easy to increase the maximum luminance of the pixel without increasing the power consumption of the drive circuit. Can get to.
  • the data voltage output from the drive circuit is applied to the control terminals of the first and second drive transistors, and the applied voltage is applied. Can be held.
  • the first and second drive transistors by providing a capacitive element between the control terminal of the first and second drive transistors and one conduction terminal of the first drive transistor, the first and second drive transistors The voltage of the control terminal can be held.
  • the voltage at the control terminal of the first and second drive transistors is reduced. Can be held.
  • the seventh aspect of the present invention by providing a capacitive element between the control terminal of the first and second drive transistors and the control line, the voltage at the control terminal of the first and second drive transistors is held. be able to.
  • the current flowing through the light emitting element is controlled with a high degree of freedom, and the luminance of the pixel is high. Can be controlled.
  • a selection circuit is configured to switch a current output from the first and second drive transistors to which of the plurality of light emitting elements using a plurality of light emission control transistors. Can do.
  • FIG. 5 is a circuit diagram of a first example of a data holding unit shown in FIG. 4.
  • FIG. 5 is a circuit diagram of a second example of the data holding unit shown in FIG. 4.
  • FIG. 5 is a circuit diagram of a third example of the data holding unit shown in FIG. 4.
  • FIG. 5 is a circuit diagram illustrating an example of the pixel circuit illustrated in FIG. 4.
  • FIG. 9 is an equivalent circuit diagram of the pixel circuit shown in FIG. 8.
  • FIG. 9 is a characteristic diagram illustrating a relationship between a voltage difference (Vgs ⁇ Vth) and a voltage Vds in the pixel circuit illustrated in FIG. 8.
  • FIG. 9 is a characteristic diagram illustrating a relationship between a gate voltage Vg and a voltage Vds in the pixel circuit illustrated in FIG. 8.
  • FIG. 9 is a characteristic diagram illustrating a relationship between a gate voltage Vg and a current Ioled in the pixel circuit illustrated in FIG. 8. It is a circuit diagram of the pixel matrix of the conventional display apparatus. It is a block diagram of a pixel circuit included in a conventional display device.
  • FIG. 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention.
  • a display device 1 shown in FIG. 1 includes a display unit 2, a display control circuit 3, a scanning line drive circuit 4, a data line drive circuit 5, and a light emission control line drive circuit 6.
  • the display device 1 is a field sequential color organic EL display device.
  • the display device 1 divides one frame period into three subframe periods (hereinafter referred to as first to third subframe periods), and displays three subframes in one frame period, thereby performing color display. Do.
  • m and n are integers of 2 or more.
  • the display unit 2 includes m scanning lines SL1 to SLm, n data lines DL1 to DLn, 3m light emission control lines, and (m ⁇ n) pixel circuits 10.
  • Each pixel circuit 10 corresponds to one pixel.
  • EL1, EL2,..., ELm represent three emission control lines corresponding to the scanning lines SL1 to SLm, respectively.
  • the scanning lines SL1 to SLm and the 3m light emission control lines are arranged in parallel to each other.
  • the data lines DL1 to DLn are arranged in parallel to each other and orthogonal to the scanning lines SL1 to SLm.
  • the scanning lines SL1 to SLm and the data lines DL1 to DLn intersect at (m ⁇ n) locations.
  • the (m ⁇ n) pixel circuits 10 are two-dimensionally arranged corresponding to the intersections of the scanning lines SL1 to SLm and the data lines DL1 to DLn.
  • the pixel circuit 10 includes three organic EL elements that respectively emit red, green, and blue light, and is connected to one scanning line, one data line, and three light emission control lines. Three types of power supply voltages are supplied to the pixel circuit 10 using power supply lines (not shown).
  • a pixel circuit arranged corresponding to the intersection of the scanning line SLi and the data line DLj (i is an integer of 1 to m, j is an integer of 1 to n) is referred to as P (i, j).
  • the display control circuit 3 controls the scanning line driving circuit 4, the data line driving circuit 5, and the light emission control line driving circuit 6. More specifically, the display control circuit 3 outputs a control signal Cs to the scanning line drive circuit 4, outputs a control signal Cd and a video signal D1 to the data line drive circuit 5, and emits a control line drive circuit. 6 outputs a control signal Ce.
  • one frame period includes three subframe periods, and one subframe period includes m line periods (horizontal periods).
  • the control signals Cs and Ce include a signal indicating the start of the frame period, a signal indicating the start of the subframe period, a signal indicating the start of the line period, and the like.
  • the control signal Cd includes a signal indicating the head of the line period, a data clock signal, a data latch signal, and the like.
  • the scanning line driving circuit 4 drives the scanning lines SL1 to SLm based on the control signal Cs. More specifically, the scanning line driving circuit 4 selects one scanning line from the scanning lines SL1 to SLm in each line period of each subframe period, and selects a selected voltage (here, a high voltage) Level voltage). The scanning line driving circuit 4 sequentially selects the scanning lines SL1 to SLm in each subframe period by switching the scanning line to be selected for each line period.
  • the data line driving circuit 5 drives the data lines DL1 to DLn based on the control signal Cd and the video signal D1. More specifically, the data line driving circuit 5 generates n data voltages based on the video signal D1 in each line period of each subframe period, and the generated n data voltages are respectively applied to the data lines DL1 to DLn. Apply.
  • the light emission control line drive circuit 6 drives 3m light emission control lines based on the control signal Ce. More specifically, the light emission control line drive circuit 6 selects one light emission control line from among the three light emission control lines corresponding to the selected scanning line, and supplies the selected light emission control line to a predetermined time (The selection voltage is applied only for a time shorter than one subframe period (hereinafter referred to as time Te).
  • the organic EL elements in the pixel circuit 10 selectively emit light according to control by the light emission control line driving circuit 6.
  • n pixel circuits 10 connected to the scanning line SLi are selected at once.
  • the n data voltages applied to the data lines DL1 to DLn are written to the selected n pixel circuits 10, respectively.
  • the light emission control line driving circuit 6 applies a selection voltage to one light emission control line selected from the three light emission control lines corresponding to the scanning line SLi for the time Te.
  • one organic EL element corresponding to the selected light emission control line emits light for a time Te.
  • FIG. 2 is a diagram showing a display pattern sequence of the display device 1.
  • FIG. 3 is a diagram showing a part of FIG. In FIG. 2, the square represents one pixel circuit, and the characters in the square represent the colors assigned to the pixel circuits.
  • (m ⁇ n) pixel circuits are classified into first to third groups so that pixel circuits adjacent to the upper right and lower left belong to the same group.
  • the groups to which the pixel circuits P (1,1) to P (1,3) belong are referred to as first to third groups, respectively.
  • red, green, and blue are respectively assigned in the first subframe
  • green, blue, and red are respectively assigned in the second subframe. In the frame, blue, red, and green are assigned.
  • the three organic EL elements in the pixel circuit 10 selectively emit light in each subframe period according to the display pattern sequence.
  • the actual color of the pixel circuit 10 (hereinafter referred to as display color) changes according to the data voltage written in the pixel circuit 10. For example, when red is assigned to the pixel circuit P (1,1) in the first subframe, only the organic EL element that emits red light in the pixel circuit P (1,1) emits light in the first subframe period. To do.
  • the display color of the pixel circuit P (1,1) in the first subframe period is a color corresponding to the red video signal.
  • the scanning line driving circuit 4 and the data line driving circuit 5 write data voltages to the (m ⁇ n) pixel circuits 10 in one subframe period.
  • the light emission control line drive circuit 6 controls the light emission state of the organic EL elements in the (m ⁇ n) pixel circuits 10 in each subframe period.
  • the display device 1 displays one subframe in one subframe period.
  • the display device 1 performs color display by displaying three subframes in one frame period.
  • the scanning line driving circuit 4, the data line driving circuit 5, and the light emission control line driving circuit 6 function as a driving circuit that performs writing and light emission control on the plurality of pixel circuits 10 in each subframe period. .
  • FIG. 4 is a diagram showing a configuration of the display unit 2.
  • FIG. 4 shows the configuration of the pixel circuits P (1,1) to P (1,3), P (2,1) to P (2,3), P (3,1) to P (3,3). Is described.
  • the other part of the display unit 2 has the same configuration as in FIG.
  • the pixel circuit P (i, j) is connected to the scanning line SLi, the data line DLj, and the three light emission control lines ELia to ELic.
  • the pixel circuit 10 includes a data holding unit 20, three N-channel transistors Qr, Qg, Qb, and three organic EL elements Lr, Lg, Lb.
  • the organic EL elements Lr, Lg, and Lb are light emitting elements that emit red, green, and blue light, respectively.
  • the data holding unit 20 holds the voltage applied to the data line DLj during the selection period of the scanning line SLi.
  • any of the circuits shown in FIGS. 5 to 7 is used for the data holding unit 20.
  • Each of the data holding units 21 to 23 shown in FIGS. 5 to 7 includes N-channel transistors Q1, Q2, Q3, and a capacitor C1.
  • the first high-level power supply voltage Van1 is applied to the drain terminal of the transistor Q1
  • the second high-level power supply voltage Van2 is applied to the drain terminal of the transistor Q2.
  • the source terminal of the transistor Q1 and the source terminal of the transistor Q2 are connected to the drain terminals of the transistors Qr, Qg, and Qb (described as “to lighting control unit” in the figure).
  • the gate terminal of the transistor Q3 is connected to the scanning line SLi, and one conduction terminal of the transistor Q3 is connected to the data line DLj.
  • the other conduction terminal of transistor Q3 is connected to the gate terminal of transistor Q1, the gate terminal of transistor Q2, and one terminal of capacitor C1.
  • the other terminal of the capacitor C1 is connected to the drain terminal of the transistor Q1.
  • the data holding units 22 and 23 are obtained by changing the connection destination of the other terminal of the capacitor C1 with respect to the data holding unit 21.
  • the other terminal of the capacitor C1 is connected to the source terminals of the transistors Q1 and Q2.
  • the data holding unit 23 (FIG. 7), the other terminal of the capacitor C1 is connected to the control line CLi.
  • the display device 1 including the pixel circuit 10 including the data holding unit 23 is provided with m control lines CL1 to CLm parallel to the scanning lines SL1 to SLm, and a predetermined control voltage is applied to the control lines CL1 to CLm. Applied.
  • the source terminal of the transistor Q1 is connected to the source terminal of the transistor Q2, and the gate terminal of the transistor Q1 and the gate terminal of the transistor Q2 are connected to the same node.
  • the capacitor C1 is provided between the gate terminals of the transistors Q1 and Q2 and the drain terminal of the transistor Q1.
  • the capacitor C1 is provided between the gate terminals and the source terminals of the transistors Q1 and Q2.
  • the capacitor C1 is provided between the gate terminals of the transistors Q1 and Q2 and the control line CLi. Whichever data holding unit is used, the gate voltages of the transistors Q1 and Q2 can be held.
  • the source terminals of the transistors Qr, Qg, and Qb are connected to the anode terminals of the organic EL elements Lr, Lg, and Lb, respectively.
  • a low level power supply voltage Vca is applied to the cathode terminals of the organic EL elements Lr, Lg, and Lb.
  • the gate terminals of the transistors Qr, Qg, and Qb are connected to any one of the light emission control lines ELia to ELic in accordance with the display pattern sequence shown in FIG. Specifically, the gate terminals of the transistors Qr, Qg, and Qb in the first group of pixel circuits P (i, j) are connected to the light emission control lines ELia, ELib, and ELic, respectively.
  • the gate terminals of the transistors Qr, Qg, and Qb in the second group of pixel circuits P (i, j) are connected to the light emission control lines ELic, ELia, and ELib, respectively.
  • the gate terminals of the transistors Qr, Qg, Qb in the third group of pixel circuits P (i, j) are connected to the light emission control lines ELib, ELic, ELia, respectively.
  • the pixel circuit P (1,1) has the configuration shown in FIG.
  • the transistor Q1 functions as a first drive transistor that outputs a current corresponding to the voltage of the control terminal when a first power supply voltage is applied to one conduction terminal.
  • a second power supply voltage is applied to one conduction terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and the second drive transistor outputs a current corresponding to the voltage of the control terminal.
  • the transistor Q3 functions as an input transistor that applies the data voltage output from the drive circuit to the control terminals of the first and second drive transistors.
  • the capacitor C1 functions as a capacitive element that holds the voltage at the control terminals of the first and second drive transistors.
  • the transistors Qr, Qg, and Qb function as a selection circuit that switches to which of the plurality of light emitting elements the current output from the first and second drive transistors flows.
  • FIG. 9 and FIG. 10 are diagrams showing a configuration example of the power supply wiring.
  • FIGS. 9 and 10 show configuration examples of power supply wirings for supplying the first and second high-level power supply voltages Van1 and Van2.
  • the first trunk wiring for supplying the first high-level power supply voltage Van1 is provided above the arrangement area of the pixel circuit 10 in parallel with the scanning lines SL1 to SLm (not shown);
  • the first and second trunk lines are provided below the arrangement area of the pixel circuit 10.
  • a first branch wiring having both ends connected to the first trunk wiring is provided, and the first branch wiring is connected to the pixel circuit 10 in one column.
  • a second branch wiring having both ends connected to the second trunk wiring is provided, and the second branch wiring is connected to the pixel circuit 10 in one column.
  • the first trunk wiring is provided in parallel with the scanning lines SL1 to SLm (not shown) on the upper side and the lower side of the arrangement area of the pixel circuit 10, and the second trunk wiring is provided on the pixel circuit 10.
  • the data lines DL1 to DLn (not shown) are provided on the left side and the right side of the arrangement region in parallel.
  • a first branch wiring having both ends connected to the first trunk wiring is provided, and the first branch wiring is connected to the pixel circuit 10 in one column.
  • a second branch wiring having both ends connected to the second trunk wiring is provided on the upper side of each row of the pixel circuit 10, and the second branch wiring is connected to the pixel circuit 10 in one row.
  • the arrangement position of the power supply wiring may be rotated by 90 degrees.
  • first and second trunk wirings are provided on the left and right sides of the arrangement area of the pixel circuit 10, and both ends are connected to the first trunk wiring on the upper side (or lower side) of each row of the pixel circuit 10.
  • a first branch wiring connected to the pixel circuit 10 in the row is provided, and both ends of the pixel circuit 10 are connected to the second trunk wiring on the lower side (or upper side) of each row, and the first branch wiring connected to the pixel circuit 10 in the first row is connected.
  • a two-branch wiring may be provided.
  • the arrangement positions of the first trunk wiring and the first branch wiring may be interchanged with the arrangement positions of the second trunk wiring and the second branch wiring.
  • the power supply wiring for supplying the first high-level power supply voltage Van1 and the power supply wiring for supplying the second high-level power supply voltage Van2 may be formed in the same wiring layer, and part of one power supply wiring may be connected to the other power supply. You may form in the same wiring layer as wiring.
  • FIG. 11 is a timing chart of the display device 1.
  • the scanning lines SL1 to SLm are sequentially selected one line period at a time, and a selection voltage (high level voltage) is applied to the selected scanning line over one line period.
  • a selection voltage high level voltage
  • the light emission control line ELia is selected after the scanning line SLi is selected.
  • the light emission control line ELib is selected after the scanning line SLi is selected.
  • the light emission control line ELic is selected after the scanning line SLi is selected.
  • a selection voltage is applied to the selected light emission control line for a time Te.
  • FIG. 12 is a diagram showing the types of data voltages applied to the data lines during the scanning line selection period and the light emission control lines selected after the scanning line selection period.
  • data voltages corresponding to red, green, and blue video signals are referred to as R voltage, G voltage, and B voltage, respectively.
  • the R voltage, the G voltage, and the B voltage are applied to the data lines DL1 to DL3, respectively, and these voltages are applied to the pixel circuits P (1, 1) to P ( 1, 3) respectively.
  • the light emission control line EL1a is selected, the transistor Qr in the pixel circuit P (1,1), the transistor Qg in the pixel circuit P (1,2), and the transistor Qb in the pixel circuit P (1,3). Turns on.
  • the organic EL element Lr in the pixel circuit P (1,1) emits light with a luminance corresponding to the R voltage
  • the organic EL element Lg in the pixel circuit P (1,2) emits light with a luminance corresponding to the G voltage
  • the organic EL element Lb in the pixel circuit (1, 3) emits light with a luminance corresponding to the B voltage.
  • the G voltage, the B voltage, and the R voltage are applied to the data lines DL1 to DL3, respectively, and these voltages are applied to the pixel circuits P (2, 1) to P ( 2, 3) respectively.
  • the light emission control line EL2a is selected, and the transistor Qg in the pixel circuit P (2,1), the transistor Qb in the pixel circuit P (2,2), and the transistor Qr in the pixel circuit P (2,3). Turns on.
  • the organic EL element Lg in the pixel circuit P (2, 1) emits light with a luminance corresponding to the G voltage
  • the organic EL element Lb in the pixel circuit P (2, 2) emits light with a luminance corresponding to the B voltage
  • the organic EL element Lr in the pixel circuit P (2, 3) emits light with a luminance corresponding to the R voltage.
  • the organic EL element Lb in the pixel circuit P (3, 1) emits light with a luminance corresponding to the B voltage
  • the pixel circuit P (3, 2 ) In the pixel circuit P (3, 3) emits light with a luminance corresponding to the G voltage.
  • the display colors of the pixel circuits P (1,1), P (2,3), P (3,2) are colors corresponding to the red video signal (from black to red).
  • the display color of the pixel circuits P (1,2), P (2,1), P (3,3) is a color corresponding to the green video signal (in the range from black to green).
  • the display colors of the pixel circuits P (1,3), P (2,2), P (3,1) are colors corresponding to the blue video signal (colors in the range from black to blue). )become.
  • the display device 1 operates in the second and third subframe periods in the same manner as in the first subframe period. In this way, the display device 1 displays three subframes in one frame period according to the display pattern sequence shown in FIG.
  • FIG. 13 is a diagram showing a range of gradation, gate voltage, and luminance in the display device 1.
  • the gradation changes within the range from the minimum gradation to the maximum gradation.
  • the gate voltages of the transistors Q1 and Q2 change in the range from Vgmin to Vgz
  • the luminance of the organic EL element is in the range from the minimum luminance to the maximum gradation luminance (maximum luminance in gradation display). It changes with.
  • the display device 1 may make the luminance of the organic EL element higher than the maximum gradation luminance depending on the display image.
  • the maximum value of luminance used in the display device 1 is referred to as maximum luminance, and the gate voltages of the transistors Q1, Q2 corresponding to the maximum luminance are referred to as Vgmax.
  • the maximum luminance is set to be not less than 1 and not more than several times the maximum gradation luminance.
  • the brightness higher than the maximum gradation brightness is used when, for example, a small point with high brightness is displayed in a low brightness area.
  • FIG. 14 is an equivalent circuit diagram of the pixel circuit 10 during the light emission period.
  • the transistor Q3 is turned off, one of the transistors Qr, Qg, and Qb is turned on, and the other two are turned off.
  • An organic EL element L1 illustrated in FIG. 14 represents an element connected to an on-state transistor among the organic EL elements Lr, Lg, and Lb.
  • the gate voltages of the transistors Q1 and Q2 are Vg
  • the source voltages of the transistors Q1 and Q2 are Vs
  • the threshold voltages of the transistors Q1 and Q2 are Vth1 and Vth2, respectively
  • the light emission threshold voltage of the organic EL element L1 is Vtho.
  • the gate voltage Vg is equal to the data voltage applied to the data line DLj by the data line driving circuit 5.
  • the transistor Q1 outputs a current Ids1 corresponding to the gate voltage Vg.
  • the transistor Q2 outputs a current Ids2 corresponding to the same gate voltage Vg.
  • the currents Ids1 and Ids2 merge to become a current Ioled that flows through the organic EL element L1. As the gate voltage Vg increases, the currents Ids1 and Ids2 increase and the current Ioled also increases.
  • the transistor Q1 operates in the saturation region when the gate voltage Vg is in the range from Vgmin to Vgmax.
  • the transistor Q2 operates in the saturation region when the gate voltage Vg is in the range from Vgmin to Vgz, and operates in the linear region when the gate voltage Vg is in the range from Vgz to Vgmax.
  • Vds1 Van1 ⁇ Vs
  • Vds2 Van2 ⁇ Vs
  • the following expressions (3a) and (3b) are derived.
  • Vg ⁇ Van2 + Vth2 (3b) Therefore, when the gate voltage Vg is in the range from Vgmin to Vgz, the conditions for both of the transistors Q1 and Q2 to operate in the saturation region are the expressions (3a) and (3b) for the voltage Vg that satisfies Vgmin ⁇ Vg ⁇ Vgz. ) Is established (first condition).
  • both the transistors Q1 and Q2 operate in the saturation region, and when the luminance of the organic EL element is higher than the maximum gradation luminance, the transistor Q1 operates in the saturation region.
  • the voltage for the pixel circuit 10 is determined so that Q2 operates in the linear region.
  • the ratio of the currents Ids1 and Ids2 is determined so that the range from Vgmin to Vgmax falls within the range of the output voltage of the data line driving circuit 5. Further, Vth1 ⁇ Vth2 is established for the threshold voltages Vth1 and Vth2 of the transistors Q1 and Q2. For this purpose, for example, the channel length of the transistor Q1 may be shorter than the channel length of the transistor Q2. Thus, when the gate voltage is equal to or higher than Vth1 and lower than Vth2, the transistor Q1 is turned on and the transistor Q2 is turned off. At this time, the current Ids2 is substantially 0, and the current Ioled is substantially equal to the current Ids1.
  • the magnitude of the range of the gate voltage Vg in which the transistor Q1 operates in the saturation region and the transistor Q2 operates in the linear region is (Van1-Van2 + Vth1-Vth2). Therefore, according to the display device 1, the luminance of the organic EL element can be increased by the size of this range compared to the gradation display.
  • FIG. 15 is a characteristic diagram showing the relationship between the gate-source voltage and the threshold voltage difference (Vgs ⁇ Vth) and the drain-source voltage Vds for the transistors Q1 and Q2.
  • FIG. 16 is a characteristic diagram showing the relationship between the gate voltage Vg and the drain-source voltage Vds for the transistors Q1 and Q2.
  • FIG. 17 is a characteristic diagram showing the relationship between the gate voltage Vg and the current Ioled. For reference, FIG. 17 also shows the relationship when the pixel circuit 10 including the data holding units 21 and 23 is used.
  • the transistor Q1 operates in the saturation region when Vgs ⁇ Vth ⁇ 5.0V (when Vg ⁇ 10.0V).
  • Vth 2.0V
  • Vth2 2.5V
  • Van1 8.0V
  • Van2 4.0V
  • the gate voltage Vg is changed within the range from 2.6V to 10.0V.
  • the values of Van1, Van2, Vth1, and Vth2 can be suitably selected, and the luminance range corresponding to gradation display and the luminance range higher than the maximum gradation luminance can be arbitrarily determined.
  • the luminance of the pixels of the field sequential color type organic EL display device is smaller than that of the organic EL display device not using the field sequential color method. Further, when the amplitude of the data voltage is increased in order to increase the maximum luminance of the pixel, the power consumption of the data line driving circuit increases. This problem becomes more prominent in an organic EL display device having a function of making the luminance of a pixel higher than the maximum luminance in gradation display.
  • the display device 1 includes a display unit 2 including (m ⁇ n) pixel circuits 10, scanning lines SL1 to SLm, data lines DL1 to DLn, and 3m emission control lines, and scanning lines.
  • a drive circuit including a drive circuit 4, a data line drive circuit 5, and a light emission control line drive circuit 6 is provided.
  • the pixel circuit 10 includes an organic EL element Lr, Lg, and Lb, a transistor Q1 that outputs a current corresponding to a gate voltage by applying a first high-level power supply voltage Van1 to a drain terminal, and a second high-level power supply to a drain terminal.
  • the voltage Van2 is applied, the source terminal is connected to the source terminal of the transistor Q1, the transistor Q2 outputs a current corresponding to the gate voltage, and the current output from the transistors Q1 and Q2 is output from the organic EL elements Lr, Lg, and Lb. It includes a selection circuit (transistors Qr, Qg, Qb) for switching to which of them flows.
  • the transistor Q1 operates in a saturation region when the gate voltage Vg is within a predetermined range (when Vgmin ⁇ Vg ⁇ Vgmax).
  • the transistor Q2 operates in the saturation region when the gate voltage Vg is within a first range that is a part of the predetermined range (when Vgmin ⁇ Vg ⁇ Vgz), and the gate voltage Vg is the remainder of the predetermined range. When in the 2 range (when Vgz ⁇ Vg ⁇ Vgmax), it operates in the linear region.
  • the transistor Q2 that operates in the saturation region or the linear region in accordance with the gate voltage is provided in the pixel circuit 10, so that the data voltage output from the data line driving circuit 5 is increased.
  • the maximum luminance of the pixel can be increased by increasing the current flowing in any one of the organic EL elements Lr, Lg, and Lb without increasing the amplitude of. Therefore, in the field sequential color display device, the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit.
  • the voltage in the first range is a voltage used for gradation display
  • the voltage in the second range is a voltage corresponding to a luminance higher than the maximum gradation luminance. Therefore, the transistors Q1 and Q2 operate in the saturation region during gradation display, and when the luminance is higher than the maximum gradation luminance, the transistor Q1 operates in the saturation region and the transistor Q2 operates in the linear region. In this way, the operation of the transistor Q2 can be switched to make the luminance of the pixel higher than the maximum gradation luminance.
  • the gate terminals of the transistors Q1 and Q2 are connected to the same node. Therefore, it is possible to easily obtain the effect of increasing the maximum luminance of the pixel without increasing the power consumption of the driving circuit by applying the same voltage to the gate terminals of the transistors Q1 and Q2.
  • the pixel circuit 10 further includes a transistor Q3 that supplies the data voltage output from the data line driving circuit 5 to the control terminals of the transistors Q1 and Q2, and a capacitor C1 that holds the gate voltages of the transistors Q1 and Q2. .
  • the transistors Qr, Qg, and Qb are provided between the source terminals of the transistors Q1 and Q2 and the organic EL elements Lr, Lg, and Lb, respectively, and the gate terminals of the transistors Qr, Qg, and Qb are connected to the light emission control line. . Thereby, it is possible to configure a selection circuit that switches which of the organic EL elements Lr, Lg, and Lb flows the current output from the transistors Q1 and Q2.
  • the display device may be configured so that different voltages can be applied to the gate terminals of the transistors Q1 and Q2.
  • the display device according to this modification by applying different voltages to the gate terminals of the transistors Q1 and Q2, the current flowing through the organic EL element is controlled with a high degree of freedom, and the luminance of the pixel is controlled with a high degree of freedom. can do.
  • the boundary voltage Vgz at which the transistor Q2 switches operation may not be a gate voltage corresponding to the maximum gradation.
  • the voltage Vgz may be a gate voltage corresponding to a gradation obtained by multiplying the maximum gradation by ⁇ (0 ⁇ ⁇ 1).
  • the display device may include a pixel circuit different from those in FIGS.
  • the pixel circuit may include a P-channel transistor, may include a plurality of transistors Q1, may include a plurality of transistors Q2, and emits light in colors other than red, green, and blue.
  • the organic EL element to be used may be included.
  • the pixel circuit may be one in which elements other than the first and second drive transistors are connected in a form different from that shown in FIGS.
  • the display device may operate according to a display pattern sequence different from that in FIG. Also with the display devices according to these modified examples, similarly to the display device 1, the maximum luminance of the pixels can be increased without increasing the power consumption of the drive circuit.
  • the second drive transistor that operates in the saturation region or the linear region according to the voltage of the control terminal is provided with the pixel circuit. Accordingly, the maximum luminance of the pixel can be increased by increasing the current flowing through the light emitting element without increasing the amplitude of the data voltage output from the driving circuit. Therefore, in the field sequential color display device, the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit.
  • the display device of the present invention has the feature that the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit, it can be used for a display unit of various electronic devices.

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Abstract

Each pixel circuit in this field-sequential-color display device contains three organic EL elements (Lr, Lg, Lb), transistors (Q1 through Q3), a capacitor (C1), and a selection circuit comprising transistors (Qr, Qg, Qb). One transistor (Q1) operates in the saturation region when the gate voltage thereof is within a prescribed range, and another transistor (Q2) operates in the saturation region when the gate voltage thereof is within a first range that constitutes part of the prescribed range but operates in the linear region when the gate voltage thereof is within a second range that constitutes the remainder of the prescribed range. This increases the maximum luminance of the pixel without increasing the power consumption of the driving circuit.

Description

表示装置およびその駆動方法Display device and driving method thereof
　本発明は、表示装置およびその駆動方法に関し、特に、１フレーム期間に複数のサブフレームを表示する表示装置およびその駆動方法に関する。 The present invention relates to a display device and a driving method thereof, and more particularly, to a display device that displays a plurality of subframes in one frame period and a driving method thereof.
　近年、薄型、軽量、高速応答可能な表示装置として、有機ＥＬ（Electro Luminescence）表示装置が注目されている。有機ＥＬ表示装置は、２次元状に配置された複数の画素回路を備えている。有機ＥＬ表示装置の典型的な画素回路は、１個の有機ＥＬ素子と１個の駆動トランジスタを含んでいる。有機ＥＬ素子は、通過する電流の量に応じた輝度で発光する発光素子である。駆動トランジスタは、有機ＥＬ素子と直列に設けられ、有機ＥＬ素子に流れる電流の量を制御する。 In recent years, organic EL (Electro Luminescence) display devices have attracted attention as display devices that are thin, lightweight, and capable of high-speed response. The organic EL display device includes a plurality of pixel circuits arranged two-dimensionally. A typical pixel circuit of an organic EL display device includes one organic EL element and one drive transistor. The organic EL element is a light emitting element that emits light with a luminance corresponding to the amount of current passing therethrough. The drive transistor is provided in series with the organic EL element, and controls the amount of current flowing through the organic EL element.
　これとは別に、フィールドシーケンシャルカラー方式の表示装置が従来から知られている。フィールドシーケンシャルカラー方式の表示装置は、１フレーム期間に複数のサブフレームを表示することにより、カラー表示を行う。フィールドシーケンシャルカラー方式の表示装置としては、バックライトの発光色をサブフレーム期間ごとに赤、緑、および、青に切り換え、１フレーム期間に３枚のサブフレーム（赤、緑、および、青に対応したサブフレーム）を表示する液晶表示装置が知られている。 Separately, field sequential color display devices have been known. A field sequential color display device performs color display by displaying a plurality of subframes in one frame period. As a field sequential color display device, the backlight emission color is switched to red, green, and blue every subframe period, and 3 subframes (red, green, and blue are supported per frame period) Liquid crystal display devices that display subframes) are known.
　特許文献１および２には、フィールドシーケンシャルカラー方式の有機ＥＬ表示装置が記載されている。例えば、特許文献１に記載された表示装置は、１フレーム期間に３枚のサブフレームを表示する。図１８は、特許文献１の図９に記載された表示装置の画素行列の回路図である。各画素回路は、赤色に発光する有機ＥＬ素子ＯＬＥＤｒ、緑色に発光する有機ＥＬ素子ＯＬＥＤｇ、および、青色に発光する有機ＥＬ素子ＯＬＥＤｂを含んでいる。第１サブフレーム期間では発光信号線Ｅ１ｒ、Ｅ２ｒ、Ｅ３ｒが選択され、第２サブフレーム期間では発光信号線Ｅ１ｇ、Ｅ２ｇ、Ｅ３ｇが選択され、第３サブフレーム期間では発光信号線Ｅ１ｂ、Ｅ２ｂ、Ｅ３ｂが選択される。これにより、図３に示すように、画素の色を画素ごとおよびサブフレームごとに切り換えて、カラー表示を行うことができる。フィールドシーケンシャルカラー方式の有機ＥＬ表示装置によれば、１個の駆動トランジスタを用いて複数の有機ＥＬ素子の輝度を制御することにより、回路量やレイアウト面積を削減することができる。 Patent Documents 1 and 2 describe a field sequential color organic EL display device. For example, the display device described in Patent Document 1 displays three subframes in one frame period. FIG. 18 is a circuit diagram of a pixel matrix of the display device described in FIG. Each pixel circuit includes an organic EL element OLEDr that emits red light, an organic EL element OLEDg that emits green light, and an organic EL element OLEDb that emits blue light. The light emission signal lines E1r, E2r, E3r are selected in the first subframe period, the light emission signal lines E1g, E2g, E3g are selected in the second subframe period, and the light emission signal lines E1b, E2b, E3b are selected in the third subframe period. Is selected. As a result, as shown in FIG. 3, color display can be performed by switching the color of the pixel for each pixel and for each subframe. According to the organic EL display device of the field sequential color system, the circuit amount and the layout area can be reduced by controlling the luminance of a plurality of organic EL elements using one driving transistor.
　また、本願発明に関連して、特許文献３には、複数の駆動トランジスタを含む画素回路を備えた有機ＥＬ表示装置が記載されている。図１９は、特許文献３の図１に記載された画素回路のブロック図である。図１９に示す画素回路９０は、階調信号としての入力変量に対する出力電流特性が飽和特性を示す第１半導体素子９１、階調信号としての入力変量に対する出力電流特性が線形特性を示す第２半導体素子９２、および、発光素子９３を含んでいる。画素回路９０では、第１半導体素子９１によって決定される電流Ｉ１を出力する第１電流経路と、第２半導体素子９２によって決定される電流Ｉ２を出力する第２電流経路とが合流して、発光素子９３の電流経路に接続される。画素回路９０を備えた有機ＥＬ表示装置によれば、所定のドライバ出力範囲内で階調表示を行うための電圧範囲を十分に確保しながら、より高いピーク輝度を発生することができる。 In connection with the present invention, Patent Document 3 describes an organic EL display device including a pixel circuit including a plurality of drive transistors. FIG. 19 is a block diagram of the pixel circuit described in FIG. 19 includes a first semiconductor element 91 in which an output current characteristic with respect to an input variable as a gradation signal exhibits a saturation characteristic, and a second semiconductor in which an output current characteristic with respect to the input variable as a gradation signal exhibits a linear characteristic. An element 92 and a light emitting element 93 are included. In the pixel circuit 90, the first current path that outputs the current I1 determined by the first semiconductor element 91 and the second current path that outputs the current I2 determined by the second semiconductor element 92 merge to emit light. It is connected to the current path of the element 93. According to the organic EL display device including the pixel circuit 90, it is possible to generate higher peak luminance while sufficiently ensuring a voltage range for performing gradation display within a predetermined driver output range.
日本国特開２００５－２６６７７０号公報Japanese Unexamined Patent Publication No. 2005-266770 日本国特開２００５－２６６７７３号公報Japanese Unexamined Patent Publication No. 2005-266773 国際公開第２００９／９８８０２号International Publication No. 2009/98802
　フィールドシーケンシャルカラー方式の有機ＥＬ表示装置では、各有機ＥＬ素子は１サブフレーム期間でしか発光しない。このため、各有機ＥＬ素子の発光期間の長さは、フィールドシーケンシャルカラー方式ではない有機ＥＬ表示装置（以下、一般的な有機ＥＬ表示装置という）と比べて１／ｋ（ｋは１フレーム期間に表示されるサブフレームの枚数）になる。したがって、他の条件が同じであれば、フィールドシーケンシャルカラー方式の有機ＥＬ表示装置の画素の輝度は、一般的な有機ＥＬ表示装置と比べて１／ｋになる。 In the field sequential color type organic EL display device, each organic EL element emits light only in one subframe period. For this reason, the length of the light emission period of each organic EL element is 1 / k (k is one frame period) as compared with an organic EL display device that is not a field sequential color system (hereinafter referred to as a general organic EL display device). The number of subframes displayed). Therefore, if the other conditions are the same, the luminance of the pixel of the field sequential color organic EL display device is 1 / k compared to a general organic EL display device.
　駆動トランジスタが飽和領域で動作する場合、有機ＥＬ素子の輝度は、画素回路に書き込まれるデータ電圧の２乗に比例する。このため、フィールドシーケンシャルカラー方式の有機ＥＬ表示装置において、画素の最大輝度を一般的な有機ＥＬ表示装置と同じにするためには、データ電圧の振幅を一般的な有機ＥＬ表示装置と比べて√ｋ倍以上にする必要がある。例えば、１フレーム期間に３枚のサブフレームを表示する場合には、データ電圧の振幅を一般的な有機ＥＬ表示装置と比べて√３倍以上にする必要がある。 When the driving transistor operates in the saturation region, the luminance of the organic EL element is proportional to the square of the data voltage written in the pixel circuit. For this reason, in the field sequential color organic EL display device, in order to make the maximum luminance of the pixel the same as that of a general organic EL display device, the amplitude of the data voltage is √ compared with that of a general organic EL display device. It is necessary to make k times or more. For example, when three subframes are displayed in one frame period, the amplitude of the data voltage needs to be √3 times or more as compared with a general organic EL display device.
　データ電圧の振幅を大きくするためには、データ線駆動回路の耐電圧を高くする必要がある。ところが、データ線駆動回路の耐電圧を高くすると、データ線駆動回路の消費電力が増大する。このようにフィールドシーケンシャルカラー方式の有機ＥＬ表示装置には、画素の最大輝度を高くするためにデータ電圧の振幅を大きくすると、データ線駆動回路の消費電力が増大するという問題がある。この問題は、画素の輝度を階調表示における最大輝度よりも高くする機能を有する有機ＥＬ表示装置においてより顕著になる。 In order to increase the amplitude of the data voltage, it is necessary to increase the withstand voltage of the data line driving circuit. However, increasing the withstand voltage of the data line driving circuit increases the power consumption of the data line driving circuit. As described above, the field sequential color organic EL display device has a problem that the power consumption of the data line driving circuit increases when the amplitude of the data voltage is increased in order to increase the maximum luminance of the pixel. This problem becomes more prominent in an organic EL display device having a function of making the luminance of a pixel higher than the maximum luminance in gradation display.
　それ故に、本発明は、駆動回路の消費電力を増大させずに画素の最大輝度を高くしたフィールドシーケンシャルカラー方式の表示装置を提供することを目的とする。 Therefore, an object of the present invention is to provide a field sequential color display device in which the maximum luminance of a pixel is increased without increasing the power consumption of a driving circuit.
　本発明の第１の局面は、１フレーム期間に複数のサブフレームを表示する表示装置であって、
　２次元状に配置された複数の画素回路を含む表示部と、
　各サブフレーム期間において、前記複数の画素回路に対して書き込みおよび発光制御を行う駆動回路とを備え、
　前記画素回路は、
　　互いに異なる色に発光する複数の発光素子と、
　　一方の導通端子に第１電源電圧が印加され、制御端子の電圧に応じた電流を出力する第１駆動トランジスタと、
　　一方の導通端子に第２電源電圧が印加され、他方の導通端子が前記第１駆動トランジスタの他方の導通端子に接続され、制御端子の電圧に応じた電流を出力する第２駆動トランジスタと、
　　前記第１および第２駆動トランジスタから出力された電流を前記複数の発光素子のいずれに流すかを切り替える選択回路とを含み、
　前記第１駆動トランジスタは、制御端子の電圧が所定範囲内にあるときには飽和領域で動作し、前記第２駆動トランジスタは、制御端子の電圧が前記所定範囲の一部である第１範囲内にあるときには飽和領域で動作し、制御端子の電圧が前記所定範囲の残部である第２範囲内にあるときには線形領域で動作することを特徴とする。 A first aspect of the present invention is a display device that displays a plurality of subframes in one frame period,
A display unit including a plurality of pixel circuits arranged two-dimensionally;
A drive circuit that performs writing and light emission control on the plurality of pixel circuits in each sub-frame period,
The pixel circuit includes:
A plurality of light emitting elements that emit light in different colors;
A first drive transistor that applies a first power supply voltage to one conduction terminal and outputs a current corresponding to the voltage of the control terminal;
A second power supply voltage is applied to one conduction terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and a second drive transistor that outputs a current according to the voltage of the control terminal;
A selection circuit for switching which of the plurality of light emitting elements allows the current output from the first and second drive transistors to flow;
The first drive transistor operates in a saturation region when the voltage at the control terminal is within a predetermined range, and the second drive transistor is within a first range where the voltage at the control terminal is part of the predetermined range. It sometimes operates in the saturation region, and operates in the linear region when the voltage at the control terminal is within the second range which is the remainder of the predetermined range.
　本発明の第２の局面は、本発明の第１の局面において、
　前記第１範囲内の電圧は階調表示で用いられる電圧であり、前記第２範囲内の電圧は階調表示における最大輝度よりも高い輝度に対応した電圧であることを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
The voltage in the first range is a voltage used in gradation display, and the voltage in the second range is a voltage corresponding to a luminance higher than the maximum luminance in gradation display.
　本発明の第３の局面は、本発明の第１の局面において、
　前記第１および第２駆動トランジスタの制御端子は、同じ節点に接続されていることを特徴とする。 According to a third aspect of the present invention, in the first aspect of the present invention,
The control terminals of the first and second driving transistors are connected to the same node.
　本発明の第４の局面は、本発明の第３の局面において、
　前記画素回路は、前記駆動回路から出力されたデータ電圧を前記第１および第２駆動トランジスタの制御端子に与える入力トランジスタと、前記第１および第２駆動トランジスタの制御端子の電圧を保持する容量素子とをさらに含むことを特徴とする。 According to a fourth aspect of the present invention, in the third aspect of the present invention,
The pixel circuit includes an input transistor that supplies a data voltage output from the drive circuit to control terminals of the first and second drive transistors, and a capacitive element that holds a voltage of the control terminal of the first and second drive transistors. And further comprising.
　本発明の第５の局面は、本発明の第４の局面において、
　前記容量素子は、前記第１および第２駆動トランジスタの制御端子と前記第１駆動トランジスタの一方の導通端子との間に設けられていることを特徴とする。 According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
The capacitive element is provided between a control terminal of the first and second drive transistors and one conduction terminal of the first drive transistor.
　本発明の第６の局面は、本発明の第４の局面において、
　前記容量素子は、前記第１および第２駆動トランジスタの制御端子と他方の導通端子との間に設けられていることを特徴とする。 A sixth aspect of the present invention is the fourth aspect of the present invention,
The capacitive element is provided between a control terminal of the first and second drive transistors and the other conduction terminal.
　本発明の第７の局面は、本発明の第４の局面において、
　前記容量素子は、前記第１および第２駆動トランジスタの制御端子と制御線との間に設けられていることを特徴とする。 According to a seventh aspect of the present invention, in the fourth aspect of the present invention,
The capacitive element is provided between a control terminal and a control line of the first and second drive transistors.
　本発明の第８の局面は、本発明の第１の局面において、
　前記第１および第２駆動トランジスタの制御端子には異なる電圧が印加可能に構成されていることを特徴とする。 According to an eighth aspect of the present invention, in the first aspect of the present invention,
The control terminals of the first and second drive transistors are configured to be able to apply different voltages.
　本発明の第９の局面は、本発明の第１の局面において、
　前記選択回路は、それぞれが前記第１および第２駆動トランジスタの他方の導通端子と前記複数の発光素子との間に設けられ、発光制御線に接続された制御端子を有する複数の発光制御トランジスタを含むことを特徴とする。 According to a ninth aspect of the present invention, in the first aspect of the present invention,
The selection circuit includes a plurality of light emission control transistors each having a control terminal provided between the other conduction terminal of the first and second drive transistors and the plurality of light emitting elements and connected to a light emission control line. It is characterized by including.
　本発明の第１０の局面は、本発明の第１の局面において、
　前記表示部は、複数の走査線と複数のデータ線と複数の発光制御線とをさらに含み、
　前記駆動回路は、各サブフレーム期間において前記複数の走査線を順に選択する走査線駆動回路と、各サブフレーム期間の各ライン期間において映像信号に応じたデータ電圧を前記複数のデータ線に印加するデータ線駆動回路と、各サブフレーム期間において前記複数の発光制御線を駆動する発光制御線駆動回路とを含むことを特徴とする。 According to a tenth aspect of the present invention, in the first aspect of the present invention,
The display unit further includes a plurality of scanning lines, a plurality of data lines, and a plurality of light emission control lines,
The driving circuit applies a data voltage corresponding to a video signal to the plurality of data lines in each line period of each subframe period, and a scanning line driving circuit that sequentially selects the plurality of scanning lines in each subframe period. A data line driving circuit; and a light emission control line driving circuit for driving the plurality of light emission control lines in each subframe period.
　本発明の第１１の局面は、２次元状に配置された複数の画素回路と、複数の走査線と、複数のデータ線と、複数の発光制御線とを含み、１フレーム期間に複数のサブフレームを表示する表示装置の駆動方法であって、
　各サブフレーム期間において前記複数の走査線を順に選択するステップと、
　各サブフレーム期間の各ライン期間において映像信号に応じたデータ電圧を前記複数のデータ線に印加するステップと、
　各サブフレーム期間において前記複数の発光制御線を駆動するステップとを備え、
　前記画素回路は、互いに異なる色に発光する複数の発光素子と、一方の導通端子に第１電源電圧が印加され、制御端子の電圧に応じた電流を出力する第１駆動トランジスタと、一方の導通端子に第２電源電圧が印加され、他方の導通端子が前記第１駆動トランジスタの他方の導通端子に接続され、制御端子の電圧に応じた電流を出力する第２駆動トランジスタと、前記第１および第２駆動トランジスタから出力された電流を前記複数の発光素子のいずれに流すかを切り替える選択回路とを含み、
　前記第１駆動トランジスタは、制御端子の電圧が所定範囲内にあるときには飽和領域で動作し、前記第２駆動トランジスタは、制御端子の電圧が前記所定範囲の一部である第１範囲内にあるときには飽和領域で動作し、制御端子の電圧が前記所定範囲の残部である第２範囲内にあるときには線形領域で動作することを特徴とする。 An eleventh aspect of the present invention includes a plurality of pixel circuits, a plurality of scanning lines, a plurality of data lines, and a plurality of light emission control lines arranged two-dimensionally, and a plurality of sub-circuits in one frame period. A driving method of a display device for displaying a frame,
Sequentially selecting the plurality of scan lines in each subframe period;
Applying a data voltage corresponding to a video signal to each of the plurality of data lines in each line period of each subframe period;
Driving the plurality of light emission control lines in each subframe period,
The pixel circuit includes a plurality of light emitting elements that emit light of different colors, a first drive transistor that outputs a current corresponding to a voltage of a control terminal by applying a first power supply voltage to one conduction terminal, and one conduction A second power supply voltage is applied to the terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and the second drive transistor outputs a current corresponding to the voltage of the control terminal; A selection circuit for switching to which of the plurality of light emitting elements the current output from the second drive transistor flows,
The first drive transistor operates in a saturation region when the voltage at the control terminal is within a predetermined range, and the second drive transistor is within a first range where the voltage at the control terminal is part of the predetermined range. It sometimes operates in the saturation region, and operates in the linear region when the voltage at the control terminal is within the second range which is the remainder of the predetermined range.
　本発明の第１、第１０または第１１の局面によれば、飽和領域で動作する第１駆動トランジスタに加えて、制御端子の電圧に応じて飽和領域または線形領域で動作する第２駆動トランジスタを画素回路に設けることにより、駆動回路から出力されるデータ電圧の振幅を大きくすることなく、発光素子を流れる電流を増加させて、画素の最大輝度を高くすることができる。したがって、フィールドシーケンシャルカラー方式の表示装置において、駆動回路の消費電力を増大させずに、画素の最大輝度を高くすることができる。 According to the first, tenth, or eleventh aspects of the present invention, in addition to the first drive transistor that operates in the saturation region, the second drive transistor that operates in the saturation region or the linear region according to the voltage of the control terminal is provided. By providing the pixel circuit, the maximum luminance of the pixel can be increased by increasing the current flowing through the light emitting element without increasing the amplitude of the data voltage output from the driver circuit. Therefore, in the field sequential color display device, the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit.
　本発明の第２の局面によれば、階調表示のときには第１および第２駆動トランジスタは飽和領域で動作し、階調表示における最大輝度よりも輝度を高くするときには、第１駆動トランジスタは飽和領域で動作し、第２駆動トランジスタは線形領域で動作する。このように第２駆動トランジスタの動作を切り替えて、画素の輝度を階調表示における最大輝度よりも高くすることができる。 According to the second aspect of the present invention, the first and second drive transistors operate in the saturation region during gradation display, and the first drive transistor is saturated when the luminance is higher than the maximum luminance in gradation display. The second driving transistor operates in a linear region. In this way, the operation of the second driving transistor can be switched to make the luminance of the pixel higher than the maximum luminance in gradation display.
　本発明の第３の局面によれば、第１および第２駆動トランジスタの制御端子に同じ電圧を印加することにより、駆動回路の消費電力を増大させずに画素の最大輝度を高くする効果を容易に得ることができる。 According to the third aspect of the present invention, by applying the same voltage to the control terminals of the first and second drive transistors, it is easy to increase the maximum luminance of the pixel without increasing the power consumption of the drive circuit. Can get to.
　本発明の第４の局面によれば、画素回路に入力トランジスタと容量素子を設けることにより、駆動回路から出力されたデータ電圧を第１および第２駆動トランジスタの制御端子に与え、与えた電圧を保持することができる。 According to the fourth aspect of the present invention, by providing the pixel circuit with the input transistor and the capacitive element, the data voltage output from the drive circuit is applied to the control terminals of the first and second drive transistors, and the applied voltage is applied. Can be held.
　本発明の第５の局面によれば、第１および第２駆動トランジスタの制御端子と第１駆動トランジスタの一方の導通端子との間に容量素子を設けることにより、第１および第２駆動トランジスタの制御端子の電圧を保持することができる。 According to the fifth aspect of the present invention, by providing a capacitive element between the control terminal of the first and second drive transistors and one conduction terminal of the first drive transistor, the first and second drive transistors The voltage of the control terminal can be held.
　本発明の第６の局面によれば、第１および第２駆動トランジスタの制御端子と他方の導通端子との間に容量素子を設けることにより、第１および第２駆動トランジスタの制御端子の電圧を保持することができる。 According to the sixth aspect of the present invention, by providing a capacitive element between the control terminal of the first and second drive transistors and the other conduction terminal, the voltage at the control terminal of the first and second drive transistors is reduced. Can be held.
　本発明の第７の局面によれば、第１および第２駆動トランジスタの制御端子と制御線との間に容量素子を設けることにより、第１および第２駆動トランジスタの制御端子の電圧を保持することができる。 According to the seventh aspect of the present invention, by providing a capacitive element between the control terminal of the first and second drive transistors and the control line, the voltage at the control terminal of the first and second drive transistors is held. be able to.
　本発明の第８の局面によれば、第１および第２駆動トランジスタの制御端子に異なる電圧を印加することにより、発光素子を流れる電流を高い自由度で制御し、画素の輝度を高い自由度で制御することができる。 According to the eighth aspect of the present invention, by applying different voltages to the control terminals of the first and second drive transistors, the current flowing through the light emitting element is controlled with a high degree of freedom, and the luminance of the pixel is high. Can be controlled.
　本発明の第９の局面によれば、複数の発光制御トランジスタを用いて、第１および第２駆動トランジスタから出力された電流を複数の発光素子のいずれに流すかを切り替える選択回路を構成することができる。 According to the ninth aspect of the present invention, a selection circuit is configured to switch a current output from the first and second drive transistors to which of the plurality of light emitting elements using a plurality of light emission control transistors. Can do.
本発明の実施形態に係る表示装置の構成を示すブロック図である。It is a block diagram which shows the structure of the display apparatus which concerns on embodiment of this invention. 図１に示す表示装置の表示パターンシーケンスを示す図である。It is a figure which shows the display pattern sequence of the display apparatus shown in FIG. 図２の一部を示す図である。It is a figure which shows a part of FIG. 図１に示す表示装置の表示部の構成を示す図である。It is a figure which shows the structure of the display part of the display apparatus shown in FIG. 図４に示すデータ保持部の第１例の回路図である。FIG. 5 is a circuit diagram of a first example of a data holding unit shown in FIG. 4. 図４に示すデータ保持部の第２例の回路図である。FIG. 5 is a circuit diagram of a second example of the data holding unit shown in FIG. 4. 図４に示すデータ保持部の第３例の回路図である。FIG. 5 is a circuit diagram of a third example of the data holding unit shown in FIG. 4. 図４に示す画素回路の例を示す回路図である。FIG. 5 is a circuit diagram illustrating an example of the pixel circuit illustrated in FIG. 4. 図１に示す表示装置の電源配線の第１構成例を示す図である。It is a figure which shows the 1st structural example of the power supply wiring of the display apparatus shown in FIG. 図１に示す表示装置の電源配線の第２構成例を示す図である。It is a figure which shows the 2nd structural example of the power supply wiring of the display apparatus shown in FIG. 図１に示す表示装置のタイミングチャートである。It is a timing chart of the display apparatus shown in FIG. 図１に示す表示装置におけるデータ電圧の種類と選択される発光制御線を示す図である。It is a figure which shows the kind of data voltage in the display apparatus shown in FIG. 1, and the light emission control line selected. 図１に示す表示装置における階調とゲート電圧と輝度の範囲を示す図である。It is a figure which shows the range of the gradation in the display apparatus shown in FIG. 1, a gate voltage, and a brightness | luminance. 図８に示す画素回路の等価回路図である。FIG. 9 is an equivalent circuit diagram of the pixel circuit shown in FIG. 8. 図８に示す画素回路における電圧の差（Ｖｇｓ－Ｖｔｈ）と電圧Ｖｄｓとの関係を示す特性図である。FIG. 9 is a characteristic diagram illustrating a relationship between a voltage difference (Vgs−Vth) and a voltage Vds in the pixel circuit illustrated in FIG. 8. 図８に示す画素回路におけるゲート電圧Ｖｇと電圧Ｖｄｓとの関係を示す特性図である。FIG. 9 is a characteristic diagram illustrating a relationship between a gate voltage Vg and a voltage Vds in the pixel circuit illustrated in FIG. 8. 図８に示す画素回路におけるゲート電圧Ｖｇと電流Ｉｏｌｅｄとの関係を示す特性図である。FIG. 9 is a characteristic diagram illustrating a relationship between a gate voltage Vg and a current Ioled in the pixel circuit illustrated in FIG. 8. 従来の表示装置の画素行列の回路図である。It is a circuit diagram of the pixel matrix of the conventional display apparatus. 従来の表示装置に含まれる画素回路のブロック図である。It is a block diagram of a pixel circuit included in a conventional display device.
　図１は、本発明の実施形態に係る表示装置の構成を示すブロック図である。図１に示す表示装置１は、表示部２、表示制御回路３、走査線駆動回路４、データ線駆動回路５、および、発光制御線駆動回路６を備えている。表示装置１は、フィールドシーケンシャルカラー方式の有機ＥＬ表示装置である。表示装置１は、１フレーム期間を３個のサブフレーム期間（以下、第１～第３サブフレーム期間という）に分割し、１フレーム期間に３枚のサブフレームを表示することにより、カラー表示を行う。以下、ｍおよびｎは２以上の整数であるとする。 FIG. 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention. A display device 1 shown in FIG. 1 includes a display unit 2, a display control circuit 3, a scanning line drive circuit 4, a data line drive circuit 5, and a light emission control line drive circuit 6. The display device 1 is a field sequential color organic EL display device. The display device 1 divides one frame period into three subframe periods (hereinafter referred to as first to third subframe periods), and displays three subframes in one frame period, thereby performing color display. Do. Hereinafter, it is assumed that m and n are integers of 2 or more.
　表示部２は、ｍ本の走査線ＳＬ１～ＳＬｍ、ｎ本のデータ線ＤＬ１～ＤＬｎ、３ｍ本の発光制御線、および、（ｍ×ｎ）個の画素回路１０を含んでいる。各画素回路１０は、１個の画素に対応する。図１において、ＥＬ１、ＥＬ２、…、ＥＬｍは、それぞれ、走査線ＳＬ１～ＳＬｍに対応した３本の発光制御線を表す。走査線ＳＬ１～ＳＬｍと３ｍ本の発光制御線は、互いに平行に配置される。データ線ＤＬ１～ＤＬｎは、互いに平行に走査線ＳＬ１～ＳＬｍと直交するように配置される。走査線ＳＬ１～ＳＬｍとデータ線ＤＬ１～ＤＬｎは、（ｍ×ｎ）箇所で交差する。（ｍ×ｎ）個の画素回路１０は、走査線ＳＬ１～ＳＬｍとデータ線ＤＬ１～ＤＬｎの交点に対応して２次元状に配置される。画素回路１０は、赤色、緑色、および、青色にそれぞれ発光する３個の有機ＥＬ素子を含み、１本の走査線、１本のデータ線、および、３本の発光制御線に接続される。画素回路１０には、電源線（図示せず）を用いて３種類の電源電圧が供給される。以下、走査線ＳＬｉとデータ線ＤＬｊ（ｉは１以上ｍ以下の整数、ｊは１以上ｎ以下の整数）の交点に対応して配置された画素回路をＰ（ｉ，ｊ）という。 The display unit 2 includes m scanning lines SL1 to SLm, n data lines DL1 to DLn, 3m light emission control lines, and (m × n) pixel circuits 10. Each pixel circuit 10 corresponds to one pixel. In FIG. 1, EL1, EL2,..., ELm represent three emission control lines corresponding to the scanning lines SL1 to SLm, respectively. The scanning lines SL1 to SLm and the 3m light emission control lines are arranged in parallel to each other. The data lines DL1 to DLn are arranged in parallel to each other and orthogonal to the scanning lines SL1 to SLm. The scanning lines SL1 to SLm and the data lines DL1 to DLn intersect at (m × n) locations. The (m × n) pixel circuits 10 are two-dimensionally arranged corresponding to the intersections of the scanning lines SL1 to SLm and the data lines DL1 to DLn. The pixel circuit 10 includes three organic EL elements that respectively emit red, green, and blue light, and is connected to one scanning line, one data line, and three light emission control lines. Three types of power supply voltages are supplied to the pixel circuit 10 using power supply lines (not shown). Hereinafter, a pixel circuit arranged corresponding to the intersection of the scanning line SLi and the data line DLj (i is an integer of 1 to m, j is an integer of 1 to n) is referred to as P (i, j).
　表示制御回路３は、走査線駆動回路４、データ線駆動回路５、および、発光制御線駆動回路６を制御する。より詳細には、表示制御回路３は、走査線駆動回路４に対して制御信号Ｃｓを出力し、データ線駆動回路５に対して制御信号Ｃｄと映像信号Ｄ１を出力し、発光制御線駆動回路６に対して制御信号Ｃｅを出力する。表示装置１では、１フレーム期間は３個のサブフレーム期間を含み、１サブフレーム期間はｍ個のライン期間（水平期間）を含む。制御信号Ｃｓ、Ｃｅには、フレーム期間の先頭を示す信号、サブフレーム期間の先頭を示す信号、ライン期間の先頭を示す信号などが含まれる。制御信号Ｃｄには、ライン期間の先頭を示す信号、データクロック信号、データラッチ信号などが含まれる。 The display control circuit 3 controls the scanning line driving circuit 4, the data line driving circuit 5, and the light emission control line driving circuit 6. More specifically, the display control circuit 3 outputs a control signal Cs to the scanning line drive circuit 4, outputs a control signal Cd and a video signal D1 to the data line drive circuit 5, and emits a control line drive circuit. 6 outputs a control signal Ce. In the display device 1, one frame period includes three subframe periods, and one subframe period includes m line periods (horizontal periods). The control signals Cs and Ce include a signal indicating the start of the frame period, a signal indicating the start of the subframe period, a signal indicating the start of the line period, and the like. The control signal Cd includes a signal indicating the head of the line period, a data clock signal, a data latch signal, and the like.
　走査線駆動回路４は、制御信号Ｃｓに基づき、走査線ＳＬ１～ＳＬｍを駆動する。より詳細には、走査線駆動回路４は、各サブフレーム期間の各ライン期間において走査線ＳＬ１～ＳＬｍの中から１本の走査線を選択し、選択した走査線に選択電圧（ここでは、ハイレベル電圧）を印加する。走査線駆動回路４は、選択する走査線をライン期間ごとに切り換えることにより、各サブフレーム期間において走査線ＳＬ１～ＳＬｍを順に選択する。 The scanning line driving circuit 4 drives the scanning lines SL1 to SLm based on the control signal Cs. More specifically, the scanning line driving circuit 4 selects one scanning line from the scanning lines SL1 to SLm in each line period of each subframe period, and selects a selected voltage (here, a high voltage) Level voltage). The scanning line driving circuit 4 sequentially selects the scanning lines SL1 to SLm in each subframe period by switching the scanning line to be selected for each line period.
　データ線駆動回路５は、制御信号Ｃｄと映像信号Ｄ１に基づき、データ線ＤＬ１～ＤＬｎを駆動する。より詳細には、データ線駆動回路５は、各サブフレーム期間の各ライン期間において映像信号Ｄ１に基づきｎ個のデータ電圧を生成し、生成したｎ個のデータ電圧をデータ線ＤＬ１～ＤＬｎにそれぞれ印加する。 The data line driving circuit 5 drives the data lines DL1 to DLn based on the control signal Cd and the video signal D1. More specifically, the data line driving circuit 5 generates n data voltages based on the video signal D1 in each line period of each subframe period, and the generated n data voltages are respectively applied to the data lines DL1 to DLn. Apply.
　発光制御線駆動回路６は、制御信号Ｃｅに基づき、３ｍ本の発光制御線を駆動する。より詳細には、発光制御線駆動回路６は、選択された走査線に対応した３本の発光制御線の中から１本の発光制御線を選択し、選択した発光制御線に所定の時間（１サブフレーム期間よりも短い時間。以下、時間Ｔｅという）だけ選択電圧を印加する。画素回路１０内の有機ＥＬ素子は、発光制御線駆動回路６による制御に従い選択的に発光する。 The light emission control line drive circuit 6 drives 3m light emission control lines based on the control signal Ce. More specifically, the light emission control line drive circuit 6 selects one light emission control line from among the three light emission control lines corresponding to the selected scanning line, and supplies the selected light emission control line to a predetermined time ( The selection voltage is applied only for a time shorter than one subframe period (hereinafter referred to as time Te). The organic EL elements in the pixel circuit 10 selectively emit light according to control by the light emission control line driving circuit 6.
　走査線ＳＬｉの選択期間では、走査線ＳＬｉに接続されたｎ個の画素回路１０が一括して選択される。このとき、データ線ＤＬ１～ＤＬｎに印加されたｎ個のデータ電圧は、選択されたｎ個の画素回路１０にそれぞれ書き込まれる。その後、発光制御線駆動回路６は、走査線ＳＬｉに対応した３本の発光制御線の中から選択した１本の発光制御線に時間Ｔｅだけ選択電圧を印加する。これにより、選択された発光制御線に対応した１個の有機ＥＬ素子が時間Ｔｅだけ発光する。 In the selection period of the scanning line SLi, n pixel circuits 10 connected to the scanning line SLi are selected at once. At this time, the n data voltages applied to the data lines DL1 to DLn are written to the selected n pixel circuits 10, respectively. Thereafter, the light emission control line driving circuit 6 applies a selection voltage to one light emission control line selected from the three light emission control lines corresponding to the scanning line SLi for the time Te. Thereby, one organic EL element corresponding to the selected light emission control line emits light for a time Te.
　表示装置１では、第１～第３サブフレームにおいて（ｍ×ｎ）個の画素回路のそれぞれに、赤、緑、および、青のうちのいずれかを割り当てる表示パターンシーケンスが定められている。図２は、表示装置１の表示パターンシーケンスを示す図である。図３は、図２の一部を示す図である。図２において、正方形は１個の画素回路を表し、正方形内の文字は画素回路に割り当てられた色を表す。図２に示すように、（ｍ×ｎ）個の画素回路は、右上と左下に隣接する画素回路が同じグループに属するように第１～第３グループに分類される。以下、画素回路Ｐ（１，１）～Ｐ（１，３）が属するグループを、それぞれ、第１～第３グループという。第１～第３グループの画素回路に対して、第１サブフレームでは赤、緑、および、青がそれぞれ割り当てられ、第２サブフレームでは緑、青、および、赤がそれぞれ割り当てられ、第３サブフレームでは青、赤、および、緑がそれぞれ割り当てられる。 In the display device 1, a display pattern sequence for assigning one of red, green, and blue to each of the (m × n) pixel circuits in the first to third subframes is defined. FIG. 2 is a diagram showing a display pattern sequence of the display device 1. FIG. 3 is a diagram showing a part of FIG. In FIG. 2, the square represents one pixel circuit, and the characters in the square represent the colors assigned to the pixel circuits. As shown in FIG. 2, (m × n) pixel circuits are classified into first to third groups so that pixel circuits adjacent to the upper right and lower left belong to the same group. Hereinafter, the groups to which the pixel circuits P (1,1) to P (1,3) belong are referred to as first to third groups, respectively. For the first to third group of pixel circuits, red, green, and blue are respectively assigned in the first subframe, and green, blue, and red are respectively assigned in the second subframe. In the frame, blue, red, and green are assigned.
　画素回路１０内の３個の有機ＥＬ素子は、表示パターンシーケンスに従い、各サブフレーム期間において選択的に発光する。画素回路１０の実際の色（以下、表示色という）は、画素回路１０に書き込まれたデータ電圧に応じて変化する。例えば、第１サブフレームにおいて画素回路Ｐ（１，１）に赤が割り当てられている場合、第１サブフレーム期間では画素回路Ｐ（１，１）内の赤色に発光する有機ＥＬ素子だけが発光する。第１サブフレーム期間における画素回路Ｐ（１，１）の表示色は、赤の映像信号に応じた色になる。 The three organic EL elements in the pixel circuit 10 selectively emit light in each subframe period according to the display pattern sequence. The actual color of the pixel circuit 10 (hereinafter referred to as display color) changes according to the data voltage written in the pixel circuit 10. For example, when red is assigned to the pixel circuit P (1,1) in the first subframe, only the organic EL element that emits red light in the pixel circuit P (1,1) emits light in the first subframe period. To do. The display color of the pixel circuit P (1,1) in the first subframe period is a color corresponding to the red video signal.
　走査線駆動回路４とデータ線駆動回路５は、１サブフレーム期間に（ｍ×ｎ）個の画素回路１０にデータ電圧を書き込む。発光制御線駆動回路６は、各サブフレーム期間において（ｍ×ｎ）個の画素回路１０内の有機ＥＬ素子の発光状態を制御する。これにより、表示装置１は１サブフレーム期間に１枚のサブフレームを表示する。表示装置１は、１フレーム期間に３枚のサブフレームを表示することにより、カラー表示を行う。このように走査線駆動回路４、データ線駆動回路５、および、発光制御線駆動回路６は、各サブフレーム期間において、複数の画素回路１０に対して書き込みおよび発光制御を行う駆動回路として機能する。 The scanning line driving circuit 4 and the data line driving circuit 5 write data voltages to the (m × n) pixel circuits 10 in one subframe period. The light emission control line drive circuit 6 controls the light emission state of the organic EL elements in the (m × n) pixel circuits 10 in each subframe period. As a result, the display device 1 displays one subframe in one subframe period. The display device 1 performs color display by displaying three subframes in one frame period. As described above, the scanning line driving circuit 4, the data line driving circuit 5, and the light emission control line driving circuit 6 function as a driving circuit that performs writing and light emission control on the plurality of pixel circuits 10 in each subframe period. .
　図４は、表示部２の構成を示す図である。図４には、画素回路Ｐ（１，１）～Ｐ（１，３）、Ｐ（２，１）～Ｐ（２，３）、Ｐ（３，１）～Ｐ（３，３）の構成が記載されている。表示部２の他の部分は、図４と同じ構成を有する。画素回路Ｐ（ｉ，ｊ）は走査線ＳＬｉ、データ線ＤＬｊ、および、３本の発光制御線ＥＬｉａ～ＥＬｉｃに接続される。画素回路１０は、データ保持部２０、３個のＮチャネル型のトランジスタＱｒ、Ｑｇ、Ｑｂ、および、３個の有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂを含んでいる。有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂは、それぞれ、赤色、緑色、および、青色に発光する発光素子である。 FIG. 4 is a diagram showing a configuration of the display unit 2. FIG. 4 shows the configuration of the pixel circuits P (1,1) to P (1,3), P (2,1) to P (2,3), P (3,1) to P (3,3). Is described. The other part of the display unit 2 has the same configuration as in FIG. The pixel circuit P (i, j) is connected to the scanning line SLi, the data line DLj, and the three light emission control lines ELia to ELic. The pixel circuit 10 includes a data holding unit 20, three N-channel transistors Qr, Qg, Qb, and three organic EL elements Lr, Lg, Lb. The organic EL elements Lr, Lg, and Lb are light emitting elements that emit red, green, and blue light, respectively.
　データ保持部２０は、走査線ＳＬｉの選択期間にデータ線ＤＬｊに印加された電圧を保持する。データ保持部２０には、例えば、図５～図７に示す回路のいずれかが用いられる。図５～図７に示すデータ保持部２１～２３は、いずれも、Ｎチャネル型のトランジスタＱ１、Ｑ２、Ｑ３、および、コンデンサＣ１を含んでいる。 The data holding unit 20 holds the voltage applied to the data line DLj during the selection period of the scanning line SLi. For example, any of the circuits shown in FIGS. 5 to 7 is used for the data holding unit 20. Each of the data holding units 21 to 23 shown in FIGS. 5 to 7 includes N-channel transistors Q1, Q2, Q3, and a capacitor C1.
　データ保持部２１（図５）では、トランジスタＱ１のドレイン端子には第１ハイレベル電源電圧Ｖａｎ１が印加され、トランジスタＱ２のドレイン端子には第２ハイレベル電源電圧Ｖａｎ２が印加される。トランジスタＱ１のソース端子とトランジスタＱ２のソース端子は、トランジスタＱｒ、Ｑｇ、Ｑｂのドレイン端子に接続される（図では「点灯制御部へ」と記載）。トランジスタＱ３のゲート端子は走査線ＳＬｉに接続され、トランジスタＱ３の一方の導通端子はデータ線ＤＬｊに接続される。トランジスタＱ３の他方の導通端子は、トランジスタＱ１のゲート端子、トランジスタＱ２のゲート端子、および、コンデンサＣ１の一方の端子に接続される。コンデンサＣ１の他方の端子は、トランジスタＱ１のドレイン端子に接続される。 In the data holding unit 21 (FIG. 5), the first high-level power supply voltage Van1 is applied to the drain terminal of the transistor Q1, and the second high-level power supply voltage Van2 is applied to the drain terminal of the transistor Q2. The source terminal of the transistor Q1 and the source terminal of the transistor Q2 are connected to the drain terminals of the transistors Qr, Qg, and Qb (described as “to lighting control unit” in the figure). The gate terminal of the transistor Q3 is connected to the scanning line SLi, and one conduction terminal of the transistor Q3 is connected to the data line DLj. The other conduction terminal of transistor Q3 is connected to the gate terminal of transistor Q1, the gate terminal of transistor Q2, and one terminal of capacitor C1. The other terminal of the capacitor C1 is connected to the drain terminal of the transistor Q1.
　データ保持部２２、２３は、データ保持部２１についてコンデンサＣ１の他方の端子の接続先を変更したものである。データ保持部２２（図６）では、コンデンサＣ１の他方の端子は、トランジスタＱ１、Ｑ２のソース端子に接続される。データ保持部２３（図７）では、コンデンサＣ１の他方の端子は、制御線ＣＬｉに接続される。データ保持部２３を含む画素回路１０を備えた表示装置１には、走査線ＳＬ１～ＳＬｍと平行にｍ本の制御線ＣＬ１～ＣＬｍが設けられ、制御線ＣＬ１～ＣＬｍには所定の制御電圧が印加される。 The data holding units 22 and 23 are obtained by changing the connection destination of the other terminal of the capacitor C1 with respect to the data holding unit 21. In the data holding unit 22 (FIG. 6), the other terminal of the capacitor C1 is connected to the source terminals of the transistors Q1 and Q2. In the data holding unit 23 (FIG. 7), the other terminal of the capacitor C1 is connected to the control line CLi. The display device 1 including the pixel circuit 10 including the data holding unit 23 is provided with m control lines CL1 to CLm parallel to the scanning lines SL1 to SLm, and a predetermined control voltage is applied to the control lines CL1 to CLm. Applied.
　このように画素回路１０では、トランジスタＱ１のソース端子はトランジスタＱ２のソース端子に接続され、トランジスタＱ１のゲート端子とトランジスタＱ２のゲート端子は同じ節点に接続される。データ保持部２１では、コンデンサＣ１は、トランジスタＱ１、Ｑ２のゲート端子とトランジスタＱ１のドレイン端子との間に設けられる。データ保持部２２では、コンデンサＣ１は、トランジスタＱ１、Ｑ２のゲート端子とソース端子との間に設けられる。データ保持部２３では、コンデンサＣ１は、トランジスタＱ１、Ｑ２のゲート端子と制御線ＣＬｉとの間に設けられる。いずれのデータ保持部を用いても、トランジスタＱ１、Ｑ２のゲート電圧を保持することができる。 Thus, in the pixel circuit 10, the source terminal of the transistor Q1 is connected to the source terminal of the transistor Q2, and the gate terminal of the transistor Q1 and the gate terminal of the transistor Q2 are connected to the same node. In the data holding unit 21, the capacitor C1 is provided between the gate terminals of the transistors Q1 and Q2 and the drain terminal of the transistor Q1. In the data holding unit 22, the capacitor C1 is provided between the gate terminals and the source terminals of the transistors Q1 and Q2. In the data holding unit 23, the capacitor C1 is provided between the gate terminals of the transistors Q1 and Q2 and the control line CLi. Whichever data holding unit is used, the gate voltages of the transistors Q1 and Q2 can be held.
　図４に示すように、トランジスタＱｒ、Ｑｇ、Ｑｂのソース端子は、有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂのアノード端子にそれぞれ接続される。有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂのカソード端子には、ローレベル電源電圧Ｖｃａが印加される。トランジスタＱｒ、Ｑｇ、Ｑｂのゲート端子は、図２に示す表示パターンシーケンスに従い、発光制御線ＥＬｉａ～ＥＬｉｃのうちのいずれかに接続される。具体的には、第１グループの画素回路Ｐ（ｉ，ｊ）内のトランジスタＱｒ、Ｑｇ、Ｑｂのゲート端子は、発光制御線ＥＬｉａ、ＥＬｉｂ、ＥＬｉｃにそれぞれ接続される。第２グループの画素回路Ｐ（ｉ，ｊ）内のトランジスタＱｒ、Ｑｇ、Ｑｂのゲート端子は、発光制御線ＥＬｉｃ、ＥＬｉａ、ＥＬｉｂにそれぞれ接続される。第３グループの画素回路Ｐ（ｉ，ｊ）内のトランジスタＱｒ、Ｑｇ、Ｑｂのゲート端子は、発光制御線ＥＬｉｂ、ＥＬｉｃ、ＥＬｉａにそれぞれ接続される。例えば、データ保持部２０としてデータ保持部２２を用いた場合、画素回路Ｐ（１，１）は図８に示す構成を有する。 As shown in FIG. 4, the source terminals of the transistors Qr, Qg, and Qb are connected to the anode terminals of the organic EL elements Lr, Lg, and Lb, respectively. A low level power supply voltage Vca is applied to the cathode terminals of the organic EL elements Lr, Lg, and Lb. The gate terminals of the transistors Qr, Qg, and Qb are connected to any one of the light emission control lines ELia to ELic in accordance with the display pattern sequence shown in FIG. Specifically, the gate terminals of the transistors Qr, Qg, and Qb in the first group of pixel circuits P (i, j) are connected to the light emission control lines ELia, ELib, and ELic, respectively. The gate terminals of the transistors Qr, Qg, and Qb in the second group of pixel circuits P (i, j) are connected to the light emission control lines ELic, ELia, and ELib, respectively. The gate terminals of the transistors Qr, Qg, Qb in the third group of pixel circuits P (i, j) are connected to the light emission control lines ELib, ELic, ELia, respectively. For example, when the data holding unit 22 is used as the data holding unit 20, the pixel circuit P (1,1) has the configuration shown in FIG.
　トランジスタＱ１は、一方の導通端子に第１電源電圧が印加され、制御端子の電圧に応じた電流を出力する第１駆動トランジスタとして機能する。トランジスタＱ２は、一方の導通端子に第２電源電圧が印加され、他方の導通端子が第１駆動トランジスタの他方の導通端子に接続され、制御端子の電圧に応じた電流を出力する第２駆動トランジスタとして機能する。トランジスタＱ３は、駆動回路から出力されたデータ電圧を第１および第２駆動トランジスタの制御端子に与える入力トランジスタとして機能する。コンデンサＣ１は、第１および第２駆動トランジスタの制御端子の電圧を保持する容量素子として機能する。トランジスタＱｒ、Ｑｇ、Ｑｂは、第１および第２駆動トランジスタから出力された電流を複数の発光素子のいずれに流すかを切り替える選択回路として機能する。 The transistor Q1 functions as a first drive transistor that outputs a current corresponding to the voltage of the control terminal when a first power supply voltage is applied to one conduction terminal. In the transistor Q2, a second power supply voltage is applied to one conduction terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and the second drive transistor outputs a current corresponding to the voltage of the control terminal. Function as. The transistor Q3 functions as an input transistor that applies the data voltage output from the drive circuit to the control terminals of the first and second drive transistors. The capacitor C1 functions as a capacitive element that holds the voltage at the control terminals of the first and second drive transistors. The transistors Qr, Qg, and Qb function as a selection circuit that switches to which of the plurality of light emitting elements the current output from the first and second drive transistors flows.
　図９および図１０は、電源配線の構成例を示す図である。図９および図１０には、第１および第２ハイレベル電源電圧Ｖａｎ１、Ｖａｎ２を供給する電源配線の構成例が記載されている。図９に示す構成例では、画素回路１０の配置領域の上側に走査線ＳＬ１～ＳＬｍ（図示せず）と平行に、第１ハイレベル電源電圧Ｖａｎ１を供給するための第１幹配線と、第２ハイレベル電源電圧Ｖａｎ２を供給するための第２幹配線とが設けられる。画素回路１０の配置領域の下側にも同様に、第１および第２幹配線が設けられる。画素回路１０の各列の左側には両端が第１幹配線に接続された第１枝配線が設けられ、第１枝配線は１列の画素回路１０に接続される。画素回路１０の各列の右側には両端が第２幹配線に接続された第２枝配線が設けられ、第２枝配線は１列の画素回路１０に接続される。 FIG. 9 and FIG. 10 are diagrams showing a configuration example of the power supply wiring. FIGS. 9 and 10 show configuration examples of power supply wirings for supplying the first and second high-level power supply voltages Van1 and Van2. In the configuration example shown in FIG. 9, the first trunk wiring for supplying the first high-level power supply voltage Van1 is provided above the arrangement area of the pixel circuit 10 in parallel with the scanning lines SL1 to SLm (not shown); And a second trunk wiring for supplying the two high-level power supply voltage Van2. Similarly, the first and second trunk lines are provided below the arrangement area of the pixel circuit 10. On the left side of each column of the pixel circuit 10, a first branch wiring having both ends connected to the first trunk wiring is provided, and the first branch wiring is connected to the pixel circuit 10 in one column. On the right side of each column of the pixel circuit 10, a second branch wiring having both ends connected to the second trunk wiring is provided, and the second branch wiring is connected to the pixel circuit 10 in one column.
　図１０に示す構成例では、第１幹配線は画素回路１０の配置領域の上側と下側に走査線ＳＬ１～ＳＬｍ（図示せず）と平行に設けられ、第２幹配線は画素回路１０の配置領域の左側と右側にデータ線ＤＬ１～ＤＬｎ（図示せず）と平行に設けられる。画素回路１０の各列の左側には両端が第１幹配線に接続された第１枝配線が設けられ、第１枝配線は１列の画素回路１０に接続される。画素回路１０の各行の上側には両端が第２幹配線に接続された第２枝配線が設けられ、第２枝配線は１行の画素回路１０に接続される。 In the configuration example shown in FIG. 10, the first trunk wiring is provided in parallel with the scanning lines SL1 to SLm (not shown) on the upper side and the lower side of the arrangement area of the pixel circuit 10, and the second trunk wiring is provided on the pixel circuit 10. The data lines DL1 to DLn (not shown) are provided on the left side and the right side of the arrangement region in parallel. On the left side of each column of the pixel circuit 10, a first branch wiring having both ends connected to the first trunk wiring is provided, and the first branch wiring is connected to the pixel circuit 10 in one column. A second branch wiring having both ends connected to the second trunk wiring is provided on the upper side of each row of the pixel circuit 10, and the second branch wiring is connected to the pixel circuit 10 in one row.
　なお、図９に示す構成例において、電源配線の配置位置を９０度回転させてもよい。具体的には、画素回路１０の配置領域の左側と右側に第１および第２幹配線を設け、画素回路１０の各行の上側（または下側）に両端が第１幹配線に接続され、１行の画素回路１０に接続された第１枝配線を設け、画素回路１０の各行の下側（または上側）に両端が第２幹配線に接続され、１行の画素回路１０に接続された第２枝配線を設けてもよい。また、図１０に示す構成例において、第１幹配線および第１枝配線の配置位置と、第２幹配線および第２枝配線の配置位置とを入れ替えてもよい。また、第１ハイレベル電源電圧Ｖａｎ１を供給する電源配線と第２ハイレベル電源電圧Ｖａｎ２を供給する電源配線とを同じ配線層に形成してもよく、一方の電源配線の一部を他方の電源配線と同じ配線層に形成してもよい。 In the configuration example shown in FIG. 9, the arrangement position of the power supply wiring may be rotated by 90 degrees. Specifically, first and second trunk wirings are provided on the left and right sides of the arrangement area of the pixel circuit 10, and both ends are connected to the first trunk wiring on the upper side (or lower side) of each row of the pixel circuit 10. A first branch wiring connected to the pixel circuit 10 in the row is provided, and both ends of the pixel circuit 10 are connected to the second trunk wiring on the lower side (or upper side) of each row, and the first branch wiring connected to the pixel circuit 10 in the first row is connected. A two-branch wiring may be provided. In the configuration example shown in FIG. 10, the arrangement positions of the first trunk wiring and the first branch wiring may be interchanged with the arrangement positions of the second trunk wiring and the second branch wiring. Further, the power supply wiring for supplying the first high-level power supply voltage Van1 and the power supply wiring for supplying the second high-level power supply voltage Van2 may be formed in the same wiring layer, and part of one power supply wiring may be connected to the other power supply. You may form in the same wiring layer as wiring.
　図１１は、表示装置１のタイミングチャートである。図１１に示すように、各サブフレーム期間において、走査線ＳＬ１～ＳＬｍが１ライン期間ずつ順に選択され、選択された走査線には１ライン期間に亘って選択電圧（ハイレベル電圧）が印加される。第１サブフレーム期間では、走査線ＳＬｉが選択された後に発光制御線ＥＬｉａが選択される。第２サブフレーム期間では、走査線ＳＬｉが選択された後に発光制御線ＥＬｉｂが選択される。第３サブフレーム期間では、走査線ＳＬｉが選択された後に発光制御線ＥＬｉｃが選択される。選択された発光制御線には、時間Ｔｅだけ選択電圧が印加される。 FIG. 11 is a timing chart of the display device 1. As shown in FIG. 11, in each subframe period, the scanning lines SL1 to SLm are sequentially selected one line period at a time, and a selection voltage (high level voltage) is applied to the selected scanning line over one line period. The In the first subframe period, the light emission control line ELia is selected after the scanning line SLi is selected. In the second subframe period, the light emission control line ELib is selected after the scanning line SLi is selected. In the third subframe period, the light emission control line ELic is selected after the scanning line SLi is selected. A selection voltage is applied to the selected light emission control line for a time Te.
　図１２は、走査線の選択期間にデータ線に印加されるデータ電圧の種類、および、走査線の選択期間の後に選択される発光制御線を示す図である。以下、赤、緑、および、青の映像信号に対応したデータ電圧を、それぞれ、Ｒ電圧、Ｇ電圧、および、Ｂ電圧という。 FIG. 12 is a diagram showing the types of data voltages applied to the data lines during the scanning line selection period and the light emission control lines selected after the scanning line selection period. Hereinafter, data voltages corresponding to red, green, and blue video signals are referred to as R voltage, G voltage, and B voltage, respectively.
　第１サブフレーム期間の走査線ＳＬ１の選択期間では、データ線ＤＬ１～ＤＬ３にＲ電圧、Ｇ電圧、および、Ｂ電圧がそれぞれ印加され、これらの電圧は画素回路Ｐ（１，１）～Ｐ（１，３）にそれぞれ書き込まれる。その後、発光制御線ＥＬ１ａが選択され、画素回路Ｐ（１，１）内のトランジスタＱｒ、画素回路Ｐ（１，２）内のトランジスタＱｇ、および、画素回路Ｐ（１，３）内のトランジスタＱｂがオンする。したがって、画素回路Ｐ（１，１）内の有機ＥＬ素子ＬｒはＲ電圧に応じた輝度で発光し、画素回路Ｐ（１，２）内の有機ＥＬ素子ＬｇはＧ電圧に応じた輝度で発光し、画素回路（１，３）内の有機ＥＬ素子ＬｂはＢ電圧に応じた輝度で発光する。 In the selection period of the scanning line SL1 in the first subframe period, the R voltage, the G voltage, and the B voltage are applied to the data lines DL1 to DL3, respectively, and these voltages are applied to the pixel circuits P (1, 1) to P ( 1, 3) respectively. Thereafter, the light emission control line EL1a is selected, the transistor Qr in the pixel circuit P (1,1), the transistor Qg in the pixel circuit P (1,2), and the transistor Qb in the pixel circuit P (1,3). Turns on. Therefore, the organic EL element Lr in the pixel circuit P (1,1) emits light with a luminance corresponding to the R voltage, and the organic EL element Lg in the pixel circuit P (1,2) emits light with a luminance corresponding to the G voltage. The organic EL element Lb in the pixel circuit (1, 3) emits light with a luminance corresponding to the B voltage.
　第１サブフレーム期間の走査線ＳＬ２の選択期間では、データ線ＤＬ１～ＤＬ３にＧ電圧、Ｂ電圧、および、Ｒ電圧がそれぞれ印加され、これらの電圧は画素回路Ｐ（２，１）～Ｐ（２，３）にそれぞれ書き込まれる。その後、発光制御線ＥＬ２ａが選択され、画素回路Ｐ（２，１）内のトランジスタＱｇ、画素回路Ｐ（２，２）内のトランジスタＱｂ、および、画素回路Ｐ（２，３）内のトランジスタＱｒがオンする。したがって、画素回路Ｐ（２，１）内の有機ＥＬ素子ＬｇはＧ電圧に応じた輝度で発光し、画素回路Ｐ（２，２）内の有機ＥＬ素子ＬｂはＢ電圧に応じた輝度で発光し、画素回路Ｐ（２，３）内の有機ＥＬ素子ＬｒはＲ電圧に応じた輝度で発光する。 In the selection period of the scanning line SL2 in the first subframe period, the G voltage, the B voltage, and the R voltage are applied to the data lines DL1 to DL3, respectively, and these voltages are applied to the pixel circuits P (2, 1) to P ( 2, 3) respectively. Thereafter, the light emission control line EL2a is selected, and the transistor Qg in the pixel circuit P (2,1), the transistor Qb in the pixel circuit P (2,2), and the transistor Qr in the pixel circuit P (2,3). Turns on. Therefore, the organic EL element Lg in the pixel circuit P (2, 1) emits light with a luminance corresponding to the G voltage, and the organic EL element Lb in the pixel circuit P (2, 2) emits light with a luminance corresponding to the B voltage. The organic EL element Lr in the pixel circuit P (2, 3) emits light with a luminance corresponding to the R voltage.
　同様に、第１サブフレーム期間の走査線ＳＬ３の選択期間の後に、画素回路Ｐ（３，１）内の有機ＥＬ素子ＬｂはＢ電圧に応じた輝度で発光し、画素回路Ｐ（３，２）内の有機ＥＬ素子ＬｒはＲ電圧に応じた輝度で発光し、画素回路Ｐ（３，３）内の有機ＥＬ素子ＬｇはＧ電圧に応じた輝度で発光する。この結果、第１サブフレーム期間では、画素回路Ｐ（１，１）、Ｐ（２，３）、Ｐ（３，２）の表示色は赤の映像信号に応じた色（黒から赤までの範囲内の色）になり、画素回路Ｐ（１，２）、Ｐ（２，１）、Ｐ（３，３）の表示色は緑の映像信号に応じた色（黒から緑までの範囲内の色）になり、画素回路Ｐ（１，３）、Ｐ（２，２）、Ｐ（３，１）の表示色は青の映像信号に応じた色（黒から青までの範囲内の色）になる。 Similarly, after the selection period of the scanning line SL3 in the first subframe period, the organic EL element Lb in the pixel circuit P (3, 1) emits light with a luminance corresponding to the B voltage, and the pixel circuit P (3, 2 ) In the pixel circuit P (3, 3) emits light with a luminance corresponding to the G voltage. As a result, in the first subframe period, the display colors of the pixel circuits P (1,1), P (2,3), P (3,2) are colors corresponding to the red video signal (from black to red). The display color of the pixel circuits P (1,2), P (2,1), P (3,3) is a color corresponding to the green video signal (in the range from black to green). The display colors of the pixel circuits P (1,3), P (2,2), P (3,1) are colors corresponding to the blue video signal (colors in the range from black to blue). )become.
　表示装置１は、第２および第３サブフレーム期間において、第１サブフレーム期間と同様に動作する。このようにして表示装置１は、図２に示す表示パターンシーケンスに従い、１フレーム期間に３枚のサブフレームを表示する。 The display device 1 operates in the second and third subframe periods in the same manner as in the first subframe period. In this way, the display device 1 displays three subframes in one frame period according to the display pattern sequence shown in FIG.
　図１３は、表示装置１における階調とゲート電圧と輝度の範囲を示す図である。表示装置１では、階調は、最小階調から最大階調までの範囲内で変化する。これに対応して、トランジスタＱ１、Ｑ２のゲート電圧はＶｇｍｉｎからＶｇｚまでの範囲内で変化し、有機ＥＬ素子の輝度は最小輝度から最大階調輝度（階調表示における最大輝度）までの範囲内で変化する。表示装置１は、表示画像によっては、有機ＥＬ素子の輝度を最大階調輝度よりも高くすることがある。以下、表示装置１で用いられる輝度の最大値を最大輝度といい、最大輝度に対応したトランジスタＱ１、Ｑ２のゲート電圧をＶｇｍａｘという。最大輝度は、例えば、最大階調輝度の１倍以上かつ数倍以下に設定される。最大階調輝度よりも高い輝度は、例えば、低輝度の領域の中に高輝度の小さな点を表示する場合などに用いられる。 FIG. 13 is a diagram showing a range of gradation, gate voltage, and luminance in the display device 1. In the display device 1, the gradation changes within the range from the minimum gradation to the maximum gradation. Correspondingly, the gate voltages of the transistors Q1 and Q2 change in the range from Vgmin to Vgz, and the luminance of the organic EL element is in the range from the minimum luminance to the maximum gradation luminance (maximum luminance in gradation display). It changes with. The display device 1 may make the luminance of the organic EL element higher than the maximum gradation luminance depending on the display image. Hereinafter, the maximum value of luminance used in the display device 1 is referred to as maximum luminance, and the gate voltages of the transistors Q1, Q2 corresponding to the maximum luminance are referred to as Vgmax. For example, the maximum luminance is set to be not less than 1 and not more than several times the maximum gradation luminance. The brightness higher than the maximum gradation brightness is used when, for example, a small point with high brightness is displayed in a low brightness area.
　図１４は、発光期間における画素回路１０の等価回路図である。発光期間では、トランジスタＱ３はオフ状態になり、トランジスタＱｒ、Ｑｇ、Ｑｂのうちのいずれか１個がオン状態になり、残りの２個はオフ状態になる。図１４に示す有機ＥＬ素子Ｌ１は、有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂのうち、オン状態のトランジスタに接続されたものを表す。以下、トランジスタＱ１、Ｑ２のゲート電圧をＶｇ、トランジスタＱ１、Ｑ２のソース電圧をＶｓ、トランジスタＱ１、Ｑ２の閾値電圧をそれぞれＶｔｈ１、Ｖｔｈ２、有機ＥＬ素子Ｌ１の発光閾値電圧をＶｔｈｏとする。 FIG. 14 is an equivalent circuit diagram of the pixel circuit 10 during the light emission period. In the light emission period, the transistor Q3 is turned off, one of the transistors Qr, Qg, and Qb is turned on, and the other two are turned off. An organic EL element L1 illustrated in FIG. 14 represents an element connected to an on-state transistor among the organic EL elements Lr, Lg, and Lb. Hereinafter, the gate voltages of the transistors Q1 and Q2 are Vg, the source voltages of the transistors Q1 and Q2 are Vs, the threshold voltages of the transistors Q1 and Q2 are Vth1 and Vth2, respectively, and the light emission threshold voltage of the organic EL element L1 is Vtho.
　信号の伝搬損失を無視すれば、ゲート電圧Ｖｇは、データ線駆動回路５がデータ線ＤＬｊに印加するデータ電圧に等しい。トランジスタＱ１は、ゲート電圧Ｖｇに応じた電流Ｉｄｓ１を出力する。トランジスタＱ２は、同じゲート電圧Ｖｇに応じた電流Ｉｄｓ２を出力する。電流Ｉｄｓ１、Ｉｄｓ２は合流し、有機ＥＬ素子Ｌ１を流れる電流Ｉｏｌｅｄとなる。ゲート電圧Ｖｇが高いほど、電流Ｉｄｓ１、Ｉｄｓ２は多くなり、電流Ｉｏｌｅｄも多くなる。 If the signal propagation loss is ignored, the gate voltage Vg is equal to the data voltage applied to the data line DLj by the data line driving circuit 5. The transistor Q1 outputs a current Ids1 corresponding to the gate voltage Vg. The transistor Q2 outputs a current Ids2 corresponding to the same gate voltage Vg. The currents Ids1 and Ids2 merge to become a current Ioled that flows through the organic EL element L1. As the gate voltage Vg increases, the currents Ids1 and Ids2 increase and the current Ioled also increases.
　トランジスタＱ１は、ゲート電圧ＶｇがＶｇｍｉｎからＶｇｍａｘまでの範囲内にあるときには飽和領域で動作する。トランジスタＱ２は、ゲート電圧ＶｇがＶｇｍｉｎからＶｇｚまでの範囲内にあるときには飽和領域で動作し、ゲート電圧ＶｇがＶｇｚからＶｇｍａｘまでの範囲内にあるときには線形領域で動作する。 The transistor Q1 operates in the saturation region when the gate voltage Vg is in the range from Vgmin to Vgmax. The transistor Q2 operates in the saturation region when the gate voltage Vg is in the range from Vgmin to Vgz, and operates in the linear region when the gate voltage Vg is in the range from Vgz to Vgmax.
　トランジスタＱ１、Ｑ２が上記のように動作するためには、以下の第１～第３の条件を満たす必要がある。トランジスタＱ１のゲート－ソース間電圧をＶｇｓ１、トランジスタＱ１のドレイン－ソース間電圧をＶｄｓ１、トランジスタＱ２のゲート－ソース間電圧をＶｇｓ２、トランジスタＱ２のドレイン－ソース間電圧をＶｄｓ２としたとき、トランジスタＱ１、Ｑ２が共に飽和領域で動作するための条件は、次式（１ａ）、（１ｂ）で与えられる。
　　Ｖｇｓ１－Ｖｔｈ１≦Ｖｄｓ１　…（１ａ）
　　Ｖｇｓ２－Ｖｔｈ２≦Ｖｄｓ２　…（１ｂ）
　トランジスタＱ１が飽和領域で動作し、トランジスタＱ２が線形領域で動作するための条件は、次式（２ａ）、（２ｂ）で与えられる。
　　Ｖｇｓ１－Ｖｔｈ１≦Ｖｄｓ１　…（２ａ）
　　Ｖｇｓ２－Ｖｔｈ２＞Ｖｄｓ２　…（２ｂ） In order for the transistors Q1 and Q2 to operate as described above, the following first to third conditions must be satisfied. When the gate-source voltage of the transistor Q1 is Vgs1, the drain-source voltage of the transistor Q1 is Vds1, the gate-source voltage of the transistor Q2 is Vgs2, and the drain-source voltage of the transistor Q2 is Vds2, the transistor Q1, Conditions for both Q2 to operate in the saturation region are given by the following equations (1a) and (1b).
Vgs1-Vth1 ≦ Vds1 (1a)
Vgs2-Vth2 ≦ Vds2 (1b)
Conditions for the transistor Q1 to operate in the saturation region and the transistor Q2 to operate in the linear region are given by the following equations (2a) and (2b).
Vgs1-Vth1 ≦ Vds1 (2a)
Vgs2-Vth2> Vds2 (2b)
　式（１ａ）、（１ｂ）にＶｇｓ１＝Ｖｇｓ２＝Ｖｇ－Ｖｓ、Ｖｄｓ１＝Ｖａｎ１－Ｖｓ、Ｖｄｓ２＝Ｖａｎ２－Ｖｓを代入すると、次式（３ａ）、（３ｂ）が導かれる。
　　Ｖｇ≦Ｖａｎ１＋Ｖｔｈ１　…（３ａ）
　　Ｖｇ≦Ｖａｎ２＋Ｖｔｈ２　…（３ｂ）
　したがって、ゲート電圧ＶｇがＶｇｍｉｎからＶｇｚまでの範囲内にあるときにトランジスタＱ１、Ｑ２が共に飽和領域で動作するための条件は、Ｖｇｍｉｎ≦Ｖｇ≦Ｖｇｚを満たす電圧Ｖｇについて式（３ａ）、（３ｂ）が成立することである（第１の条件）。 Substituting Vgs1 = Vgs2 = Vg−Vs, Vds1 = Van1−Vs, and Vds2 = Van2−Vs into the expressions (1a) and (1b), the following expressions (3a) and (3b) are derived.
Vg ≦ Van1 + Vth1 (3a)
Vg ≦ Van2 + Vth2 (3b)
Therefore, when the gate voltage Vg is in the range from Vgmin to Vgz, the conditions for both of the transistors Q1 and Q2 to operate in the saturation region are the expressions (3a) and (3b) for the voltage Vg that satisfies Vgmin ≦ Vg ≦ Vgz. ) Is established (first condition).
　同様に、式（２ａ）、（２ｂ）から次式（４ａ）、（４ｂ）が導かれ、式（４ａ）、（４ｂ）から次式（５）が導かれる。
　　Ｖｇ≦Ｖａｎ１＋Ｖｔｈ１　…（４ａ）
　　Ｖｇ＞Ｖａｎ２＋Ｖｔｈ２　…（４ｂ）
　　Ｖａｎ２＋Ｖｔｈ２＜Ｖｇ≦Ｖａｎ１＋Ｖｔｈ１　…（５）
　したがって、ゲート電圧ＶｇがＶｇｚからＶｇｍａｘまでの範囲内にあるときにトランジスタＱ１が飽和領域で動作し、トランジスタＱ２が線形領域で動作するための条件は、Ｖｇｚ＜Ｖｇ≦Ｖｇｍａｘを満たす電圧Ｖｇについて式（５）が成立することである（第２の条件）。なお、式（５）より、式（３ｂ）が成立すれば式（３ａ）は必ず成立するので、第１の条件では必ずしも式（３ａ）を考慮する必要はない。 Similarly, the following equations (4a) and (4b) are derived from the equations (2a) and (2b), and the following equation (5) is derived from the equations (4a) and (4b).
Vg ≦ Van1 + Vth1 (4a)
Vg> Van2 + Vth2 (4b)
Van2 + Vth2 <Vg ≦ Van1 + Vth1 (5)
Therefore, when the gate voltage Vg is in the range from Vgz to Vgmax, the condition for the transistor Q1 to operate in the saturation region and the transistor Q2 to operate in the linear region is the expression for the voltage Vg that satisfies Vgz <Vg ≦ Vgmax. (5) is satisfied (second condition). In addition, from Formula (5), if Formula (3b) is materialized, Formula (3a) will necessarily be materialized, Therefore In the 1st condition, it is not necessary to consider Formula (3a).
　また、消費電力の損失を防止するためには、ソース電圧Ｖｓが高いときでもトランジスタＱ２に逆方向電流が流れないことが必要である。したがって、Ｖｇｍｉｎ≦Ｖｇ≦Ｖｇｍａｘを満たす電圧Ｖｇについて、次式（６）が成立する必要がある（第３の条件）。
　　Ｖｄｓ２＞０　…（６） Further, in order to prevent the loss of power consumption, it is necessary that no reverse current flows through the transistor Q2 even when the source voltage Vs is high. Therefore, for the voltage Vg that satisfies Vgmin ≦ Vg ≦ Vgmax, the following equation (6) needs to be satisfied (third condition).
Vds2> 0 (6)
　表示装置１では、階調表示を行うときには、トランジスタＱ１、Ｑ２が共に飽和領域で動作し、有機ＥＬ素子の輝度を最大階調輝度よりも高くするときには、トランジスタＱ１が飽和領域で動作し、トランジスタＱ２が線形領域で動作するように、画素回路１０に関する電圧が決定される。 In the display device 1, when performing gradation display, both the transistors Q1 and Q2 operate in the saturation region, and when the luminance of the organic EL element is higher than the maximum gradation luminance, the transistor Q1 operates in the saturation region. The voltage for the pixel circuit 10 is determined so that Q2 operates in the linear region.
　電流Ｉｄｓ１、Ｉｄｓ２の割合は、ＶｇｍｉｎからＶｇｍａｘまでの範囲がデータ線駆動回路５の出力電圧の範囲内に入るように決定される。また、トランジスタＱ１、Ｑ２の閾値電圧Ｖｔｈ１、Ｖｔｈ２について、Ｖｔｈ１＜Ｖｔｈ２が成立するようにする。このためには、例えば、トランジスタＱ１のチャネル長をトランジスタＱ２のチャネル長よりも短くすればよい。これにより、ゲート電圧がＶｔｈ１以上かつＶｔｈ２未満のときには、トランジスタＱ１はオンし、トランジスタＱ２はオフする。このとき、電流Ｉｄｓ２はほぼ０になり、電流Ｉｏｌｅｄは電流Ｉｄｓ１にほぼ等しくなる。 The ratio of the currents Ids1 and Ids2 is determined so that the range from Vgmin to Vgmax falls within the range of the output voltage of the data line driving circuit 5. Further, Vth1 <Vth2 is established for the threshold voltages Vth1 and Vth2 of the transistors Q1 and Q2. For this purpose, for example, the channel length of the transistor Q1 may be shorter than the channel length of the transistor Q2. Thus, when the gate voltage is equal to or higher than Vth1 and lower than Vth2, the transistor Q1 is turned on and the transistor Q2 is turned off. At this time, the current Ids2 is substantially 0, and the current Ioled is substantially equal to the current Ids1.
　式（５）より、トランジスタＱ１が飽和領域で動作し、トランジスタＱ２が線形領域で動作するゲート電圧Ｖｇの範囲の大きさは、（Ｖａｎ１－Ｖａｎ２＋Ｖｔｈ１－Ｖｔｈ２）である。したがって、表示装置１によれば、有機ＥＬ素子の輝度を階調表示のときよりもこの範囲の大きさの分だけ高くすることができる。 From Equation (5), the magnitude of the range of the gate voltage Vg in which the transistor Q1 operates in the saturation region and the transistor Q2 operates in the linear region is (Van1-Van2 + Vth1-Vth2). Therefore, according to the display device 1, the luminance of the organic EL element can be increased by the size of this range compared to the gradation display.
　また、ゲート電圧ＶｇがＶｇｍｉｎに等しいときに、トランジスタＱ１のゲート－ソース間電圧がＶｔｈ１になり、有機ＥＬ素子Ｌ１のアノード－カソード間電圧がＶｔｈｏになるので、次式（７）が成立する。
　　Ｖｇｍｉｎ＝Ｖｓ＋Ｖｔｈ１
　　　　　　　＝Ｖａｃ＋Ｖｔｈｏ＋Ｖｔｈ１　…（７） Further, when the gate voltage Vg is equal to Vgmin, the gate-source voltage of the transistor Q1 becomes Vth1 and the anode-cathode voltage of the organic EL element L1 becomes Vth0, so the following equation (7) is established.
Vgmin = Vs + Vth1
= Vac + Vtho + Vth1 (7)
　以下、画素回路１０に関する電圧の具体例を説明する。ここでは、画素回路１０はデータ保持部２２（図６）を含み、Ｖｔｈ１＝２．０Ｖ、Ｖｔｈ２＝２．５Ｖ、Ｖａｎ１＝８．０Ｖ、Ｖａｎ２＝４．０Ｖ、Ｖａｃ＝－４．０Ｖ、Ｖｔｈｏ＝４．６Ｖであるとする。図１５は、トランジスタＱ１、Ｑ２について、ゲート－ソース間電圧と閾値電圧の差（Ｖｇｓ－Ｖｔｈ）とドレイン－ソース間電圧Ｖｄｓとの関係を示す特性図である。図１６は、トランジスタＱ１、Ｑ２について、ゲート電圧Ｖｇとドレイン－ソース間電圧Ｖｄｓとの関係を示す特性図である。図１７は、ゲート電圧Ｖｇと電流Ｉｏｌｅｄとの関係を示す特性図である。図１７には、参考として、データ保持部２１、２３を含む画素回路１０を用いた場合の関係も記載されている。 Hereinafter, a specific example of the voltage related to the pixel circuit 10 will be described. Here, the pixel circuit 10 includes a data holding unit 22 (FIG. 6), and Vth1 = 2.0V, Vth2 = 2.5V, Van1 = 8.0V, Van2 = 4.0V, Vac = −4.0V, Vtho. = 4.6V. FIG. 15 is a characteristic diagram showing the relationship between the gate-source voltage and the threshold voltage difference (Vgs−Vth) and the drain-source voltage Vds for the transistors Q1 and Q2. FIG. 16 is a characteristic diagram showing the relationship between the gate voltage Vg and the drain-source voltage Vds for the transistors Q1 and Q2. FIG. 17 is a characteristic diagram showing the relationship between the gate voltage Vg and the current Ioled. For reference, FIG. 17 also shows the relationship when the pixel circuit 10 including the data holding units 21 and 23 is used.
　図１５および図１６に示すように、トランジスタＱ１は、Ｖｇｓ－Ｖｔｈ≦５．０Ｖのとき（Ｖｇ≦１０．０Ｖのとき）には飽和領域で動作する。トランジスタＱ２は、Ｖｇｓ－Ｖｔｈ≦１．８Ｖのとき（Ｖｇ≦６．５Ｖのとき）には飽和領域で動作し、Ｖｇｓ－Ｖｔｈ＞１．８Ｖのとき（Ｖｇ＞６．５Ｖのとき）には線形領域で動作する。この例では、Ｖｇｚ＝６．５Ｖとなる。Ｖｇ≦６．５Ｖのときには、トランジスタＱ１、Ｑ２は飽和領域で動作するので、電流Ｉｏｌｅｄはゲート電圧Ｖｇの２乗に比例する。このため、Ｖｇ≦６．５Ｖのときには、画素回路１０の電圧－電流特性は、γ＝２．２のγ特性によく一致する。 As shown in FIGS. 15 and 16, the transistor Q1 operates in the saturation region when Vgs−Vth ≦ 5.0V (when Vg ≦ 10.0V). The transistor Q2 operates in a saturation region when Vgs−Vth ≦ 1.8V (when Vg ≦ 6.5V), and when Vgs−Vth> 1.8V (when Vg> 6.5V). Operates in the linear region. In this example, Vgz = 6.5V. When Vg ≦ 6.5V, since the transistors Q1 and Q2 operate in the saturation region, the current Ioled is proportional to the square of the gate voltage Vg. For this reason, when Vg ≦ 6.5V, the voltage-current characteristic of the pixel circuit 10 matches well with the γ characteristic of γ = 2.2.
　この例では、式（７）より、Ｖｇｍｉｎ＝２．６Ｖとなる。したがって、ゲート電圧Ｖｇが２．６Ｖから６．５Ｖまでの範囲内にあるときには、階調表示が行われる。また、Ｖｇｚ＋（Ｖａｎ１－Ｖａｎ２＋Ｖｔｈ１－Ｖｔｈ２）＝１０．０Ｖである。したがって、ゲート電圧Ｖｇが６．５Ｖから１０．０Ｖまでの範囲内にあるときには、有機ＥＬ素子の輝度は最大階調輝度よりも高くなる。この例では、有機ＥＬ素子の輝度を階調表示のときよりも３．５Ｖ分だけ高くすることができる。 In this example, Vgmin = 2.6V from Equation (7). Therefore, when the gate voltage Vg is in the range from 2.6V to 6.5V, gradation display is performed. Further, Vgz + (Van1-Van2 + Vth1-Vth2) = 10.0V. Therefore, when the gate voltage Vg is in the range from 6.5 V to 10.0 V, the luminance of the organic EL element is higher than the maximum gradation luminance. In this example, the luminance of the organic EL element can be increased by 3.5 V compared to the gradation display.
　なお、以上の例では、Ｖｔｈ＝２．０Ｖ、Ｖｔｈ２＝２．５Ｖ、Ｖａｎ１＝８．０Ｖ、Ｖａｎ２＝４．０Ｖとして、ゲート電圧Ｖｇを２．６Ｖから１０．０Ｖまでの範囲内で変化させることとしたが、Ｖａｎ１、Ｖａｎ２、Ｖｔｈ１、Ｖｔｈ２の値を好適に選択して、階調表示に対応した輝度の範囲と最大階調輝度よりも高い輝度の範囲を任意に決定することができる。 In the above example, Vth = 2.0V, Vth2 = 2.5V, Van1 = 8.0V, Van2 = 4.0V, and the gate voltage Vg is changed within the range from 2.6V to 10.0V. However, the values of Van1, Van2, Vth1, and Vth2 can be suitably selected, and the luminance range corresponding to gradation display and the luminance range higher than the maximum gradation luminance can be arbitrarily determined.
　以下、本実施形態に係る表示装置１の効果を説明する。上述したように、フィールドシーケンシャルカラー方式の有機ＥＬ表示装置の画素の輝度は、フィールドシーケンシャルカラー方式ではない有機ＥＬ表示装置よりも小さくなる。また、画素の最大輝度を高くするためにデータ電圧の振幅を大きくすると、データ線駆動回路の消費電力が増大する。この問題は、画素の輝度を階調表示における最大輝度よりも高くする機能を有する有機ＥＬ表示装置においてより顕著になる。 Hereinafter, effects of the display device 1 according to the present embodiment will be described. As described above, the luminance of the pixels of the field sequential color type organic EL display device is smaller than that of the organic EL display device not using the field sequential color method. Further, when the amplitude of the data voltage is increased in order to increase the maximum luminance of the pixel, the power consumption of the data line driving circuit increases. This problem becomes more prominent in an organic EL display device having a function of making the luminance of a pixel higher than the maximum luminance in gradation display.
　本実施形態に係る表示装置１は、（ｍ×ｎ）個の画素回路１０と走査線ＳＬ１～ＳＬｍとデータ線ＤＬ１～ＤＬｎと３ｍ本の発光制御線とを含む表示部２、および、走査線駆動回路４とデータ線駆動回路５と発光制御線駆動回路６とを含む駆動回路を備えている。画素回路１０は、有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂと、ドレイン端子に第１ハイレベル電源電圧Ｖａｎ１が印加され、ゲート電圧に応じた電流を出力するトランジスタＱ１と、ドレイン端子に第２ハイレベル電源電圧Ｖａｎ２が印加され、ソース端子がトランジスタＱ１のソース端子に接続され、ゲート電圧に応じた電流を出力するトランジスタＱ２と、トランジスタＱ１、Ｑ２から出力された電流を有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂのいずれに流すかを切り替える選択回路（トランジスタＱｒ、Ｑｇ、Ｑｂ）とを含んでいる。トランジスタＱ１は、ゲート電圧Ｖｇが所定範囲内にあるとき（Ｖｇｍｉｎ≦Ｖｇ≦Ｖｇｍａｘのとき）には飽和領域で動作する。トランジスタＱ２は、ゲート電圧Ｖｇが所定範囲の一部である第１範囲内にあるとき（Ｖｇｍｉｎ≦Ｖｇ≦Ｖｇｚのとき）には飽和領域で動作し、ゲート電圧Ｖｇが所定範囲の残部である第２範囲内にあるとき（Ｖｇｚ＜Ｖｇ≦Ｖｇｍａｘのとき）には線形領域で動作する。 The display device 1 according to the present embodiment includes a display unit 2 including (m × n) pixel circuits 10, scanning lines SL1 to SLm, data lines DL1 to DLn, and 3m emission control lines, and scanning lines. A drive circuit including a drive circuit 4, a data line drive circuit 5, and a light emission control line drive circuit 6 is provided. The pixel circuit 10 includes an organic EL element Lr, Lg, and Lb, a transistor Q1 that outputs a current corresponding to a gate voltage by applying a first high-level power supply voltage Van1 to a drain terminal, and a second high-level power supply to a drain terminal. The voltage Van2 is applied, the source terminal is connected to the source terminal of the transistor Q1, the transistor Q2 outputs a current corresponding to the gate voltage, and the current output from the transistors Q1 and Q2 is output from the organic EL elements Lr, Lg, and Lb. It includes a selection circuit (transistors Qr, Qg, Qb) for switching to which of them flows. The transistor Q1 operates in a saturation region when the gate voltage Vg is within a predetermined range (when Vgmin ≦ Vg ≦ Vgmax). The transistor Q2 operates in the saturation region when the gate voltage Vg is within a first range that is a part of the predetermined range (when Vgmin ≦ Vg ≦ Vgz), and the gate voltage Vg is the remainder of the predetermined range. When in the 2 range (when Vgz <Vg ≦ Vgmax), it operates in the linear region.
　このように、飽和領域で動作するトランジスタＱ１に加えて、ゲート電圧に応じて飽和領域または線形領域で動作するトランジスタＱ２を画素回路１０に設けることにより、データ線駆動回路５から出力されるデータ電圧の振幅を大きくすることなく、有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂのいずれかに流れる電流を増加させて、画素の最大輝度を高くすることができる。したがって、フィールドシーケンシャルカラー方式の表示装置において、駆動回路の消費電力を増大させずに、画素の最大輝度を高くすることができる。 Thus, in addition to the transistor Q1 that operates in the saturation region, the transistor Q2 that operates in the saturation region or the linear region in accordance with the gate voltage is provided in the pixel circuit 10, so that the data voltage output from the data line driving circuit 5 is increased. The maximum luminance of the pixel can be increased by increasing the current flowing in any one of the organic EL elements Lr, Lg, and Lb without increasing the amplitude of. Therefore, in the field sequential color display device, the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit.
　また、第１範囲内の電圧は階調表示で用いられる電圧であり、第２範囲内の電圧は最大階調輝度よりも高い輝度に対応した電圧である。このため、階調表示のときにはトランジスタＱ１、Ｑ２は飽和領域で動作し、輝度を最大階調輝度よりも高くするときには、トランジスタＱ１は飽和領域で動作し、トランジスタＱ２は線形領域で動作する。このようにトランジスタＱ２の動作を切り替えて、画素の輝度を最大階調輝度よりも高くすることができる。 Also, the voltage in the first range is a voltage used for gradation display, and the voltage in the second range is a voltage corresponding to a luminance higher than the maximum gradation luminance. Therefore, the transistors Q1 and Q2 operate in the saturation region during gradation display, and when the luminance is higher than the maximum gradation luminance, the transistor Q1 operates in the saturation region and the transistor Q2 operates in the linear region. In this way, the operation of the transistor Q2 can be switched to make the luminance of the pixel higher than the maximum gradation luminance.
　また、トランジスタＱ１、Ｑ２のゲート端子は、同じ節点に接続されている。したがって、トランジスタＱ１、Ｑ２のゲート端子に同じ電圧を印加して、駆動回路の消費電力を増大させずに画素の最大輝度を高くする効果を容易に得ることができる。また、画素回路１０は、データ線駆動回路５から出力されたデータ電圧をトランジスタＱ１、Ｑ２の制御端子に与えるトランジスタＱ３と、トランジスタＱ１、Ｑ２のゲート電圧を保持するコンデンサＣ１とをさらに含んでいる。画素回路１０にトランジスタＱ３とコンデンサＣ１を設けることにより、データ線駆動回路５から出力されたデータ電圧をトランジスタＱ１、Ｑ２のゲート端子に与え、与えた電圧を保持することができる。また、トランジスタＱｒ、Ｑｇ、ＱｂはトランジスタＱ１、Ｑ２のソース端子と有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂとの間にそれぞれ設けられ、トランジスタＱｒ、Ｑｇ、Ｑｂのゲート端子は発光制御線に接続される。これにより、トランジスタＱ１、Ｑ２から出力された電流を有機ＥＬ素子Ｌｒ、Ｌｇ、Ｌｂのいずれに流すかを切り替える選択回路を構成することができる。 The gate terminals of the transistors Q1 and Q2 are connected to the same node. Therefore, it is possible to easily obtain the effect of increasing the maximum luminance of the pixel without increasing the power consumption of the driving circuit by applying the same voltage to the gate terminals of the transistors Q1 and Q2. The pixel circuit 10 further includes a transistor Q3 that supplies the data voltage output from the data line driving circuit 5 to the control terminals of the transistors Q1 and Q2, and a capacitor C1 that holds the gate voltages of the transistors Q1 and Q2. . By providing the transistor Q3 and the capacitor C1 in the pixel circuit 10, the data voltage output from the data line driving circuit 5 can be applied to the gate terminals of the transistors Q1 and Q2, and the applied voltage can be held. The transistors Qr, Qg, and Qb are provided between the source terminals of the transistors Q1 and Q2 and the organic EL elements Lr, Lg, and Lb, respectively, and the gate terminals of the transistors Qr, Qg, and Qb are connected to the light emission control line. . Thereby, it is possible to configure a selection circuit that switches which of the organic EL elements Lr, Lg, and Lb flows the current output from the transistors Q1 and Q2.
　本実施形態に係る表示装置１については、各種の変形例を構成することができる。例えば、トランジスタＱ１、Ｑ２のゲート端子に対して異なる電圧を印加できるように表示装置を構成してもよい。この変形例に係る表示装置によれば、トランジスタＱ１、Ｑ２のゲート端子に異なる電圧を印加することにより、有機ＥＬ素子を流れる電流を高い自由度で制御し、画素の輝度を高い自由度で制御することができる。また、トランジスタＱ２が動作を切り替える境界の電圧Ｖｇｚは、最大階調に対応したゲート電圧でなくてもよい。電圧Ｖｇｚは、最大階調をα倍（０＜α＜１）した階調に対応したゲート電圧でもよい。また、表示装置は、図４～図８とは異なる画素回路を備えていてもよい。例えば、画素回路は、Ｐチャネル型のトランジスタを含んでいてもよく、トランジスタＱ１を複数含んでいてもよく、トランジスタＱ２を複数含んでいてもよく、赤、緑、および、青以外の色に発光する有機ＥＬ素子を含んでいてもよい。また、画素回路は、第１および第２駆動トランジスタ以外の素子を図４～図８とは異なる形態に接続したものでもよい。また、表示装置は、図２とは異なる表示パターンシーケンスに従って動作してもよい。これら変形例に係る表示装置によっても、表示装置１と同様に、駆動回路の消費電力を増大させずに、画素の最大輝度を高くすることができる。 Various modifications can be configured for the display device 1 according to the present embodiment. For example, the display device may be configured so that different voltages can be applied to the gate terminals of the transistors Q1 and Q2. According to the display device according to this modification, by applying different voltages to the gate terminals of the transistors Q1 and Q2, the current flowing through the organic EL element is controlled with a high degree of freedom, and the luminance of the pixel is controlled with a high degree of freedom. can do. Further, the boundary voltage Vgz at which the transistor Q2 switches operation may not be a gate voltage corresponding to the maximum gradation. The voltage Vgz may be a gate voltage corresponding to a gradation obtained by multiplying the maximum gradation by α (0 <α <1). Further, the display device may include a pixel circuit different from those in FIGS. For example, the pixel circuit may include a P-channel transistor, may include a plurality of transistors Q1, may include a plurality of transistors Q2, and emits light in colors other than red, green, and blue. The organic EL element to be used may be included. Further, the pixel circuit may be one in which elements other than the first and second drive transistors are connected in a form different from that shown in FIGS. The display device may operate according to a display pattern sequence different from that in FIG. Also with the display devices according to these modified examples, similarly to the display device 1, the maximum luminance of the pixels can be increased without increasing the power consumption of the drive circuit.
　以上に示すように、本発明の表示装置によれば、飽和領域で動作する第１駆動トランジスタに加えて、制御端子の電圧に応じて飽和領域または線形領域で動作する第２駆動トランジスタを画素回路に設けることにより、駆動回路から出力されるデータ電圧の振幅を大きくすることなく、発光素子を流れる電流を増加させて、画素の最大輝度を高くすることができる。したがって、フィールドシーケンシャルカラー方式の表示装置において、駆動回路の消費電力を増大させずに、画素の最大輝度を高くすることができる。 As described above, according to the display device of the present invention, in addition to the first drive transistor that operates in the saturation region, the second drive transistor that operates in the saturation region or the linear region according to the voltage of the control terminal is provided with the pixel circuit. Accordingly, the maximum luminance of the pixel can be increased by increasing the current flowing through the light emitting element without increasing the amplitude of the data voltage output from the driving circuit. Therefore, in the field sequential color display device, the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit.
　本発明の表示装置は、駆動回路の消費電力を増大させずに、画素の最大輝度を高くすることができるという特徴を有するので、各種の電子機器の表示部などに利用することができる。 Since the display device of the present invention has the feature that the maximum luminance of the pixel can be increased without increasing the power consumption of the driving circuit, it can be used for a display unit of various electronic devices.
　１…表示装置
　２…表示部
　３…表示制御回路
　４…走査線駆動回路
　５…データ線駆動回路
　６…発光制御線駆動回路
　１０…画素回路
　２０、２１、２２、２３…データ保持部 DESCRIPTION OF SYMBOLS 1 ... Display apparatus 2 ... Display part 3 ... Display control circuit 4 ... Scanning line drive circuit 5 ... Data line drive circuit 6 ... Light emission control line drive circuit 10 ... Pixel circuit 20, 21, 22, 23 ... Data holding part

Claims (11)

  1. 　１フレーム期間に複数のサブフレームを表示する表示装置であって、
    　２次元状に配置された複数の画素回路を含む表示部と、
    　各サブフレーム期間において、前記複数の画素回路に対して書き込みおよび発光制御を行う駆動回路とを備え、
    　前記画素回路は、
    　　互いに異なる色に発光する複数の発光素子と、
    　　一方の導通端子に第１電源電圧が印加され、制御端子の電圧に応じた電流を出力する第１駆動トランジスタと、
    　　一方の導通端子に第２電源電圧が印加され、他方の導通端子が前記第１駆動トランジスタの他方の導通端子に接続され、制御端子の電圧に応じた電流を出力する第２駆動トランジスタと、
    　　前記第１および第２駆動トランジスタから出力された電流を前記複数の発光素子のいずれに流すかを切り替える選択回路とを含み、
    　前記第１駆動トランジスタは、制御端子の電圧が所定範囲内にあるときには飽和領域で動作し、前記第２駆動トランジスタは、制御端子の電圧が前記所定範囲の一部である第１範囲内にあるときには飽和領域で動作し、制御端子の電圧が前記所定範囲の残部である第２範囲内にあるときには線形領域で動作することを特徴とする、表示装置。     A display device that displays a plurality of subframes in one frame period,
    A display unit including a plurality of pixel circuits arranged two-dimensionally;
    A drive circuit that performs writing and light emission control on the plurality of pixel circuits in each sub-frame period,
    The pixel circuit includes:
    A plurality of light emitting elements that emit light in different colors;
    A first drive transistor that applies a first power supply voltage to one conduction terminal and outputs a current corresponding to the voltage of the control terminal;
    A second power supply voltage is applied to one conduction terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and a second drive transistor that outputs a current according to the voltage of the control terminal;
    A selection circuit for switching which of the plurality of light emitting elements allows the current output from the first and second drive transistors to flow;
    The first drive transistor operates in a saturation region when the voltage at the control terminal is within a predetermined range, and the second drive transistor is within a first range where the voltage at the control terminal is part of the predetermined range. The display device, which sometimes operates in a saturation region, and operates in a linear region when the voltage of the control terminal is within a second range which is the remainder of the predetermined range.
  2. 　前記第１範囲内の電圧は階調表示で用いられる電圧であり、前記第２範囲内の電圧は階調表示における最大輝度よりも高い輝度に対応した電圧であることを特徴とする、請求項１に記載の表示装置。 The voltage in the first range is a voltage used in gradation display, and the voltage in the second range is a voltage corresponding to a luminance higher than the maximum luminance in gradation display. The display device according to 1.
  3. 　前記第１および第２駆動トランジスタの制御端子は、同じ節点に接続されていることを特徴とする、請求項１に記載の表示装置。 The display device according to claim 1, wherein the control terminals of the first and second drive transistors are connected to the same node.
  4. 　前記画素回路は、前記駆動回路から出力されたデータ電圧を前記第１および第２駆動トランジスタの制御端子に与える入力トランジスタと、前記第１および第２駆動トランジスタの制御端子の電圧を保持する容量素子とをさらに含むことを特徴とする、請求項３に記載の表示装置。 The pixel circuit includes an input transistor that supplies a data voltage output from the drive circuit to control terminals of the first and second drive transistors, and a capacitive element that holds a voltage of the control terminal of the first and second drive transistors. The display device according to claim 3, further comprising:
  5. 　前記容量素子は、前記第１および第２駆動トランジスタの制御端子と前記第１駆動トランジスタの一方の導通端子との間に設けられていることを特徴とする、請求項４に記載の表示装置。 The display device according to claim 4, wherein the capacitive element is provided between a control terminal of the first and second drive transistors and one conduction terminal of the first drive transistor.
  6. 　前記容量素子は、前記第１および第２駆動トランジスタの制御端子と他方の導通端子との間に設けられていることを特徴とする、請求項４に記載の表示装置。 The display device according to claim 4, wherein the capacitive element is provided between a control terminal of the first and second drive transistors and the other conduction terminal.
  7. 　前記容量素子は、前記第１および第２駆動トランジスタの制御端子と制御線との間に設けられていることを特徴とする、請求項４に記載の表示装置。 The display device according to claim 4, wherein the capacitive element is provided between a control terminal and a control line of the first and second drive transistors.
  8. 　前記第１および第２駆動トランジスタの制御端子には異なる電圧が印加可能に構成されていることを特徴とする、請求項１に記載の表示装置。 The display device according to claim 1, wherein different voltages can be applied to control terminals of the first and second drive transistors.
  9. 　前記選択回路は、それぞれが前記第１および第２駆動トランジスタの他方の導通端子と前記複数の発光素子との間に設けられ、発光制御線に接続された制御端子を有する複数の発光制御トランジスタを含むことを特徴とする、請求項１に記載の表示装置。 The selection circuit includes a plurality of light emission control transistors each having a control terminal provided between the other conduction terminal of the first and second drive transistors and the plurality of light emitting elements and connected to a light emission control line. The display device according to claim 1, further comprising:
  10. 　前記表示部は、複数の走査線と複数のデータ線と複数の発光制御線とをさらに含み、
    　前記駆動回路は、各サブフレーム期間において前記複数の走査線を順に選択する走査線駆動回路と、各サブフレーム期間の各ライン期間において映像信号に応じたデータ電圧を前記複数のデータ線に印加するデータ線駆動回路と、各サブフレーム期間において前記複数の発光制御線を駆動する発光制御線駆動回路とを含むことを特徴とする、請求項１に記載の表示装置。     The display unit further includes a plurality of scanning lines, a plurality of data lines, and a plurality of light emission control lines,
    The driving circuit applies a data voltage corresponding to a video signal to the plurality of data lines in each line period of each subframe period, and a scanning line driving circuit that sequentially selects the plurality of scanning lines in each subframe period. The display device according to claim 1, further comprising: a data line driving circuit; and a light emission control line driving circuit that drives the plurality of light emission control lines in each subframe period.
  11. 　２次元状に配置された複数の画素回路と、複数の走査線と、複数のデータ線と、複数の発光制御線とを含み、１フレーム期間に複数のサブフレームを表示する表示装置の駆動方法であって、
    　各サブフレーム期間において前記複数の走査線を順に選択するステップと、
    　各サブフレーム期間の各ライン期間において映像信号に応じたデータ電圧を前記複数のデータ線に印加するステップと、
    　各サブフレーム期間において前記複数の発光制御線を駆動するステップとを備え、
    　前記画素回路は、互いに異なる色に発光する複数の発光素子と、一方の導通端子に第１電源電圧が印加され、制御端子の電圧に応じた電流を出力する第１駆動トランジスタと、一方の導通端子に第２電源電圧が印加され、他方の導通端子が前記第１駆動トランジスタの他方の導通端子に接続され、制御端子の電圧に応じた電流を出力する第２駆動トランジスタと、前記第１および第２駆動トランジスタから出力された電流を前記複数の発光素子のいずれに流すかを切り替える選択回路とを含み、
    　前記第１駆動トランジスタは、制御端子の電圧が所定範囲内にあるときには飽和領域で動作し、前記第２駆動トランジスタは、制御端子の電圧が前記所定範囲の一部である第１範囲内にあるときには飽和領域で動作し、制御端子の電圧が前記所定範囲の残部である第２範囲内にあるときには線形領域で動作することを特徴とする、表示装置の駆動方法。     A display device driving method including a plurality of pixel circuits arranged in a two-dimensional manner, a plurality of scanning lines, a plurality of data lines, and a plurality of light emission control lines, and displaying a plurality of subframes in one frame period Because
    Sequentially selecting the plurality of scan lines in each subframe period;
    Applying a data voltage corresponding to a video signal to each of the plurality of data lines in each line period of each subframe period;
    Driving the plurality of light emission control lines in each subframe period,
    The pixel circuit includes a plurality of light emitting elements that emit light of different colors, a first drive transistor that outputs a current corresponding to a voltage of a control terminal by applying a first power supply voltage to one conduction terminal, and one conduction A second power supply voltage is applied to the terminal, the other conduction terminal is connected to the other conduction terminal of the first drive transistor, and the second drive transistor outputs a current corresponding to the voltage of the control terminal; A selection circuit for switching to which of the plurality of light emitting elements the current output from the second drive transistor flows,
    The first drive transistor operates in a saturation region when the voltage at the control terminal is within a predetermined range, and the second drive transistor is within a first range where the voltage at the control terminal is part of the predetermined range. A method for driving a display device, characterized in that it sometimes operates in a saturation region, and operates in a linear region when a voltage at a control terminal is within a second range that is the remainder of the predetermined range.
PCT/JP2014/068012 2013-07-30 2014-07-07 Display device and method for driving same WO2015016007A1 (en)

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