WO2015012454A1

WO2015012454A1 - Method of improving network performance by controlling virtual link, and network system employing same

Info

Publication number: WO2015012454A1
Application number: PCT/KR2013/011648
Authority: WO
Inventors: 박부식
Original assignee: 전자부품연구원
Priority date: 2013-07-24
Filing date: 2013-12-16
Publication date: 2015-01-29
Also published as: KR101434422B1

Abstract

The present invention relates to a method of improving network performance by controlling a virtual link and a network system employing the same. The purpose of the present invention is to provide a method of improving the performance of an AFDX network for converting and transmitting BAG and Lmax of a virtual link and performing frame reassembly, and an AFDX network system employing the same. The method comprises the steps of: receiving at least one frame from a first end system and a second end system; converting BAG and Lmax of a virtual link on the basis of a conversion table; transmitting fragmented frames; and reassembling the received frames and transmitting the completed frames. According to the present invention, it is possible to reduce the capacity requirement for a switch internal memory by performing optimal fragmentation when transmitting frames. Further, it is possible to lower the price of a memory and switch development costs in developing a switch by reducing a maximum memory size.

Description

Method for Improving Network Performance by Adjusting Virtual Link and Applying Network System

The present invention relates to a method for improving network performance and a network system using the same, and more particularly, to a method for improving performance by frame fragmentation in a network in which a maximum allowable value for end-to-end data transmission delay time is set, and a network system using the same. .

Avionics Full-DupleX Ethernet Switched Network (AFDX) is the core network system specification for the latest avionics system, Integrated Modular Avionics (IMA). Standardized by ARINC 664.

COTS (Cost-Off-The-Shelf) technology is based on the existing Ethernet to secure reliability and economics and meet the deterministic quality-of-service (QoS) requirements of avionics systems. There is a special MAC (Media Access Control) function.

A virtual link is established on a 100 Mb / s Ethernet link, which can be shared and used by multiple applications. Each virtual link is predefined with the maximum available bandwidth to guarantee QoS. The transmission capacity of each virtual link is defined by the minimum transmission interval (BAG) and the maximum transmission length (Lmax).

In the AFDX network, end-system (ES), which is the source or destination of data, is set up with several virtual links. The ES is then connected to the switch. The ES shall transmit frames according to the BAG and Lmax of the established virtual link. The switch monitors whether a frame received from the ES or another switch is transmitting according to a preset appointment, and discards the frame in the case of a violating frame.

Commercial Ethernet is difficult to predict how many nodes will be connected to the switch or how many switches will be connected to form a network, whereas AFDX networks can be configured according to the design because the avionics are pre-determined when designing the aircraft. In order to guarantee the definite QoS, the configuration information of the entire network is determined and reflected in advance.

Inside the Ethernet switch there is a memory for switching, which temporarily holds frames to prevent head of line blocking when frames arriving at multiple input ports attempt to exit to the same output port. However, the size of this memory depends on the length of the frame.

When frames arriving at multiple input ports go out to one output port, a frame having a maximum length Lmax for a particular virtual link simultaneously arrives at the input ports and exits to the same output ports. Therefore, when configuring switching with hardware, it is necessary to keep the Lmax value small because the maximum size of the frame determines the memory size. The smaller the memory size, the lower the production cost.

However, if Lmax is kept small, the header overhead is caused, and the utilization rate of network bandwidth becomes that bad.

FIG. 1 illustrates a frame delay situation in an AFDX network when a conventional method is applied.

The existing ARINC 664 defines virtual link management as follows.

All virtual links have BAG and Lmax values. The VLID (Virtual Link Identifier) is described as a 16-bit value in every frame MAC Destination Address field.

Every switch has pre-stored routing information about which input port the virtual link through its switch enters and to which output port (s).

Based on the routing information, each switch checks whether the input frame exceeds the Lmax length and whether it is transmitted with the bandwidth allowed for the BAG.

The AFDX Switch inspects the incoming traffic through the token bucket algorithm. (Policing) However, according to the ARINC 664 Part 7 Chapter 2.0 Switch Specification specification, a switch can be implemented by selecting one of two types of token bucket algorithms.

One is Byte-based and the other is Frame-based. Or both. In the case of applying a frame-based algorithm, the number of transmissions of the frames is used as a meaningful value for QoS, and thus, an increase in the number of frames cannot be transmitted due to fragmentation.

In addition, in the case of byte-based, a frame may not be transmitted due to excess data generated by adding a header.

In addition, in the conventional AFDX, the virtual link value included in the frame is not changed in the middle or the settings of LmaX and BAG for the same virtual link are not changed.

Referring to FIG. 1, an example of delay generation in a conventional AFDX network includes an edge switch receiving frames VL # 1 and VL # 2 from two end systems ES # 1 and ES # 2, respectively. (Sa) first transmits a relatively longer second virtual link frame (VL # 2 frame), and then, in the core switch S4, the second virtual link frame (VL # 2 frame) and the third virtual link frame (VL #). 3 frames) arrive at the same time. In this case, when the third virtual link VL # 3 is switched first, the delay time of the first virtual link frame VL # 1 frame arriving at the edge switch Sd is further increased.

Thus, when frames of different virtual links arrive at each switch at the same time, an unfair case may occur in which frames of a particular virtual link are excessively delayed.

If the delay time exceeds the maximum delay required by the system, the system configuration is difficult to use.

According to the present invention, the BAG and Lmax of the virtual link are converted and transmitted using a translation table, and then the virtual link is adjusted to perform frame reassembly, so that every frame can meet the required QoS without excessive delay. It is an object of the present invention to provide an improvement method and a system using the same.

According to an aspect of the present invention, a network system includes a transform unit for receiving at least one frame from a first end system and a second end system, and then simultaneously converting BAG and Lmax of the frame based on a conversion table, A first edge switch for transmitting a frame; And a reassembly unit configured to determine validity of the frame received from the first edge switch, and to reassemble the frame if the frame is valid, and to transmit a completed frame to a destination end system. .

According to another aspect of the present invention, a method for improving network performance includes receiving a frame through at least one virtual link; Converting BAG and Lmax of the virtual link based on a conversion table and fragmenting and transmitting the frame based on the conversion table; Receiving the fragmented frame and reassembling the fragmented frame if the received frame is valid.

According to the present invention, it is possible to reduce the requirement of the switch internal memory capacity by performing the optimal fragmentation during frame transmission. Lowering the maximum memory size can reduce memory and switch development costs in switch development.

In addition, Lmax length fragmentation reduces the end-to-end delay time when frames arriving at multiple input ports go out to one output port, and the upper range of network delay can be set lower than before, improving network performance. You can.

In addition, the number of packets that can be transmitted within the same delay range is increased to increase the number of virtual links, thereby improving network performance.

1 illustrates a frame transmission flow in an AFDX network.

2 is a block diagram of a network system according to an embodiment of the present invention.

3 is a block diagram of a conversion unit according to an embodiment of the present invention.

4 illustrates an internal memory of a frame buffer according to an embodiment of the present invention.

5 is a diagram illustrating a frame buffer viewed from another point of view according to an embodiment of the present invention.

6 is a diagram illustrating a conversion table according to an embodiment of the present invention.

7 is a block diagram of a reassembly according to an embodiment of the present invention.

8 illustrates an operation of a reassembly memory in an edge switch performing reassembly according to an embodiment of the present invention.

9 is a view illustrating a situation in which payload reassembly is completed according to an embodiment of the present invention.

10 illustrates reassembly of a frame according to an embodiment of the present invention.

FIG. 11 illustrates reassembly of a frame in a second edge switch according to an exemplary embodiment of the present invention. FIG.

12 illustrates reassembly of frames in a third end system according to an embodiment of the present invention.

13 illustrates a general Ethernet frame structure.

14 illustrates an AFDX Ethernet frame structure.

15 is a diagram illustrating frame transmission when BAG and Lmax are changed according to an embodiment of the present invention.

16 is a flowchart illustrating a method for improving network performance according to an embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the embodiments are to make the disclosure of the present invention complete, and those skilled in the art to which the present invention pertains. It is provided to fully inform the scope of the invention, and the invention is defined by the scope of the claims. Meanwhile, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to a component, step, operation and / or device that is present in one or more other components, steps, operations and / or elements. Or does not exclude additions.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a block diagram of a network system according to an embodiment of the present invention. As shown in FIG. 2, the network system according to the present invention includes one of the first to

third end systems

100, 200, and 600, the first edge switch 300, the second edge switch 500, and an edge switch. The above core switch 400 is included.

The network system to which the present invention is applied is characterized in that the maximum allowable value for the end-to-end data transmission delay is set. As a representative example, AFionics Full- DupleX Ethernet Switched Network).

For convenience of description, the following describes the present invention with an AFDX network system as an example, but the scope of the present invention is not limited to AFDX, that is, the network system inside the aircraft, but for the end-to-end data transmission delay time. It will be apparent to those skilled in the art that the maximum allowable value may be reached if the network is configured.

Referring to FIG. 2, the first edge switch 300 receives at least one frame from the first end system 100 and the second end system 200, and then selects a BAG of each virtual link based on a translation table. The converter 310 converts Lmax and transmits a fragmented frame.

The second edge switch 500 includes a reassembly unit 510 which determines the validity of the frame received from the first edge switch 300 and reassembles the frame if the frame is valid, and ends the completed frame at the destination end. Transfer it to the system.

Meanwhile, in the present specification, the first edge switch 300 and the second edge switch 500, the first end system 100, the second end system 200, and the third end system 600 will be described. This is for the convenience of explanation and for the purpose of better understanding, and in a network system according to the present invention, two or more switches (including edge switches and core switches) may exist between two end systems, and two or more multiple end systems may exist. Of course.

In the present invention, the first edge switch 300 connected to the transmitting end system (100, 200) includes a conversion unit 310, and obtains the converted Lmax 'and BAG' satisfying Equation 1 below Therefore, frame fragmentation is performed and transmitted to the next switch in the network.

Equation 1

Lmax: Existing setting (Lmax of the virtual link predefined in the first-end system)

Lmax ': New setting (Lmax of the virtual link newly defined on the first edge switch)

BAG: Existing configuration (BAG of virtual link previously defined in the first-end system)

BAG ': New setting (BAG of the second virtual link newly defined on the first edge switch)

Here, Lmax means Ethernet payload length excluding MAC Destination Address, MAC Source Address, EtherType, Sequence number and FCS.

Lmax, BAG, Lmax ', and BAG' are only valid integers. At this time, when BAG 'is already determined and a new Lmax' is determined accordingly, Lmax 'is calculated by Equation 1. At this time, when Lmax 'is already determined and a new BAG' is determined accordingly, BAG 'is obtained by Equation 1. At this time, when BAG 'is not an integer, the largest integer smaller than that number is the maximum valid number.

Determination of Lmax 'in the converter 310 is preferably performed in consideration of the end-to-end delay time required in the network and the maximum buffer capacity in the switch.

In other words, Lmax 'is determined to be smaller than the maximum buffer capacity of each switch in the network including the end system, but the most appropriate value is determined through iterative attempts to find Lmax' which is capable of network operation that can satisfy the allowable inter-delay. do.

When Lmax 'is determined, BAG' is determined according to Equation 1 described above, and the virtual link parameters of the end system are adjusted according to Lmax 'and BAG' to fragment the frame from the end system according to Lmax 'and transmit the fragmented Lmax' to BAG. do.

Meanwhile, according to the AFDX network standard (ARINC664), the unit of BAG is ms. However, some developers can use more precise units.

-Converter-

3 is a block diagram of the conversion unit 310 included in the first edge switch 300 according to an embodiment of the present invention. The conversion unit 310 converts the BAG and Lmax of each virtual link based on the conversion table.

More specifically, the conversion unit 310 creates a conversion table using Equation 1 and performs setting conversion of the virtual link.

The converter 310 includes a frame buffer 312, a scheduler 314, a frame transmitter 316, and a BAG timer 318.

In detail, the frame buffer 312 stores a frame remaining without being transmitted. That is, the frame buffer 312 stores the remaining frames that are not split and transmitted for fragmentation.

The scheduler 314 transmits the first fragment of the frame payload based on the conversion table, stores the remaining portion of the frame in the frame buffer 312, and controls to sequentially transmit subsequent fragments in accordance with the converted BAG.

The frame transmitter 316 transmits a fragmented frame corresponding to the conversion table in response to the control signal from the scheduler 314.

In addition, the scheduler 314 controls to sequentially transmit subsequent fragments corresponding to the conversion table at the time when the BAG timer 318 expires.

Specifically, the framer (not shown) configures the same header to the newly split Ethernet payload to generate a frame and attaches a new sequence number. Since the number of frames increases due to fragmentation, a new sequence number must be managed.

For each virtual link, a sequence number counter is used as an 8-bit counter. The sequence counting speed also increases in proportion to the ratio of the BAG size.

4 conceptually illustrates an internal structure of the frame buffer unit 312. In Lmax, an area for storing the maximum frame length including the header and the like is prepared for each virtual link. When a frame arrives from the ES, it is stored in a buffer.

Subsequently, the fragmented frame corresponding to the first part is transmitted with a new header, a sequence number, and an FCS.

As shown in FIG. 4, it is possible to implement a structure in which the already sent part is stored in the memory, and the data of the already sent fragment can be implemented in a structure not stored in the memory.

If it is the latter, it will be implemented in FIFO form, and only the fragment data which is not sent yet is stored in internal memory. All data stored in the frame buffer 122 must be transmitted until the next frame arrives from the ES. Therefore, the frame

The size of the buffer unit 312 is sufficient to store one frame of the maximum size for each virtual link.

FIG. 4 is a diagram illustrating a case where n virtual links are shown. In FIG. 4, Lmax is 1/2 times for the first virtual link, 1/4 times for the second virtual link, and 3 times for the third virtual link. The case where it became 1/8 times was shown. Since the Lmax values after conversion in the first virtual link, the second virtual link, and the third virtual link are different from each other, the lengths of the first transmitted frames are different.

Of course, this is only when a frame with a new Lmax value longer than Lmax 'arrives.

If a frame shorter than Lmax 'arrives, only the header transformation will be processed and delivered without fragmentation, that is, without buffering.

Specifically, in the third virtual link, instead of having a shorter Lmax length, frames are transmitted more frequently than the second virtual link. In FIG. 4, the configuration of the BAG for each virtual link is not shown. This may be considered to be the case where the BAGs of the second virtual link and the third virtual link are the same.

If the BAG of the third virtual link is 1/8 times larger than the BAG of the second virtual link, even if Lmax is set to 1/2 times, frames are not sent more often.

5 is a diagram illustrating a frame buffer viewed from another viewpoint according to an embodiment of the present invention. As shown in Fig. 5, the second fragment frame of the second virtual link is transmitted when the reference time point expires of the converted first BAG 'of the second virtual link.

In this case, the third virtual link has already finished transmitting the second fragment frame, and transmits the third fragment frame.

In FIG. 5, the left and right arrows indicate a frame, and the left side is a frame input from the first edge switch 110. One frame is received, which is fragmented and split several times, like the right arrow.

-Information about the virtual link-

The information on the virtual link in the conversion table is composed of information before conversion (Config # 1) and information after conversion (Config # 2). When the frame arrives at the input port of the first edge switch 300, first, filtering and Policing through Integrity Check are performed as in the conventional AFDX MAC. Integrity Check is the process of checking the validity of a frame. Validation of the frame includes checking constant values in the header, checking for FCS errors, checking whether the frame length is shorter than the minimum length or longer than the maximum length Lmax.

Policing checks to see if the frame is valid and arrives at the virtual link settings before conversion. If entered before the BAG interval, the frame is ignored. According to the ARINC 664 Part 7 Specification 4.0 Switch Specification chapter, Policing on a switch is based on the token bucket algorithm.

If conversion is required among the frames passed in this way, it enters the conversion unit 310. In the case of a virtual link having no translation information in the translation table, it is directly transmitted to the redundant module (not shown) from Policing without passing through the conversion unit 310 to be transmitted to another switch.

-Conversion table-

6 is a diagram illustrating a conversion table according to an embodiment of the present invention. As shown in FIG. 6, the first edge switch 300 has a conversion table. When n virtual links need translation, there are n virtual link translation information. The values located in Config # 2 (after conversion) satisfy the condition of Equation 1.

For example, a virtual link of Config # 1 (before conversion) with a BAG of 8 ms and an Lmax of 1499 bytes is converted to Config # 2, which translates into a Bmax of 750 bytes at 4 ms. Dividing 1499 bytes by the BAG variation has a value of 749.5, with a minimum integer greater than this value being 750.

When the virtual link ID is 3, the BAG is reduced to 1 and Lmax 'is 187.375 bytes according to Equation 1 when the transmission frequency is increased. So with the new Config # 2, Lmax 'is determined to be 188 bytes, the smallest integer greater than 187.375.

There are three virtual links, each fragmented differently. When fragmented, the values of new Lmax and BAG are determined using Equation 1.

7 is a configuration diagram of the reassembly unit 510 of the second edge switch 500 according to an embodiment of the present invention. As shown in FIG. 7, the second edge switch 500 is a switch directly in front of the third end system 600 which is a destination of the transmission frame. The second edge switch 500 determines whether the received frame is valid using Equation (1). The reassembly unit 510 includes a reassembly memory 512, a reassembly control unit 514, a frame transmission unit 516, and a framer 518.

More specifically, the reassembly memory 512 stores only the payload of the frame when the received frame is valid.

The reassembly control unit 514 stores the frame sequence number and checks whether the frame sequence number is an error.

The frame transmitter 516 checks whether the stored frame is a complete payload and transfers the completed payload to the framer 518.

The framer 518 completes and transmits the frame by attaching a pre-conversion header, a sequence number, and an FCS corresponding to Config # 1 of the conversion table to the payload received from the frame transmitter 516.

8 is a conceptual diagram illustrating a mode in which a conversion frame is accumulated in the reassembly memory 512 in the second edge switch 500 performing reassembly according to an embodiment of the present invention.

The received frame accumulates only the payload in the reassembly memory 512 as shown in FIG. 8.

-Payload Reassembly Completed-

9 is a view illustrating a situation in which payload reassembly is completed according to an embodiment of the present invention. The header, sequence number, and FCS are added to the payload of the completed frame to make it into an Ethernet frame and delivered to the end switch. At this time, the sequence number is restored and assigned as in the fragmentation process.

-When reassembling the frame-

10 is a view illustrating a frame reassembly process according to an embodiment of the present invention. The second edge switch 500 checks the validity of the received frame by performing Integrity and Policing checks according to the information (Config # 2) after the conversion. If the received frame is a valid frame, only the payload is stored in the reassembly memory 512. Then, the reassembly control unit 514 stores the sequence number of the received frame in the SEQ memory (not shown) and checks whether there is no sequence number error in every received frame.

When all fragmented frames arrive without error, the frame payer 516 reads from the reassembled memory 512 and transfers them to the framer 518. The framer 518 transmits an Ethernet frame by attaching a header, a sequence number, and an FCS that match the pre-conversion information (Config # 1) to the received payload.

The Frame Check Sequence (FCS) checks the occurrence of an error in the bit string of the frames following the SFD.

When the second edge switch 500 reassembles the frame and delivers the frame to the third end system 600, the second edge switch 500 may exchange the frame with the same virtual link setup as the first and

second end systems

100 and 200, which are transmission end systems. have.

If the third end system 600 is set to Config # 2 and there is no edge switch to be reassembled, the third end system 600 receives the converted frame in the same manner as the receiving process of the existing AFDX frame. .

When reassembling the frame in the third-end system 600

In another embodiment, the reassembly of the fragmented frame may be performed in the third end system 600 which is the final destination of the frame instead of the second edge switch 500.

To this end, the third end system 600 includes a reassembly unit 610 that performs the same function as the reassembly unit 510.

FIG. 11 is a view illustrating reassembly of a frame at a second edge switch 500 according to an embodiment of the present invention, and FIG. 12 is a view illustrating a third end system 600 according to another embodiment of the present invention. A diagram illustrating reassembly of a frame.

The first edge switch 300 of FIG. 11 receives the hatched frame, fragments it into two pieces, and transmits the same to the core switch 400. The core switch 400 delivers the fragmented hatched frame to the second edge switch 500 according to the existing AFDX network standard. The second edge switch 500 reassembles the hatched fragmented frame and delivers it to the end system (not shown).

In the case of a thin border frame, it is delivered without fragmentation. The thick frame is input to the input port of the core switch 410 and then divided into two parts and delivered to the second edge switch 500, and then reassembled and delivered to the third end system 600.

In the above two embodiments, the method of receiving at the last stage is different. In the embodiment illustrated in FIG. 11, the second edge switch 500 performs frame reassembly and delivers the completed frame to the third end system 600.

In the embodiment illustrated in FIG. 12, the second edge switch 500 transmits as received, and the third end system 600 performs frame reassembly.

Therefore, the settings in the second edge switch 500 and the third end system 600 are different according to the two cases.

In FIG. 11, the third end system 600 has the same BAG and Lmax as the first end system 100 and the second end system 200. Each end system does not know the fragmentation process.

In FIG. 12, new virtual link setting values set in the first edge switch 300, the core switch S1 400, the core switch S2 410, and the second edge switch 500 in the third end system 600. The same value is set. No special reassembly and transfer to the original configuration is necessary. Thus, FIG. 12 is simpler in network configuration than in FIG. However, the BAG and Lmax settings do not match between end switches or end systems, which may cause confusion during maintenance.

For example, in the case of a virtual link transmitting a thick border frame, the virtual link configuration of ES # 3 and the virtual frame corresponding to the same frame of ES # 8 are different. Therefore, the virtual link configuration may be different even though the frame is substantially the same.

FIG. 13 illustrates a general Ethernet frame structure and FIG. 14 illustrates an AFDX Ethernet frame structure. Unlike general frame, AFDX Ethernet frame has 1 byte space where sequence number is stored before FCS (Frame Check Sequence).

Because of the sequence number field, payload can be sent one byte less than a regular Ethernet frame. In normal frames, up to 1500 bytes can be transmitted, while AFDX can deliver up to 1499 bytes in one payload.

And in Ethernet, there are frames up to 9000 bytes called jumbo frames. However, the frame structure is not changed, but the Ethernet payload is increased, so that the contents of the present patent can be easily applied to jumbo frames.

There is a 96-bit empty space called interframe spacing (IFS) between frames. This is made in consideration of the technical delay time required for transmitting / receiving a frame.

15 is a diagram illustrating frame transmission when BAG and Lmax are changed according to an embodiment of the present invention. As shown in Fig. 15, the frame transmission is shown when the BAG is twice as fast (value is 1/2 times) and Lmax is shortened by 1/2 times.

In fact, fragmentation increases the total amount of traffic used. Added headers, FCS IFS, etc. The engineer who decides to set up the AFDX will need to determine each value in the translation table, taking into account the increased amount of traffic when creating the translation table.

At the end of the frame payload is a sequence number of 1 byte. It is a number managed independently for each virtual link. It has a value from 0 to 255. The initial value starts with 0. And when it reaches 255, it turns to 1 and cycles. When the sender wants to initialize the sequence number, 0 is transmitted. When the receiving end receives the sequence number of 0, the receiving end judges the sequence number initialization on the transmitting side and initializes the sequence number.

In the fragmentation and reassembly process, the number of frames is changed, resulting in a difference in the operation of the sequence number. Frames are sent more frequently on the virtual link in Config # 2 than the virtual link set in Config # 1.

In addition, if Lmax is twice as long as Lmax 'but the payload carried in actual transmission is less than half of Lmax, fragmentation does not occur. In this case, the sequence number is the same before or after the conversion.

However, if a case in which a payload larger than half the size of Lmax is transmitted at least once occurs, the sequence number is changed from that time.

When the first edge switch 300 receives a frame having a sequence number of 0, the fragmented frame sequence number also starts again from zero. Even during the reassembly process, if the first fragmented frame sequence number is zero, the sequence number of the reassembled frame is also initialized to zero.

In case of IP (Internet Protocol), ID (Identification) field and More field are used for fragmentation. Packets with the same ID value indicate fragmentation, and whether or not the last fragmented packet is confirmed by the value of the More field.

However, AFDX frames do not provide a separate field for fragmentation like IP.

AFDX operates deterministicly according to BAG and Lmax according to network profiling to ensure deterministic QoS.

Frame reassembly completion operation logic

BAG_a: BAG before conversion

BAG_b: BAG after conversion

Lmax_a: Lmax before conversion

Lmax_b: Lmax after conversion

T1: time when the first fragmented frame arrived

Tc: The time when the currently received fragmented frame arrived

N: Number of fragmented frames received so far

DIFF_BAG: The minimum integer value greater than or equal to BAG_a / BAG_b, which is greater than 1.

Whenever a frame arrives,

First, it is checked whether the BAG_a time has elapsed. If so, the fragmented frame can no longer arrive.

This is because the frame arrived after the BAG_a time has elapsed is a new frame.

If Tc-T1 is greater than or equal to BAG_a, the second edge switch 500 considers that the number of previously received and reassembled frames is less than DIFF_BAG but the reassembled data is complete. In this case, the second edge switch 500 transfers the frame to the framer.

The sequence number N is initialized to zero. In addition, the currently received fragmented frame becomes the first fragmented frame, and stores the fragmented frame in the front part of the reassembly memory.

Next, if the currently received sequence number is 0, it is initialized together, otherwise it is incremented by 1. If it is 255, change it to 1.

If a subsequent frame arrives without the BAG_a time yet, an additional fragmented frame may have arrived.

Therefore, the reassembly process is performed according to the following conditions 1) to 4).

1) If N + 1 is equal to DIFF_BAG, the second edge switch 500 confirms that the last fragmented frame has arrived. That is, the frame that was previously received and reassembled is completed. The second edge switch 500 transfers the completed frame to the framer and initializes N to zero. If N is 0, the currently received fragmented frame becomes the first fragmented frame.

2) The second edge switch 500 stores the received frame in the front part of the reassembly memory. If the currently received sequence number is 0, it is initialized together. Otherwise, it is increased. If the sequence number is continuously increased to 255, change it to 1.

3) When N + 1 is less than DIFF_BAG THEN, the second edge switch 500 may not know whether the currently received fragmented frame is the last. Accordingly, the second edge switch 500 attaches and stores the frame to the reassembly memory.

4) If the above 1) to 3) does not correspond, the second edge switch 500 is determined to be an error situation.

15 is a flowchart illustrating a method for improving AFDX network performance according to an embodiment of the present invention.

As shown in FIG. 15, first, the first edge switch 300 receives a frame from at least one virtual link from a transmission end system (S310).

Next, the received frame is fragmented based on the conversion table and transmitted (S320). In detail, the conversion unit 310 converts the BAG and Lmax of each virtual link based on the conversion table. In this case, the conversion unit 310 creates a conversion table and performs virtual link conversion using Equation 1.

More specifically, the scheduler 314 in the converter 310 transmits the first fragment according to the converted Lmax in the frame payload based on the conversion table, stores the remaining part of the frame in the frame buffer 312, and then converts It transmits sequentially in Lmax unit converted to BAG.

The frame transmitter 316 transmits the fragmented frame under the control of the scheduler 314.

After receiving the fragmented frame via the virtual link, the second edge switch 500 confirms the validity of the received frame and reassembles the frame if the received frame is valid (S330).

Specifically, the second edge switch 500 determines the validity of the received frame using Equation 1. When the second edge switch 500 determines that the received frame is valid, only the payload of the received frame is stored, the frame sequence number is stored, and the frame sequence number is checked for errors.

Then, it is checked whether the stored frame is a completed payload and checks whether the stored frame is reassembled.

Specifically, if the difference between the arrival time of the first fragmented frame and the currently received fragmented frame arrival time is greater than or equal to the BAG before conversion, the second edge switch 500 confirms that the reassembly is completed.

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and changes without departing from the essential characteristics of the present invention. Therefore, the embodiments represented in the present invention are not intended to limit the technical spirit of the present invention, but to describe, and the scope of the present invention is not limited by the embodiments. The scope of protection of the present invention should be interpreted by the claims below, and all technical ideas that are equivalent to or equivalent to the scope of the present invention should be construed as being included in the scope of the present invention.

Claims

In a network system having a maximum allowable value for the end-to-end data transmission delay,

After receiving at least one frame from each of the first end system and the second end system through each virtual link, Bandwidth Allocation Gap (BAG) and maximum transmission length ( A first edge switch including a conversion unit for converting Lmax) and fragmenting and transmitting a frame according to the converted BAG and Lmax; And

A second edge switch for determining a validity of a frame received from the first edge switch, and reassembling the frame if the frame is valid, and transmitting the completed frame to a destination end system.

Network system comprising a.
The method of claim 1, wherein the conversion unit

Creating the conversion table and performing the configuration conversion of the virtual link using the following equation

Network system.

Lmax: Existing setting (Lmax of the virtual link predefined in the first-end system)

Lmax ': New setting (Lmax of the virtual link newly defined on the first edge switch)

BAG: Existing configuration (BAG of virtual link previously defined in the first-end system)

BAG ': New setting (BAG of the second virtual link newly defined on the first edge switch)

Here, Lmax means Ethernet payload length excluding MAC Destination Address, MAC Source Address, EtherType, Sequence number and FCS.
The method of claim 1, wherein the conversion unit

A frame buffer for storing frames remaining without being transmitted;

A scheduler configured to transmit a first fragment of the frame payload based on the conversion table, store the remaining portion of the frame in the frame buffer, and then sequentially transmit subsequent fragments according to the converted BAG; And

And a frame transmitter for transmitting a fragmented frame corresponding to the conversion table in response to a control signal from the scheduler.

Network system.
The method of claim 3, further comprising a BAG timer,

The scheduler controls to sequentially transmit subsequent fragments corresponding to the conversion table when the BAG timer expires

Network system.
The method of claim 1, wherein the second edge switch determines whether the received frame is valid using the converted BAG and Lmax.

Network system.
The method of claim 1, wherein the reassembly portion

A reassembly memory for storing only payload of the frame when the received frame is valid;

A reassembly control unit for storing the frame sequence number and checking whether the frame sequence number is an error;

A frame transmitter which checks whether a stored frame becomes a complete payload and transmits the payload; And

And a framer for completing and transmitting a frame by attaching a header, a sequence number, and an FCS corresponding to a pre-conversion setting of the virtual link to the payload received from the frame transmitter.

Network system.
The method of claim 1, wherein the second edge switch

If the difference between the first fragmented frame arrival time and the currently received fragmented frame arrival time is greater than or equal to the BAG before the conversion, confirming that the frame reassembly is completed.

Network system.
In a network system having a maximum allowable value for the end-to-end data transmission delay,

After receiving at least one frame from each of the first end system and the second end system through each virtual link, Bandwidth Allocation Gap (BAG) and maximum transmission length (Lmax), which is the minimum transmittable interval of each virtual link, based on the conversion table. Edge switch for converting the fragment into frames based on the converted BAG and Lmax; And

And a third end system including a reassembly unit for determining validity of a frame received from the edge switch and reassembling the frame if the frame is valid.

Network system.
The method of claim 8, wherein the third end system determines whether the received frame is valid using the converted BAG and Lmax.

Network system.
The method of claim 8, wherein the reassembly portion

A reassembly memory for storing only payload of the frame when the received frame is valid;

A reassembly control unit for storing the sequence number of the frame and checking whether the sequence number is an error;

A frame transmitter which checks whether a stored frame becomes a complete payload and transmits the payload; And

And a framer for completing and transmitting a frame by attaching a header, a sequence number, and an FCS corresponding to a pre-conversion setting of the virtual link to the payload received from the frame transmitter.

Network system.
In the performance improvement method of a network system in which the maximum allowable value for the end-to-end data transmission delay time is set,

Receiving a frame over at least one virtual link;

Converting a bandwidth Allocation Gap (BAG) and a maximum transmission length (Lmax), which are minimum transmittable intervals of the virtual link, based on a conversion table, and fragmenting and transmitting the frame based on the conversion table; And

Receiving a fragmented frame and reassembling the fragmented frame if the received frame is valid

Network performance improvement method comprising a.
The method of claim 11, wherein the transmitting step

Creating the conversion table and converting the settings of the virtual link using the following equation

To improve network performance.

Lmax: Existing setting (Lmax of the virtual link predefined in the first-end system)

Lmax ': New setting (Lmax of the virtual link newly defined on the first edge switch)

BAG: Existing configuration (BAG of virtual link previously defined in the first-end system)

BAG ': New setting (BAG of the second virtual link newly defined on the first edge switch)

Here, Lmax means Ethernet payload length excluding MAC Destination Address, MAC Source Address, EtherType, Sequence number and FCS.
The method of claim 11, wherein the transmitting step

Storing a frame remaining without being transmitted;

Transmitting a first fragment of the frame payload based on the conversion table and storing the remaining portion of the frame in a frame buffer; And

Transmitting a fragmented frame corresponding to the conversion table

Containing more

To improve network performance.
The method of claim 11, wherein the reassembling comprises determining whether a received frame is valid using BAG and Lmax.

To improve network performance.
The method of claim 11, wherein the reassembling is

Storing only the payload of the frame if the received frame is valid;

Storing a sequence number of the frame;

Checking whether a frame sequence number error occurs;

Checking whether the stored frame becomes a complete payload; And

Further comprising checking whether the stored frame reassembly is complete

To improve network performance.
The method of claim 15, wherein checking whether the reassembly is completed

If the difference between the first fragmentation frame arrival time and the currently received fragmentation frame arrival time is greater than or equal to the BAG before conversion, the reassembly is confirmed.

To improve network performance.