KR101434422B1 - Method for improving network by modulating virtual link and the system thereof - Google Patents

Abstract

The present invention relates to a method to improve network performance by controlling a virtual link and a network system applying the same. The purpose of the present invention is to provide a method to improve AFDX network performance which converts and transmits BAG and Lmax of a virtual link, and performs frame reassembly; and an AFDX network system applying the same. The method of the present invention receives at least one frame from a first end system and a second end system, converts BAG and Lmax of a virtual link based on a conversion table, transmits fragmented frames, and reassembles the received frames and transmits the completed frames. According to the present invention, the switch memory requirements can be reduced by performing optimized fragmentation when transmitting frames. The costs of the memory in developing the switch and the switch development costs can be reduced by decreasing the maximum memory size. Also, the network performance can be improved by setting up an upper range of network delay lower than the existing technology since an end-to-end delay time decreases when frames arrived in a plurality of input ports outputs through one output port through the fragmentation of the length Lmax. Furthermore, the network performance can be improved by increasing the number of virtual links since the amount of packets can be transmitted with the same delay range.

Description

TECHNICAL FIELD The present invention relates to a method for improving network performance by adjusting a virtual link and a network system using the same,

The present invention relates to a network performance improvement method and a network system to which the present invention is applied. More specifically, the present invention relates to a method for improving performance by frame fragmentation in a network in which a maximum allowable value for a data transmission delay time between terminals is set, and a network system using the method .

AFDX (Avionics Full-DupleX Ethernet Switched Network) is the core network system standard of IMA (Integrated Modular Avionics), the latest avionics system. It is standardized by ARINC 664.

As a technology of cost-off-the-shelf (COTS) concept, it is based on existing Ethernet to secure reliability and economy, and to satisfy deterministic quality-of-service (QoS) requirements in avionics systems. There is a special MAC (Media Access Control) function.

A virtual link is established on a 100 Mb / s Ethernet link, which can be shared by multiple applications, and each virtual link has a predefined maximum available bandwidth to guarantee QoS. The transmission capacity of each virtual link is defined by BAG (Bandwidth Allocation Gap) and maximum transmission length (Lmax).

In the AFDX network, a plurality of virtual links are set in an end system (ES) as a source or a destination of data. And the ES is connected to the switch. The ES shall transmit the frame according to the BAG and Lmax of the set virtual link. Then, the switch monitors whether the frame received from the ES or another switch is transmitting according to a preset appointment, and discards the frame in case of a violating frame.

In commercial Ethernet, it is difficult to predict how many nodes are connected to the switch and how many switches are connected to form the network. In comparison with AFDX network, avionics are predefined in the aircraft design. And determines and reflects the setting information of the entire network in order to ensure a definite QoS.

Inside the Ethernet switch there is a memory for switching which keeps the frames for a while to prevent head of line blocking when frames arriving at different input ports are going to the same output port. However, the size of this memory depends on the length of the frame.

When frames arriving at a plurality of input ports go out to one output port, a frame having a maximum length Lmax for a specific virtual link simultaneously arrives at the input ports and tries to go to the same output ports. Therefore, it is necessary to keep the Lmax value small because the maximum size of the frame determines the memory size when the switching is configured by the hardware. The smaller the memory size, the lower the production cost.

 However, when the Lmax is kept small, the header overhead is generated, and the utilization rate of the network bandwidth becomes worse.

1 is a diagram for explaining a frame delay situation in an AFDX network when a conventional scheme is applied.

The existing ARINC 664 defines the virtual link management method as follows.

All virtual links have BAG and Lmax values. The VLID (Virtual Link Identifier) is described as a 16-bit value in all frame MAC Destination address fields.

Every switch has pre-stored routing information about which input port the virtual link through its switch will go to and which output port (s) it is going to.

Each switch checks whether the input frame exceeds the Lmax length based on the routing information and checks whether it is transmitted with the allowed bandwidth according to the BAG.

The AFDX Switch examines the incoming traffic through the Token bucket algorithm. (Policing) By the way, according to ARINC 664 Part 7 Chapter 2.0 Switch Specification specification switch can choose one of two way token bucket algorithm.

One is byte-based and the other is frame-based. Or both. In the case of applying a frame-based algorithm, the number of frames transmitted is used as a meaningful value in QoS, so that it is sometimes impossible to transmit an extended frame due to fragmentation.

In addition, in the case of byte-based, frames may not be transmitted due to excess data generated by adding a header.

In addition, in the conventional AFDX, the virtual link value included in the frame is not changed on the way, or the setting of Lmax and BAG for the same virtual link is not changed.

Referring to FIG. 1, a case of delay generation in the conventional AFDX network will be described. An edge switch receives frames (VL # 1 and VL # 2 frames) from two end systems ES # 1 and ES # The second virtual link frame (VL # 2 frame) and the third virtual link frame (VL # 2 frame) are transmitted from the core switch (S4) 3 frames) arrive at the same time. At this time, if the third virtual link VL # 3 is first switched, the delay time of the first virtual link frame (VL # 1 frame) arriving at the edge switch Sd is further increased.

Therefore, when a frame of a different virtual link arrives at each switch at the same time, an unfair case may occur in which a frame of a specific virtual link is excessively delayed.

If this delay time exceeds the maximum delay time required by the system, there is a problem that the system configuration is difficult to use.

The present invention adjusts the setting of the virtual link so that the BAG and Lmax of the virtual link are converted and transmitted using the conversion table and then the frame reassembly is performed so that the network performance And a system to which the present invention is applied.

A network system according to an aspect of the present invention includes a converting unit for receiving at least one frame from a first end system and a second end system and simultaneously converting BAG and Lmax of the frame based on a conversion table, A first edge switch for transmitting a frame; And a reassembly unit for determining the validity of the frame received from the first edge switch and reassembling the frame if the frame is valid, and a second edge switch for transmitting the completed frame to the destination end system .

According to another aspect of the present invention, there is provided a method for improving network performance, comprising: receiving a frame through at least one virtual link; Converting the BAG and Lmax of the virtual link based on the conversion table, and fragmenting and transmitting the frame based thereon; And receiving the fragmented frame and reassembling the fragmented frame if the received frame is valid.

According to the present invention, it is possible to reduce the necessity of the capacity of the internal memory of the switch by performing optimal fragmentation at the time of frame transmission. By lowering the maximum memory size, it is possible to reduce the cost of memory development and switch development costs.

In addition, when the frames arriving at a plurality of input ports are output to one output port through the fragmentation of Lmax length, the end-to-end delay time is reduced, and the upper range of the network delay can be set lower than before. .

In addition, since the number of packets that can be transmitted within the same delay range increases, the number of virtual links can be increased, thereby improving network performance.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a frame transmission flow in an AFDX network.
2 is a configuration diagram of a network system according to an embodiment of the present invention;
3 is a configuration diagram of a conversion unit according to an embodiment of the present invention;
4 illustrates an internal memory of a frame buffer according to an embodiment of the present invention.
5 is a view of a frame buffer viewed from another perspective according to an embodiment of the present invention.
6 illustrates a conversion table according to an embodiment of the present invention.
7 is a configuration diagram of a reassembly unit according to an embodiment of the present invention;
8 illustrates operation of a reassembly memory in an edge switch performing reassembly according to an embodiment of the present invention.
9 is a view showing a state in which payload reassembly according to an embodiment of the present invention is completed.
10 illustrates reassembly of a frame according to an embodiment of the present invention.
11 illustrates reassembling a frame in a second edge switch according to an embodiment of the present invention.
Figure 12 illustrates reassembling a frame in a third end system according to an embodiment of the present invention;
13 is a diagram illustrating a general Ethernet frame structure;
14 shows an AFDX Ethernet frame structure;
15 is a diagram illustrating frame transmission when BAG and Lmax are changed according to an embodiment of the present invention;
16 is a flowchart of a network performance improvement method according to an embodiment of the present invention;

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is defined by the scope of the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms " comprises, " and / or "comprising" refer to the presence or absence of one or more other components, steps, operations, and / Or additions.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of a network system according to an embodiment of the present invention. 2, a network system according to the present invention includes first to third end systems 100, 200, and 600, a first edge switch 300, a second edge switch 500, Or more of the core switch 400.

The network system to which the present invention is applied is characterized in that the maximum allowable value for the data transmission delay time between ends is set. For example, the network system standard AFDX (Avionics Full- DupleX Ethernet Switched Network).

The AFDX network system will be described below with reference to the present invention. However, the scope of the present invention is not limited to the AFDX, that is, the network system inside the aircraft, It will be apparent to those skilled in the art that the maximum allowable value may be set in a network.

Referring to FIG. 2, the first edge switch 300 receives at least one frame from the first end system 100 and the second end system 200, and then, based on the conversion table, And a conversion unit 310 for converting Lmax, and transmits the fragmented frame.

The second edge switch 500 includes a reassembler 510 that determines the validity of the frame received from the first edge switch 300 and reassembles the frame if the frame is valid, System.

While the first edge switch 300 and the second edge switch 500, the first end system 100, the second end system 200, and the third end system 600 are mainly described herein, In the network system according to the present invention, there are two or more switches (including an edge switch and a core switch) between two end systems and two or more end systems exist. Of course.

In the present invention, the first edge switch 300 connected to the transmission side end systems 100 and 200 includes a conversion unit 310 and obtains the converted Lmax 'and BAG' satisfying the following equation (1) It performs frame fragmentation and sends it to the next switch in the network.

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Lmax ': the new setting (Lmax of the newly defined virtual link in the first edge switch)

BAG: The existing configuration (BAG of the virtual link already defined in the first end system)

BAG ': a new setting (BAG of the second virtual link newly defined in the first edge switch)

Here, Lmax denotes an Ethernet payload length excluding a MAC Destination Address, a MAC Source Address, an EtherType, a Sequence number, and an FCS.

Only integers are valid for Lmax, BAG, Lmax ', and BAG'. At this time, when BAG 'has already been determined and a new Lmax' corresponding thereto is determined, Lmax 'is obtained by Equation (1). At this time, when Lmax 'has already been determined and a new BAG' corresponding thereto is determined, BAG 'is obtained by the following equation (1). At this time, when BAG 'is not an integer, the maximum integer smaller than the number is the maximum effective number.

The determination of Lmax 'in the conversion unit 310 is preferably performed in consideration of an end-to-end delay time required in the network and a maximum buffer capacity in the switch.

That is, Lmax 'is determined to be smaller than the maximum buffer capacity of each switch in the network including the end system, but Lmax', which is capable of network operation capable of meeting the allowable inter-species delay time, do.

When Lmax 'is determined, BAG' is determined according to Equation (1) described above, and the end link system adjusts the virtual link parameters of the end system according to the Lmax 'and BAG' to fragment the frame from the end system according to the BAG do.

On the other hand, according to the AFDX network standard (ARINC664), the unit of BAG is ms. However, developers can use more precise units.

- conversion part -

3 is a configuration diagram of the conversion unit 310 included in the first edge switch 300 according to an embodiment of the present invention. The conversion unit 310 converts the BAG and Lmax of each virtual link based on the conversion table.

More specifically, the conversion unit 310 creates a conversion table using Equation (1) and performs setting conversion of the virtual link.

The converting unit 310 includes a frame buffer 312, a scheduler 314, a frame transmitting unit 316, and a BAG timer 318.

Specifically, the frame buffer 312 stores the frames that are not transmitted. That is, the frame buffer 312 stores the remaining frames without fragmenting for fragmentation.

The scheduler 314 controls the transmission of the first fragment of the frame payload based on the conversion table and the rest of the frames in the frame buffer 312 and sequentially transmits the subsequent fragments in accordance with the converted BAG.

The frame transmission unit 316 transmits the fragmented frame corresponding to the conversion table in response to the control signal from the scheduler 314. [

In addition, the scheduler 314 controls to sequentially transmit subsequent fragments corresponding to the conversion table at the time when the BAG timer 318 expires.

Specifically, the framer (not shown) constructs the same header as the previous one in the newly fragmented Ethernet payload to create a frame and attach a new sequence number. Since the number of frames is increased by fragmentation, a new sequence number must be managed.

For each virtual link, the sequence number counter is used as an 8-bit counter. The sequence counting rate increases in proportion to the ratio of the BAG size.

FIG. 4 conceptually shows the internal structure of the frame buffer unit 312. Lmax is provided with an area for storing the maximum frame length including the header and the like for each virtual link. When the frame arrives from the ES, it is stored in the buffer.

Then, the fragmented frame corresponding to the former part is transmitted with a new header, a sequence number and an FCS.

As shown in FIG. 4, it is possible to implement a structure in which an already sent portion is stored in a memory, and a structure in which data of a previously sent fragment is not stored in a memory.

In the latter case, it will be implemented in FIFO format, and only the data of the fragment that has not yet been sent is stored in the internal memory. The data stored in the frame buffer unit 122 must be transmitted all the way until the next frame arrives from the ES. Therefore,

 The size of the buffer unit 312 may be sufficient to store one frame of the maximum size for each virtual link.

4 shows a case where the virtual link is n. In FIG. 4, Lmax is 1/2 times that of the first virtual link and 1/4 times that of the second virtual link. In the case of the third virtual link 1/8 times. Since the Lmax values after the conversion in the first virtual link, the second virtual link, and the third virtual link are different from each other, the lengths of frames transmitted at first are different from each other.

This is, of course, limited only when a new Lmax value arrives at a frame longer than Lmax '.

If a frame shorter than Lmax 'arrives, it will process and deliver only header fragmentation without fragmentation, that is, without buffering.

Specifically, in the third virtual link, the frame is transmitted more frequently than the second virtual link instead of the Lmax length being short. In FIG. 4, the configuration for each virtual link-specific BAG is not shown, but it can be seen that the BAGs of the second virtual link and the third virtual link are equal to each other.

If the BAG of the third virtual link is 1/8 times that of the BAG of the second virtual link, even if Lmax is set to 1/2, the frame is not sent more frequently.

5 is a view illustrating a frame buffer according to another embodiment of the present invention. As shown in FIG. 5, the second fragment frame of the second virtual link is transmitted at the point in time when the first BAG 'converted from the reference time point of the second virtual link expires.

At this time, in the case of the third virtual link, the second fragment frame transmission is already completed, and the third fragment frame is transmitted.

Left and right arrows in FIG. 5 indicate a frame, and the left side is a frame input from the first edge switch 110. One frame is received, fragmented, and broken down like a right arrow several times.

- Information about virtual links -

The information on the virtual link in the conversion table is composed of pre-conversion information (Config # 1) and post-conversion information (Config # 2). When the frame arrives at the input port of the first edge switch 300, filtering and policing are performed through Integrity Check as in the existing AFDX MAC. Integrity Check is the process of validating a frame. Validation of the frame includes checking the constant value in the header, checking the FCS error, checking whether the frame length is shorter than the minimum length, or whether it is longer than the maximum length Lmax.

In the case of policing, if the frame is confirmed to be correct, it is checked whether the virtual link has arrived before the conversion. If it is input before the BAG interval, the frame is ignored. According to ARINC 664 Part 7 Specification 4.0 Switch Specification chapter, policing in switch operates based on token bucket algorithm.

If it is necessary to convert among the passed frames, the conversion unit 310 is entered. In the case of a virtual link having no conversion information in the conversion table, it is directly transferred from the policing to the redundant module (not shown) without passing through the conversion unit 310, and is transmitted to another switch.

- Conversion table -

6 is a diagram illustrating a conversion table according to an embodiment of the present invention. As shown in Fig. 6, the first edge switch 300 has a conversion table. When there are n virtual links requiring conversion, there are n virtual link conversion information. The values located in Config # 2 (after conversion) satisfy the condition of Equation (1).

For example, a virtual link of Config # 1 (before conversion) with a BAG of 8 ms and Lmax of 1499 bytes is converted to Config # 2, and the BAG is converted to Lmax 750 bytes at 4 ms. Dividing 1499 bytes by the BAG amplitude has a value of 749.5, which is the minimum integer greater than 750.

When the virtual link ID is 3, BAG is decreased to 1, and Lmax 'is 187.375 bytes according to Equation 1 when the transmission frequency is increased. Thus, with the new Config # 2, Lmax 'is determined to be 188 bytes, which is the smallest integer greater than 187.375.

There are three virtual links, each fragmented differently. When fragmented, the values of the new Lmax and BAG are determined using Equation (1).

7 is a configuration diagram of a reassembly unit 510 of the second edge switch 500 according to the embodiment of the present invention. As shown in FIG. 7, the second edge switch 500 is a switch immediately before the third end system 600, which is a destination of a transmission frame, and determines whether the received frame is valid using Equation (1). The reassembly unit 510 includes a reassembly memory 512, a reassembly control unit 514, a frame transfer unit 516, and a framer 518.

More specifically, the reassembly memory 512 stores only the payload of the frame when the received frame is valid.

The reassembly control unit 514 stores the frame sequence number and confirms whether the frame sequence number is erroneous.

The frame transfer unit 516 confirms that the stored frame is the completed payload and transfers the completed payload to the framer 518. [

The framer 518 attaches the pre-conversion header, the sequence number, and the FCS corresponding to the Config # 1 of the conversion table to the payload received from the frame transmission unit 516 to complete and transmit the frame.

8 is a conceptual diagram showing an aspect in which a conversion frame is accumulated in the reassembly memory 512 in the second edge switch 500 performing the reassembly according to the embodiment of the present invention.

The received frame accumulates only the payload in the reassembly memory 512 as shown in FIG.

- Payload reassembly completed -

FIG. 9 is a view showing a state where payload reassembly according to an embodiment of the present invention is completed. Information such as a header, a sequence number, and FCS is added to the payload of the completed frame, and the packet is made into an Ethernet frame and transmitted to the end switch. At this time, as in the fragmentation process, the sequence number is restored and given.

- When reassembling the frame -

10 is a view illustrating a frame reassembling process according to an embodiment of the present invention. The second edge switch 500 performs integrity and policing according to the converted information (Config # 2) and confirms the validity of the received frame. If the received frame is a valid frame, only the payload is stored in the reassembly memory 512. [ Then, the reassembly control unit 514 stores the sequence number of the frame received in the SEQ memory (not shown), and confirms whether there is a sequence number error for each received frame.

When the fragmented frame arrives without any error, the frame transfer unit 516 reads from the reassembly memory 512 and transfers it to the framer 518. The framer 518 transmits an Ethernet frame by attaching a header, a sequence number, and an FCS corresponding to the pre-conversion information (Config # 1) to the received payload.

The Frame Check Sequence (FCS) checks the occurrence of errors in the bitstream of the frames following the SFD.

When the second edge switch 500 reassembles the frame and transmits it to the third end system 600, the second edge switch 500 can exchange frames with the same virtual link setting as the first and second end systems 100 and 200, have.

If the third end system 600 is set to " Config # 2 ", and there is no edge switch for reassembling, the third end system 600 receives the converted frame in the same manner as the conventional AFDX frame receiving process .

When reassembling the frame in the third end system 600 -

Alternatively, in another embodiment, the reassembly of the fragmented frame may take place in the third end system 600, which is the final destination of the frame, rather than the second edge switch 500.

To this end, the third end system 600 includes a reassembly unit 610 that performs the same function as the reassembly unit 510.

11 is a view showing reassembly of a frame at a second edge switch 500 according to an embodiment of the present invention, and Fig. 12 is a view showing a third end system 600 according to another embodiment of the present invention Lt; RTI ID = 0.0 > reassembly. ≪ / RTI >

The first edge switch 300 of FIG. 11 receives a shaded frame, fragmentizes the frame into two, transmits the frame twice, and transmits the frame to the core switch 400. The core switch 400 then delivers the fragmented shaded frame to the second edge switch 500 in accordance with the existing AFDX network standard. The second edge switch 500 reassembles the shaded fragmented frame and delivers it to an end system (not shown).

In the case of a thin border frame, the fragmentation process is not performed. The bold frame frame is input to the input port of the core switch 410 and is fragmented and divided into two parts to be transmitted to the second edge switch 500, which is reassembled and transferred to the third end system 600.

In the above two embodiments, the receiving method is different in the final stage. In the embodiment shown in FIG. 11, the second edge switch 500 performs frame reassembly and delivers the completed frame to the third end system 600.

In the embodiment shown in FIG. 12, the second edge switch 500 transmits as it is received, and the third end system 600 performs frame reassembly.

Therefore, the settings of the second edge switch 500 and the third end system 600 are different according to two cases.

11, the third end system 600 has the same BAG, Lmax as the first end system 100 and the second end system 200. [ Each end system can not know the fragmentation process.

12, a new virtual link setting value set in the first edge switch 300, the core switch S1 400, the core switch S2 410, and the second edge switch 500 is set in the third end system 600, Is set to the same value as " The process of special reassembly and transmission according to the original setting is not necessary. Therefore, Fig. 12 shows a simpler network setting than the case of Fig. However, the BAG and Lmax settings between the end switches or the end systems are not appropriate, which may cause confusion during maintenance.

For example, in the case of a virtual link transmitting a bold frame, the virtual link setting of the ES # 3 and the virtual link of the same frame of the ES # 8 are different from each other. Therefore, it is possible that the virtual link setting may be different even though it is substantially the same frame.

FIG. 13 is a diagram illustrating a general Ethernet frame structure, and FIG. 14 is a diagram illustrating an AFDX Ethernet frame structure. Unlike a normal frame, an AFDX Ethernet frame has a 1-byte space in which a sequence number is stored, and is located in front of an FCS (Frame Check Sequence).

Because of the sequence number area, the payload can be sent one byte less than a regular Ethernet frame. In normal frames, up to 1500 bytes can be transmitted. In AFDX, 14 bytes in 1 byte, which is small, can be transmitted at the maximum payload.

And Ethernet has a large frame of up to 9000 bytes called jumbo frames. However, since the frame structure is not changed but the Ethernet payload is increased, the contents of this patent can be easily applied to the jumbo frame.

There is a 96-bit blank space called Interframe spacing (IFS) between frames. This is done in consideration of the technical delay time required to transmit / receive the frame.

15 is a diagram illustrating frame transmission when BAG and Lmax are changed according to an embodiment of the present invention. As shown in Fig. 15, the frame transmission is shown when the BAG is doubled (the value is doubled) and the Lmax is reduced by 1/2.

In fact, the amount of total traffic used due to fragmentation increases. Added header, FCS IFS, and so on. The engineer determining the AFDX setting will have to determine each of the values in the conversion table considering the amount of traffic increased when creating the conversion table.

At the end of the frame payload, a sequence number of 1 byte is attached. A number managed independently for each virtual link, with a value between 0 and 255, with an initial value of 0. When it becomes 255, it changes to 1 and circulates. When it is desired to initialize the sequence number on the transmitting side, 0 is carried and transmitted. When the receiving end receives the sequence number 0, the receiving end determines that the sequence number of the transmitting end is initialized and initializes the sequence number.

The number of frames changes during fragmentation and reassembly, resulting in differences in the operation of sequence numbers. More frequent frames are transmitted in the virtual link of Config # 2 than the virtual link set in Config # 1.

Also, if Lmax is twice longer than Lmax 'but the payload to be actually transmitted is less than half of Lmax, the fragmentation process does not occur. In this case, the sequence number is the same before or after the conversion.

However, if a payload exceeding half the Lmax is carried and transmitted, even once, the sequence number will change from then on.

If the first edge switch 300 receives a frame with a sequence number of zero, the fragmented frame sequence number also starts from zero. If the first fragmented frame sequence number is 0 in the process of reassembly, the sequence number of the reassembled frame is also initialized to zero.

For IP (Internet Protocol), ID (Identification) field and More field are used for fragmentation. Packets with the same ID value are fragmented, and the final fragmented packet is identified by the value of the More field.

However, AFDX frames do not provide separate fields for fragmentation, such as IP.

AFDX operates deterministically according to BAG and Lmax according to network profiling to ensure deterministic QoS.

- Frame reassembly complete operation logic -

BAG_a: BAG before conversion

BAG_b: BAG after conversion

Lmax_a: Lmax before conversion

Lmax_b: Lmax after conversion

T1: Time when the first fragmented frame arrived

Tc: Time at which the currently received fragmented frame arrived

N: Number of fragmented frames received so far

DIFF_BAG: Minimum integer value greater than or equal to BAG_a / BAG_b, greater than 1.

Each time a frame arrives, it performs the following operation.

First, it is checked whether the BAG_a time has elapsed. If elapsed, the fragmented frame can no longer arrive.

 This is because the frame after the BAG_a time has elapsed is a new frame.

If Tc - T1 is greater than or equal to BAG_a, the second edge switch 500 considers the reassembled data to be complete, although the number of previously received and reassembled frames is less than DIFF_BAG. In this case, the second edge switch 500 delivers the frame to the framer.

Then, the sequence number N is initialized to zero. In addition, the currently received fragmented frame becomes the first fragmented frame, and the fragmented frame is stored in the first part of the reassembly memory.

Next, if the currently received sequence number is 0, initialize together, otherwise increase 1. If it is 255, change it to 1.

If the subsequent frame arrives without BAG_a time yet, then the additional fragmented frame may have arrived.

Therefore, the reassembling process is performed according to the following conditions 1) to 4).

1) If N + 1 is equal to DIFF_BAG, the second edge switch 500 confirms that the last fragmented frame has arrived. That is, the frame that was previously received and reassembled is complete. The second edge switch 500 passes the completed frame to the framer and initializes N to zero. If N is zero, the currently received fragmented frame is the first fragmented frame.

2) The second edge switch 500 keeps the received frame at the front of the reassembly memory. If the currently received sequence number is 0, initialize it together, otherwise increase it. If the sequence number continuously increases to 255, it is changed to 1.

3) If N + 1 is less than DIFF_BAG THEN, the second edge switch 500 can not know whether the currently received fragmented frame is the last frame. Thus, the second edge switch 500 keeps the frame past the reassembly memory.

4) If it does not correspond to the above 1) to 3), the second edge switch 500 judges an error situation.

15 is a flowchart of an AFDX network performance improvement method according to an embodiment of the present invention.

As shown in FIG. 15, first, the first edge switch 300 receives a frame from the transmitting end system through at least one virtual link (S310).

Next, the received frame is fragmented based on the conversion table and transmitted (S320). Specifically, the conversion unit 310 converts BAG and Lmax of each virtual link based on the conversion table. In this case, the converting unit 310 creates a conversion table using Equation (1) and performs virtual link conversion.

More specifically, the scheduler 314 in the conversion unit 310 transmits the first fragment according to the Lmax of the frame payload based on the conversion table, stores the remaining part of the frame in the frame buffer 312, And sequentially transmitted in units of Lmax converted in accordance with the received BAG.

The frame transmission unit 316 transmits the fragmented frame under the control of the scheduler 314. [

The second edge switch 500 receiving the fragmented frame via the virtual link confirms the validity of the received frame and reassembles the frame if the received frame is valid (S330).

Specifically, the second edge switch 500 determines the validity of the received frame using Equation (1). If the second edge switch 500 determines that the received frame is valid, it stores only the payload of the received frame, stores the frame sequence number, and verifies whether the frame sequence number is erroneous.

Then, it is confirmed whether the stored frame is the completed payload, and whether the stored frame reassembly is completed or not is confirmed.

Specifically, if the difference between the first fragmented frame arrival time and the currently received fragmented frame arrival time is greater than or equal to the pre-conversion BAG, the second edge switch 500 confirms reassembly completion.

According to the present invention, it is possible to reduce the necessity of the capacity of the internal memory of the switch by performing optimal fragmentation at the time of frame transmission. By lowering the maximum memory size, it is possible to reduce the cost of memory development and switch development costs.

In addition, when the frames arriving at a plurality of input ports are output to one output port through the fragmentation of Lmax length, the end-to-end delay time is reduced, and the upper range of the network delay can be set lower than before. .

In addition, since the number of packets that can be transmitted within the same delay range increases, the number of virtual links can be increased, thereby improving network performance.

The foregoing description is merely illustrative of the technical idea of the present invention and various changes and modifications may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments described in the present invention are not intended to limit the scope of the present invention, but are intended to be illustrative, and the scope of the present invention is not limited by these embodiments. It is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents, which fall within the scope of the present invention as claimed.

100: first end system
200: second end system 300: first edge switch
310:
312: frame buffer 314: scheduler
316: frame transmission unit 318: BAG timer
400: core switch
500: second edge switch
510: reassembly portion
512: reassembly memory 514: reassembly control unit
516: a frame transmitting unit 518: a framer
600: Third end system
610: Reassembly section

Claims (16)

In a network system in which a maximum allowable value for a data transmission delay time between end points is set,
The method comprising: receiving at least one frame from each of the first end system and the second end system via each virtual link and then transmitting a BAG (Bandwidth Allocation Gap) and a maximum transmission length A first edge switch for fragmenting and transmitting a frame according to the converted BAG and Lmax; And
And a reassembly unit for judging the validity of the frame received from the first edge switch and reassembling the frame if the frame is valid, and a second edge switch for transmitting the completed frame to the destination end system
≪ / RTI >
The apparatus of claim 1, wherein the converting unit
The conversion table is created using the following equation and the setting conversion of the virtual link is performed
In network system.

Lmax: Existing configuration (Lmax of the virtual link already defined in the first end system)
Lmax ': the new setting (Lmax of the newly defined virtual link in the first edge switch)
BAG: The existing configuration (BAG of the virtual link already defined in the first end system)
BAG ': a new setting (BAG of the second virtual link newly defined in the first edge switch)
Here, Lmax denotes an Ethernet payload length excluding a MAC Destination Address, a MAC Source Address, an EtherType, a Sequence number, and an FCS.
The apparatus of claim 1, wherein the converting unit
A frame buffer for storing frames that are not transmitted;
A scheduler for transmitting a first fragment of the frame payload based on the conversion table, storing a remaining portion of the frame in the frame buffer, and sequentially transmitting a subsequent fragment in accordance with the converted BAG; And
And a frame transmission unit for transmitting a fragmented frame corresponding to the conversion table in response to a control signal from the scheduler
In network system.
4. The apparatus of claim 3, further comprising a BAG timer,
The scheduler controls to sequentially transmit a subsequent fragment corresponding to the conversion table at the time when the BAG timer expires
In network system. The apparatus of claim 1, wherein the second edge switch is configured to determine whether the received frame is valid using the converted BAG and Lmax
In network system. The apparatus of claim 1, wherein the reassembly unit
A reassembly memory for storing only the payload of the frame when the received frame is valid;
A reassembly control unit for storing the frame sequence number and checking whether the frame sequence number is erroneous;
A frame transmitting unit for confirming whether the stored frame is a completed payload and for transmitting the payload; And
And a framer that completes and transmits a frame by attaching a header, a sequence number, and an FCS corresponding to the pre-conversion setting of the virtual link to the payload received from the frame transmitting unit
In network system. 2. The apparatus of claim 1, wherein the second edge switch
If the difference between the arrival time of the first fragmented frame and the arrival time of the fragmented frame that is currently received is greater than the BAG before the conversion,
In network system. In a network system in which a maximum allowable value for a data transmission delay time between end points is set,
The method comprising: receiving at least one frame from each of the first end system and the second end system via each virtual link and then transmitting a BAG (Bandwidth Allocation Gap) and a maximum transmission length (Lmax An edge switch for fragmenting and transmitting the frame based on the converted BAG and Lmax; And
And a reassembly unit for determining the validity of the frame received from the edge switch and reassembling the frame if the frame is valid
In network system. The method of claim 8, wherein the third end system determines whether the received frame is valid using the converted BAG and Lmax
In network system. 9. The apparatus of claim 8, wherein the reassembly portion
A reassembly memory for storing only the payload of the frame when the received frame is valid;
A reassembly control unit for storing the sequence number of the frame and checking whether the sequence number is erroneous;
A frame transmitting unit for confirming whether the stored frame is a completed payload and for transmitting the payload; And
And a framer that completes and transmits a frame by attaching a header, a sequence number, and an FCS corresponding to the pre-conversion setting of the virtual link to the payload received from the frame transmitting unit
In network system. A method for improving performance of a network system in which a maximum allowable value for a data transmission delay time between ends is set,
Receiving a frame over at least one virtual link;
Converting a BAG (Bandwidth Allocation Gap) and a maximum transmission length (Lmax), which are the minimum transferable intervals of the virtual link, based on the conversion table, fragmenting and transmitting the frame based thereon; And
Receiving the fragmented frame and reassembling the fragmented frame if the received frame is valid
/ RTI > 12. The method of claim 11, wherein the transmitting comprises:
The conversion table is created using the following equation and the setting of the virtual link is changed
To improve network performance.

Lmax: Existing configuration (Lmax of the virtual link already defined in the first end system)
Lmax ': the new setting (Lmax of the newly defined virtual link in the first edge switch)
BAG: The existing configuration (BAG of the virtual link already defined in the first end system)
BAG ': a new setting (BAG of the second virtual link newly defined in the first edge switch)
Here, Lmax denotes an Ethernet payload length excluding a MAC Destination Address, a MAC Source Address, an EtherType, a Sequence number, and an FCS. 12. The method of claim 11, wherein the transmitting comprises:
Storing a frame that is left untransferred;
Transmitting a first fragment of the frame payload based on the conversion table and storing the remaining portion of the frame in a frame buffer; And
Transmitting a fragmented frame corresponding to the translation table
Further comprising
To improve network performance.
12. The method of claim 11, wherein the reassembling step comprises: determining whether a received frame is valid using BAG and Lmax
To improve network performance. 12. The method of claim 11, wherein reassembling
Storing only the payload of the frame if the received frame is valid;
Storing a sequence number of the frame;
Determining whether the frame sequence number is erroneous;
Confirming that the stored frame is a completed payload; And
Confirming whether the stored frame reassembly has been completed or not
To improve network performance. [16] The method of claim 15,
If the difference between the arrival time of the first fragmented frame and the arrival time of the fragmented frame currently received is greater than the BAG before the conversion, confirmation is made that the reassembly is completed
To improve network performance.

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