JP2013048415A - Embedded end-to-end delay information for data networks - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an end-to-end system where a value in a delay field of a frame corresponding to a virtual link is updated.SOLUTION: A system 100 comprises a plurality of nodes, at least one of the plurality of nodes inserts, on a per-virtual link basis, a delay value into a dynamic delay field of a frame corresponding to the respective virtual link, and the dynamic delay value represents latency of frames of the respective virtual link. The system comprises a switch having a plurality of ports, and each port is coupled to one of the plurality of nodes. The switch routes frames received from the plurality of nodes to one or more of the plurality of nodes. At least one of the plurality of nodes stores frames received from the switch in a buffer and updates the value in the dynamic delay field to reflect the end-to-end system delay.

Description

[001] This application is related to copending US patent application, which is hereby incorporated by reference in its entirety.
[002] US Application Patent No. 13 / 073,260, filed March 28, 2011 under the title of "VERSATILE SOURCE PORT ENFORCEMENT FOR DATA NETWORKS" No. H0028046-5409), which is referred to herein as the '046 application.

  [003] US patent application Ser. No. 13 / 073,269 filed on Mar. 28, 2011 (Attorney Docket No. H0028047), entitled “CENTRALIZED TRAFFIC SHAPING FOR DATA NETWORKS”. -5409), which is referred to herein as the '048 application.

  [004] Some conventional data networks use virtual links. For example, Chapter 7 of AirLink (ARINC) 664 defines an Ethernet that enables analysis of traffic flows that are analyzed in relation to transmission timing between full-duplex switched Ethernet network endpoints. Yes. The virtual link at the Ethernet network level is realized by a multicast group using a multicast Ethernet address unique to the entire network managed locally. That is, all virtual link frames use the same Ethernet multicast destination address, while frames of different virtual links use different Ethernet multicast destination addresses. Thus, a virtual link frame can be identified by the destination Ethernet address of the frame at the Ethernet network level.

  It is an object of the present invention to provide an end-to-end system that updates the value in the delay field of a frame corresponding to a virtual link to reflect real-time delay.

  [005] In one embodiment, a system is provided. The system includes a plurality of nodes, and at least one of the plurality of nodes is configured to insert a delay value for each virtual link in a dynamic delay field of a frame corresponding to each virtual link. The dynamic delay value indicates the waiting time of each frame of the virtual link. The system also includes a switching device having a plurality of ports, each port being connected to one node of the plurality of nodes. The switching device is configured to route frames received from a plurality of nodes to one or more nodes of the plurality of nodes. At least one of the plurality of nodes is configured to store a frame received from the switching device in a buffer and update a value in the dynamic delay field to reflect an end-to-end system delay .

  [006] It is understood that the drawings show only exemplary embodiments and therefore should not be considered to limit the scope of the invention, and additional exemplary embodiments are added through the use of the accompanying drawings. With specific specificity and details.

[007] FIG. 1 is a block diagram of one embodiment of a system. [008] FIG. 4 is a block diagram of one embodiment of an exemplary frame. [009] Fig. 6 is a flow chart illustrating an embodiment of a frame transmission method.

[0010] The various features described in accordance with common practice are not drawn to scale but are drawn to emphasize specific features relevant to the exemplary embodiments.
[0011] In the following detailed description, reference is made to the accompanying drawings, which are shown by way of illustration of specific exemplary embodiments, which form a part hereof. However, it will be appreciated that other embodiments may be utilized and that logical, mechanical, and electrical changes may be performed. In addition, the methods presented in the drawings and specification should not be construed as limiting the order in which individual actions are performed. Accordingly, the following detailed description should not be accepted in a limiting sense.

  FIG. 1 is a block diagram of one embodiment for an exemplary system 100. The system 100 includes a plurality of nodes 102-1 to 102-N (also referred to as end systems) and at least one switching device 104. The system 100 is configured to transmit a frame between the nodes 102-1 to 102-N using a virtual link via the switching device 104. In this specification, a virtual link is a unidirectional logical path that connects two or more nodes 102-1 to 102-N via a switching device 104. For example, in some embodiments, the system 100 implements a protocol that is compatible with Chapter 7 of the Air Link (ARINC) standard 664 (also referred to as Full Duplex Switched Ethernet (AFDX) for aircraft). Some are full duplex switched Ethernet networks. In some embodiments, the virtual link is limited to having one and only one source node 102-1 to 102-N as defined in Chapter 7 of ARINC standard 664. . However, in another embodiment, the switching device 104 is configured to support multiple nodes 102-1 to 102-N as valid source nodes for the single virtual link described in the '046 application. Some are.

  [0013] Each of the nodes 102-1 to 102-N is communicatively connected to each of the subsystems 120. The implementation of each subsystem 120 depends on the implementation of the system 100. In this example, system 100 is implemented as an aircraft system, for example. Thus, each subsystem 120 is implemented as one of, but not limited to, a flight computer system, a navigation system, a global navigation satellite system (GNSS), and the like. Accordingly, subsystems 120-1 and 120-N are respectively connected to one or more sensors 126 and one or more actuators 128 corresponding to the implementations of subsystems 120-1 and 120-N, respectively. In addition, in this embodiment, the subsystem 120-2 is implemented as a gateway connected to another network 130 such as the Internet.

  [0014] Each subsystem 120 provides data to each of nodes 102-1 through 102-N. In addition, each subsystem 120 includes an advanced application 125 implemented at the application layer. The term “application layer” is known to those skilled in the art and refers herein to programs and services that implement advanced functionality to accomplish tasks on the network, such as protocols that implement specific user applications. doing. Each of the nodes 102-1 to 102-N processes data in turn and outputs it via one or more corresponding virtual links. Specifically, each of the nodes 102-1 to 102-N includes a controller or processing unit 124, and the corresponding delay rule 122 stored in the memory 132 of each of the nodes 102-1 to 102-N. Based on this, it is configured to insert a delay value for each of the one or more virtual links into the field of the corresponding Ethernet frame. One or more delay values may be used by the corresponding Ethernet frame while residing in the nodes 102-1 to 102-N or while being transmitted from the nodes 102-1 to 102-N to another device in the system 100. Indicates the delay or latency experienced. In some embodiments, the delay value is a dynamic value measured by each of the nodes 102-1 to 102-N, such as, for example, a frame delay waiting in an output queue, but is not limited thereto. do not do. In addition, in some embodiments, the delay value is preconfigured, such as a wired transmission delay from a transmission port of a node of the system 100 to a reception port of another device, and the nodes 102-1 to 102- There are also static values stored in N, but not limited thereto.

  [0015] In addition, the controller 124 is configured to determine, based on the delay rule 122, what virtual link delay value or multiple delay values to add to the corresponding frame. For example, one or more static delay values may be selected based on the contents of the frame corresponding to each virtual link. That is, a static delay value or a plurality of delay values may include a virtual link ID, an Internet protocol (IP) source address, a destination IP address, a user datagram protocol (UDP) source port, a UDP destination port, or One or more of the other fields included in the Ethernet frame payload may be selected based on information. In some embodiments, the controller 124 is configured to update a checksum (also referred to as a frame check sequence (FCS) or cyclic redundancy check (CRC)) based on the inserted delay value. There is also. It will be appreciated that in some embodiments, the checksum can reside in a different frame than the inserted delay value frame, as in the embodiment implementing fragmented frame packets. Further, in some embodiments, the delay value is added only to a particular frame of the virtual link based on the delay rule 122, such as the first fragment of a fragmented UDP packet.

  [0016] After inserting the delay value and performing another process on the frame, such as monitoring that the virtual link ensures that it meets the bandwidth allocation gap (BAG) requirements, the node 102-1 102-N transmit each frame of the virtual link to the switching device 104. The switching device 104 receives the frame via the corresponding ports 106-1 to 106-N. The switching device 104 processes each received frame in the arithmetic processing device 114. For example, the processing unit 114 is configured to determine whether a frame is received on a port for which the virtual link of the corresponding frame is valid. In addition, the arithmetic processing unit 114 is configured to output the effectively received frame to one or more nodes 102-1 to 102-N based on the routing table 118 stored in the memory 116. Route to the above ports 106-1 to 106-N.

  [0017] In this embodiment, in addition to the nodes 102-1 to 102-N, the arithmetic processing unit 114 receives the (delay field) of the received frame based on the delay rule 123 stored in the memory 116. It is configured to insert a delay value for each of one or more virtual links in the field. In some embodiments, for example, the delay value inserted into a particular frame is determined based on the port 106 through which the received frame has passed. In addition, in some embodiments, the arithmetic processing unit 104 is configured to insert a delay value into a frame corresponding to a part of the virtual link although it is not a frame corresponding to all the virtual links. is there. In some embodiments, the delay value inserted into the frame indicates a range of values rather than a specific value.

  [0018] The processing unit 114 is a software program for performing various methods, process tasks, calculation functions, and control functions used when inserting a delay value for each virtual link in the field of an Ethernet frame. Includes or functions with firmware, or other computer readable instructions. Such instructions are typically stored on any suitable computer readable medium used for storage of computer readable instructions or data structures. A computer-readable medium may be implemented as any available medium that can be accessed by a general purpose or special purpose computer, or a processor or any programmable logic. Suitable processor readable media may include storage devices or storage media such as magnetic or optical media. For example, a storage device or a storage medium may be a conventional hard disk, CD ROM (synchronous SDRAM (SDRAM), double data rate (DDR) RAM, RAMBUS dynamic RAM (RDRAM ™), static RAM ( Volatile or non-volatile media such as random access memory (RAM), read only memory (ROM), electrically erasable ROM (EEPROM), flash memory, etc. obtain. Suitable processor readable media may also include transmission media such as electrical signals, electromagnetic signals, or digital signals transmitted via communication media such as network and / or wireless links.

  [0019] In the switching device, the arithmetic processing device 104 routes the received frame to the nodes 102-1 to 102-N based on the routing table 118. Received frames are stored in each node's buffers 127-1 to 127 -N until accessed by the advanced application 125 in the corresponding subsystem 120. Receiving nodes 102-1 to 102-N insert dynamic time stamps into the delay field at the physical layer. The term “physical layer” is known to those skilled in the art and refers herein to the physical hardware components of a system, such as transmission media, pin adapters, network adapters, host bus adapters, circuit elements, etc. It is not limited to. In addition, the term “dynamic time stamp” is used herein to refer to a time stamp that is updated to reflect changes in delay time. For example, when the corresponding message is stored in the buffers 127-1 to 127 -N, the controller 124 uses a component in the physical layer and inserts a time stamp in the dynamic delay field. In addition, the arithmetic processing unit updates the time stamp when another event occurs. For example, the timestamp in the dynamic delay field may be updated upon access to an application or service 125 message operating at a specific interval or application layer.

  [0020] At the application layer, the controller 124 updates the value in the dynamic delay field when the application reads or writes the message stored in the buffers 127-1 to 127-N. Thus, the dynamic delay field is constantly updated, providing end-to-end system real-time delay to the application 125 residing at the application layer. The real-time delay of an end-to-end system is a delay with respect to a sender from the time of message transmission to the time when the message is accessed. Thus, the static value may be initially inserted into the delay field by the corresponding node 102-1 to 102-N, but the static value is updated to reflect the real-time delay.

  [0021] FIG. 2 is a block diagram illustrating an exemplary frame 200 communicated between nodes 102-1 to 102-N and switching device 104. As shown in FIG. Frame 200 includes a preamble 202, a start of frame (SOF) 204, and an interframe gap (IFG) 234 that are known to those skilled in the art. In addition, the frame 200 includes an Ethernet frame 206. The Ethernet frame includes a header 208 and a payload 210. The Ethernet header 208 includes a transmission destination address 212 and a transmission source address 214. The destination address 212 includes a fixed field 216 and a virtual link identifier 218. A virtual link identifier is used to route a frame at the switching device using a routing table that indicates the output port with which the virtual link is associated. The Ethernet header 208 also includes a type field 220 known to those skilled in the art.

  [0022] The Ethernet payload 210 includes a delay field 222, an IP header 224, and an IP payload 226. Both or one of the nodes 102-1 to 102-N and the switching device 104 are configured to insert a delay value into the delay field 222. In particular, the location of the delay field 222 of the Ethernet payload 210 of FIG. 2 is provided as an example, but is not limited thereto. Specifically, when the frame passes through the device, the delay field 222 is checked by checking the content of the frame against the rules (for example, the delay rule 122) stored in the nodes 102-1 to 102-N or the switching device 104. The position and / or length of each can be determined dynamically. In addition, in the implementation, the stored rule indicates what delay value to insert based on one or more information of virtual link ID, IP address, or UDP port number There is also. Thus, whether to insert a static delay value, a dynamic delay value, or a combination of a static delay value and a dynamic delay value, and a value or range of values to be inserted into the delay field 222 is virtual. It is determined individually for each link ID.

  [0023] In this example, the IP payload 226 is comprised of a UDP header 228 and a UDP payload 230 that are known to those skilled in the art. In addition, the Ethernet frame 206 includes a frame check sequence 232. In some embodiments, the frame check sequence 232 is updated to reflect the delay value inserted in the delay field 222.

  [0024] FIG. 3 is a flow diagram illustrating one embodiment of a method 300 for communicating the aforementioned frame to a system such as system 100. In block 302, the delay value for each virtual link is inserted into the delay field of the corresponding frame of each virtual link at the source node. The delay value indicates the waiting time of each frame of the virtual link. In this specification, the transmission source node is a node designated as the transmission source of the frame for each virtual link. Therefore, in this specification, a destination node is a node for each virtual link, and a frame that arrives from a corresponding source node is designated as a routed target node.

  [0025] In some embodiments, inserting a delay value into the delay field includes inserting at least one value of a dynamic delay value and a static delay value. In addition, in some embodiments, inserting the delay value includes updating a checksum in a corresponding frame based on the inserted delay value.

  [0026] At block 304, a corresponding frame having a delay field is transmitted from the source node to the switching device. In some embodiments, at block 306, the switching device is configured to insert a delay value into the delay field. In the above embodiment, inserting the delay value comprises adding a static value, a dynamic value, or a combination of a static value and a dynamic value to the received value included in the delay field; Substituting the received value with a value that is the result of adding to the received value. In addition, inserting the delay value includes updating any checksum affected by the inserted delay value. In another embodiment, the switching device does not insert a delay value. At block 308, the corresponding frame is routed to one or more destination nodes based on each virtual link. In this embodiment, the frame is transmitted and routed using a protocol that is compatible with the ARINC 664 Chapter 7 standard. However, it will be appreciated that other protocols may be used in other embodiments.

  [0027] At block 310, the value in the delay field is updated to reflect the real-time delay of the end-to-end system. The delay field may be updated when a specific event occurs, for example, a frame access by an application layer application.

Exemplary Embodiment
[0028] Example 1 is a system including a plurality of nodes, in which at least one of the plurality of nodes sets a delay value for each virtual link in a dynamic delay field of a frame corresponding to each virtual link. Including a switch configured to insert, a dynamic delay value indicating a frame latency for each virtual link, and a switching device having a plurality of ports, each port having a plurality of nodes And the switching device is configured to route a frame received from the plurality of nodes to one or more nodes of the plurality of nodes, and at least one of the plurality of nodes. One node stores the frame received from the switching device in the buffer and sets the value in the dynamic delay field to reflect the end-to-end system delay. Configured new to.

  [0029] Example 2 includes the system of Example 1, wherein at least one node configured to update the value in the dynamic delay field is dynamically updated when the frame is accessed by the application. Configured to update the delay field.

  [0030] Example 3 includes any of the systems of Examples 1-2, wherein at least one node corresponds to the virtual link ID of the corresponding frame, the Internet Protocol (IP) source address of the corresponding frame, A delay value to be inserted based on one or more of the following information: the recipient IP address of the frame, the User Datagram Protocol (UDP) source port of the corresponding frame, and the UDP destination port of the corresponding frame Configured to determine.

  [0031] Example 4 includes any of the systems of Examples 1-3, wherein at least one node is configured to insert a delay value into a portion of all frames corresponding to each virtual link. .

  [0032] Example 5 includes any of the systems of Examples 1-4, wherein at least one node updates the checksum of the corresponding frame based on the delay value inserted into the delay field. Configured as follows.

  [0033] Example 6 includes any of the systems of Examples 1-5, wherein at least one node is configured to dynamically determine the position or length of the delay field of the corresponding frame.

  [0034] Example 7 includes any of the systems of Examples 1-6, in which the switching device inserts a delay value for each virtual link in the delay field of the corresponding frame received from at least one node. Configured as follows.

  [0035] Example 8 includes any of the systems of Examples 1-7, wherein the switching device and the plurality of nodes are configured to implement a protocol compatible with Chapter 7 of ARINC 664.

  [0036] Example 9 includes a communication device that includes a memory having stored delay rules, where the delay rules are one or more per virtual link in a delay field in a corresponding frame of each virtual link. Information that is used when inserting the delay value of the corresponding frame, and the arithmetic processing unit compares the information contained in the corresponding frame with the delay rule and compares the information in the corresponding frame. Is configured to insert a delay value for each of the one or more virtual links, and the processing unit is further configured to update a delay field in the received frame until the frame is accessed by an application. .

  [0037] Example 10 includes the communication device of Example 9, where the processing unit has a virtual link ID of the corresponding frame, an Internet protocol (IP) source address of the corresponding frame, and a recipient IP of the corresponding frame. A delay value to be inserted is determined based on a comparison between at least one of the address, the user datagram protocol (UDP) source port of the corresponding frame, and the UDP source port of the corresponding frame and a delay rule. Configured as follows.

[0038] Example 11 includes any of the communication devices of Examples 9-10, wherein the processing unit is configured to insert at least one dynamic delay value and static delay value for each virtual link. The
[0039] Example 12 includes any of the communication devices of Examples 9-11, and based on the delay value inserted by the arithmetic processing unit into the corresponding frame, the checksum in the corresponding frame is calculated. Configured to update.

  [0040] Example 13 includes any of the communication devices of Examples 9-12, wherein the communication device is configured to implement a protocol that is compatible with the ARINC 664 Chapter 7 standard. , Or one of the switching devices configured to implement a protocol that is compatible with the ARINC 664 Chapter 7 standard.

  [0041] Example 14 includes any of the communication devices of Examples 9-13, wherein the processing unit is configured to dynamically determine the position or length of the delay field in the corresponding frame. The

  [0042] Example 15 includes any of the communication devices of Examples 9-14, where the processing unit displays a delay value in a portion of all frames corresponding to each virtual link based on a delay rule. Configured to insert.

  [0043] Example 16 includes a method for transmitting a frame, wherein a delay value for each virtual link is inserted into a delay field of a frame corresponding to each virtual link at a source node, A value indicating the latency of each frame of the virtual link, a step of transmitting a corresponding frame having a delay field from the node to the switching device, and a delay field based on each virtual link Routing a corresponding frame from the switching device to one or more destination nodes, and in one or more destination nodes, in the delay field to reflect the real-time delay of the end-to-end system Updating the value.

  [0044] Example 17 includes the method of Example 16, wherein updating the value in the delay field includes updating the value in the delay field when the frame is accessed by the application. Yes.

  [0045] Example 18 includes any of the methods of Examples 16-17, wherein inserting a delay value updates a checksum in a corresponding frame based on the inserted delay value. Contains.

  [0046] Example 19 includes any of the methods of Examples 16-18, wherein transmitting a corresponding frame corresponds using a protocol compatible with the ARINC 664 Chapter 7 standard. Transmitting the frame, wherein routing the corresponding frame includes routing the corresponding frame using a protocol compatible with the ARINC 664 Chapter 7 standard. Yes.

  [0047] Example 20 includes any of the methods of Examples 16-19 and further includes inserting a delay value for each virtual link in a delay field of a corresponding frame in the switching device. .

  [0048] Although specific embodiments are illustrated and described herein, those of ordinary skill in the art will be able to substitute any computational process to accomplish the same purpose for the specific embodiments shown. It will be fully understood. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 100 System 102-1 Node 102-2 Node 102-N Node 104 Switching device 106-1 Port 106-2 Port 106-N Port 114 Processing unit 116 Memory 118 Routing table 120-1 Subsystem 120-2 Subsystem 120 -N subsystem 122-1 delay rule 122-2 delay rule 123-N delay rule 124-1 controller 124-2 controller 124-N controller 125-1 one or more applications 125-2 one or more applications 125-N One or more applications 126 Sensor 128 Actuator 127-1 Buffer 127-2 Buffer 127-N Buffer 130 Network 132-1 Memory 132-2 Memory 13 -N memory 200 frame 202 preamble 204 frame start 206 Ethernet frame 208 Ethernet header 210 Ethernet payload 212 destination address 214 source address field 216 fixed field 218 virtual link identifier field 220 type field 222 delay field 224 IP header field 226 IP payload 228 UDP header 230 UDP payload field 232 Frame check sequence field 234 Interframe gap field

Claims (3)

A plurality of nodes (102-1 to 102-N), wherein at least one of the plurality of nodes has a delay value for each virtual link in a dynamic delay field of a frame corresponding to each virtual link. A plurality of nodes, wherein the dynamic delay value represents a latency time of the frame of each respective virtual link;
A switching device (104) having a plurality of ports (106-1 to 106-N), wherein each port is connected to one node of the plurality of nodes (102-1 to 102-N) A device (104),
The switching device (104) routes a frame received from the plurality of nodes (102-1 to 102-N) to one or more nodes of the plurality of nodes (102-1 to 102-N). Configured as
At least one of the plurality of nodes (102-1 to 102-N) stores a frame received from the switching device (104) in a buffer (127), and reflects an end-to-end system delay. A system (100) configured to update a value in the dynamic delay field.   The at least one node configured to update a value in the dynamic delay field is configured to update the dynamic delay field when the frame is accessed by an application. The described system (100).   The system (100) of claim 1, wherein the switching device (104) is configured to insert a delay value for each virtual link in the delay field of a corresponding frame received from the at least one node.

Images